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d678a59d |
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18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com> |
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935b60f8 |
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30-Apr-2024 |
Tom Rini <trini@konsulko.com> |
arm: fsl-layerscape: Remove <common.h> and add needed includes Remove <common.h> from all fsl-layerscape related files and when needed add missing include files directly. Acked-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com> |
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e7ec875d |
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05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of SYS_FSL_ERRATUM_A010539 This converts 1 usage of this option to the non-SPL form, since there is no SPL_SYS_FSL_ERRATUM_A010539 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> |
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6e7df1d1 |
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10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
global: Finish CONFIG -> CFG migration At this point, the remaining places where we have a symbol that is defined as CONFIG_... are in fairly odd locations. While as much dead code has been removed as possible, some of these locations are simply less obvious at first. In other cases, this code is used, but was defined in such a way as to have been missed by earlier checks. Perform a rename of all such remaining symbols to be CFG_... rather than CONFIG_... Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
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1d457dbb |
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04-Dec-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_MAX_MEM_MAPPED to CFG Perform a simple rename of CONFIG_MAX_MEM_MAPPED to CFG_MAX_MEM_MAPPED Signed-off-by: Tom Rini <trini@konsulko.com> |
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4fd9373b |
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02-Dec-2022 |
Tom Rini <trini@konsulko.com> |
net: Remove more legacy functions Remove some of the board and arch specific non-DM_ETH helper code. Signed-off-by: Tom Rini <trini@konsulko.com> |
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65cc0e2a |
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16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
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aa6e94de |
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16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
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ecc8d425 |
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16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_PCI* to CFG_SYS_PCI* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_PCI and CONFIG_SYS_PCIE namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
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6cc04547 |
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28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
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8fd11135 |
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25-Sep-2022 |
Sean Anderson <sean.anderson@seco.com> |
arm64: layerscape: Support SYSRESET CONFIG_SYSRESET provides its own implementation of reset_cpu. Disable our version when it is enabled. Signed-off-by: Sean Anderson <sean.anderson@seco.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> |
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ce9c579e |
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13-Jun-2022 |
Andre Przywara <andre.przywara@arm.com> |
armv8: always use current exception level for TCR_ELx access Currently get_tcr() takes an "el" parameter, to select the proper version of the TCR_ELx system register. This is problematic in case of the Apple M1, since it runs with HCR_EL2.E2H fixed to 1, so TCR_EL2 is actually using the TCR_EL1 layout, and we get the wrong version. For U-Boot's purposes the only sensible choice here is the current exception level, and indeed most callers treat it like that, so let's remove that parameter and read the current EL inside the function. This allows us to check for the E2H bit, and pretend it's EL1 in this case. There are two callers which don't care about the EL, and they pass 0, which looks wrong, but is irrelevant in these two cases, since we don't use the return value there. So the change cannot affect those two. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Mark Kettenis <kettenis@openbsd.org> Tested-by: Mark Kettenis <kettenis@openbsd.org> |
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cda8f873 |
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11-May-2022 |
Ye Li <ye.li@nxp.com> |
caam: Fix crash in case caam_jr_probe failed If probing caam_jr returns failure, the variable "dev" will not be initialized, so we can't use dev->name for the error print. Otherwise it will cause crash. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Gaurav Jain <gaurav.jain@nxp.com> |
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cb14cc88 |
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22-Apr-2022 |
Michael Walle <michael@walle.cc> |
armv8: layerscape: get rid of smc_call() There are two different implementations to do a secure monitor call: smc_call() and arm_smccc_smc(). The former is defined in fwcall.c and seems to be an ad-hoc implementation. The latter is imported from linux. smc_call() is also only available if CONFIG_ARMV8_PSCI is not defined. This makes it impossible to have both PSCI calls and PSCI implementation in one u-boot build. The layerscape SoC code decide at runtime via check_psci() if there is a PSCI support. Therefore, this is a prerequisite patch to add PSCI implementation support for the layerscape SoCs. Note, for the TFA part, this is only compile time tested with (ls1028ardb_tfa_defconfig). Signed-off-by: Michael Walle <michael@walle.cc> [Rebased] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
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dfb6da55 |
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05-Apr-2022 |
Marek Vasut <marex@denx.de> |
armv8: layerscape: env: Switch to arch_env_get_location() Implement arch_env_get_location() instead of env_get_location(), so that the env_get_location() can be implemented on board level and override the arch_env_get_location() architecture defaults. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Adam Ford <aford173@gmail.com> Cc: Fabio Estevam <festevam@denx.de> Cc: Marek Behún <marek.behun@nic.cz> Cc: Peng Fan <peng.fan@nxp.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefano Babic <sbabic@denx.de> Cc: Tim Harvey <tharvey@gateworks.com> Cc: Tom Rini <trini@konsulko.com> Cc: Tommaso Merciai <tomm.merciai@gmail.com> Cc: Vladimir Oltean <vladimir.oltean@nxp.com> |
#
8976556a |
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24-Mar-2022 |
Gaurav Jain <gaurav.jain@nxp.com> |
Layerscape: Enable Job ring driver model. LS(1021/1012/1028/1043/1046/1088/2088), LX2160, LX2162 platforms are enabled with JR driver model. removed sec_init() call from board files. sec is initialized based on job ring information processed from device tree. Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Michael Walle <michael@walle.cc> |
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f9147d63 |
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25-Feb-2022 |
Tom Rini <trini@konsulko.com> |
Convert CONFIG_CHIP_SELECTS_PER_CTRL to Kconfig This converts the following to Kconfig: CONFIG_CHIP_SELECTS_PER_CTRL Cc: Alison Wang <alison.wang@nxp.com> Cc: Pramod Kumar <pramod.kumar_1@nxp.com> Cc: Priyanka Jain <priyanka.jain@nxp.com> Cc: Rajesh Bhagat <rajesh.bhagat@nxp.com> Cc: Vladimir Oltean <olteanv@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com> |
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2f8a6db5 |
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14-Dec-2021 |
Tom Rini <trini@konsulko.com> |
Finish conversion of CONFIG_SYS_CLK_FREQ to Kconfig In order to finish moving this symbol to Kconfig for all platforms, we need to do a few more things. First, for all platforms that define this to a function, introduce CONFIG_DYNAMIC_SYS_CLK_FREQ, similar to CONFIG_DYNAMIC_DDR_CLK_FREQ and populate clock_legacy.h. This entails also switching all users from CONFIG_SYS_CLK_FREQ to get_board_sys_clk() and updating a few preprocessor tests. With that done, all platforms that define a value here can be converted to Kconfig, and a fall-back of zero is sufficiently safe to use (and what is used today in cases where code may or may not have this available). Make sure that code which calls this function includes <clock_legacy.h> to get the prototype. Signed-off-by: Tom Rini <trini@konsulko.com> |
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77b11f76 |
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18-Sep-2021 |
Vladimir Oltean <vladimir.oltean@nxp.com> |
net: replace the "xfi" phy-mode with "10gbase-r" As part of the effort of making U-Boot work with the same device tree as Linux, there is an issue with the "xfi" phy-mode. To be precise, in Linux there was a discussion (for those who have time to read: https://lore.kernel.org/netdev/1576768881-24971-2-git-send-email-madalin.bucur@oss.nxp.com/) which led to a patch: https://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next.git/commit/?id=c114574ebfdf42f826776f717c8056a00fa94881 TL;DR: "xfi" was standardized in Linux as "10gbase-r". This patch changes the relevant occurrences in U-Boot to use "10gbase-r" instead of "xfi" wherever applicable. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> |
#
84c2e044 |
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20-Apr-2021 |
Jiafei Pan <Jiafei.Pan@nxp.com> |
armv8: layerscape: add PSCI support for cpu release For cpu release command, check whether PSCI is supported firstly, if supported, use PSCI to kick off secondary cores, otherwise still use spin table. Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com> [Fixed checkpatch alignment CHECKs] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
35b65dd8 |
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15-Dec-2020 |
Harald Seiler <hws@denx.de> |
reset: Remove addr parameter from reset_cpu() Historically, the reset_cpu() function had an `addr` parameter which was meant to pass in an address of the reset vector location, where the CPU should reset to. This feature is no longer used anywhere in U-Boot as all reset_cpu() implementations now ignore the passed value. Generic code has been added which always calls reset_cpu() with `0` which means this feature can no longer be used easily anyway. Over time, many implementations seem to have "misunderstood" the existence of this parameter as a way to customize/parameterize the reset (e.g. COLD vs WARM resets). As this is not properly supported, the code will almost always not do what it is intended to (because all call-sites just call reset_cpu() with 0). To avoid confusion and to clean up the codebase from unused left-overs of the past, remove the `addr` parameter entirely. Code which intends to support different kinds of resets should be rewritten as a sysreset driver instead. This transformation was done with the following coccinelle patch: @@ expression argvalue; @@ - reset_cpu(argvalue) + reset_cpu() @@ identifier argname; type argtype; @@ - reset_cpu(argtype argname) + reset_cpu(void) { ... } Signed-off-by: Harald Seiler <hws@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> |
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401d1c4f |
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30-Oct-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop asm/global_data.h from common header Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
3a187cff |
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29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
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c760095a |
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23-Oct-2020 |
Razvan Ionut Cirjan <razvanionut.cirjan@nxp.com> |
net: lx2160a.c: Update to set ECx_PMUX precedence As per hardware documentation, ECx_PMUX has precedence over SerDes protocol. For LX2160/LX2162 if DPMACs 17 and 18 are enabled as SGMII through SerDes protocol but ECx_PMUX configured them as RGMII, then the ports will be configured as RGMII and not SGMII. Signed-off-by: Razvan Ionut Cirjan <razvanionut.cirjan@nxp.com> [Rebased] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
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d31f3a1b |
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09-Sep-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2160a: fix reset sequence Make sure that SW_RST_REQ and RST_REQ_MSK are cleared before triggering hardware reset request. Signed-off-by: Thirupathaiah Annapureddy <thiruan@linux.microsoft.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
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b75d8dc5 |
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26-Jun-2020 |
Masahiro Yamada <masahiroy@kernel.org> |
treewide: convert bd_t to struct bd_info by coccinelle The Linux coding style guide (Documentation/process/coding-style.rst) clearly says: It's a **mistake** to use typedef for structures and pointers. Besides, using typedef for structures is annoying when you try to make headers self-contained. Let's say you have the following function declaration in a header: void foo(bd_t *bd); This is not self-contained since bd_t is not defined. To tell the compiler what 'bd_t' is, you need to include <asm/u-boot.h> #include <asm/u-boot.h> void foo(bd_t *bd); Then, the include direcective pulls in more bloat needlessly. If you use 'struct bd_info' instead, it is enough to put a forward declaration as follows: struct bd_info; void foo(struct bd_info *bd); Right, typedef'ing bd_t is a mistake. I used coccinelle to generate this commit. The semantic patch that makes this change is as follows: <smpl> @@ typedef bd_t; @@ -bd_t +struct bd_info </smpl> Signed-off-by: Masahiro Yamada <masahiroy@kernel.org> |
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25a5818f |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop asm/ptrace.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
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f7ae49fc |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
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90526e9f |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop net.h from common header Move this header out of the common header. Network support is used in quite a few places but it still does not warrant blanket inclusion. Note that this net.h header itself has quite a lot in it. It could be split into the driver-mode support, functions, structures, checksumming, etc. Signed-off-by: Simon Glass <sjg@chromium.org> |
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714497e3 |
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16-May-2020 |
Michael Walle <michael@walle.cc> |
efi_loader: round the memory area in efi_add_memory_map() Virtually all callers of this function do the rounding on their own. Some do it right, some don't. Instead of doing this in each caller, do the rounding in efi_add_memory_map(). Change the size parameter to bytes instead of pages and remove aligning and size calculation in all callers. There is no more need to make the original efi_add_memory_map() (which takes pages as size) available outside the module. Thus rename it to efi_add_memory_map_pg() and make it static to prevent further misuse outside the module. Signed-off-by: Michael Walle <michael@walle.cc> Add missing comma in sunxi_display.c. Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de> |
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6eb32a03 |
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23-Apr-2020 |
Madalin Bucur <madalin.bucur@oss.nxp.com> |
driver: net: fm: add DM ETH support Probe the FMan MACs based on the device tree while retaining the legacy code/functionality. One notable change introduced here is that, for DM_ETH, the name of the interfaces is corrected to the fmX-macY format, that avoids the referral to the MAC block names which were incorrect for FMan v3 devices (i.e. DTSEC, TGEC) and had weird formatting (i.e. FM1@DTSEC6, FM1@TGEC1). The legacy code is left unchanged in this respect. Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
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6ebd4883 |
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27-Apr-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
fsl-layerscape: Add RESV_RAM check in resv_ram addr The initialization of gd->arch.resv_ram pointer should depend on if the RESV_RAM config is enabled. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Wasim Khan <wasim.khan@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
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0d9d557d |
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10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
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db41d65a |
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28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move hang() to the same header as panic() At present panic() is in the vsprintf.h header file. That does not seem like an obvious choice for hang(), even though it relates to panic(). So let's put hang() in its own header. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Migrate a few more files] Signed-off-by: Tom Rini <trini@konsulko.com> |
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9b4a205f |
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28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move RAM-sizing functions to init.h These functions relate to memory init so move them into the init header. Signed-off-by: Simon Glass <sjg@chromium.org> |
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3499dd03 |
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27-Nov-2019 |
Alex Marginean <alexandru.marginean@nxp.com> |
ls1028a: Configure stream IDs for integrated PCI and fix up Linux DT Hardware comes out of reset with implicit values, but these are outside the accepted range for Layerscape gen 3 chassis spec used on LS1028A. Allocate different IDs and fix up Linux DT to use them. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
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b5981474 |
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14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some CPU functions out of common.h These functions belong in cpu_func.h since they do not use driver model. Move them over. Don't bother adding comments since these functions should be deleted. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
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68a6aa85 |
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14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move mii_init() function out of common.h This function belongs in mii.h so move it over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
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2189d5f1 |
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14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
Move strtomhz() to vsprintf.h At present this function sits in its own file but it does not really justify it. There are similar string functions in vsprintf.h, so move it there. Also add the missing function comment. Use the vsprintf.h include file explicitly where needed. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
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812ff53c |
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30-Oct-2019 |
Pankaj Bansal <pankaj.bansal@nxp.com> |
fsl-layerscape: fix warning if no hwconfig is defined While getting the 'subarg' of 'hwconfig' env variable in config_core_prefetch(), if no hwconfig variable is defined, below warning is received: WARNING: Calling __hwconfig without a buffer and before environment is ready Fix this by checking 'hwconfig' env variable. If not found return without further processing. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Tested-by: Michael Walle <michael@walle.cc> |
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28f9393b |
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17-Oct-2019 |
Mathew McBride <matt@traverse.com.au> |
fsl-layerscape: do not use layerscape EFI reset if PSCI used If the secure world reset handlers are used (via CONFIG_PSCI_RESET), then do not use the layerscape-specific implementation. Signed-off-by: Mathew McBride <matt@traverse.com.au> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
6ed69523 |
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18-Sep-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add more personalities support Add LS1027A, LS1018A and LS1017A personalities support to LS1028A SoC family. LS1028A is the prime personality of LS1028A SoC family. LS1027A is a lower funtionality version of QorIQ LS1028A which does not support the multimedia subsystems, such as LCD controller, GPU, and eDP PHY. The QorIQ LS1018A and LS1017A SoCs are single 64-bit Arm A72 core, low power versions of the QorIQ LS1028A and LS1027A SoCs respectively. Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
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0490cab5 |
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08-Aug-2019 |
Thomas Schaefer <thomas.schaefer@kontron.com> |
armv8: ls1028a: configure PMU's PCTBENR to enable WDT The SP805-WDT module on LS1028A requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. The watchdog clock needs to be enabled first. Signed-off-by: Thomas Schaefer <thomas.schaefer@kontron.com> Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
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f3998fdc |
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02-Aug-2019 |
Simon Glass <sjg@chromium.org> |
env: Rename environment.h to env_internal.h This file contains lots of internal details about the environment. Most code can include env.h instead, calling the functions there as needed. Rename this file and add a comment at the top to indicate its internal nature. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> [trini: Fixup apalis-tk1.c] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
3a7d5571 |
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01-Aug-2019 |
Simon Glass <sjg@chromium.org> |
env: Move env_get_f() to env.h Move this function over to the new header file. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
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d9532e80 |
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23-Apr-2019 |
Udit Agarwal <udit.agarwal@nxp.com> |
armv8: fsl-layerscape: Set env_loc to ENVL_NOWHERE with CONFIG_ENV_IS_NOWHERE. ENVL_NOWHERE is dependent on CONFIG_ENV_IS_NOWHERE and not on CONFIG_CHAIN_OF_TRUST so return ENVL_NOWHERE when CONFIG_ENV_IS_NOWHERE is enabled Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
059d9422 |
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08-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: lx2160a: add MMU table entries for PCIe The lx2160a have up to 6 PCIe controllers and have different address and size of PCIe region. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
8348e798 |
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08-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: layerscape: use PCIe address macro for precompile PCIe MMU entry Change to use PCIe address macro to determine if precompile the PCIe MMU table entry. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
10015025 |
|
03-May-2019 |
Trevor Woerner <trevor@toganlabs.com> |
CONFIG_SPL_SYS_[DI]CACHE_OFF: add While converting CONFIG_SYS_[DI]CACHE_OFF to Kconfig, there are instances where these configuration items are conditional on SPL. This commit adds SPL variants of these configuration items, uses CONFIG_IS_ENABLED(), and updates the configurations as required. Acked-by: Alexey Brodkin <abrodkin@synopsys.com> Signed-off-by: Trevor Woerner <trevor@toganlabs.com> [trini: Make the default depend on the setting for full U-Boot, update more zynq hardware] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
2e53759d |
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29-Oct-2018 |
Pankaj Bansal <pankaj.bansal@nxp.com> |
armv8: fsl-layerscape: reorder rgmii dpmacs' enablement some dpmacs in armv8a based freescale layerscape SOCs can be configured via both serdes(sgmii, xfi, xlaui etc) bits and via EC*_PMUX(rgmii) bits in RCW. e.g. dpmac 17 and 18 in LX2160A can be configured as SGMII from serdes bits and as RGMII via EC1_PMUX/EC2_PMUX bits Now if a dpmac is enabled by serdes bits then it takes precedence over EC*_PMUX bits. i.e. in LX2160A if we select serdes protocol that configures dpmac17 as SGMII and set the EC1_PMUX as RGMII, then the dpmac is SGMII and not RGMII. Therefore, move the fsl_rgmii_init after fsl_serdes_init. in fsl_rgmii_init function of SOC, we will check if the dpmac is enabled or not? if it is (fsl_serdes_init has already enabled the dpmac), then don't enable it. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
ec88ff80 |
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19-Dec-2018 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1043a: add SVR definitions for 23x23 package silicon LS1043A/LS1023A 23x23 package silicon has different SVR:VAR_PER. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
d23da2ae |
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26-Dec-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: fixes for TFABOOT framework Fixes for TFABOOT framework - update eMMC bootsrc to SD_MMC - Increase buffer size for mcinitcmd from 256 to 512 - Fix mcinitcmd and bootcmd for Secure Boot Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
4909b89e |
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29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
d6fdec21 |
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29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8:fsl-layerscape: Add support for Chassis 3.2 NXP layerscape architecture Chassis 3.2 builds upon chassis3 architecture with changes like DDR Memory map change, removal of IFC and support of upto 8 I2C controller. Patch add README.lsch3_2 and the above changes under macro CONFIG_NXP_LSCH3_2. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
56db948b |
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05-Nov-2018 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: Update parsing boot source Workaround of erratum A010539 clears the RCW source field in PORSR1 register, causing failure of detecting boot source using this method. Use SMC call if U-Boot runs at EL2. If SMC is not implemented or running at EL3, continue to read PORSR1 and presume QSPI as boot source if erratum workaround A010539 is enabled and RCW source is cleared. Signed-off-by: York Sun <york.sun@nxp.com> |
#
681d489e |
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05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: layerscape: add SMC calls for DDR size and bank info Adds SMC calls for getting DDR size and bank info for TFABOOT. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
2141d250 |
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05-Nov-2018 |
Pankit Garg <pankit.garg@nxp.com> |
armv8: fsl-layerscape: bootcmd identification for TFABOOT Adds bootcmd identificaton on basis on boot source, valid in TFABOOT configuration. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> [YS: remove unnecessary braces] Reviewed-by: York Sun <york.sun@nxp.com> |
#
4c417384 |
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05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com> |
#
535d76a1 |
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05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: layerscape: Add TFABOOT support Adds TFABOOT support config option and add generic code to enable execution from DDR. Signed-off-by: York Sun <york.sun@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> |
#
e3506480 |
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05-Nov-2018 |
Pankit Garg <pankit.garg@nxp.com> |
armv8: fsl-layerscape: change tlb base from OCRAM to DDR in EL < 3 Change tlb base address from OCRAM to DDR when exception level is less than 3. Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
d171c707 |
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05-Nov-2018 |
York Sun <york.sun@nxp.com> |
move data structure out of cpu.h Move static definitions to cpu.c file, as it doesn't allow the cpu.h file to be included in multiple c files. Signed-off-by: York Sun <york.sun@nxp.com> |
#
9b5e6396 |
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30-Aug-2018 |
Stephen Warren <swarren@nvidia.com> |
efi_loader: simplify ifdefs Use CONFIG_IS_ENABLED(EFI_LOADER) to avoid explicitly checking CONFIG_SPL too. This simplifies the conditional. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Alexander Graf <agraf@suse.de> |
#
9cce5663 |
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16-Jul-2018 |
Joe Hershberger <joe.hershberger@ni.com> |
arm: Prevent redefinition error in fsl-layerscape The include/phy.h will start including dm.h, which pulls in linux/compat.h after the attempted redefinition in arch/arm/include/asm/armv8/mmu.h, so move this include to allow redefinition. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> |
#
83d290c5 |
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06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
482fc90c |
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06-Feb-2018 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
efi_loader: add missing EFI_RESET_PLATFORM_SPECIFIC EFI_RESET_PLATFORM_SPECIFIC is one of the values that can be used for the EFI service ResetSystem. The missing definition is added. The value has to handled in efi_reset_system(). Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Alexander Graf <agraf@suse.de> |
#
22c793e6 |
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03-Mar-2018 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
efi_loader: exit status for efi_reset_system_init efi_reset_system_init provides the architecture or board specific initialization of the EFI subsystem. Errors should be caught and signalled by a return code. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Alexander Graf <agraf@suse.de> |
#
958b2ed5 |
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09-Jan-2018 |
Zhang Ying-22455 <ying.zhang22455@nxp.com> |
armv8/ls1088a: configure PMU's PCTBENR to enable WDT The SP805-WDT module on LS1088A requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. The watchdog clock needs to be enabled first. Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
44262327 |
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15-Dec-2017 |
Ahmed Mansour <ahmed.mansour@nxp.com> |
drivers/misc: Share qbman init between archs This patch adds changes necessary to move functionality present in PowerPC folders with ARM architectures that have DPAA1 QBMan hardware - Create new board/freescale/common/fsl_portals.c to house shared device tree fixups for DPAA1 devices with ARM and PowerPC cores - Add new header file to top includes directory to allow files in both architectures to grab the function prototypes - Port inhibit_portals() from PowerPC to ARM. This function is used in setup to disable interrupts on all QMan and BMan portals. It is needed because the interrupts are enabled by default for all portals including unused/uninitialised portals. When the kernel attempts to go to deep sleep the unused portals prevent it from doing so Signed-off-by: Ahmed Mansour <ahmed.mansour@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
a8f33034 |
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03-Dec-2017 |
Wenbin song <wenbin.song@nxp.com> |
armv8: ls1043a/ls2080a: check SoC by device ID Check LS1043A/LS2080a by device ID without using personality ID to determine revision number. This check applies to all various personalities of the same SoC family. Signed-off-by: Wenbin Song <wenbin.song@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
2db53cfe |
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09-Nov-2017 |
Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
armv8: fsl-layerscape: Add support of disabling core prefetch Instruction prefetch feature is by default enabled during core release. This patch add support of disabling instruction prefetch by setting core mask in PPA. Here each core mask bit represents a core and prefetch is disabled at the time of core release. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
7eb40f0f |
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28-Sep-2017 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: Avoid running dram_init_banksize again gd->ram_size is reduced in this function to reserve secure memory. Avoid running this function again to further reduce memory size. This fixes issue for SPL boot with PPA image loaded in which case secure memory is incorrectly allocated due to repeated calling. Signed-off-by: York Sun <york.sun@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
710d0cd7 |
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03-Oct-2017 |
Sumit Garg <sumit.garg@nxp.com> |
armv8: fsl-layerscape: Allocate Secure memory from first ddr region This change is required due to trusted OS (OP-TEE) not being position independent code, it requires compile time fixed base address. To take care of this it is assumed that all layerscape armv8 platforms has minimum 2G ddr in first region. So we can have fixed address space (66 MB -> (2MB for PPA + 64MB for trusted OS)) allocated from top of first 2G ddr region and compile trusted OS with this fixed base address. But one exception here is ls1012 where we have only 1G (rdb) or 512M (frdm) ddr memory. For those we can have different fixed compile time base addresses for trusted OS. Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
e9303a41 |
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07-Sep-2017 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: Fix MC reserved memory calculation In case high region memory doesn't have enough space for Management Complex (MC), the return value should indicate a failure so the caller can handle it accordingly. Signed-off-by: York Sun <york.sun@nxp.com> Reported-by: Ebony Zhu <ebony.zhu@nxp.com> |
#
17d066fc |
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31-Aug-2017 |
Ashish Kumar <Ashish.Kumar@nxp.com> |
armv8: fsl-layerscape: Support to add RGMII for ls1088aqds This patch adds support for RGMII protocol NXP's LDPAA2 support RGMII protocol. LS1088A is the first Soc supporting both RGMII and SGMII. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Amrita Kumari <amrita.kumari@nxp.com> Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
63b2316c |
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10-Aug-2017 |
Ashish Kumar <Ashish.Kumar@nxp.com> |
fsl-layerscape: Consolidate registers space defination for CCI-400 bus CoreLink Cache Coherent Interconnect (CCI) provides full cache coherency between two clusters of multi-core CPUs and I/O coherency for devices and I/O masters. This patch add new config option SYS_FSL_HAS_CCI400 and moves existing register space definaton of CCI-400 bus to fsl_immap to be shared. CONFIG_SYS_CCI400_ADDR is replaced with SYS_CCI400_OFFSET in Kconfig. Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> [YS: revised commit message, squashed patches for armv8 and armv7] Reviewed-by: York Sun <york.sun@nxp.com> |
#
6e2941d7 |
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17-May-2017 |
Simon Glass <sjg@chromium.org> |
common: freescale: Move arch-specific declarations The declarations should not be in common.h. Move them to the arch-specific headers. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Fixup thinko defined(FSL_LSCH3) -> defined(CONFIG_FSL_LSCH3)] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
399e2bb6 |
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15-May-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Make U-Boot EL2 safe When U-Boot boots from EL2, skip some lowlevel init code requiring EL3, including CCI-400/CCN-504, trust zone, GIC, etc. These initialization tasks are carried out before U-Boot runs. This applies to the RAM version image used for SPL boot if PPA is loaded first. Signed-off-by: York Sun <york.sun@nxp.com> |
#
1f55a938 |
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05-May-2017 |
Santan Kumar <santan.kumar@nxp.com> |
armv8: ls2080aqds: Add support for SD boot Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
e809e747 |
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27-Apr-2017 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: fsl-layerscape: Add NXP LS2081A, LS2041A SoC support The QorIQ LS2081A SoC has eight 64-bit ARM v8 Cortex A72 cores and is built on layerscape architecture. It is 40-pin derivative of LS2084A (non-AIOP personality of LS2088A). So feature-wise it is same as LS2084A. LS2041A is a 4-core personality of LS2081A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
026f30ec |
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18-Apr-2017 |
Yuantian Tang <andy.tang@nxp.com> |
arm: psci: make psci usable on single core socs PSCI can be used on both multiple and single core socs. Current implementation only allows PSCI to work on multiple core socs. This patch removes this restriction so that PSCI can work on single core socs as well. Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
4a3ab193 |
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27-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: ls2080a: Drop macro CONFIG_LS2080A Use CONFIG_ARCH_LS2080A instead. Signed-off-by: York Sun <york.sun@nxp.com> |
#
3eace37e |
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06-Apr-2017 |
Simon Glass <sjg@chromium.org> |
arm: freescale: Rename initdram() to fsl_initdram() This function name shadows a global name but is in fact different. This is very confusing. Rename it to help with the following refactoring. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
76b00aca |
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31-Mar-2017 |
Simon Glass <sjg@chromium.org> |
board_f: Drop setup_dram_config() wrapper By making dram_init_banksize() return an error code we can drop the wrapper. Adjust this and clean up all implementations. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
088454cd |
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31-Mar-2017 |
Simon Glass <sjg@chromium.org> |
board_f: Drop return value from initdram() At present we cannot use this function as an init sequence call without a wrapper, since it returns the RAM size. Adjust it to set the RAM size in global_data instead, and return 0 on success. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
52c41180 |
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31-Mar-2017 |
Simon Glass <sjg@chromium.org> |
board_f: Drop board_type parameter from initdram() It looks like only cm5200 and tqm8xx use this feature, so we don't really need it in generic code. Drop it and have the users access gd->board_type directly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
3d8553f0 |
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02-Mar-2017 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
pci: layerscape: add LS2088A series SoC pcie support The LS2088A series SoCs has different physical memory map address and CCSR registers address against LS2080A series SoCs. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
eea1cb77 |
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13-Feb-2017 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8/fsl-layerscape: Update erratum A009635 implementation Erratum A009635 is valid only for LS2080A SoC and its personality. Add SoC svr check. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
4961eafc |
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06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Update early MMU for DDR after initialization In early MMU table, DDR has to be mapped as device memory to avoid speculative access. After DDR is initialized, it needs to be updated to normal memory to allow code execution. To simplify the code, dram_init() is moved into a common file as a weak function. Signed-off-by: York Sun <york.sun@nxp.com> |
#
a045a0c3 |
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06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Fix the sequence of changing MMU table This patch follows the break-before-make process when making changes to MMU table. MMU is disabled before changing TTBR to avoid any potential race condition. Signed-off-by: York Sun <york.sun@nxp.com> |
#
24f55496 |
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06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Update MMU mapping with actual DDR size Update mapping with actual DDR size. Non-existing memory should not be mapped as "normal" memory to avoid speculative access. Signed-off-by: York Sun <york.sun@nxp.com> |
#
36cc0de0 |
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06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Rewrite memory reservation For ARMv8 Layerscape SoCs, secure memory and MC memorey are reserved at the end of DDR. DDR is spit into two or three banks. This patch reverts commit aabd7ddb and simplifies the calculation of reserved memory, and moves the code into common SoC file. Secure memory is carved out first. DDR bank size is reduced. Reserved memory is then allocated on the top of available memory. U-Boot still has access to reserved memory as data transferring is needed. Device tree is fixed with reduced memory size to hide the reserved memory from OS. The same region is reserved for efi_loader. Signed-off-by: York Sun <york.sun@nxp.com> |
#
daa92644 |
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16-Jan-2017 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
ARMv8/sec_firmware: relocated and renamed the config FSL_PPA_ARMV8_PSCI Moved the config FSL_PPA_ARMV8_PSCI from fsl-layerscape's Kconfig to Kconfig under armv8 and renamed it to SEC_FIRMWARE_ARMV8_PSCI. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
904110c7 |
|
10-Jan-2017 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8/fsl-lsch2: refactor the clock system initialization Up to now, there are 3 kind of SoCs under Layerscape Chassis 2, like LS1043A, LS1046A and LS1012A. But the clocks tree has a lot of differences, for instance, the IP modules have different dividers to derive its clock from Platform PLL. And the core cluster PLL and platform PLL maybe have different reference clocks, such as LS1012A. Another problem is which clock/PLL should be described by sys_info->freq_systembus, it is confused in Layerscape Chissis 2. This patch is to bind the sys_info->freq_systembus to the Platform PLL, and handle the different divider of IP modules separately between different SoCs, and separate reference clocks of core cluster PLL and platform PLL. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
2d16a1a6 |
|
07-Dec-2016 |
macro.wave.z@gmail.com <macro.wave.z@gmail.com> |
ARMv8: LS1043A: change macro CONFIG_ARMV8_PSCI definition NXP/Freescale uses macro CONFIG_ARMV8_PSCI to enable their private PSCI implementation in PPA firmware, but this macro naming too generic, so this patch replaces it with a specic one CONFIG_FSL_PPA_ARMV8_PSCI. And this macro CONFIG_ARMV8_PSCI will be used for a generic PSCI for ARMv8 which will be added in following patchs. Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
02fb2761 |
|
20-Nov-2016 |
Shengzhou Liu <Shengzhou.Liu@nxp.com> |
fsl/ddr: Add erratum_a009942_check_cpo and clean related erratum - add additional function erratum_a009942_check_cpo to check if the board needs tuning CPO calibration for optimal setting. - move ERRATUM_A009942(with revision to check cpo_sample option) from fsl_ddr_gen4.c to ctrl_regs.c for reuse on all DDR4/DDR3 parts. - move ERRATUM_A008378 from fsl_ddr_gen4.c to ctrl_regs.c - remove obsolete ERRATUM_A004934 which is replaced with ERRATUM_A009942. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> [YS: Replaced CONFIG_QEMU_E500 with CONFIG_ARCH_QEMU_E500] Reviewed-by: York Sun <york.sun@nxp.com> |
#
e87c673c |
|
16-Nov-2016 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8/fsl-lsch3: Update code to release secondary cores NXP ARMv8 SoC LS2080A release all secondary cores in one-go. But other new SoCs like LS2088A, LS1088A release secondary cores one by one. Update code to release secondary cores based on SoC SVR Add code to release cores one by one for non LS2080A SoCs Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> [YS: remove "inline" from declaration of initiator_type] Reviewed-by: York Sun <york.sun@nxp.com> |
#
f6b96ff6 |
|
16-Nov-2016 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Use SVR based timer base address detection Timer controller base address has been changed from LS2080A SoC (and its personalities) to new SoCs like LS2088A, LS1088A. Use SVR based timer base address detection to avoid compile time #ifdef. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
f6a70b3a |
|
16-Nov-2016 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add generic get_svr() in assembly Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
78d57842 |
|
16-Nov-2016 |
Alexander Graf <agraf@csgraf.de> |
armv8: fsl-layerscape: Add support for efi_loader RTS reset When implementing efi loader support, we can expose runtime services for payloads. One such service is CPU reset. This patch implements RTS CPU reset support for layerscape systems. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: York Sun <york.sun@nxp.com> |
#
ef9a5fd8 |
|
13-Sep-2016 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: Fix "cpu status" command The core position is not continuous for some SoCs. For example, valid cores may present at position 0, 1, 4, 5, 8, 9, etc. Some registers (including boot release register) only count existing cores. Current implementation of cpu_mask() complies with the continuous numbering. However, command "cpu status" queries the spin table with actual core position. Add functions to calculate core position from core number, to correctly calculate offsets. Tested on LS2080ARDB and LS1043ARDB. Signed-off-by: York Sun <york.sun@nxp.com> |
#
5d1a7a9d |
|
13-Sep-2016 |
Wenbin Song <wenbin.song@nxp.com> |
armv8/fsl-layerscape: print SoC revsion number The exact SoC revsion number can be recognized from U-Boot log. Signed-off-by: Wenbin Song <wenbin.song@nxp.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
cbe7706a |
|
26-Sep-2016 |
Tom Rini <trini@konsulko.com> |
Merge git://git.denx.de/u-boot-fsl-qoriq trini: Drop local memset() from examples/standalone/mem_to_mem_idma2intr.c Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
1221ce45 |
|
20-Sep-2016 |
Masahiro Yamada <masahiroy@kernel.org> |
treewide: replace #include <asm/errno.h> with <linux/errno.h> Now, arch/${ARCH}/include/asm/errno.h and include/linux/errno.h have the same content. (both just wrap <asm-generic/errno.h>) Replace all include directives for <asm/errno.h> with <linux/errno.h>. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> [trini: Fixup include/clk.] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
b63a9506 |
|
03-Aug-2016 |
York Sun <york.sun@nxp.com> |
armv8: ls2080a: Remove debug server support Debug server feature has been dropped from roadmap. Signed-off-by: York Sun <york.sun@nxp.com> |
#
ed7a3943 |
|
22-Jul-2016 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: mmu: Fix enabling MMU MMU bit in SCTLR needs to be set explicitly after tables are created. It isn't an issue for EL3 becuase this bit is already set by early MMU setup. But for other exception levels this bit was not set. Signed-off-by: York Sun <york.sun@nxp.com> |
#
79119a4d |
|
05-Jul-2016 |
Alison Wang <b18965@freescale.com> |
armv8: fsl-layerscape: Add A72 core detection Add support to detect Cortex-A72 core for printing it out. The Initiator Version of A72 core should be 0x4. Signed-off-by: Alison Wang <alison.wang@nxp.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
032d5bb4 |
|
28-Jun-2016 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
ARMv8/Layerscape: switch SMP method accordingly If the PSCI and PPA is ready, skip the fixup for spin-table and waking secondary cores. Otherwise, change SMP method to spin-table, and the device node of PSCI will be removed. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
85cdf38e |
|
28-Jun-2016 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: fsl-layerscape: add i/d-cache enable function to enable_caches This function assume that the d-cache and MMU has been enabled earlier, so it just created MMU table in main memory. But the assumption is not always correct, for example, the early setup is done in EL3, while enable_caches() is called when the PE has turned into another EL. Define the function mmu_setup() for fsl-layerscape to cover the weak one. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
5ad5823d |
|
24-Jun-2016 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Convert to use common MMU framework Drop platform code to create static MMU tables. Use common framework to create MMU tables on the run. Tested on LS2080ARDB with secure and non-secure ram scenarios. Signed-off-by: York Sun <york.sun@nxp.com> |
#
e61a7534 |
|
24-Jun-2016 |
York Sun <york.sun@nxp.com> |
armv8: Move secure_ram variable out of generic global data Secure_ram variable was put in generic global data. But only ARMv8 uses this variable. Move it to ARM specific data structure. Signed-off-by: York Sun <york.sun@nxp.com> |
#
a10a31ec |
|
18-Jun-2016 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of git://git.denx.de/u-boot-usb Signed-off-by: Tom Rini <trini@konsulko.com> Conflicts: arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
|
#
6fb522dc |
|
12-Jun-2016 |
Sriram Dash <sriram.dash@nxp.com> |
arm64: fsl-layerscape: add get_svr and IS_SVR_REV helper Adds get_svr and IS_SVR_REV helpers for ARMv8 platforms, similar to PPC and ARMv7. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> |
#
a758177f |
|
07-Jun-2016 |
Yunhui Cui <yunhui.cui@nxp.com> |
armv8/ls2080a: configure PMU's PCTBENR to enable WDT The SP805-WDT module on LS2080A requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. The watchdog clock needs to be enabled first. Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
acb8f5e9 |
|
21-Apr-2016 |
Alison Wang <b18965@freescale.com> |
armv8: fsl-layerscape: Remove unnecessary flushing dcache As the issue about the stack will get corrupted when switching between the early and final mmu tables is fixed by commit 70e21b064, the workaround to flush dcache is unnecessary and should be removed. Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
3c1d218a |
|
04-Apr-2016 |
York Sun <york.sun@nxp.com> |
armv8: LS2080A: Consolidate LS2080A and LS2085A LS2080A is the primary SoC, and LS2085A is a personality with AIOP and DPAA DDR. The RDB and QDS boards support both personality. By detecting the SVR at runtime, a single image per board can support both SoCs. It gives users flexibility to swtich SoC without the need to reprogram the board. Signed-off-by: York Sun <york.sun@nxp.com> CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
c05016ab |
|
21-Mar-2016 |
Alexander Graf <agraf@csgraf.de> |
arm64: Fix layerscape mmu setup With commit 7985cdf we converted all systems except for the Layerscape SoCs to the generic descriptor table based page table setup. On the Layerscape SoCs however, we just provide an empty table stub and do the setup ourselves. To reserve enough memory for the tables, we need to override the default counting mechanism which would end up with an empty table because we have no maps. Fixes: 7985cdf Reported-by: York Sun <york.sun@nxp.com> CC: Alison Wang <alison.wang@nxp.com> CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Alexander Graf <agraf@suse.de> Tested-by: York Sun <york.sun@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
7985cdf7 |
|
03-Mar-2016 |
Alexander Graf <agraf@csgraf.de> |
arm64: Remove non-full-va map code By now the code to only have a single page table level with 64k page size and 42 bit address space is no longer used by any board in tree, so we can safely remove it. To clean up code, move the layerscape mmu code to the new defines, removing redundant field definitions. Signed-off-by: Alexander Graf <agraf@suse.de> |
#
c0492141 |
|
07-Dec-2015 |
York Sun <yorksun@freescale.com> |
armv8: fsl-layerscale: Rewrite reserving memory for MC and debug server MC and debug server are not board-specific. Move reserving memory to SoC file, using the new board_reserve_ram_top function. Reduce debug server memory by 2MB to make room for secure memory. In the system with MC and debug server, the top of u-boot memory is not the end of memory. PRAM is not used for this reservation. Signed-off-by: York Sun <yorksun@freescale.com> |
#
c107c0c0 |
|
04-Dec-2015 |
York Sun <yorksun@freescale.com> |
armv8: fsl-layerscape: Make DDR non secure in MMU tables DDR has been set as secure in MMU tables. Non-secure master such as SDHC DMA cannot access data correctly. Mixing secure and non- secure MMU entries requirs the MMU tables themselves in secure memory. This patch moves MMU tables into a secure DDR area. Early MMU tables are changed to set DDR as non-secure. A new table is added into final MMU tables so secure memory can have 2MB granuality. gd->secure_ram tracks the location of this secure memory. For ARMv8 SoCs, the RAM base is not zero and RAM is divided into several banks. gd->secure_ram needs to be maintained before using. This maintenance is board-specific, depending on the SoC and memory bank of the secure memory falls into. Signed-off-by: York Sun <yorksun@freescale.com> |
#
b4017364 |
|
04-Nov-2015 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
armv8: ls2085a: Add workaround of errata A009635 If the core runs at higher than x3 speed of the platform, there is possiblity about sev instruction to getting missed by other cores. This is because of SoC Run Control block may not able to sample the EVENTI(Sev) signals. Configure Run Control and EPU to periodically send out EVENTI signals to wake up A57 cores. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
d764129d |
|
04-Nov-2015 |
Alison Wang <b18965@freescale.com> |
armv8/layerscape: Update MMU table with execute-never bits For most device addresses excution shouldn't be allowed. Revise the MMU table to enforce execute-never bits. OCRAM, DDR and IFC are allowed for excution. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Alison Wang <alison.wang@freescale.com> Reported-by: Zhichun Hua <zhichun.hua@freescale.com> |
#
44937214 |
|
09-Nov-2015 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
armv8: LS2080A: Rename LS2085A to reflect LS2080A LS2080A is a prime personality of Freescale’s LS2085A. It is a non-AIOP personality without support of DP-DDR, L2 switch, 1588, PCIe endpoint etc. So renaming existing LS2085A code base to reflect LS2080A (Prime personality) Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> [York Sun: Dropped #ifdef in cpu.c for cpu_type_list] Reviewed-by: York Sun <yorksun@freescale.com> |
#
e8297341 |
|
26-Oct-2015 |
Shaohui Xie <Shaohui.Xie@freescale.com> |
armv8/ls1043a: Add Fman support Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
8281c58f |
|
26-Oct-2015 |
Mingkai Hu <Mingkai.Hu@freescale.com> |
armv8/fsl_lsch2: Add fsl_lsch2 SoC Freescale LayerScape with Chassis Generation 2 is a set of SoCs with ARMv8 cores and 2rd generation of Chassis. Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
9f3183d2 |
|
26-Oct-2015 |
Mingkai Hu <Mingkai.Hu@freescale.com> |
armv8/fsl_lsch3: Change arch to fsl-layerscape There are two LS series processors are built on ARMv8 Layersacpe architecture currently, LS2085A and LS1043A. They are based on ARMv8 core although use different chassis, so create fsl-layerscape to refactor the common code for the LS series processors which also paves the way for adding LS1043A platform. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
935b60f8 |
|
30-Apr-2024 |
Tom Rini <trini@konsulko.com> |
arm: fsl-layerscape: Remove <common.h> and add needed includes Remove <common.h> from all fsl-layerscape related files and when needed add missing include files directly. Acked-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
e7ec875d |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of SYS_FSL_ERRATUM_A010539 This converts 1 usage of this option to the non-SPL form, since there is no SPL_SYS_FSL_ERRATUM_A010539 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> |
#
6e7df1d1 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
global: Finish CONFIG -> CFG migration At this point, the remaining places where we have a symbol that is defined as CONFIG_... are in fairly odd locations. While as much dead code has been removed as possible, some of these locations are simply less obvious at first. In other cases, this code is used, but was defined in such a way as to have been missed by earlier checks. Perform a rename of all such remaining symbols to be CFG_... rather than CONFIG_... Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
1d457dbb |
|
04-Dec-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_MAX_MEM_MAPPED to CFG Perform a simple rename of CONFIG_MAX_MEM_MAPPED to CFG_MAX_MEM_MAPPED Signed-off-by: Tom Rini <trini@konsulko.com> |
#
4fd9373b |
|
02-Dec-2022 |
Tom Rini <trini@konsulko.com> |
net: Remove more legacy functions Remove some of the board and arch specific non-DM_ETH helper code. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
ecc8d425 |
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16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_PCI* to CFG_SYS_PCI* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_PCI and CONFIG_SYS_PCIE namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
8fd11135 |
|
25-Sep-2022 |
Sean Anderson <sean.anderson@seco.com> |
arm64: layerscape: Support SYSRESET CONFIG_SYSRESET provides its own implementation of reset_cpu. Disable our version when it is enabled. Signed-off-by: Sean Anderson <sean.anderson@seco.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> |
#
ce9c579e |
|
13-Jun-2022 |
Andre Przywara <andre.przywara@arm.com> |
armv8: always use current exception level for TCR_ELx access Currently get_tcr() takes an "el" parameter, to select the proper version of the TCR_ELx system register. This is problematic in case of the Apple M1, since it runs with HCR_EL2.E2H fixed to 1, so TCR_EL2 is actually using the TCR_EL1 layout, and we get the wrong version. For U-Boot's purposes the only sensible choice here is the current exception level, and indeed most callers treat it like that, so let's remove that parameter and read the current EL inside the function. This allows us to check for the E2H bit, and pretend it's EL1 in this case. There are two callers which don't care about the EL, and they pass 0, which looks wrong, but is irrelevant in these two cases, since we don't use the return value there. So the change cannot affect those two. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Mark Kettenis <kettenis@openbsd.org> Tested-by: Mark Kettenis <kettenis@openbsd.org> |
#
cda8f873 |
|
11-May-2022 |
Ye Li <ye.li@nxp.com> |
caam: Fix crash in case caam_jr_probe failed If probing caam_jr returns failure, the variable "dev" will not be initialized, so we can't use dev->name for the error print. Otherwise it will cause crash. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Gaurav Jain <gaurav.jain@nxp.com> |
#
cb14cc88 |
|
22-Apr-2022 |
Michael Walle <michael@walle.cc> |
armv8: layerscape: get rid of smc_call() There are two different implementations to do a secure monitor call: smc_call() and arm_smccc_smc(). The former is defined in fwcall.c and seems to be an ad-hoc implementation. The latter is imported from linux. smc_call() is also only available if CONFIG_ARMV8_PSCI is not defined. This makes it impossible to have both PSCI calls and PSCI implementation in one u-boot build. The layerscape SoC code decide at runtime via check_psci() if there is a PSCI support. Therefore, this is a prerequisite patch to add PSCI implementation support for the layerscape SoCs. Note, for the TFA part, this is only compile time tested with (ls1028ardb_tfa_defconfig). Signed-off-by: Michael Walle <michael@walle.cc> [Rebased] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
dfb6da55 |
|
05-Apr-2022 |
Marek Vasut <marex@denx.de> |
armv8: layerscape: env: Switch to arch_env_get_location() Implement arch_env_get_location() instead of env_get_location(), so that the env_get_location() can be implemented on board level and override the arch_env_get_location() architecture defaults. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Adam Ford <aford173@gmail.com> Cc: Fabio Estevam <festevam@denx.de> Cc: Marek Behún <marek.behun@nic.cz> Cc: Peng Fan <peng.fan@nxp.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefano Babic <sbabic@denx.de> Cc: Tim Harvey <tharvey@gateworks.com> Cc: Tom Rini <trini@konsulko.com> Cc: Tommaso Merciai <tomm.merciai@gmail.com> Cc: Vladimir Oltean <vladimir.oltean@nxp.com> |
#
8976556a |
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24-Mar-2022 |
Gaurav Jain <gaurav.jain@nxp.com> |
Layerscape: Enable Job ring driver model. LS(1021/1012/1028/1043/1046/1088/2088), LX2160, LX2162 platforms are enabled with JR driver model. removed sec_init() call from board files. sec is initialized based on job ring information processed from device tree. Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Michael Walle <michael@walle.cc> |
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f9147d63 |
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25-Feb-2022 |
Tom Rini <trini@konsulko.com> |
Convert CONFIG_CHIP_SELECTS_PER_CTRL to Kconfig This converts the following to Kconfig: CONFIG_CHIP_SELECTS_PER_CTRL Cc: Alison Wang <alison.wang@nxp.com> Cc: Pramod Kumar <pramod.kumar_1@nxp.com> Cc: Priyanka Jain <priyanka.jain@nxp.com> Cc: Rajesh Bhagat <rajesh.bhagat@nxp.com> Cc: Vladimir Oltean <olteanv@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
2f8a6db5 |
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14-Dec-2021 |
Tom Rini <trini@konsulko.com> |
Finish conversion of CONFIG_SYS_CLK_FREQ to Kconfig In order to finish moving this symbol to Kconfig for all platforms, we need to do a few more things. First, for all platforms that define this to a function, introduce CONFIG_DYNAMIC_SYS_CLK_FREQ, similar to CONFIG_DYNAMIC_DDR_CLK_FREQ and populate clock_legacy.h. This entails also switching all users from CONFIG_SYS_CLK_FREQ to get_board_sys_clk() and updating a few preprocessor tests. With that done, all platforms that define a value here can be converted to Kconfig, and a fall-back of zero is sufficiently safe to use (and what is used today in cases where code may or may not have this available). Make sure that code which calls this function includes <clock_legacy.h> to get the prototype. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
77b11f76 |
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18-Sep-2021 |
Vladimir Oltean <vladimir.oltean@nxp.com> |
net: replace the "xfi" phy-mode with "10gbase-r" As part of the effort of making U-Boot work with the same device tree as Linux, there is an issue with the "xfi" phy-mode. To be precise, in Linux there was a discussion (for those who have time to read: https://lore.kernel.org/netdev/1576768881-24971-2-git-send-email-madalin.bucur@oss.nxp.com/) which led to a patch: https://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next.git/commit/?id=c114574ebfdf42f826776f717c8056a00fa94881 TL;DR: "xfi" was standardized in Linux as "10gbase-r". This patch changes the relevant occurrences in U-Boot to use "10gbase-r" instead of "xfi" wherever applicable. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> |
#
84c2e044 |
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20-Apr-2021 |
Jiafei Pan <Jiafei.Pan@nxp.com> |
armv8: layerscape: add PSCI support for cpu release For cpu release command, check whether PSCI is supported firstly, if supported, use PSCI to kick off secondary cores, otherwise still use spin table. Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com> [Fixed checkpatch alignment CHECKs] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
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35b65dd8 |
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15-Dec-2020 |
Harald Seiler <hws@denx.de> |
reset: Remove addr parameter from reset_cpu() Historically, the reset_cpu() function had an `addr` parameter which was meant to pass in an address of the reset vector location, where the CPU should reset to. This feature is no longer used anywhere in U-Boot as all reset_cpu() implementations now ignore the passed value. Generic code has been added which always calls reset_cpu() with `0` which means this feature can no longer be used easily anyway. Over time, many implementations seem to have "misunderstood" the existence of this parameter as a way to customize/parameterize the reset (e.g. COLD vs WARM resets). As this is not properly supported, the code will almost always not do what it is intended to (because all call-sites just call reset_cpu() with 0). To avoid confusion and to clean up the codebase from unused left-overs of the past, remove the `addr` parameter entirely. Code which intends to support different kinds of resets should be rewritten as a sysreset driver instead. This transformation was done with the following coccinelle patch: @@ expression argvalue; @@ - reset_cpu(argvalue) + reset_cpu() @@ identifier argname; type argtype; @@ - reset_cpu(argtype argname) + reset_cpu(void) { ... } Signed-off-by: Harald Seiler <hws@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> |
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401d1c4f |
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30-Oct-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop asm/global_data.h from common header Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com> |
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3a187cff |
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29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
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c760095a |
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23-Oct-2020 |
Razvan Ionut Cirjan <razvanionut.cirjan@nxp.com> |
net: lx2160a.c: Update to set ECx_PMUX precedence As per hardware documentation, ECx_PMUX has precedence over SerDes protocol. For LX2160/LX2162 if DPMACs 17 and 18 are enabled as SGMII through SerDes protocol but ECx_PMUX configured them as RGMII, then the ports will be configured as RGMII and not SGMII. Signed-off-by: Razvan Ionut Cirjan <razvanionut.cirjan@nxp.com> [Rebased] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
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d31f3a1b |
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09-Sep-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2160a: fix reset sequence Make sure that SW_RST_REQ and RST_REQ_MSK are cleared before triggering hardware reset request. Signed-off-by: Thirupathaiah Annapureddy <thiruan@linux.microsoft.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
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b75d8dc5 |
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26-Jun-2020 |
Masahiro Yamada <masahiroy@kernel.org> |
treewide: convert bd_t to struct bd_info by coccinelle The Linux coding style guide (Documentation/process/coding-style.rst) clearly says: It's a **mistake** to use typedef for structures and pointers. Besides, using typedef for structures is annoying when you try to make headers self-contained. Let's say you have the following function declaration in a header: void foo(bd_t *bd); This is not self-contained since bd_t is not defined. To tell the compiler what 'bd_t' is, you need to include <asm/u-boot.h> #include <asm/u-boot.h> void foo(bd_t *bd); Then, the include direcective pulls in more bloat needlessly. If you use 'struct bd_info' instead, it is enough to put a forward declaration as follows: struct bd_info; void foo(struct bd_info *bd); Right, typedef'ing bd_t is a mistake. I used coccinelle to generate this commit. The semantic patch that makes this change is as follows: <smpl> @@ typedef bd_t; @@ -bd_t +struct bd_info </smpl> Signed-off-by: Masahiro Yamada <masahiroy@kernel.org> |
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25a5818f |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop asm/ptrace.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
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f7ae49fc |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
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90526e9f |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop net.h from common header Move this header out of the common header. Network support is used in quite a few places but it still does not warrant blanket inclusion. Note that this net.h header itself has quite a lot in it. It could be split into the driver-mode support, functions, structures, checksumming, etc. Signed-off-by: Simon Glass <sjg@chromium.org> |
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714497e3 |
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16-May-2020 |
Michael Walle <michael@walle.cc> |
efi_loader: round the memory area in efi_add_memory_map() Virtually all callers of this function do the rounding on their own. Some do it right, some don't. Instead of doing this in each caller, do the rounding in efi_add_memory_map(). Change the size parameter to bytes instead of pages and remove aligning and size calculation in all callers. There is no more need to make the original efi_add_memory_map() (which takes pages as size) available outside the module. Thus rename it to efi_add_memory_map_pg() and make it static to prevent further misuse outside the module. Signed-off-by: Michael Walle <michael@walle.cc> Add missing comma in sunxi_display.c. Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de> |
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6eb32a03 |
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23-Apr-2020 |
Madalin Bucur <madalin.bucur@oss.nxp.com> |
driver: net: fm: add DM ETH support Probe the FMan MACs based on the device tree while retaining the legacy code/functionality. One notable change introduced here is that, for DM_ETH, the name of the interfaces is corrected to the fmX-macY format, that avoids the referral to the MAC block names which were incorrect for FMan v3 devices (i.e. DTSEC, TGEC) and had weird formatting (i.e. FM1@DTSEC6, FM1@TGEC1). The legacy code is left unchanged in this respect. Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
6ebd4883 |
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27-Apr-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
fsl-layerscape: Add RESV_RAM check in resv_ram addr The initialization of gd->arch.resv_ram pointer should depend on if the RESV_RAM config is enabled. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Wasim Khan <wasim.khan@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
0d9d557d |
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10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
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db41d65a |
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28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move hang() to the same header as panic() At present panic() is in the vsprintf.h header file. That does not seem like an obvious choice for hang(), even though it relates to panic(). So let's put hang() in its own header. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Migrate a few more files] Signed-off-by: Tom Rini <trini@konsulko.com> |
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9b4a205f |
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28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move RAM-sizing functions to init.h These functions relate to memory init so move them into the init header. Signed-off-by: Simon Glass <sjg@chromium.org> |
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3499dd03 |
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27-Nov-2019 |
Alex Marginean <alexandru.marginean@nxp.com> |
ls1028a: Configure stream IDs for integrated PCI and fix up Linux DT Hardware comes out of reset with implicit values, but these are outside the accepted range for Layerscape gen 3 chassis spec used on LS1028A. Allocate different IDs and fix up Linux DT to use them. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
b5981474 |
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14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some CPU functions out of common.h These functions belong in cpu_func.h since they do not use driver model. Move them over. Don't bother adding comments since these functions should be deleted. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
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68a6aa85 |
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14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move mii_init() function out of common.h This function belongs in mii.h so move it over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
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2189d5f1 |
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14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
Move strtomhz() to vsprintf.h At present this function sits in its own file but it does not really justify it. There are similar string functions in vsprintf.h, so move it there. Also add the missing function comment. Use the vsprintf.h include file explicitly where needed. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
812ff53c |
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30-Oct-2019 |
Pankaj Bansal <pankaj.bansal@nxp.com> |
fsl-layerscape: fix warning if no hwconfig is defined While getting the 'subarg' of 'hwconfig' env variable in config_core_prefetch(), if no hwconfig variable is defined, below warning is received: WARNING: Calling __hwconfig without a buffer and before environment is ready Fix this by checking 'hwconfig' env variable. If not found return without further processing. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Tested-by: Michael Walle <michael@walle.cc> |
#
28f9393b |
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17-Oct-2019 |
Mathew McBride <matt@traverse.com.au> |
fsl-layerscape: do not use layerscape EFI reset if PSCI used If the secure world reset handlers are used (via CONFIG_PSCI_RESET), then do not use the layerscape-specific implementation. Signed-off-by: Mathew McBride <matt@traverse.com.au> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
6ed69523 |
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18-Sep-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add more personalities support Add LS1027A, LS1018A and LS1017A personalities support to LS1028A SoC family. LS1028A is the prime personality of LS1028A SoC family. LS1027A is a lower funtionality version of QorIQ LS1028A which does not support the multimedia subsystems, such as LCD controller, GPU, and eDP PHY. The QorIQ LS1018A and LS1017A SoCs are single 64-bit Arm A72 core, low power versions of the QorIQ LS1028A and LS1027A SoCs respectively. Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
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0490cab5 |
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08-Aug-2019 |
Thomas Schaefer <thomas.schaefer@kontron.com> |
armv8: ls1028a: configure PMU's PCTBENR to enable WDT The SP805-WDT module on LS1028A requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. The watchdog clock needs to be enabled first. Signed-off-by: Thomas Schaefer <thomas.schaefer@kontron.com> Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
f3998fdc |
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02-Aug-2019 |
Simon Glass <sjg@chromium.org> |
env: Rename environment.h to env_internal.h This file contains lots of internal details about the environment. Most code can include env.h instead, calling the functions there as needed. Rename this file and add a comment at the top to indicate its internal nature. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> [trini: Fixup apalis-tk1.c] Signed-off-by: Tom Rini <trini@konsulko.com> |
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3a7d5571 |
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01-Aug-2019 |
Simon Glass <sjg@chromium.org> |
env: Move env_get_f() to env.h Move this function over to the new header file. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
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d9532e80 |
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23-Apr-2019 |
Udit Agarwal <udit.agarwal@nxp.com> |
armv8: fsl-layerscape: Set env_loc to ENVL_NOWHERE with CONFIG_ENV_IS_NOWHERE. ENVL_NOWHERE is dependent on CONFIG_ENV_IS_NOWHERE and not on CONFIG_CHAIN_OF_TRUST so return ENVL_NOWHERE when CONFIG_ENV_IS_NOWHERE is enabled Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
d4ad111d |
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10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
059d9422 |
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08-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: lx2160a: add MMU table entries for PCIe The lx2160a have up to 6 PCIe controllers and have different address and size of PCIe region. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
8348e798 |
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08-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: layerscape: use PCIe address macro for precompile PCIe MMU entry Change to use PCIe address macro to determine if precompile the PCIe MMU table entry. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
10015025 |
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03-May-2019 |
Trevor Woerner <trevor@toganlabs.com> |
CONFIG_SPL_SYS_[DI]CACHE_OFF: add While converting CONFIG_SYS_[DI]CACHE_OFF to Kconfig, there are instances where these configuration items are conditional on SPL. This commit adds SPL variants of these configuration items, uses CONFIG_IS_ENABLED(), and updates the configurations as required. Acked-by: Alexey Brodkin <abrodkin@synopsys.com> Signed-off-by: Trevor Woerner <trevor@toganlabs.com> [trini: Make the default depend on the setting for full U-Boot, update more zynq hardware] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
2e53759d |
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29-Oct-2018 |
Pankaj Bansal <pankaj.bansal@nxp.com> |
armv8: fsl-layerscape: reorder rgmii dpmacs' enablement some dpmacs in armv8a based freescale layerscape SOCs can be configured via both serdes(sgmii, xfi, xlaui etc) bits and via EC*_PMUX(rgmii) bits in RCW. e.g. dpmac 17 and 18 in LX2160A can be configured as SGMII from serdes bits and as RGMII via EC1_PMUX/EC2_PMUX bits Now if a dpmac is enabled by serdes bits then it takes precedence over EC*_PMUX bits. i.e. in LX2160A if we select serdes protocol that configures dpmac17 as SGMII and set the EC1_PMUX as RGMII, then the dpmac is SGMII and not RGMII. Therefore, move the fsl_rgmii_init after fsl_serdes_init. in fsl_rgmii_init function of SOC, we will check if the dpmac is enabled or not? if it is (fsl_serdes_init has already enabled the dpmac), then don't enable it. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
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ec88ff80 |
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19-Dec-2018 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1043a: add SVR definitions for 23x23 package silicon LS1043A/LS1023A 23x23 package silicon has different SVR:VAR_PER. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
d23da2ae |
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26-Dec-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: fixes for TFABOOT framework Fixes for TFABOOT framework - update eMMC bootsrc to SD_MMC - Increase buffer size for mcinitcmd from 256 to 512 - Fix mcinitcmd and bootcmd for Secure Boot Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
4909b89e |
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29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
d6fdec21 |
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29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8:fsl-layerscape: Add support for Chassis 3.2 NXP layerscape architecture Chassis 3.2 builds upon chassis3 architecture with changes like DDR Memory map change, removal of IFC and support of upto 8 I2C controller. Patch add README.lsch3_2 and the above changes under macro CONFIG_NXP_LSCH3_2. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
56db948b |
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05-Nov-2018 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: Update parsing boot source Workaround of erratum A010539 clears the RCW source field in PORSR1 register, causing failure of detecting boot source using this method. Use SMC call if U-Boot runs at EL2. If SMC is not implemented or running at EL3, continue to read PORSR1 and presume QSPI as boot source if erratum workaround A010539 is enabled and RCW source is cleared. Signed-off-by: York Sun <york.sun@nxp.com> |
#
681d489e |
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05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: layerscape: add SMC calls for DDR size and bank info Adds SMC calls for getting DDR size and bank info for TFABOOT. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
2141d250 |
|
05-Nov-2018 |
Pankit Garg <pankit.garg@nxp.com> |
armv8: fsl-layerscape: bootcmd identification for TFABOOT Adds bootcmd identificaton on basis on boot source, valid in TFABOOT configuration. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> [YS: remove unnecessary braces] Reviewed-by: York Sun <york.sun@nxp.com> |
#
4c417384 |
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05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com> |
#
535d76a1 |
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05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: layerscape: Add TFABOOT support Adds TFABOOT support config option and add generic code to enable execution from DDR. Signed-off-by: York Sun <york.sun@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> |
#
e3506480 |
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05-Nov-2018 |
Pankit Garg <pankit.garg@nxp.com> |
armv8: fsl-layerscape: change tlb base from OCRAM to DDR in EL < 3 Change tlb base address from OCRAM to DDR when exception level is less than 3. Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
d171c707 |
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05-Nov-2018 |
York Sun <york.sun@nxp.com> |
move data structure out of cpu.h Move static definitions to cpu.c file, as it doesn't allow the cpu.h file to be included in multiple c files. Signed-off-by: York Sun <york.sun@nxp.com> |
#
9b5e6396 |
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30-Aug-2018 |
Stephen Warren <swarren@nvidia.com> |
efi_loader: simplify ifdefs Use CONFIG_IS_ENABLED(EFI_LOADER) to avoid explicitly checking CONFIG_SPL too. This simplifies the conditional. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Alexander Graf <agraf@suse.de> |
#
9cce5663 |
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16-Jul-2018 |
Joe Hershberger <joe.hershberger@ni.com> |
arm: Prevent redefinition error in fsl-layerscape The include/phy.h will start including dm.h, which pulls in linux/compat.h after the attempted redefinition in arch/arm/include/asm/armv8/mmu.h, so move this include to allow redefinition. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> |
#
83d290c5 |
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06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
482fc90c |
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06-Feb-2018 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
efi_loader: add missing EFI_RESET_PLATFORM_SPECIFIC EFI_RESET_PLATFORM_SPECIFIC is one of the values that can be used for the EFI service ResetSystem. The missing definition is added. The value has to handled in efi_reset_system(). Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Alexander Graf <agraf@suse.de> |
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22c793e6 |
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03-Mar-2018 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
efi_loader: exit status for efi_reset_system_init efi_reset_system_init provides the architecture or board specific initialization of the EFI subsystem. Errors should be caught and signalled by a return code. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Alexander Graf <agraf@suse.de> |
#
958b2ed5 |
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09-Jan-2018 |
Zhang Ying-22455 <ying.zhang22455@nxp.com> |
armv8/ls1088a: configure PMU's PCTBENR to enable WDT The SP805-WDT module on LS1088A requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. The watchdog clock needs to be enabled first. Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
44262327 |
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15-Dec-2017 |
Ahmed Mansour <ahmed.mansour@nxp.com> |
drivers/misc: Share qbman init between archs This patch adds changes necessary to move functionality present in PowerPC folders with ARM architectures that have DPAA1 QBMan hardware - Create new board/freescale/common/fsl_portals.c to house shared device tree fixups for DPAA1 devices with ARM and PowerPC cores - Add new header file to top includes directory to allow files in both architectures to grab the function prototypes - Port inhibit_portals() from PowerPC to ARM. This function is used in setup to disable interrupts on all QMan and BMan portals. It is needed because the interrupts are enabled by default for all portals including unused/uninitialised portals. When the kernel attempts to go to deep sleep the unused portals prevent it from doing so Signed-off-by: Ahmed Mansour <ahmed.mansour@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
a8f33034 |
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03-Dec-2017 |
Wenbin song <wenbin.song@nxp.com> |
armv8: ls1043a/ls2080a: check SoC by device ID Check LS1043A/LS2080a by device ID without using personality ID to determine revision number. This check applies to all various personalities of the same SoC family. Signed-off-by: Wenbin Song <wenbin.song@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
2db53cfe |
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09-Nov-2017 |
Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
armv8: fsl-layerscape: Add support of disabling core prefetch Instruction prefetch feature is by default enabled during core release. This patch add support of disabling instruction prefetch by setting core mask in PPA. Here each core mask bit represents a core and prefetch is disabled at the time of core release. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
7eb40f0f |
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28-Sep-2017 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: Avoid running dram_init_banksize again gd->ram_size is reduced in this function to reserve secure memory. Avoid running this function again to further reduce memory size. This fixes issue for SPL boot with PPA image loaded in which case secure memory is incorrectly allocated due to repeated calling. Signed-off-by: York Sun <york.sun@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
710d0cd7 |
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03-Oct-2017 |
Sumit Garg <sumit.garg@nxp.com> |
armv8: fsl-layerscape: Allocate Secure memory from first ddr region This change is required due to trusted OS (OP-TEE) not being position independent code, it requires compile time fixed base address. To take care of this it is assumed that all layerscape armv8 platforms has minimum 2G ddr in first region. So we can have fixed address space (66 MB -> (2MB for PPA + 64MB for trusted OS)) allocated from top of first 2G ddr region and compile trusted OS with this fixed base address. But one exception here is ls1012 where we have only 1G (rdb) or 512M (frdm) ddr memory. For those we can have different fixed compile time base addresses for trusted OS. Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
e9303a41 |
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07-Sep-2017 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: Fix MC reserved memory calculation In case high region memory doesn't have enough space for Management Complex (MC), the return value should indicate a failure so the caller can handle it accordingly. Signed-off-by: York Sun <york.sun@nxp.com> Reported-by: Ebony Zhu <ebony.zhu@nxp.com> |
#
17d066fc |
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31-Aug-2017 |
Ashish Kumar <Ashish.Kumar@nxp.com> |
armv8: fsl-layerscape: Support to add RGMII for ls1088aqds This patch adds support for RGMII protocol NXP's LDPAA2 support RGMII protocol. LS1088A is the first Soc supporting both RGMII and SGMII. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Amrita Kumari <amrita.kumari@nxp.com> Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
63b2316c |
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10-Aug-2017 |
Ashish Kumar <Ashish.Kumar@nxp.com> |
fsl-layerscape: Consolidate registers space defination for CCI-400 bus CoreLink Cache Coherent Interconnect (CCI) provides full cache coherency between two clusters of multi-core CPUs and I/O coherency for devices and I/O masters. This patch add new config option SYS_FSL_HAS_CCI400 and moves existing register space definaton of CCI-400 bus to fsl_immap to be shared. CONFIG_SYS_CCI400_ADDR is replaced with SYS_CCI400_OFFSET in Kconfig. Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> [YS: revised commit message, squashed patches for armv8 and armv7] Reviewed-by: York Sun <york.sun@nxp.com> |
#
6e2941d7 |
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17-May-2017 |
Simon Glass <sjg@chromium.org> |
common: freescale: Move arch-specific declarations The declarations should not be in common.h. Move them to the arch-specific headers. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Fixup thinko defined(FSL_LSCH3) -> defined(CONFIG_FSL_LSCH3)] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
399e2bb6 |
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15-May-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Make U-Boot EL2 safe When U-Boot boots from EL2, skip some lowlevel init code requiring EL3, including CCI-400/CCN-504, trust zone, GIC, etc. These initialization tasks are carried out before U-Boot runs. This applies to the RAM version image used for SPL boot if PPA is loaded first. Signed-off-by: York Sun <york.sun@nxp.com> |
#
1f55a938 |
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05-May-2017 |
Santan Kumar <santan.kumar@nxp.com> |
armv8: ls2080aqds: Add support for SD boot Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
e809e747 |
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27-Apr-2017 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: fsl-layerscape: Add NXP LS2081A, LS2041A SoC support The QorIQ LS2081A SoC has eight 64-bit ARM v8 Cortex A72 cores and is built on layerscape architecture. It is 40-pin derivative of LS2084A (non-AIOP personality of LS2088A). So feature-wise it is same as LS2084A. LS2041A is a 4-core personality of LS2081A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
026f30ec |
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18-Apr-2017 |
Yuantian Tang <andy.tang@nxp.com> |
arm: psci: make psci usable on single core socs PSCI can be used on both multiple and single core socs. Current implementation only allows PSCI to work on multiple core socs. This patch removes this restriction so that PSCI can work on single core socs as well. Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
4a3ab193 |
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27-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: ls2080a: Drop macro CONFIG_LS2080A Use CONFIG_ARCH_LS2080A instead. Signed-off-by: York Sun <york.sun@nxp.com> |
#
3eace37e |
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06-Apr-2017 |
Simon Glass <sjg@chromium.org> |
arm: freescale: Rename initdram() to fsl_initdram() This function name shadows a global name but is in fact different. This is very confusing. Rename it to help with the following refactoring. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
76b00aca |
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31-Mar-2017 |
Simon Glass <sjg@chromium.org> |
board_f: Drop setup_dram_config() wrapper By making dram_init_banksize() return an error code we can drop the wrapper. Adjust this and clean up all implementations. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
088454cd |
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31-Mar-2017 |
Simon Glass <sjg@chromium.org> |
board_f: Drop return value from initdram() At present we cannot use this function as an init sequence call without a wrapper, since it returns the RAM size. Adjust it to set the RAM size in global_data instead, and return 0 on success. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
52c41180 |
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31-Mar-2017 |
Simon Glass <sjg@chromium.org> |
board_f: Drop board_type parameter from initdram() It looks like only cm5200 and tqm8xx use this feature, so we don't really need it in generic code. Drop it and have the users access gd->board_type directly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
3d8553f0 |
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02-Mar-2017 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
pci: layerscape: add LS2088A series SoC pcie support The LS2088A series SoCs has different physical memory map address and CCSR registers address against LS2080A series SoCs. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
eea1cb77 |
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13-Feb-2017 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8/fsl-layerscape: Update erratum A009635 implementation Erratum A009635 is valid only for LS2080A SoC and its personality. Add SoC svr check. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
4961eafc |
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06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Update early MMU for DDR after initialization In early MMU table, DDR has to be mapped as device memory to avoid speculative access. After DDR is initialized, it needs to be updated to normal memory to allow code execution. To simplify the code, dram_init() is moved into a common file as a weak function. Signed-off-by: York Sun <york.sun@nxp.com> |
#
a045a0c3 |
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06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Fix the sequence of changing MMU table This patch follows the break-before-make process when making changes to MMU table. MMU is disabled before changing TTBR to avoid any potential race condition. Signed-off-by: York Sun <york.sun@nxp.com> |
#
24f55496 |
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06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Update MMU mapping with actual DDR size Update mapping with actual DDR size. Non-existing memory should not be mapped as "normal" memory to avoid speculative access. Signed-off-by: York Sun <york.sun@nxp.com> |
#
36cc0de0 |
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06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Rewrite memory reservation For ARMv8 Layerscape SoCs, secure memory and MC memorey are reserved at the end of DDR. DDR is spit into two or three banks. This patch reverts commit aabd7ddb and simplifies the calculation of reserved memory, and moves the code into common SoC file. Secure memory is carved out first. DDR bank size is reduced. Reserved memory is then allocated on the top of available memory. U-Boot still has access to reserved memory as data transferring is needed. Device tree is fixed with reduced memory size to hide the reserved memory from OS. The same region is reserved for efi_loader. Signed-off-by: York Sun <york.sun@nxp.com> |
#
daa92644 |
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16-Jan-2017 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
ARMv8/sec_firmware: relocated and renamed the config FSL_PPA_ARMV8_PSCI Moved the config FSL_PPA_ARMV8_PSCI from fsl-layerscape's Kconfig to Kconfig under armv8 and renamed it to SEC_FIRMWARE_ARMV8_PSCI. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
904110c7 |
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10-Jan-2017 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8/fsl-lsch2: refactor the clock system initialization Up to now, there are 3 kind of SoCs under Layerscape Chassis 2, like LS1043A, LS1046A and LS1012A. But the clocks tree has a lot of differences, for instance, the IP modules have different dividers to derive its clock from Platform PLL. And the core cluster PLL and platform PLL maybe have different reference clocks, such as LS1012A. Another problem is which clock/PLL should be described by sys_info->freq_systembus, it is confused in Layerscape Chissis 2. This patch is to bind the sys_info->freq_systembus to the Platform PLL, and handle the different divider of IP modules separately between different SoCs, and separate reference clocks of core cluster PLL and platform PLL. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
2d16a1a6 |
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07-Dec-2016 |
macro.wave.z@gmail.com <macro.wave.z@gmail.com> |
ARMv8: LS1043A: change macro CONFIG_ARMV8_PSCI definition NXP/Freescale uses macro CONFIG_ARMV8_PSCI to enable their private PSCI implementation in PPA firmware, but this macro naming too generic, so this patch replaces it with a specic one CONFIG_FSL_PPA_ARMV8_PSCI. And this macro CONFIG_ARMV8_PSCI will be used for a generic PSCI for ARMv8 which will be added in following patchs. Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
02fb2761 |
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20-Nov-2016 |
Shengzhou Liu <Shengzhou.Liu@nxp.com> |
fsl/ddr: Add erratum_a009942_check_cpo and clean related erratum - add additional function erratum_a009942_check_cpo to check if the board needs tuning CPO calibration for optimal setting. - move ERRATUM_A009942(with revision to check cpo_sample option) from fsl_ddr_gen4.c to ctrl_regs.c for reuse on all DDR4/DDR3 parts. - move ERRATUM_A008378 from fsl_ddr_gen4.c to ctrl_regs.c - remove obsolete ERRATUM_A004934 which is replaced with ERRATUM_A009942. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> [YS: Replaced CONFIG_QEMU_E500 with CONFIG_ARCH_QEMU_E500] Reviewed-by: York Sun <york.sun@nxp.com> |
#
e87c673c |
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16-Nov-2016 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8/fsl-lsch3: Update code to release secondary cores NXP ARMv8 SoC LS2080A release all secondary cores in one-go. But other new SoCs like LS2088A, LS1088A release secondary cores one by one. Update code to release secondary cores based on SoC SVR Add code to release cores one by one for non LS2080A SoCs Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> [YS: remove "inline" from declaration of initiator_type] Reviewed-by: York Sun <york.sun@nxp.com> |
#
f6b96ff6 |
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16-Nov-2016 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Use SVR based timer base address detection Timer controller base address has been changed from LS2080A SoC (and its personalities) to new SoCs like LS2088A, LS1088A. Use SVR based timer base address detection to avoid compile time #ifdef. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
f6a70b3a |
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16-Nov-2016 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add generic get_svr() in assembly Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
78d57842 |
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16-Nov-2016 |
Alexander Graf <agraf@csgraf.de> |
armv8: fsl-layerscape: Add support for efi_loader RTS reset When implementing efi loader support, we can expose runtime services for payloads. One such service is CPU reset. This patch implements RTS CPU reset support for layerscape systems. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: York Sun <york.sun@nxp.com> |
#
ef9a5fd8 |
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13-Sep-2016 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: Fix "cpu status" command The core position is not continuous for some SoCs. For example, valid cores may present at position 0, 1, 4, 5, 8, 9, etc. Some registers (including boot release register) only count existing cores. Current implementation of cpu_mask() complies with the continuous numbering. However, command "cpu status" queries the spin table with actual core position. Add functions to calculate core position from core number, to correctly calculate offsets. Tested on LS2080ARDB and LS1043ARDB. Signed-off-by: York Sun <york.sun@nxp.com> |
#
5d1a7a9d |
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13-Sep-2016 |
Wenbin Song <wenbin.song@nxp.com> |
armv8/fsl-layerscape: print SoC revsion number The exact SoC revsion number can be recognized from U-Boot log. Signed-off-by: Wenbin Song <wenbin.song@nxp.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
cbe7706a |
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26-Sep-2016 |
Tom Rini <trini@konsulko.com> |
Merge git://git.denx.de/u-boot-fsl-qoriq trini: Drop local memset() from examples/standalone/mem_to_mem_idma2intr.c Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
1221ce45 |
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20-Sep-2016 |
Masahiro Yamada <masahiroy@kernel.org> |
treewide: replace #include <asm/errno.h> with <linux/errno.h> Now, arch/${ARCH}/include/asm/errno.h and include/linux/errno.h have the same content. (both just wrap <asm-generic/errno.h>) Replace all include directives for <asm/errno.h> with <linux/errno.h>. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> [trini: Fixup include/clk.] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
b63a9506 |
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03-Aug-2016 |
York Sun <york.sun@nxp.com> |
armv8: ls2080a: Remove debug server support Debug server feature has been dropped from roadmap. Signed-off-by: York Sun <york.sun@nxp.com> |
#
ed7a3943 |
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22-Jul-2016 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: mmu: Fix enabling MMU MMU bit in SCTLR needs to be set explicitly after tables are created. It isn't an issue for EL3 becuase this bit is already set by early MMU setup. But for other exception levels this bit was not set. Signed-off-by: York Sun <york.sun@nxp.com> |
#
79119a4d |
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05-Jul-2016 |
Alison Wang <b18965@freescale.com> |
armv8: fsl-layerscape: Add A72 core detection Add support to detect Cortex-A72 core for printing it out. The Initiator Version of A72 core should be 0x4. Signed-off-by: Alison Wang <alison.wang@nxp.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
032d5bb4 |
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28-Jun-2016 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
ARMv8/Layerscape: switch SMP method accordingly If the PSCI and PPA is ready, skip the fixup for spin-table and waking secondary cores. Otherwise, change SMP method to spin-table, and the device node of PSCI will be removed. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
85cdf38e |
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28-Jun-2016 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: fsl-layerscape: add i/d-cache enable function to enable_caches This function assume that the d-cache and MMU has been enabled earlier, so it just created MMU table in main memory. But the assumption is not always correct, for example, the early setup is done in EL3, while enable_caches() is called when the PE has turned into another EL. Define the function mmu_setup() for fsl-layerscape to cover the weak one. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
5ad5823d |
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24-Jun-2016 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Convert to use common MMU framework Drop platform code to create static MMU tables. Use common framework to create MMU tables on the run. Tested on LS2080ARDB with secure and non-secure ram scenarios. Signed-off-by: York Sun <york.sun@nxp.com> |
#
e61a7534 |
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24-Jun-2016 |
York Sun <york.sun@nxp.com> |
armv8: Move secure_ram variable out of generic global data Secure_ram variable was put in generic global data. But only ARMv8 uses this variable. Move it to ARM specific data structure. Signed-off-by: York Sun <york.sun@nxp.com> |
#
a10a31ec |
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18-Jun-2016 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of git://git.denx.de/u-boot-usb Signed-off-by: Tom Rini <trini@konsulko.com> Conflicts: arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
|
#
6fb522dc |
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12-Jun-2016 |
Sriram Dash <sriram.dash@nxp.com> |
arm64: fsl-layerscape: add get_svr and IS_SVR_REV helper Adds get_svr and IS_SVR_REV helpers for ARMv8 platforms, similar to PPC and ARMv7. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> |
#
a758177f |
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07-Jun-2016 |
Yunhui Cui <yunhui.cui@nxp.com> |
armv8/ls2080a: configure PMU's PCTBENR to enable WDT The SP805-WDT module on LS2080A requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. The watchdog clock needs to be enabled first. Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
acb8f5e9 |
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21-Apr-2016 |
Alison Wang <b18965@freescale.com> |
armv8: fsl-layerscape: Remove unnecessary flushing dcache As the issue about the stack will get corrupted when switching between the early and final mmu tables is fixed by commit 70e21b064, the workaround to flush dcache is unnecessary and should be removed. Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
3c1d218a |
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04-Apr-2016 |
York Sun <york.sun@nxp.com> |
armv8: LS2080A: Consolidate LS2080A and LS2085A LS2080A is the primary SoC, and LS2085A is a personality with AIOP and DPAA DDR. The RDB and QDS boards support both personality. By detecting the SVR at runtime, a single image per board can support both SoCs. It gives users flexibility to swtich SoC without the need to reprogram the board. Signed-off-by: York Sun <york.sun@nxp.com> CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
c05016ab |
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21-Mar-2016 |
Alexander Graf <agraf@csgraf.de> |
arm64: Fix layerscape mmu setup With commit 7985cdf we converted all systems except for the Layerscape SoCs to the generic descriptor table based page table setup. On the Layerscape SoCs however, we just provide an empty table stub and do the setup ourselves. To reserve enough memory for the tables, we need to override the default counting mechanism which would end up with an empty table because we have no maps. Fixes: 7985cdf Reported-by: York Sun <york.sun@nxp.com> CC: Alison Wang <alison.wang@nxp.com> CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Alexander Graf <agraf@suse.de> Tested-by: York Sun <york.sun@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
7985cdf7 |
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03-Mar-2016 |
Alexander Graf <agraf@csgraf.de> |
arm64: Remove non-full-va map code By now the code to only have a single page table level with 64k page size and 42 bit address space is no longer used by any board in tree, so we can safely remove it. To clean up code, move the layerscape mmu code to the new defines, removing redundant field definitions. Signed-off-by: Alexander Graf <agraf@suse.de> |
#
c0492141 |
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07-Dec-2015 |
York Sun <yorksun@freescale.com> |
armv8: fsl-layerscale: Rewrite reserving memory for MC and debug server MC and debug server are not board-specific. Move reserving memory to SoC file, using the new board_reserve_ram_top function. Reduce debug server memory by 2MB to make room for secure memory. In the system with MC and debug server, the top of u-boot memory is not the end of memory. PRAM is not used for this reservation. Signed-off-by: York Sun <yorksun@freescale.com> |
#
c107c0c0 |
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04-Dec-2015 |
York Sun <yorksun@freescale.com> |
armv8: fsl-layerscape: Make DDR non secure in MMU tables DDR has been set as secure in MMU tables. Non-secure master such as SDHC DMA cannot access data correctly. Mixing secure and non- secure MMU entries requirs the MMU tables themselves in secure memory. This patch moves MMU tables into a secure DDR area. Early MMU tables are changed to set DDR as non-secure. A new table is added into final MMU tables so secure memory can have 2MB granuality. gd->secure_ram tracks the location of this secure memory. For ARMv8 SoCs, the RAM base is not zero and RAM is divided into several banks. gd->secure_ram needs to be maintained before using. This maintenance is board-specific, depending on the SoC and memory bank of the secure memory falls into. Signed-off-by: York Sun <yorksun@freescale.com> |
#
b4017364 |
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04-Nov-2015 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
armv8: ls2085a: Add workaround of errata A009635 If the core runs at higher than x3 speed of the platform, there is possiblity about sev instruction to getting missed by other cores. This is because of SoC Run Control block may not able to sample the EVENTI(Sev) signals. Configure Run Control and EPU to periodically send out EVENTI signals to wake up A57 cores. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
d764129d |
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04-Nov-2015 |
Alison Wang <b18965@freescale.com> |
armv8/layerscape: Update MMU table with execute-never bits For most device addresses excution shouldn't be allowed. Revise the MMU table to enforce execute-never bits. OCRAM, DDR and IFC are allowed for excution. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Alison Wang <alison.wang@freescale.com> Reported-by: Zhichun Hua <zhichun.hua@freescale.com> |
#
44937214 |
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09-Nov-2015 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
armv8: LS2080A: Rename LS2085A to reflect LS2080A LS2080A is a prime personality of Freescale’s LS2085A. It is a non-AIOP personality without support of DP-DDR, L2 switch, 1588, PCIe endpoint etc. So renaming existing LS2085A code base to reflect LS2080A (Prime personality) Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> [York Sun: Dropped #ifdef in cpu.c for cpu_type_list] Reviewed-by: York Sun <yorksun@freescale.com> |
#
e8297341 |
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26-Oct-2015 |
Shaohui Xie <Shaohui.Xie@freescale.com> |
armv8/ls1043a: Add Fman support Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
8281c58f |
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26-Oct-2015 |
Mingkai Hu <Mingkai.Hu@freescale.com> |
armv8/fsl_lsch2: Add fsl_lsch2 SoC Freescale LayerScape with Chassis Generation 2 is a set of SoCs with ARMv8 cores and 2rd generation of Chassis. Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
9f3183d2 |
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26-Oct-2015 |
Mingkai Hu <Mingkai.Hu@freescale.com> |
armv8/fsl_lsch3: Change arch to fsl-layerscape There are two LS series processors are built on ARMv8 Layersacpe architecture currently, LS2085A and LS1043A. They are based on ARMv8 core although use different chassis, so create fsl-layerscape to refactor the common code for the LS series processors which also paves the way for adding LS1043A platform. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
e7ec875d |
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05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of SYS_FSL_ERRATUM_A010539 This converts 1 usage of this option to the non-SPL form, since there is no SPL_SYS_FSL_ERRATUM_A010539 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> |
#
6e7df1d1 |
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10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
global: Finish CONFIG -> CFG migration At this point, the remaining places where we have a symbol that is defined as CONFIG_... are in fairly odd locations. While as much dead code has been removed as possible, some of these locations are simply less obvious at first. In other cases, this code is used, but was defined in such a way as to have been missed by earlier checks. Perform a rename of all such remaining symbols to be CFG_... rather than CONFIG_... Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
1d457dbb |
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04-Dec-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_MAX_MEM_MAPPED to CFG Perform a simple rename of CONFIG_MAX_MEM_MAPPED to CFG_MAX_MEM_MAPPED Signed-off-by: Tom Rini <trini@konsulko.com> |
#
4fd9373b |
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02-Dec-2022 |
Tom Rini <trini@konsulko.com> |
net: Remove more legacy functions Remove some of the board and arch specific non-DM_ETH helper code. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
65cc0e2a |
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16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
aa6e94de |
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16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
ecc8d425 |
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16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_PCI* to CFG_SYS_PCI* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_PCI and CONFIG_SYS_PCIE namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
6cc04547 |
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28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
8fd11135 |
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25-Sep-2022 |
Sean Anderson <sean.anderson@seco.com> |
arm64: layerscape: Support SYSRESET CONFIG_SYSRESET provides its own implementation of reset_cpu. Disable our version when it is enabled. Signed-off-by: Sean Anderson <sean.anderson@seco.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> |
#
ce9c579e |
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13-Jun-2022 |
Andre Przywara <andre.przywara@arm.com> |
armv8: always use current exception level for TCR_ELx access Currently get_tcr() takes an "el" parameter, to select the proper version of the TCR_ELx system register. This is problematic in case of the Apple M1, since it runs with HCR_EL2.E2H fixed to 1, so TCR_EL2 is actually using the TCR_EL1 layout, and we get the wrong version. For U-Boot's purposes the only sensible choice here is the current exception level, and indeed most callers treat it like that, so let's remove that parameter and read the current EL inside the function. This allows us to check for the E2H bit, and pretend it's EL1 in this case. There are two callers which don't care about the EL, and they pass 0, which looks wrong, but is irrelevant in these two cases, since we don't use the return value there. So the change cannot affect those two. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Mark Kettenis <kettenis@openbsd.org> Tested-by: Mark Kettenis <kettenis@openbsd.org> |
#
cda8f873 |
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11-May-2022 |
Ye Li <ye.li@nxp.com> |
caam: Fix crash in case caam_jr_probe failed If probing caam_jr returns failure, the variable "dev" will not be initialized, so we can't use dev->name for the error print. Otherwise it will cause crash. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Gaurav Jain <gaurav.jain@nxp.com> |
#
cb14cc88 |
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22-Apr-2022 |
Michael Walle <michael@walle.cc> |
armv8: layerscape: get rid of smc_call() There are two different implementations to do a secure monitor call: smc_call() and arm_smccc_smc(). The former is defined in fwcall.c and seems to be an ad-hoc implementation. The latter is imported from linux. smc_call() is also only available if CONFIG_ARMV8_PSCI is not defined. This makes it impossible to have both PSCI calls and PSCI implementation in one u-boot build. The layerscape SoC code decide at runtime via check_psci() if there is a PSCI support. Therefore, this is a prerequisite patch to add PSCI implementation support for the layerscape SoCs. Note, for the TFA part, this is only compile time tested with (ls1028ardb_tfa_defconfig). Signed-off-by: Michael Walle <michael@walle.cc> [Rebased] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
dfb6da55 |
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05-Apr-2022 |
Marek Vasut <marex@denx.de> |
armv8: layerscape: env: Switch to arch_env_get_location() Implement arch_env_get_location() instead of env_get_location(), so that the env_get_location() can be implemented on board level and override the arch_env_get_location() architecture defaults. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Adam Ford <aford173@gmail.com> Cc: Fabio Estevam <festevam@denx.de> Cc: Marek Behún <marek.behun@nic.cz> Cc: Peng Fan <peng.fan@nxp.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefano Babic <sbabic@denx.de> Cc: Tim Harvey <tharvey@gateworks.com> Cc: Tom Rini <trini@konsulko.com> Cc: Tommaso Merciai <tomm.merciai@gmail.com> Cc: Vladimir Oltean <vladimir.oltean@nxp.com> |
#
8976556a |
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24-Mar-2022 |
Gaurav Jain <gaurav.jain@nxp.com> |
Layerscape: Enable Job ring driver model. LS(1021/1012/1028/1043/1046/1088/2088), LX2160, LX2162 platforms are enabled with JR driver model. removed sec_init() call from board files. sec is initialized based on job ring information processed from device tree. Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Michael Walle <michael@walle.cc> |
#
f9147d63 |
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25-Feb-2022 |
Tom Rini <trini@konsulko.com> |
Convert CONFIG_CHIP_SELECTS_PER_CTRL to Kconfig This converts the following to Kconfig: CONFIG_CHIP_SELECTS_PER_CTRL Cc: Alison Wang <alison.wang@nxp.com> Cc: Pramod Kumar <pramod.kumar_1@nxp.com> Cc: Priyanka Jain <priyanka.jain@nxp.com> Cc: Rajesh Bhagat <rajesh.bhagat@nxp.com> Cc: Vladimir Oltean <olteanv@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
2f8a6db5 |
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14-Dec-2021 |
Tom Rini <trini@konsulko.com> |
Finish conversion of CONFIG_SYS_CLK_FREQ to Kconfig In order to finish moving this symbol to Kconfig for all platforms, we need to do a few more things. First, for all platforms that define this to a function, introduce CONFIG_DYNAMIC_SYS_CLK_FREQ, similar to CONFIG_DYNAMIC_DDR_CLK_FREQ and populate clock_legacy.h. This entails also switching all users from CONFIG_SYS_CLK_FREQ to get_board_sys_clk() and updating a few preprocessor tests. With that done, all platforms that define a value here can be converted to Kconfig, and a fall-back of zero is sufficiently safe to use (and what is used today in cases where code may or may not have this available). Make sure that code which calls this function includes <clock_legacy.h> to get the prototype. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
77b11f76 |
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18-Sep-2021 |
Vladimir Oltean <vladimir.oltean@nxp.com> |
net: replace the "xfi" phy-mode with "10gbase-r" As part of the effort of making U-Boot work with the same device tree as Linux, there is an issue with the "xfi" phy-mode. To be precise, in Linux there was a discussion (for those who have time to read: https://lore.kernel.org/netdev/1576768881-24971-2-git-send-email-madalin.bucur@oss.nxp.com/) which led to a patch: https://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next.git/commit/?id=c114574ebfdf42f826776f717c8056a00fa94881 TL;DR: "xfi" was standardized in Linux as "10gbase-r". This patch changes the relevant occurrences in U-Boot to use "10gbase-r" instead of "xfi" wherever applicable. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> |
#
84c2e044 |
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20-Apr-2021 |
Jiafei Pan <Jiafei.Pan@nxp.com> |
armv8: layerscape: add PSCI support for cpu release For cpu release command, check whether PSCI is supported firstly, if supported, use PSCI to kick off secondary cores, otherwise still use spin table. Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com> [Fixed checkpatch alignment CHECKs] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
35b65dd8 |
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15-Dec-2020 |
Harald Seiler <hws@denx.de> |
reset: Remove addr parameter from reset_cpu() Historically, the reset_cpu() function had an `addr` parameter which was meant to pass in an address of the reset vector location, where the CPU should reset to. This feature is no longer used anywhere in U-Boot as all reset_cpu() implementations now ignore the passed value. Generic code has been added which always calls reset_cpu() with `0` which means this feature can no longer be used easily anyway. Over time, many implementations seem to have "misunderstood" the existence of this parameter as a way to customize/parameterize the reset (e.g. COLD vs WARM resets). As this is not properly supported, the code will almost always not do what it is intended to (because all call-sites just call reset_cpu() with 0). To avoid confusion and to clean up the codebase from unused left-overs of the past, remove the `addr` parameter entirely. Code which intends to support different kinds of resets should be rewritten as a sysreset driver instead. This transformation was done with the following coccinelle patch: @@ expression argvalue; @@ - reset_cpu(argvalue) + reset_cpu() @@ identifier argname; type argtype; @@ - reset_cpu(argtype argname) + reset_cpu(void) { ... } Signed-off-by: Harald Seiler <hws@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
401d1c4f |
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30-Oct-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop asm/global_data.h from common header Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
3a187cff |
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29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
c760095a |
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23-Oct-2020 |
Razvan Ionut Cirjan <razvanionut.cirjan@nxp.com> |
net: lx2160a.c: Update to set ECx_PMUX precedence As per hardware documentation, ECx_PMUX has precedence over SerDes protocol. For LX2160/LX2162 if DPMACs 17 and 18 are enabled as SGMII through SerDes protocol but ECx_PMUX configured them as RGMII, then the ports will be configured as RGMII and not SGMII. Signed-off-by: Razvan Ionut Cirjan <razvanionut.cirjan@nxp.com> [Rebased] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
d31f3a1b |
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09-Sep-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2160a: fix reset sequence Make sure that SW_RST_REQ and RST_REQ_MSK are cleared before triggering hardware reset request. Signed-off-by: Thirupathaiah Annapureddy <thiruan@linux.microsoft.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
b75d8dc5 |
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26-Jun-2020 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
treewide: convert bd_t to struct bd_info by coccinelle The Linux coding style guide (Documentation/process/coding-style.rst) clearly says: It's a **mistake** to use typedef for structures and pointers. Besides, using typedef for structures is annoying when you try to make headers self-contained. Let's say you have the following function declaration in a header: void foo(bd_t *bd); This is not self-contained since bd_t is not defined. To tell the compiler what 'bd_t' is, you need to include <asm/u-boot.h> #include <asm/u-boot.h> void foo(bd_t *bd); Then, the include direcective pulls in more bloat needlessly. If you use 'struct bd_info' instead, it is enough to put a forward declaration as follows: struct bd_info; void foo(struct bd_info *bd); Right, typedef'ing bd_t is a mistake. I used coccinelle to generate this commit. The semantic patch that makes this change is as follows: <smpl> @@ typedef bd_t; @@ -bd_t +struct bd_info </smpl> Signed-off-by: Masahiro Yamada <masahiroy@kernel.org> |
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25a5818f |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop asm/ptrace.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
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f7ae49fc |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
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90526e9f |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop net.h from common header Move this header out of the common header. Network support is used in quite a few places but it still does not warrant blanket inclusion. Note that this net.h header itself has quite a lot in it. It could be split into the driver-mode support, functions, structures, checksumming, etc. Signed-off-by: Simon Glass <sjg@chromium.org> |
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714497e3 |
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16-May-2020 |
Michael Walle <michael@walle.cc> |
efi_loader: round the memory area in efi_add_memory_map() Virtually all callers of this function do the rounding on their own. Some do it right, some don't. Instead of doing this in each caller, do the rounding in efi_add_memory_map(). Change the size parameter to bytes instead of pages and remove aligning and size calculation in all callers. There is no more need to make the original efi_add_memory_map() (which takes pages as size) available outside the module. Thus rename it to efi_add_memory_map_pg() and make it static to prevent further misuse outside the module. Signed-off-by: Michael Walle <michael@walle.cc> Add missing comma in sunxi_display.c. Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de> |
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6eb32a03 |
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23-Apr-2020 |
Madalin Bucur <madalin.bucur@oss.nxp.com> |
driver: net: fm: add DM ETH support Probe the FMan MACs based on the device tree while retaining the legacy code/functionality. One notable change introduced here is that, for DM_ETH, the name of the interfaces is corrected to the fmX-macY format, that avoids the referral to the MAC block names which were incorrect for FMan v3 devices (i.e. DTSEC, TGEC) and had weird formatting (i.e. FM1@DTSEC6, FM1@TGEC1). The legacy code is left unchanged in this respect. Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
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6ebd4883 |
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27-Apr-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
fsl-layerscape: Add RESV_RAM check in resv_ram addr The initialization of gd->arch.resv_ram pointer should depend on if the RESV_RAM config is enabled. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Wasim Khan <wasim.khan@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
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0d9d557d |
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10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
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db41d65a |
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28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move hang() to the same header as panic() At present panic() is in the vsprintf.h header file. That does not seem like an obvious choice for hang(), even though it relates to panic(). So let's put hang() in its own header. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Migrate a few more files] Signed-off-by: Tom Rini <trini@konsulko.com> |
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9b4a205f |
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28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move RAM-sizing functions to init.h These functions relate to memory init so move them into the init header. Signed-off-by: Simon Glass <sjg@chromium.org> |
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3499dd03 |
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27-Nov-2019 |
Alex Marginean <alexandru.marginean@nxp.com> |
ls1028a: Configure stream IDs for integrated PCI and fix up Linux DT Hardware comes out of reset with implicit values, but these are outside the accepted range for Layerscape gen 3 chassis spec used on LS1028A. Allocate different IDs and fix up Linux DT to use them. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
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b5981474 |
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14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some CPU functions out of common.h These functions belong in cpu_func.h since they do not use driver model. Move them over. Don't bother adding comments since these functions should be deleted. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
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68a6aa85 |
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14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move mii_init() function out of common.h This function belongs in mii.h so move it over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
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2189d5f1 |
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14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
Move strtomhz() to vsprintf.h At present this function sits in its own file but it does not really justify it. There are similar string functions in vsprintf.h, so move it there. Also add the missing function comment. Use the vsprintf.h include file explicitly where needed. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
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812ff53c |
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30-Oct-2019 |
Pankaj Bansal <pankaj.bansal@nxp.com> |
fsl-layerscape: fix warning if no hwconfig is defined While getting the 'subarg' of 'hwconfig' env variable in config_core_prefetch(), if no hwconfig variable is defined, below warning is received: WARNING: Calling __hwconfig without a buffer and before environment is ready Fix this by checking 'hwconfig' env variable. If not found return without further processing. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Tested-by: Michael Walle <michael@walle.cc> |
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28f9393b |
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17-Oct-2019 |
Mathew McBride <matt@traverse.com.au> |
fsl-layerscape: do not use layerscape EFI reset if PSCI used If the secure world reset handlers are used (via CONFIG_PSCI_RESET), then do not use the layerscape-specific implementation. Signed-off-by: Mathew McBride <matt@traverse.com.au> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
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6ed69523 |
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18-Sep-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add more personalities support Add LS1027A, LS1018A and LS1017A personalities support to LS1028A SoC family. LS1028A is the prime personality of LS1028A SoC family. LS1027A is a lower funtionality version of QorIQ LS1028A which does not support the multimedia subsystems, such as LCD controller, GPU, and eDP PHY. The QorIQ LS1018A and LS1017A SoCs are single 64-bit Arm A72 core, low power versions of the QorIQ LS1028A and LS1027A SoCs respectively. Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
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0490cab5 |
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08-Aug-2019 |
Thomas Schaefer <thomas.schaefer@kontron.com> |
armv8: ls1028a: configure PMU's PCTBENR to enable WDT The SP805-WDT module on LS1028A requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. The watchdog clock needs to be enabled first. Signed-off-by: Thomas Schaefer <thomas.schaefer@kontron.com> Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
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f3998fdc |
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02-Aug-2019 |
Simon Glass <sjg@chromium.org> |
env: Rename environment.h to env_internal.h This file contains lots of internal details about the environment. Most code can include env.h instead, calling the functions there as needed. Rename this file and add a comment at the top to indicate its internal nature. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> [trini: Fixup apalis-tk1.c] Signed-off-by: Tom Rini <trini@konsulko.com> |
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3a7d5571 |
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01-Aug-2019 |
Simon Glass <sjg@chromium.org> |
env: Move env_get_f() to env.h Move this function over to the new header file. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
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d9532e80 |
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23-Apr-2019 |
Udit Agarwal <udit.agarwal@nxp.com> |
armv8: fsl-layerscape: Set env_loc to ENVL_NOWHERE with CONFIG_ENV_IS_NOWHERE. ENVL_NOWHERE is dependent on CONFIG_ENV_IS_NOWHERE and not on CONFIG_CHAIN_OF_TRUST so return ENVL_NOWHERE when CONFIG_ENV_IS_NOWHERE is enabled Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
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d4ad111d |
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10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
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059d9422 |
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08-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: lx2160a: add MMU table entries for PCIe The lx2160a have up to 6 PCIe controllers and have different address and size of PCIe region. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
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8348e798 |
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08-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: layerscape: use PCIe address macro for precompile PCIe MMU entry Change to use PCIe address macro to determine if precompile the PCIe MMU table entry. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
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10015025 |
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03-May-2019 |
Trevor Woerner <trevor@toganlabs.com> |
CONFIG_SPL_SYS_[DI]CACHE_OFF: add While converting CONFIG_SYS_[DI]CACHE_OFF to Kconfig, there are instances where these configuration items are conditional on SPL. This commit adds SPL variants of these configuration items, uses CONFIG_IS_ENABLED(), and updates the configurations as required. Acked-by: Alexey Brodkin <abrodkin@synopsys.com> Signed-off-by: Trevor Woerner <trevor@toganlabs.com> [trini: Make the default depend on the setting for full U-Boot, update more zynq hardware] Signed-off-by: Tom Rini <trini@konsulko.com> |
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2e53759d |
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29-Oct-2018 |
Pankaj Bansal <pankaj.bansal@nxp.com> |
armv8: fsl-layerscape: reorder rgmii dpmacs' enablement some dpmacs in armv8a based freescale layerscape SOCs can be configured via both serdes(sgmii, xfi, xlaui etc) bits and via EC*_PMUX(rgmii) bits in RCW. e.g. dpmac 17 and 18 in LX2160A can be configured as SGMII from serdes bits and as RGMII via EC1_PMUX/EC2_PMUX bits Now if a dpmac is enabled by serdes bits then it takes precedence over EC*_PMUX bits. i.e. in LX2160A if we select serdes protocol that configures dpmac17 as SGMII and set the EC1_PMUX as RGMII, then the dpmac is SGMII and not RGMII. Therefore, move the fsl_rgmii_init after fsl_serdes_init. in fsl_rgmii_init function of SOC, we will check if the dpmac is enabled or not? if it is (fsl_serdes_init has already enabled the dpmac), then don't enable it. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
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ec88ff80 |
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19-Dec-2018 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1043a: add SVR definitions for 23x23 package silicon LS1043A/LS1023A 23x23 package silicon has different SVR:VAR_PER. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
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d23da2ae |
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26-Dec-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: fixes for TFABOOT framework Fixes for TFABOOT framework - update eMMC bootsrc to SD_MMC - Increase buffer size for mcinitcmd from 256 to 512 - Fix mcinitcmd and bootcmd for Secure Boot Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
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4909b89e |
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29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
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d6fdec21 |
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29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8:fsl-layerscape: Add support for Chassis 3.2 NXP layerscape architecture Chassis 3.2 builds upon chassis3 architecture with changes like DDR Memory map change, removal of IFC and support of upto 8 I2C controller. Patch add README.lsch3_2 and the above changes under macro CONFIG_NXP_LSCH3_2. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
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56db948b |
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05-Nov-2018 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: Update parsing boot source Workaround of erratum A010539 clears the RCW source field in PORSR1 register, causing failure of detecting boot source using this method. Use SMC call if U-Boot runs at EL2. If SMC is not implemented or running at EL3, continue to read PORSR1 and presume QSPI as boot source if erratum workaround A010539 is enabled and RCW source is cleared. Signed-off-by: York Sun <york.sun@nxp.com> |
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681d489e |
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05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: layerscape: add SMC calls for DDR size and bank info Adds SMC calls for getting DDR size and bank info for TFABOOT. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
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2141d250 |
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05-Nov-2018 |
Pankit Garg <pankit.garg@nxp.com> |
armv8: fsl-layerscape: bootcmd identification for TFABOOT Adds bootcmd identificaton on basis on boot source, valid in TFABOOT configuration. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> [YS: remove unnecessary braces] Reviewed-by: York Sun <york.sun@nxp.com> |
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4c417384 |
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05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com> |
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535d76a1 |
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05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: layerscape: Add TFABOOT support Adds TFABOOT support config option and add generic code to enable execution from DDR. Signed-off-by: York Sun <york.sun@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> |
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e3506480 |
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05-Nov-2018 |
Pankit Garg <pankit.garg@nxp.com> |
armv8: fsl-layerscape: change tlb base from OCRAM to DDR in EL < 3 Change tlb base address from OCRAM to DDR when exception level is less than 3. Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
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d171c707 |
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05-Nov-2018 |
York Sun <york.sun@nxp.com> |
move data structure out of cpu.h Move static definitions to cpu.c file, as it doesn't allow the cpu.h file to be included in multiple c files. Signed-off-by: York Sun <york.sun@nxp.com> |
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9b5e6396 |
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30-Aug-2018 |
Stephen Warren <swarren@nvidia.com> |
efi_loader: simplify ifdefs Use CONFIG_IS_ENABLED(EFI_LOADER) to avoid explicitly checking CONFIG_SPL too. This simplifies the conditional. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Alexander Graf <agraf@suse.de> |
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9cce5663 |
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16-Jul-2018 |
Joe Hershberger <joe.hershberger@ni.com> |
arm: Prevent redefinition error in fsl-layerscape The include/phy.h will start including dm.h, which pulls in linux/compat.h after the attempted redefinition in arch/arm/include/asm/armv8/mmu.h, so move this include to allow redefinition. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> |
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83d290c5 |
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06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
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482fc90c |
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06-Feb-2018 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
efi_loader: add missing EFI_RESET_PLATFORM_SPECIFIC EFI_RESET_PLATFORM_SPECIFIC is one of the values that can be used for the EFI service ResetSystem. The missing definition is added. The value has to handled in efi_reset_system(). Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Alexander Graf <agraf@suse.de> |
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22c793e6 |
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03-Mar-2018 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
efi_loader: exit status for efi_reset_system_init efi_reset_system_init provides the architecture or board specific initialization of the EFI subsystem. Errors should be caught and signalled by a return code. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Alexander Graf <agraf@suse.de> |
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958b2ed5 |
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09-Jan-2018 |
Zhang Ying-22455 <ying.zhang22455@nxp.com> |
armv8/ls1088a: configure PMU's PCTBENR to enable WDT The SP805-WDT module on LS1088A requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. The watchdog clock needs to be enabled first. Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
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44262327 |
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15-Dec-2017 |
Ahmed Mansour <ahmed.mansour@nxp.com> |
drivers/misc: Share qbman init between archs This patch adds changes necessary to move functionality present in PowerPC folders with ARM architectures that have DPAA1 QBMan hardware - Create new board/freescale/common/fsl_portals.c to house shared device tree fixups for DPAA1 devices with ARM and PowerPC cores - Add new header file to top includes directory to allow files in both architectures to grab the function prototypes - Port inhibit_portals() from PowerPC to ARM. This function is used in setup to disable interrupts on all QMan and BMan portals. It is needed because the interrupts are enabled by default for all portals including unused/uninitialised portals. When the kernel attempts to go to deep sleep the unused portals prevent it from doing so Signed-off-by: Ahmed Mansour <ahmed.mansour@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
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a8f33034 |
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03-Dec-2017 |
Wenbin song <wenbin.song@nxp.com> |
armv8: ls1043a/ls2080a: check SoC by device ID Check LS1043A/LS2080a by device ID without using personality ID to determine revision number. This check applies to all various personalities of the same SoC family. Signed-off-by: Wenbin Song <wenbin.song@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
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2db53cfe |
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09-Nov-2017 |
Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
armv8: fsl-layerscape: Add support of disabling core prefetch Instruction prefetch feature is by default enabled during core release. This patch add support of disabling instruction prefetch by setting core mask in PPA. Here each core mask bit represents a core and prefetch is disabled at the time of core release. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
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7eb40f0f |
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28-Sep-2017 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: Avoid running dram_init_banksize again gd->ram_size is reduced in this function to reserve secure memory. Avoid running this function again to further reduce memory size. This fixes issue for SPL boot with PPA image loaded in which case secure memory is incorrectly allocated due to repeated calling. Signed-off-by: York Sun <york.sun@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
710d0cd7 |
|
03-Oct-2017 |
Sumit Garg <sumit.garg@nxp.com> |
armv8: fsl-layerscape: Allocate Secure memory from first ddr region This change is required due to trusted OS (OP-TEE) not being position independent code, it requires compile time fixed base address. To take care of this it is assumed that all layerscape armv8 platforms has minimum 2G ddr in first region. So we can have fixed address space (66 MB -> (2MB for PPA + 64MB for trusted OS)) allocated from top of first 2G ddr region and compile trusted OS with this fixed base address. But one exception here is ls1012 where we have only 1G (rdb) or 512M (frdm) ddr memory. For those we can have different fixed compile time base addresses for trusted OS. Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
e9303a41 |
|
07-Sep-2017 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: Fix MC reserved memory calculation In case high region memory doesn't have enough space for Management Complex (MC), the return value should indicate a failure so the caller can handle it accordingly. Signed-off-by: York Sun <york.sun@nxp.com> Reported-by: Ebony Zhu <ebony.zhu@nxp.com> |
#
17d066fc |
|
31-Aug-2017 |
Ashish Kumar <Ashish.Kumar@nxp.com> |
armv8: fsl-layerscape: Support to add RGMII for ls1088aqds This patch adds support for RGMII protocol NXP's LDPAA2 support RGMII protocol. LS1088A is the first Soc supporting both RGMII and SGMII. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Amrita Kumari <amrita.kumari@nxp.com> Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
63b2316c |
|
10-Aug-2017 |
Ashish Kumar <Ashish.Kumar@nxp.com> |
fsl-layerscape: Consolidate registers space defination for CCI-400 bus CoreLink Cache Coherent Interconnect (CCI) provides full cache coherency between two clusters of multi-core CPUs and I/O coherency for devices and I/O masters. This patch add new config option SYS_FSL_HAS_CCI400 and moves existing register space definaton of CCI-400 bus to fsl_immap to be shared. CONFIG_SYS_CCI400_ADDR is replaced with SYS_CCI400_OFFSET in Kconfig. Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> [YS: revised commit message, squashed patches for armv8 and armv7] Reviewed-by: York Sun <york.sun@nxp.com> |
#
6e2941d7 |
|
17-May-2017 |
Simon Glass <sjg@chromium.org> |
common: freescale: Move arch-specific declarations The declarations should not be in common.h. Move them to the arch-specific headers. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Fixup thinko defined(FSL_LSCH3) -> defined(CONFIG_FSL_LSCH3)] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
399e2bb6 |
|
15-May-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Make U-Boot EL2 safe When U-Boot boots from EL2, skip some lowlevel init code requiring EL3, including CCI-400/CCN-504, trust zone, GIC, etc. These initialization tasks are carried out before U-Boot runs. This applies to the RAM version image used for SPL boot if PPA is loaded first. Signed-off-by: York Sun <york.sun@nxp.com> |
#
1f55a938 |
|
05-May-2017 |
Santan Kumar <santan.kumar@nxp.com> |
armv8: ls2080aqds: Add support for SD boot Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
e809e747 |
|
27-Apr-2017 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: fsl-layerscape: Add NXP LS2081A, LS2041A SoC support The QorIQ LS2081A SoC has eight 64-bit ARM v8 Cortex A72 cores and is built on layerscape architecture. It is 40-pin derivative of LS2084A (non-AIOP personality of LS2088A). So feature-wise it is same as LS2084A. LS2041A is a 4-core personality of LS2081A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
026f30ec |
|
18-Apr-2017 |
Yuantian Tang <andy.tang@nxp.com> |
arm: psci: make psci usable on single core socs PSCI can be used on both multiple and single core socs. Current implementation only allows PSCI to work on multiple core socs. This patch removes this restriction so that PSCI can work on single core socs as well. Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
4a3ab193 |
|
27-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: ls2080a: Drop macro CONFIG_LS2080A Use CONFIG_ARCH_LS2080A instead. Signed-off-by: York Sun <york.sun@nxp.com> |
#
3eace37e |
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06-Apr-2017 |
Simon Glass <sjg@chromium.org> |
arm: freescale: Rename initdram() to fsl_initdram() This function name shadows a global name but is in fact different. This is very confusing. Rename it to help with the following refactoring. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
76b00aca |
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31-Mar-2017 |
Simon Glass <sjg@chromium.org> |
board_f: Drop setup_dram_config() wrapper By making dram_init_banksize() return an error code we can drop the wrapper. Adjust this and clean up all implementations. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
088454cd |
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31-Mar-2017 |
Simon Glass <sjg@chromium.org> |
board_f: Drop return value from initdram() At present we cannot use this function as an init sequence call without a wrapper, since it returns the RAM size. Adjust it to set the RAM size in global_data instead, and return 0 on success. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
52c41180 |
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31-Mar-2017 |
Simon Glass <sjg@chromium.org> |
board_f: Drop board_type parameter from initdram() It looks like only cm5200 and tqm8xx use this feature, so we don't really need it in generic code. Drop it and have the users access gd->board_type directly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
3d8553f0 |
|
02-Mar-2017 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
pci: layerscape: add LS2088A series SoC pcie support The LS2088A series SoCs has different physical memory map address and CCSR registers address against LS2080A series SoCs. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
eea1cb77 |
|
13-Feb-2017 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8/fsl-layerscape: Update erratum A009635 implementation Erratum A009635 is valid only for LS2080A SoC and its personality. Add SoC svr check. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
4961eafc |
|
06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Update early MMU for DDR after initialization In early MMU table, DDR has to be mapped as device memory to avoid speculative access. After DDR is initialized, it needs to be updated to normal memory to allow code execution. To simplify the code, dram_init() is moved into a common file as a weak function. Signed-off-by: York Sun <york.sun@nxp.com> |
#
a045a0c3 |
|
06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Fix the sequence of changing MMU table This patch follows the break-before-make process when making changes to MMU table. MMU is disabled before changing TTBR to avoid any potential race condition. Signed-off-by: York Sun <york.sun@nxp.com> |
#
24f55496 |
|
06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Update MMU mapping with actual DDR size Update mapping with actual DDR size. Non-existing memory should not be mapped as "normal" memory to avoid speculative access. Signed-off-by: York Sun <york.sun@nxp.com> |
#
36cc0de0 |
|
06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Rewrite memory reservation For ARMv8 Layerscape SoCs, secure memory and MC memorey are reserved at the end of DDR. DDR is spit into two or three banks. This patch reverts commit aabd7ddb and simplifies the calculation of reserved memory, and moves the code into common SoC file. Secure memory is carved out first. DDR bank size is reduced. Reserved memory is then allocated on the top of available memory. U-Boot still has access to reserved memory as data transferring is needed. Device tree is fixed with reduced memory size to hide the reserved memory from OS. The same region is reserved for efi_loader. Signed-off-by: York Sun <york.sun@nxp.com> |
#
daa92644 |
|
16-Jan-2017 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
ARMv8/sec_firmware: relocated and renamed the config FSL_PPA_ARMV8_PSCI Moved the config FSL_PPA_ARMV8_PSCI from fsl-layerscape's Kconfig to Kconfig under armv8 and renamed it to SEC_FIRMWARE_ARMV8_PSCI. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
904110c7 |
|
10-Jan-2017 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8/fsl-lsch2: refactor the clock system initialization Up to now, there are 3 kind of SoCs under Layerscape Chassis 2, like LS1043A, LS1046A and LS1012A. But the clocks tree has a lot of differences, for instance, the IP modules have different dividers to derive its clock from Platform PLL. And the core cluster PLL and platform PLL maybe have different reference clocks, such as LS1012A. Another problem is which clock/PLL should be described by sys_info->freq_systembus, it is confused in Layerscape Chissis 2. This patch is to bind the sys_info->freq_systembus to the Platform PLL, and handle the different divider of IP modules separately between different SoCs, and separate reference clocks of core cluster PLL and platform PLL. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
2d16a1a6 |
|
07-Dec-2016 |
macro.wave.z@gmail.com <macro.wave.z@gmail.com> |
ARMv8: LS1043A: change macro CONFIG_ARMV8_PSCI definition NXP/Freescale uses macro CONFIG_ARMV8_PSCI to enable their private PSCI implementation in PPA firmware, but this macro naming too generic, so this patch replaces it with a specic one CONFIG_FSL_PPA_ARMV8_PSCI. And this macro CONFIG_ARMV8_PSCI will be used for a generic PSCI for ARMv8 which will be added in following patchs. Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
02fb2761 |
|
20-Nov-2016 |
Shengzhou Liu <Shengzhou.Liu@nxp.com> |
fsl/ddr: Add erratum_a009942_check_cpo and clean related erratum - add additional function erratum_a009942_check_cpo to check if the board needs tuning CPO calibration for optimal setting. - move ERRATUM_A009942(with revision to check cpo_sample option) from fsl_ddr_gen4.c to ctrl_regs.c for reuse on all DDR4/DDR3 parts. - move ERRATUM_A008378 from fsl_ddr_gen4.c to ctrl_regs.c - remove obsolete ERRATUM_A004934 which is replaced with ERRATUM_A009942. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> [YS: Replaced CONFIG_QEMU_E500 with CONFIG_ARCH_QEMU_E500] Reviewed-by: York Sun <york.sun@nxp.com> |
#
e87c673c |
|
16-Nov-2016 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8/fsl-lsch3: Update code to release secondary cores NXP ARMv8 SoC LS2080A release all secondary cores in one-go. But other new SoCs like LS2088A, LS1088A release secondary cores one by one. Update code to release secondary cores based on SoC SVR Add code to release cores one by one for non LS2080A SoCs Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> [YS: remove "inline" from declaration of initiator_type] Reviewed-by: York Sun <york.sun@nxp.com> |
#
f6b96ff6 |
|
16-Nov-2016 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Use SVR based timer base address detection Timer controller base address has been changed from LS2080A SoC (and its personalities) to new SoCs like LS2088A, LS1088A. Use SVR based timer base address detection to avoid compile time #ifdef. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
f6a70b3a |
|
16-Nov-2016 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add generic get_svr() in assembly Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
78d57842 |
|
16-Nov-2016 |
Alexander Graf <agraf@csgraf.de> |
armv8: fsl-layerscape: Add support for efi_loader RTS reset When implementing efi loader support, we can expose runtime services for payloads. One such service is CPU reset. This patch implements RTS CPU reset support for layerscape systems. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: York Sun <york.sun@nxp.com> |
#
ef9a5fd8 |
|
13-Sep-2016 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: Fix "cpu status" command The core position is not continuous for some SoCs. For example, valid cores may present at position 0, 1, 4, 5, 8, 9, etc. Some registers (including boot release register) only count existing cores. Current implementation of cpu_mask() complies with the continuous numbering. However, command "cpu status" queries the spin table with actual core position. Add functions to calculate core position from core number, to correctly calculate offsets. Tested on LS2080ARDB and LS1043ARDB. Signed-off-by: York Sun <york.sun@nxp.com> |
#
5d1a7a9d |
|
13-Sep-2016 |
Wenbin Song <wenbin.song@nxp.com> |
armv8/fsl-layerscape: print SoC revsion number The exact SoC revsion number can be recognized from U-Boot log. Signed-off-by: Wenbin Song <wenbin.song@nxp.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
cbe7706a |
|
26-Sep-2016 |
Tom Rini <trini@konsulko.com> |
Merge git://git.denx.de/u-boot-fsl-qoriq trini: Drop local memset() from examples/standalone/mem_to_mem_idma2intr.c Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
1221ce45 |
|
20-Sep-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
treewide: replace #include <asm/errno.h> with <linux/errno.h> Now, arch/${ARCH}/include/asm/errno.h and include/linux/errno.h have the same content. (both just wrap <asm-generic/errno.h>) Replace all include directives for <asm/errno.h> with <linux/errno.h>. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> [trini: Fixup include/clk.] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
b63a9506 |
|
03-Aug-2016 |
York Sun <york.sun@nxp.com> |
armv8: ls2080a: Remove debug server support Debug server feature has been dropped from roadmap. Signed-off-by: York Sun <york.sun@nxp.com> |
#
ed7a3943 |
|
22-Jul-2016 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: mmu: Fix enabling MMU MMU bit in SCTLR needs to be set explicitly after tables are created. It isn't an issue for EL3 becuase this bit is already set by early MMU setup. But for other exception levels this bit was not set. Signed-off-by: York Sun <york.sun@nxp.com> |
#
79119a4d |
|
05-Jul-2016 |
Alison Wang <b18965@freescale.com> |
armv8: fsl-layerscape: Add A72 core detection Add support to detect Cortex-A72 core for printing it out. The Initiator Version of A72 core should be 0x4. Signed-off-by: Alison Wang <alison.wang@nxp.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
032d5bb4 |
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28-Jun-2016 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
ARMv8/Layerscape: switch SMP method accordingly If the PSCI and PPA is ready, skip the fixup for spin-table and waking secondary cores. Otherwise, change SMP method to spin-table, and the device node of PSCI will be removed. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
85cdf38e |
|
28-Jun-2016 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: fsl-layerscape: add i/d-cache enable function to enable_caches This function assume that the d-cache and MMU has been enabled earlier, so it just created MMU table in main memory. But the assumption is not always correct, for example, the early setup is done in EL3, while enable_caches() is called when the PE has turned into another EL. Define the function mmu_setup() for fsl-layerscape to cover the weak one. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
5ad5823d |
|
24-Jun-2016 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Convert to use common MMU framework Drop platform code to create static MMU tables. Use common framework to create MMU tables on the run. Tested on LS2080ARDB with secure and non-secure ram scenarios. Signed-off-by: York Sun <york.sun@nxp.com> |
#
e61a7534 |
|
24-Jun-2016 |
York Sun <york.sun@nxp.com> |
armv8: Move secure_ram variable out of generic global data Secure_ram variable was put in generic global data. But only ARMv8 uses this variable. Move it to ARM specific data structure. Signed-off-by: York Sun <york.sun@nxp.com> |
#
a10a31ec |
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18-Jun-2016 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of git://git.denx.de/u-boot-usb Signed-off-by: Tom Rini <trini@konsulko.com> Conflicts: arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
|
#
6fb522dc |
|
12-Jun-2016 |
Sriram Dash <sriram.dash@nxp.com> |
arm64: fsl-layerscape: add get_svr and IS_SVR_REV helper Adds get_svr and IS_SVR_REV helpers for ARMv8 platforms, similar to PPC and ARMv7. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> |
#
a758177f |
|
07-Jun-2016 |
Yunhui Cui <yunhui.cui@nxp.com> |
armv8/ls2080a: configure PMU's PCTBENR to enable WDT The SP805-WDT module on LS2080A requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. The watchdog clock needs to be enabled first. Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
acb8f5e9 |
|
21-Apr-2016 |
Alison Wang <b18965@freescale.com> |
armv8: fsl-layerscape: Remove unnecessary flushing dcache As the issue about the stack will get corrupted when switching between the early and final mmu tables is fixed by commit 70e21b064, the workaround to flush dcache is unnecessary and should be removed. Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
3c1d218a |
|
04-Apr-2016 |
York Sun <york.sun@nxp.com> |
armv8: LS2080A: Consolidate LS2080A and LS2085A LS2080A is the primary SoC, and LS2085A is a personality with AIOP and DPAA DDR. The RDB and QDS boards support both personality. By detecting the SVR at runtime, a single image per board can support both SoCs. It gives users flexibility to swtich SoC without the need to reprogram the board. Signed-off-by: York Sun <york.sun@nxp.com> CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
c05016ab |
|
21-Mar-2016 |
Alexander Graf <agraf@csgraf.de> |
arm64: Fix layerscape mmu setup With commit 7985cdf we converted all systems except for the Layerscape SoCs to the generic descriptor table based page table setup. On the Layerscape SoCs however, we just provide an empty table stub and do the setup ourselves. To reserve enough memory for the tables, we need to override the default counting mechanism which would end up with an empty table because we have no maps. Fixes: 7985cdf Reported-by: York Sun <york.sun@nxp.com> CC: Alison Wang <alison.wang@nxp.com> CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Alexander Graf <agraf@suse.de> Tested-by: York Sun <york.sun@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
7985cdf7 |
|
03-Mar-2016 |
Alexander Graf <agraf@csgraf.de> |
arm64: Remove non-full-va map code By now the code to only have a single page table level with 64k page size and 42 bit address space is no longer used by any board in tree, so we can safely remove it. To clean up code, move the layerscape mmu code to the new defines, removing redundant field definitions. Signed-off-by: Alexander Graf <agraf@suse.de> |
#
c0492141 |
|
07-Dec-2015 |
York Sun <yorksun@freescale.com> |
armv8: fsl-layerscale: Rewrite reserving memory for MC and debug server MC and debug server are not board-specific. Move reserving memory to SoC file, using the new board_reserve_ram_top function. Reduce debug server memory by 2MB to make room for secure memory. In the system with MC and debug server, the top of u-boot memory is not the end of memory. PRAM is not used for this reservation. Signed-off-by: York Sun <yorksun@freescale.com> |
#
c107c0c0 |
|
04-Dec-2015 |
York Sun <yorksun@freescale.com> |
armv8: fsl-layerscape: Make DDR non secure in MMU tables DDR has been set as secure in MMU tables. Non-secure master such as SDHC DMA cannot access data correctly. Mixing secure and non- secure MMU entries requirs the MMU tables themselves in secure memory. This patch moves MMU tables into a secure DDR area. Early MMU tables are changed to set DDR as non-secure. A new table is added into final MMU tables so secure memory can have 2MB granuality. gd->secure_ram tracks the location of this secure memory. For ARMv8 SoCs, the RAM base is not zero and RAM is divided into several banks. gd->secure_ram needs to be maintained before using. This maintenance is board-specific, depending on the SoC and memory bank of the secure memory falls into. Signed-off-by: York Sun <yorksun@freescale.com> |
#
b4017364 |
|
04-Nov-2015 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
armv8: ls2085a: Add workaround of errata A009635 If the core runs at higher than x3 speed of the platform, there is possiblity about sev instruction to getting missed by other cores. This is because of SoC Run Control block may not able to sample the EVENTI(Sev) signals. Configure Run Control and EPU to periodically send out EVENTI signals to wake up A57 cores. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
d764129d |
|
04-Nov-2015 |
Alison Wang <b18965@freescale.com> |
armv8/layerscape: Update MMU table with execute-never bits For most device addresses excution shouldn't be allowed. Revise the MMU table to enforce execute-never bits. OCRAM, DDR and IFC are allowed for excution. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Alison Wang <alison.wang@freescale.com> Reported-by: Zhichun Hua <zhichun.hua@freescale.com> |
#
44937214 |
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09-Nov-2015 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
armv8: LS2080A: Rename LS2085A to reflect LS2080A LS2080A is a prime personality of Freescale’s LS2085A. It is a non-AIOP personality without support of DP-DDR, L2 switch, 1588, PCIe endpoint etc. So renaming existing LS2085A code base to reflect LS2080A (Prime personality) Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> [York Sun: Dropped #ifdef in cpu.c for cpu_type_list] Reviewed-by: York Sun <yorksun@freescale.com> |
#
e8297341 |
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26-Oct-2015 |
Shaohui Xie <Shaohui.Xie@freescale.com> |
armv8/ls1043a: Add Fman support Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
8281c58f |
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26-Oct-2015 |
Mingkai Hu <Mingkai.Hu@freescale.com> |
armv8/fsl_lsch2: Add fsl_lsch2 SoC Freescale LayerScape with Chassis Generation 2 is a set of SoCs with ARMv8 cores and 2rd generation of Chassis. Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
9f3183d2 |
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26-Oct-2015 |
Mingkai Hu <Mingkai.Hu@freescale.com> |
armv8/fsl_lsch3: Change arch to fsl-layerscape There are two LS series processors are built on ARMv8 Layersacpe architecture currently, LS2085A and LS1043A. They are based on ARMv8 core although use different chassis, so create fsl-layerscape to refactor the common code for the LS series processors which also paves the way for adding LS1043A platform. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
6e7df1d1 |
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10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
global: Finish CONFIG -> CFG migration At this point, the remaining places where we have a symbol that is defined as CONFIG_... are in fairly odd locations. While as much dead code has been removed as possible, some of these locations are simply less obvious at first. In other cases, this code is used, but was defined in such a way as to have been missed by earlier checks. Perform a rename of all such remaining symbols to be CFG_... rather than CONFIG_... Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
1d457dbb |
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04-Dec-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_MAX_MEM_MAPPED to CFG Perform a simple rename of CONFIG_MAX_MEM_MAPPED to CFG_MAX_MEM_MAPPED Signed-off-by: Tom Rini <trini@konsulko.com> |
#
4fd9373b |
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02-Dec-2022 |
Tom Rini <trini@konsulko.com> |
net: Remove more legacy functions Remove some of the board and arch specific non-DM_ETH helper code. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
65cc0e2a |
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16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
aa6e94de |
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16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
ecc8d425 |
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16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_PCI* to CFG_SYS_PCI* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_PCI and CONFIG_SYS_PCIE namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
6cc04547 |
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28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
8fd11135 |
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25-Sep-2022 |
Sean Anderson <sean.anderson@seco.com> |
arm64: layerscape: Support SYSRESET CONFIG_SYSRESET provides its own implementation of reset_cpu. Disable our version when it is enabled. Signed-off-by: Sean Anderson <sean.anderson@seco.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> |
#
ce9c579e |
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13-Jun-2022 |
Andre Przywara <andre.przywara@arm.com> |
armv8: always use current exception level for TCR_ELx access Currently get_tcr() takes an "el" parameter, to select the proper version of the TCR_ELx system register. This is problematic in case of the Apple M1, since it runs with HCR_EL2.E2H fixed to 1, so TCR_EL2 is actually using the TCR_EL1 layout, and we get the wrong version. For U-Boot's purposes the only sensible choice here is the current exception level, and indeed most callers treat it like that, so let's remove that parameter and read the current EL inside the function. This allows us to check for the E2H bit, and pretend it's EL1 in this case. There are two callers which don't care about the EL, and they pass 0, which looks wrong, but is irrelevant in these two cases, since we don't use the return value there. So the change cannot affect those two. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Mark Kettenis <kettenis@openbsd.org> Tested-by: Mark Kettenis <kettenis@openbsd.org> |
#
cda8f873 |
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11-May-2022 |
Ye Li <ye.li@nxp.com> |
caam: Fix crash in case caam_jr_probe failed If probing caam_jr returns failure, the variable "dev" will not be initialized, so we can't use dev->name for the error print. Otherwise it will cause crash. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Gaurav Jain <gaurav.jain@nxp.com> |
#
cb14cc88 |
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22-Apr-2022 |
Michael Walle <michael@walle.cc> |
armv8: layerscape: get rid of smc_call() There are two different implementations to do a secure monitor call: smc_call() and arm_smccc_smc(). The former is defined in fwcall.c and seems to be an ad-hoc implementation. The latter is imported from linux. smc_call() is also only available if CONFIG_ARMV8_PSCI is not defined. This makes it impossible to have both PSCI calls and PSCI implementation in one u-boot build. The layerscape SoC code decide at runtime via check_psci() if there is a PSCI support. Therefore, this is a prerequisite patch to add PSCI implementation support for the layerscape SoCs. Note, for the TFA part, this is only compile time tested with (ls1028ardb_tfa_defconfig). Signed-off-by: Michael Walle <michael@walle.cc> [Rebased] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
dfb6da55 |
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05-Apr-2022 |
Marek Vasut <marex@denx.de> |
armv8: layerscape: env: Switch to arch_env_get_location() Implement arch_env_get_location() instead of env_get_location(), so that the env_get_location() can be implemented on board level and override the arch_env_get_location() architecture defaults. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Adam Ford <aford173@gmail.com> Cc: Fabio Estevam <festevam@denx.de> Cc: Marek Behún <marek.behun@nic.cz> Cc: Peng Fan <peng.fan@nxp.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefano Babic <sbabic@denx.de> Cc: Tim Harvey <tharvey@gateworks.com> Cc: Tom Rini <trini@konsulko.com> Cc: Tommaso Merciai <tomm.merciai@gmail.com> Cc: Vladimir Oltean <vladimir.oltean@nxp.com> |
#
8976556a |
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24-Mar-2022 |
Gaurav Jain <gaurav.jain@nxp.com> |
Layerscape: Enable Job ring driver model. LS(1021/1012/1028/1043/1046/1088/2088), LX2160, LX2162 platforms are enabled with JR driver model. removed sec_init() call from board files. sec is initialized based on job ring information processed from device tree. Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Michael Walle <michael@walle.cc> |
#
f9147d63 |
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25-Feb-2022 |
Tom Rini <trini@konsulko.com> |
Convert CONFIG_CHIP_SELECTS_PER_CTRL to Kconfig This converts the following to Kconfig: CONFIG_CHIP_SELECTS_PER_CTRL Cc: Alison Wang <alison.wang@nxp.com> Cc: Pramod Kumar <pramod.kumar_1@nxp.com> Cc: Priyanka Jain <priyanka.jain@nxp.com> Cc: Rajesh Bhagat <rajesh.bhagat@nxp.com> Cc: Vladimir Oltean <olteanv@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
2f8a6db5 |
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14-Dec-2021 |
Tom Rini <trini@konsulko.com> |
Finish conversion of CONFIG_SYS_CLK_FREQ to Kconfig In order to finish moving this symbol to Kconfig for all platforms, we need to do a few more things. First, for all platforms that define this to a function, introduce CONFIG_DYNAMIC_SYS_CLK_FREQ, similar to CONFIG_DYNAMIC_DDR_CLK_FREQ and populate clock_legacy.h. This entails also switching all users from CONFIG_SYS_CLK_FREQ to get_board_sys_clk() and updating a few preprocessor tests. With that done, all platforms that define a value here can be converted to Kconfig, and a fall-back of zero is sufficiently safe to use (and what is used today in cases where code may or may not have this available). Make sure that code which calls this function includes <clock_legacy.h> to get the prototype. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
77b11f76 |
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18-Sep-2021 |
Vladimir Oltean <vladimir.oltean@nxp.com> |
net: replace the "xfi" phy-mode with "10gbase-r" As part of the effort of making U-Boot work with the same device tree as Linux, there is an issue with the "xfi" phy-mode. To be precise, in Linux there was a discussion (for those who have time to read: https://lore.kernel.org/netdev/1576768881-24971-2-git-send-email-madalin.bucur@oss.nxp.com/) which led to a patch: https://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next.git/commit/?id=c114574ebfdf42f826776f717c8056a00fa94881 TL;DR: "xfi" was standardized in Linux as "10gbase-r". This patch changes the relevant occurrences in U-Boot to use "10gbase-r" instead of "xfi" wherever applicable. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> |
#
84c2e044 |
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20-Apr-2021 |
Jiafei Pan <Jiafei.Pan@nxp.com> |
armv8: layerscape: add PSCI support for cpu release For cpu release command, check whether PSCI is supported firstly, if supported, use PSCI to kick off secondary cores, otherwise still use spin table. Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com> [Fixed checkpatch alignment CHECKs] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
35b65dd8 |
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15-Dec-2020 |
Harald Seiler <hws@denx.de> |
reset: Remove addr parameter from reset_cpu() Historically, the reset_cpu() function had an `addr` parameter which was meant to pass in an address of the reset vector location, where the CPU should reset to. This feature is no longer used anywhere in U-Boot as all reset_cpu() implementations now ignore the passed value. Generic code has been added which always calls reset_cpu() with `0` which means this feature can no longer be used easily anyway. Over time, many implementations seem to have "misunderstood" the existence of this parameter as a way to customize/parameterize the reset (e.g. COLD vs WARM resets). As this is not properly supported, the code will almost always not do what it is intended to (because all call-sites just call reset_cpu() with 0). To avoid confusion and to clean up the codebase from unused left-overs of the past, remove the `addr` parameter entirely. Code which intends to support different kinds of resets should be rewritten as a sysreset driver instead. This transformation was done with the following coccinelle patch: @@ expression argvalue; @@ - reset_cpu(argvalue) + reset_cpu() @@ identifier argname; type argtype; @@ - reset_cpu(argtype argname) + reset_cpu(void) { ... } Signed-off-by: Harald Seiler <hws@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
401d1c4f |
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30-Oct-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop asm/global_data.h from common header Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
3a187cff |
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29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
c760095a |
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23-Oct-2020 |
Razvan Ionut Cirjan <razvanionut.cirjan@nxp.com> |
net: lx2160a.c: Update to set ECx_PMUX precedence As per hardware documentation, ECx_PMUX has precedence over SerDes protocol. For LX2160/LX2162 if DPMACs 17 and 18 are enabled as SGMII through SerDes protocol but ECx_PMUX configured them as RGMII, then the ports will be configured as RGMII and not SGMII. Signed-off-by: Razvan Ionut Cirjan <razvanionut.cirjan@nxp.com> [Rebased] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
d31f3a1b |
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09-Sep-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2160a: fix reset sequence Make sure that SW_RST_REQ and RST_REQ_MSK are cleared before triggering hardware reset request. Signed-off-by: Thirupathaiah Annapureddy <thiruan@linux.microsoft.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
b75d8dc5 |
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26-Jun-2020 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
treewide: convert bd_t to struct bd_info by coccinelle The Linux coding style guide (Documentation/process/coding-style.rst) clearly says: It's a **mistake** to use typedef for structures and pointers. Besides, using typedef for structures is annoying when you try to make headers self-contained. Let's say you have the following function declaration in a header: void foo(bd_t *bd); This is not self-contained since bd_t is not defined. To tell the compiler what 'bd_t' is, you need to include <asm/u-boot.h> #include <asm/u-boot.h> void foo(bd_t *bd); Then, the include direcective pulls in more bloat needlessly. If you use 'struct bd_info' instead, it is enough to put a forward declaration as follows: struct bd_info; void foo(struct bd_info *bd); Right, typedef'ing bd_t is a mistake. I used coccinelle to generate this commit. The semantic patch that makes this change is as follows: <smpl> @@ typedef bd_t; @@ -bd_t +struct bd_info </smpl> Signed-off-by: Masahiro Yamada <masahiroy@kernel.org> |
#
25a5818f |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop asm/ptrace.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
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f7ae49fc |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
90526e9f |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop net.h from common header Move this header out of the common header. Network support is used in quite a few places but it still does not warrant blanket inclusion. Note that this net.h header itself has quite a lot in it. It could be split into the driver-mode support, functions, structures, checksumming, etc. Signed-off-by: Simon Glass <sjg@chromium.org> |
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714497e3 |
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16-May-2020 |
Michael Walle <michael@walle.cc> |
efi_loader: round the memory area in efi_add_memory_map() Virtually all callers of this function do the rounding on their own. Some do it right, some don't. Instead of doing this in each caller, do the rounding in efi_add_memory_map(). Change the size parameter to bytes instead of pages and remove aligning and size calculation in all callers. There is no more need to make the original efi_add_memory_map() (which takes pages as size) available outside the module. Thus rename it to efi_add_memory_map_pg() and make it static to prevent further misuse outside the module. Signed-off-by: Michael Walle <michael@walle.cc> Add missing comma in sunxi_display.c. Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de> |
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6eb32a03 |
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23-Apr-2020 |
Madalin Bucur <madalin.bucur@oss.nxp.com> |
driver: net: fm: add DM ETH support Probe the FMan MACs based on the device tree while retaining the legacy code/functionality. One notable change introduced here is that, for DM_ETH, the name of the interfaces is corrected to the fmX-macY format, that avoids the referral to the MAC block names which were incorrect for FMan v3 devices (i.e. DTSEC, TGEC) and had weird formatting (i.e. FM1@DTSEC6, FM1@TGEC1). The legacy code is left unchanged in this respect. Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
6ebd4883 |
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27-Apr-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
fsl-layerscape: Add RESV_RAM check in resv_ram addr The initialization of gd->arch.resv_ram pointer should depend on if the RESV_RAM config is enabled. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Wasim Khan <wasim.khan@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
0d9d557d |
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10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
db41d65a |
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28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move hang() to the same header as panic() At present panic() is in the vsprintf.h header file. That does not seem like an obvious choice for hang(), even though it relates to panic(). So let's put hang() in its own header. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Migrate a few more files] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
9b4a205f |
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28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move RAM-sizing functions to init.h These functions relate to memory init so move them into the init header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
3499dd03 |
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27-Nov-2019 |
Alex Marginean <alexandru.marginean@nxp.com> |
ls1028a: Configure stream IDs for integrated PCI and fix up Linux DT Hardware comes out of reset with implicit values, but these are outside the accepted range for Layerscape gen 3 chassis spec used on LS1028A. Allocate different IDs and fix up Linux DT to use them. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
b5981474 |
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14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some CPU functions out of common.h These functions belong in cpu_func.h since they do not use driver model. Move them over. Don't bother adding comments since these functions should be deleted. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
68a6aa85 |
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14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move mii_init() function out of common.h This function belongs in mii.h so move it over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
2189d5f1 |
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14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
Move strtomhz() to vsprintf.h At present this function sits in its own file but it does not really justify it. There are similar string functions in vsprintf.h, so move it there. Also add the missing function comment. Use the vsprintf.h include file explicitly where needed. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
812ff53c |
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30-Oct-2019 |
Pankaj Bansal <pankaj.bansal@nxp.com> |
fsl-layerscape: fix warning if no hwconfig is defined While getting the 'subarg' of 'hwconfig' env variable in config_core_prefetch(), if no hwconfig variable is defined, below warning is received: WARNING: Calling __hwconfig without a buffer and before environment is ready Fix this by checking 'hwconfig' env variable. If not found return without further processing. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Tested-by: Michael Walle <michael@walle.cc> |
#
28f9393b |
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17-Oct-2019 |
Mathew McBride <matt@traverse.com.au> |
fsl-layerscape: do not use layerscape EFI reset if PSCI used If the secure world reset handlers are used (via CONFIG_PSCI_RESET), then do not use the layerscape-specific implementation. Signed-off-by: Mathew McBride <matt@traverse.com.au> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
6ed69523 |
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18-Sep-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add more personalities support Add LS1027A, LS1018A and LS1017A personalities support to LS1028A SoC family. LS1028A is the prime personality of LS1028A SoC family. LS1027A is a lower funtionality version of QorIQ LS1028A which does not support the multimedia subsystems, such as LCD controller, GPU, and eDP PHY. The QorIQ LS1018A and LS1017A SoCs are single 64-bit Arm A72 core, low power versions of the QorIQ LS1028A and LS1027A SoCs respectively. Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
0490cab5 |
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08-Aug-2019 |
Thomas Schaefer <thomas.schaefer@kontron.com> |
armv8: ls1028a: configure PMU's PCTBENR to enable WDT The SP805-WDT module on LS1028A requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. The watchdog clock needs to be enabled first. Signed-off-by: Thomas Schaefer <thomas.schaefer@kontron.com> Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
f3998fdc |
|
02-Aug-2019 |
Simon Glass <sjg@chromium.org> |
env: Rename environment.h to env_internal.h This file contains lots of internal details about the environment. Most code can include env.h instead, calling the functions there as needed. Rename this file and add a comment at the top to indicate its internal nature. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> [trini: Fixup apalis-tk1.c] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
3a7d5571 |
|
01-Aug-2019 |
Simon Glass <sjg@chromium.org> |
env: Move env_get_f() to env.h Move this function over to the new header file. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
d9532e80 |
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23-Apr-2019 |
Udit Agarwal <udit.agarwal@nxp.com> |
armv8: fsl-layerscape: Set env_loc to ENVL_NOWHERE with CONFIG_ENV_IS_NOWHERE. ENVL_NOWHERE is dependent on CONFIG_ENV_IS_NOWHERE and not on CONFIG_CHAIN_OF_TRUST so return ENVL_NOWHERE when CONFIG_ENV_IS_NOWHERE is enabled Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
d4ad111d |
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10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
059d9422 |
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08-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: lx2160a: add MMU table entries for PCIe The lx2160a have up to 6 PCIe controllers and have different address and size of PCIe region. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
8348e798 |
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08-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: layerscape: use PCIe address macro for precompile PCIe MMU entry Change to use PCIe address macro to determine if precompile the PCIe MMU table entry. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
10015025 |
|
03-May-2019 |
Trevor Woerner <trevor@toganlabs.com> |
CONFIG_SPL_SYS_[DI]CACHE_OFF: add While converting CONFIG_SYS_[DI]CACHE_OFF to Kconfig, there are instances where these configuration items are conditional on SPL. This commit adds SPL variants of these configuration items, uses CONFIG_IS_ENABLED(), and updates the configurations as required. Acked-by: Alexey Brodkin <abrodkin@synopsys.com> Signed-off-by: Trevor Woerner <trevor@toganlabs.com> [trini: Make the default depend on the setting for full U-Boot, update more zynq hardware] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
2e53759d |
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29-Oct-2018 |
Pankaj Bansal <pankaj.bansal@nxp.com> |
armv8: fsl-layerscape: reorder rgmii dpmacs' enablement some dpmacs in armv8a based freescale layerscape SOCs can be configured via both serdes(sgmii, xfi, xlaui etc) bits and via EC*_PMUX(rgmii) bits in RCW. e.g. dpmac 17 and 18 in LX2160A can be configured as SGMII from serdes bits and as RGMII via EC1_PMUX/EC2_PMUX bits Now if a dpmac is enabled by serdes bits then it takes precedence over EC*_PMUX bits. i.e. in LX2160A if we select serdes protocol that configures dpmac17 as SGMII and set the EC1_PMUX as RGMII, then the dpmac is SGMII and not RGMII. Therefore, move the fsl_rgmii_init after fsl_serdes_init. in fsl_rgmii_init function of SOC, we will check if the dpmac is enabled or not? if it is (fsl_serdes_init has already enabled the dpmac), then don't enable it. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
ec88ff80 |
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19-Dec-2018 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1043a: add SVR definitions for 23x23 package silicon LS1043A/LS1023A 23x23 package silicon has different SVR:VAR_PER. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
d23da2ae |
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26-Dec-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: fixes for TFABOOT framework Fixes for TFABOOT framework - update eMMC bootsrc to SD_MMC - Increase buffer size for mcinitcmd from 256 to 512 - Fix mcinitcmd and bootcmd for Secure Boot Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
4909b89e |
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29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
d6fdec21 |
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29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8:fsl-layerscape: Add support for Chassis 3.2 NXP layerscape architecture Chassis 3.2 builds upon chassis3 architecture with changes like DDR Memory map change, removal of IFC and support of upto 8 I2C controller. Patch add README.lsch3_2 and the above changes under macro CONFIG_NXP_LSCH3_2. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
56db948b |
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05-Nov-2018 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: Update parsing boot source Workaround of erratum A010539 clears the RCW source field in PORSR1 register, causing failure of detecting boot source using this method. Use SMC call if U-Boot runs at EL2. If SMC is not implemented or running at EL3, continue to read PORSR1 and presume QSPI as boot source if erratum workaround A010539 is enabled and RCW source is cleared. Signed-off-by: York Sun <york.sun@nxp.com> |
#
681d489e |
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05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: layerscape: add SMC calls for DDR size and bank info Adds SMC calls for getting DDR size and bank info for TFABOOT. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
2141d250 |
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05-Nov-2018 |
Pankit Garg <pankit.garg@nxp.com> |
armv8: fsl-layerscape: bootcmd identification for TFABOOT Adds bootcmd identificaton on basis on boot source, valid in TFABOOT configuration. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> [YS: remove unnecessary braces] Reviewed-by: York Sun <york.sun@nxp.com> |
#
4c417384 |
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05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com> |
#
535d76a1 |
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05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: layerscape: Add TFABOOT support Adds TFABOOT support config option and add generic code to enable execution from DDR. Signed-off-by: York Sun <york.sun@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> |
#
e3506480 |
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05-Nov-2018 |
Pankit Garg <pankit.garg@nxp.com> |
armv8: fsl-layerscape: change tlb base from OCRAM to DDR in EL < 3 Change tlb base address from OCRAM to DDR when exception level is less than 3. Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
d171c707 |
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05-Nov-2018 |
York Sun <york.sun@nxp.com> |
move data structure out of cpu.h Move static definitions to cpu.c file, as it doesn't allow the cpu.h file to be included in multiple c files. Signed-off-by: York Sun <york.sun@nxp.com> |
#
9b5e6396 |
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30-Aug-2018 |
Stephen Warren <swarren@nvidia.com> |
efi_loader: simplify ifdefs Use CONFIG_IS_ENABLED(EFI_LOADER) to avoid explicitly checking CONFIG_SPL too. This simplifies the conditional. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Alexander Graf <agraf@suse.de> |
#
9cce5663 |
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16-Jul-2018 |
Joe Hershberger <joe.hershberger@ni.com> |
arm: Prevent redefinition error in fsl-layerscape The include/phy.h will start including dm.h, which pulls in linux/compat.h after the attempted redefinition in arch/arm/include/asm/armv8/mmu.h, so move this include to allow redefinition. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> |
#
83d290c5 |
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06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
482fc90c |
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06-Feb-2018 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
efi_loader: add missing EFI_RESET_PLATFORM_SPECIFIC EFI_RESET_PLATFORM_SPECIFIC is one of the values that can be used for the EFI service ResetSystem. The missing definition is added. The value has to handled in efi_reset_system(). Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Alexander Graf <agraf@suse.de> |
#
22c793e6 |
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03-Mar-2018 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
efi_loader: exit status for efi_reset_system_init efi_reset_system_init provides the architecture or board specific initialization of the EFI subsystem. Errors should be caught and signalled by a return code. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Alexander Graf <agraf@suse.de> |
#
958b2ed5 |
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09-Jan-2018 |
Zhang Ying-22455 <ying.zhang22455@nxp.com> |
armv8/ls1088a: configure PMU's PCTBENR to enable WDT The SP805-WDT module on LS1088A requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. The watchdog clock needs to be enabled first. Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
44262327 |
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15-Dec-2017 |
Ahmed Mansour <ahmed.mansour@nxp.com> |
drivers/misc: Share qbman init between archs This patch adds changes necessary to move functionality present in PowerPC folders with ARM architectures that have DPAA1 QBMan hardware - Create new board/freescale/common/fsl_portals.c to house shared device tree fixups for DPAA1 devices with ARM and PowerPC cores - Add new header file to top includes directory to allow files in both architectures to grab the function prototypes - Port inhibit_portals() from PowerPC to ARM. This function is used in setup to disable interrupts on all QMan and BMan portals. It is needed because the interrupts are enabled by default for all portals including unused/uninitialised portals. When the kernel attempts to go to deep sleep the unused portals prevent it from doing so Signed-off-by: Ahmed Mansour <ahmed.mansour@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
a8f33034 |
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03-Dec-2017 |
Wenbin song <wenbin.song@nxp.com> |
armv8: ls1043a/ls2080a: check SoC by device ID Check LS1043A/LS2080a by device ID without using personality ID to determine revision number. This check applies to all various personalities of the same SoC family. Signed-off-by: Wenbin Song <wenbin.song@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
2db53cfe |
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09-Nov-2017 |
Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
armv8: fsl-layerscape: Add support of disabling core prefetch Instruction prefetch feature is by default enabled during core release. This patch add support of disabling instruction prefetch by setting core mask in PPA. Here each core mask bit represents a core and prefetch is disabled at the time of core release. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
7eb40f0f |
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28-Sep-2017 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: Avoid running dram_init_banksize again gd->ram_size is reduced in this function to reserve secure memory. Avoid running this function again to further reduce memory size. This fixes issue for SPL boot with PPA image loaded in which case secure memory is incorrectly allocated due to repeated calling. Signed-off-by: York Sun <york.sun@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
710d0cd7 |
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03-Oct-2017 |
Sumit Garg <sumit.garg@nxp.com> |
armv8: fsl-layerscape: Allocate Secure memory from first ddr region This change is required due to trusted OS (OP-TEE) not being position independent code, it requires compile time fixed base address. To take care of this it is assumed that all layerscape armv8 platforms has minimum 2G ddr in first region. So we can have fixed address space (66 MB -> (2MB for PPA + 64MB for trusted OS)) allocated from top of first 2G ddr region and compile trusted OS with this fixed base address. But one exception here is ls1012 where we have only 1G (rdb) or 512M (frdm) ddr memory. For those we can have different fixed compile time base addresses for trusted OS. Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
e9303a41 |
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07-Sep-2017 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: Fix MC reserved memory calculation In case high region memory doesn't have enough space for Management Complex (MC), the return value should indicate a failure so the caller can handle it accordingly. Signed-off-by: York Sun <york.sun@nxp.com> Reported-by: Ebony Zhu <ebony.zhu@nxp.com> |
#
17d066fc |
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31-Aug-2017 |
Ashish Kumar <Ashish.Kumar@nxp.com> |
armv8: fsl-layerscape: Support to add RGMII for ls1088aqds This patch adds support for RGMII protocol NXP's LDPAA2 support RGMII protocol. LS1088A is the first Soc supporting both RGMII and SGMII. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Amrita Kumari <amrita.kumari@nxp.com> Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
63b2316c |
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10-Aug-2017 |
Ashish Kumar <Ashish.Kumar@nxp.com> |
fsl-layerscape: Consolidate registers space defination for CCI-400 bus CoreLink Cache Coherent Interconnect (CCI) provides full cache coherency between two clusters of multi-core CPUs and I/O coherency for devices and I/O masters. This patch add new config option SYS_FSL_HAS_CCI400 and moves existing register space definaton of CCI-400 bus to fsl_immap to be shared. CONFIG_SYS_CCI400_ADDR is replaced with SYS_CCI400_OFFSET in Kconfig. Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> [YS: revised commit message, squashed patches for armv8 and armv7] Reviewed-by: York Sun <york.sun@nxp.com> |
#
6e2941d7 |
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17-May-2017 |
Simon Glass <sjg@chromium.org> |
common: freescale: Move arch-specific declarations The declarations should not be in common.h. Move them to the arch-specific headers. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Fixup thinko defined(FSL_LSCH3) -> defined(CONFIG_FSL_LSCH3)] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
399e2bb6 |
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15-May-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Make U-Boot EL2 safe When U-Boot boots from EL2, skip some lowlevel init code requiring EL3, including CCI-400/CCN-504, trust zone, GIC, etc. These initialization tasks are carried out before U-Boot runs. This applies to the RAM version image used for SPL boot if PPA is loaded first. Signed-off-by: York Sun <york.sun@nxp.com> |
#
1f55a938 |
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05-May-2017 |
Santan Kumar <santan.kumar@nxp.com> |
armv8: ls2080aqds: Add support for SD boot Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
e809e747 |
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27-Apr-2017 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: fsl-layerscape: Add NXP LS2081A, LS2041A SoC support The QorIQ LS2081A SoC has eight 64-bit ARM v8 Cortex A72 cores and is built on layerscape architecture. It is 40-pin derivative of LS2084A (non-AIOP personality of LS2088A). So feature-wise it is same as LS2084A. LS2041A is a 4-core personality of LS2081A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
026f30ec |
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18-Apr-2017 |
Yuantian Tang <andy.tang@nxp.com> |
arm: psci: make psci usable on single core socs PSCI can be used on both multiple and single core socs. Current implementation only allows PSCI to work on multiple core socs. This patch removes this restriction so that PSCI can work on single core socs as well. Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
4a3ab193 |
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27-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: ls2080a: Drop macro CONFIG_LS2080A Use CONFIG_ARCH_LS2080A instead. Signed-off-by: York Sun <york.sun@nxp.com> |
#
3eace37e |
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06-Apr-2017 |
Simon Glass <sjg@chromium.org> |
arm: freescale: Rename initdram() to fsl_initdram() This function name shadows a global name but is in fact different. This is very confusing. Rename it to help with the following refactoring. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
76b00aca |
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31-Mar-2017 |
Simon Glass <sjg@chromium.org> |
board_f: Drop setup_dram_config() wrapper By making dram_init_banksize() return an error code we can drop the wrapper. Adjust this and clean up all implementations. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
088454cd |
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31-Mar-2017 |
Simon Glass <sjg@chromium.org> |
board_f: Drop return value from initdram() At present we cannot use this function as an init sequence call without a wrapper, since it returns the RAM size. Adjust it to set the RAM size in global_data instead, and return 0 on success. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
52c41180 |
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31-Mar-2017 |
Simon Glass <sjg@chromium.org> |
board_f: Drop board_type parameter from initdram() It looks like only cm5200 and tqm8xx use this feature, so we don't really need it in generic code. Drop it and have the users access gd->board_type directly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
3d8553f0 |
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02-Mar-2017 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
pci: layerscape: add LS2088A series SoC pcie support The LS2088A series SoCs has different physical memory map address and CCSR registers address against LS2080A series SoCs. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
eea1cb77 |
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13-Feb-2017 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8/fsl-layerscape: Update erratum A009635 implementation Erratum A009635 is valid only for LS2080A SoC and its personality. Add SoC svr check. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
4961eafc |
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06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Update early MMU for DDR after initialization In early MMU table, DDR has to be mapped as device memory to avoid speculative access. After DDR is initialized, it needs to be updated to normal memory to allow code execution. To simplify the code, dram_init() is moved into a common file as a weak function. Signed-off-by: York Sun <york.sun@nxp.com> |
#
a045a0c3 |
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06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Fix the sequence of changing MMU table This patch follows the break-before-make process when making changes to MMU table. MMU is disabled before changing TTBR to avoid any potential race condition. Signed-off-by: York Sun <york.sun@nxp.com> |
#
24f55496 |
|
06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Update MMU mapping with actual DDR size Update mapping with actual DDR size. Non-existing memory should not be mapped as "normal" memory to avoid speculative access. Signed-off-by: York Sun <york.sun@nxp.com> |
#
36cc0de0 |
|
06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Rewrite memory reservation For ARMv8 Layerscape SoCs, secure memory and MC memorey are reserved at the end of DDR. DDR is spit into two or three banks. This patch reverts commit aabd7ddb and simplifies the calculation of reserved memory, and moves the code into common SoC file. Secure memory is carved out first. DDR bank size is reduced. Reserved memory is then allocated on the top of available memory. U-Boot still has access to reserved memory as data transferring is needed. Device tree is fixed with reduced memory size to hide the reserved memory from OS. The same region is reserved for efi_loader. Signed-off-by: York Sun <york.sun@nxp.com> |
#
daa92644 |
|
16-Jan-2017 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
ARMv8/sec_firmware: relocated and renamed the config FSL_PPA_ARMV8_PSCI Moved the config FSL_PPA_ARMV8_PSCI from fsl-layerscape's Kconfig to Kconfig under armv8 and renamed it to SEC_FIRMWARE_ARMV8_PSCI. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
904110c7 |
|
10-Jan-2017 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8/fsl-lsch2: refactor the clock system initialization Up to now, there are 3 kind of SoCs under Layerscape Chassis 2, like LS1043A, LS1046A and LS1012A. But the clocks tree has a lot of differences, for instance, the IP modules have different dividers to derive its clock from Platform PLL. And the core cluster PLL and platform PLL maybe have different reference clocks, such as LS1012A. Another problem is which clock/PLL should be described by sys_info->freq_systembus, it is confused in Layerscape Chissis 2. This patch is to bind the sys_info->freq_systembus to the Platform PLL, and handle the different divider of IP modules separately between different SoCs, and separate reference clocks of core cluster PLL and platform PLL. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
2d16a1a6 |
|
07-Dec-2016 |
macro.wave.z@gmail.com <macro.wave.z@gmail.com> |
ARMv8: LS1043A: change macro CONFIG_ARMV8_PSCI definition NXP/Freescale uses macro CONFIG_ARMV8_PSCI to enable their private PSCI implementation in PPA firmware, but this macro naming too generic, so this patch replaces it with a specic one CONFIG_FSL_PPA_ARMV8_PSCI. And this macro CONFIG_ARMV8_PSCI will be used for a generic PSCI for ARMv8 which will be added in following patchs. Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
02fb2761 |
|
20-Nov-2016 |
Shengzhou Liu <Shengzhou.Liu@nxp.com> |
fsl/ddr: Add erratum_a009942_check_cpo and clean related erratum - add additional function erratum_a009942_check_cpo to check if the board needs tuning CPO calibration for optimal setting. - move ERRATUM_A009942(with revision to check cpo_sample option) from fsl_ddr_gen4.c to ctrl_regs.c for reuse on all DDR4/DDR3 parts. - move ERRATUM_A008378 from fsl_ddr_gen4.c to ctrl_regs.c - remove obsolete ERRATUM_A004934 which is replaced with ERRATUM_A009942. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> [YS: Replaced CONFIG_QEMU_E500 with CONFIG_ARCH_QEMU_E500] Reviewed-by: York Sun <york.sun@nxp.com> |
#
e87c673c |
|
16-Nov-2016 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8/fsl-lsch3: Update code to release secondary cores NXP ARMv8 SoC LS2080A release all secondary cores in one-go. But other new SoCs like LS2088A, LS1088A release secondary cores one by one. Update code to release secondary cores based on SoC SVR Add code to release cores one by one for non LS2080A SoCs Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> [YS: remove "inline" from declaration of initiator_type] Reviewed-by: York Sun <york.sun@nxp.com> |
#
f6b96ff6 |
|
16-Nov-2016 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Use SVR based timer base address detection Timer controller base address has been changed from LS2080A SoC (and its personalities) to new SoCs like LS2088A, LS1088A. Use SVR based timer base address detection to avoid compile time #ifdef. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
f6a70b3a |
|
16-Nov-2016 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add generic get_svr() in assembly Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
78d57842 |
|
16-Nov-2016 |
Alexander Graf <agraf@csgraf.de> |
armv8: fsl-layerscape: Add support for efi_loader RTS reset When implementing efi loader support, we can expose runtime services for payloads. One such service is CPU reset. This patch implements RTS CPU reset support for layerscape systems. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: York Sun <york.sun@nxp.com> |
#
ef9a5fd8 |
|
13-Sep-2016 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: Fix "cpu status" command The core position is not continuous for some SoCs. For example, valid cores may present at position 0, 1, 4, 5, 8, 9, etc. Some registers (including boot release register) only count existing cores. Current implementation of cpu_mask() complies with the continuous numbering. However, command "cpu status" queries the spin table with actual core position. Add functions to calculate core position from core number, to correctly calculate offsets. Tested on LS2080ARDB and LS1043ARDB. Signed-off-by: York Sun <york.sun@nxp.com> |
#
5d1a7a9d |
|
13-Sep-2016 |
Wenbin Song <wenbin.song@nxp.com> |
armv8/fsl-layerscape: print SoC revsion number The exact SoC revsion number can be recognized from U-Boot log. Signed-off-by: Wenbin Song <wenbin.song@nxp.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
cbe7706a |
|
26-Sep-2016 |
Tom Rini <trini@konsulko.com> |
Merge git://git.denx.de/u-boot-fsl-qoriq trini: Drop local memset() from examples/standalone/mem_to_mem_idma2intr.c Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
1221ce45 |
|
20-Sep-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
treewide: replace #include <asm/errno.h> with <linux/errno.h> Now, arch/${ARCH}/include/asm/errno.h and include/linux/errno.h have the same content. (both just wrap <asm-generic/errno.h>) Replace all include directives for <asm/errno.h> with <linux/errno.h>. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> [trini: Fixup include/clk.] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
b63a9506 |
|
03-Aug-2016 |
York Sun <york.sun@nxp.com> |
armv8: ls2080a: Remove debug server support Debug server feature has been dropped from roadmap. Signed-off-by: York Sun <york.sun@nxp.com> |
#
ed7a3943 |
|
22-Jul-2016 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: mmu: Fix enabling MMU MMU bit in SCTLR needs to be set explicitly after tables are created. It isn't an issue for EL3 becuase this bit is already set by early MMU setup. But for other exception levels this bit was not set. Signed-off-by: York Sun <york.sun@nxp.com> |
#
79119a4d |
|
05-Jul-2016 |
Alison Wang <b18965@freescale.com> |
armv8: fsl-layerscape: Add A72 core detection Add support to detect Cortex-A72 core for printing it out. The Initiator Version of A72 core should be 0x4. Signed-off-by: Alison Wang <alison.wang@nxp.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
032d5bb4 |
|
28-Jun-2016 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
ARMv8/Layerscape: switch SMP method accordingly If the PSCI and PPA is ready, skip the fixup for spin-table and waking secondary cores. Otherwise, change SMP method to spin-table, and the device node of PSCI will be removed. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
85cdf38e |
|
28-Jun-2016 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: fsl-layerscape: add i/d-cache enable function to enable_caches This function assume that the d-cache and MMU has been enabled earlier, so it just created MMU table in main memory. But the assumption is not always correct, for example, the early setup is done in EL3, while enable_caches() is called when the PE has turned into another EL. Define the function mmu_setup() for fsl-layerscape to cover the weak one. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
5ad5823d |
|
24-Jun-2016 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Convert to use common MMU framework Drop platform code to create static MMU tables. Use common framework to create MMU tables on the run. Tested on LS2080ARDB with secure and non-secure ram scenarios. Signed-off-by: York Sun <york.sun@nxp.com> |
#
e61a7534 |
|
24-Jun-2016 |
York Sun <york.sun@nxp.com> |
armv8: Move secure_ram variable out of generic global data Secure_ram variable was put in generic global data. But only ARMv8 uses this variable. Move it to ARM specific data structure. Signed-off-by: York Sun <york.sun@nxp.com> |
#
a10a31ec |
|
18-Jun-2016 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of git://git.denx.de/u-boot-usb Signed-off-by: Tom Rini <trini@konsulko.com> Conflicts: arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
|
#
6fb522dc |
|
12-Jun-2016 |
Sriram Dash <sriram.dash@nxp.com> |
arm64: fsl-layerscape: add get_svr and IS_SVR_REV helper Adds get_svr and IS_SVR_REV helpers for ARMv8 platforms, similar to PPC and ARMv7. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> |
#
a758177f |
|
07-Jun-2016 |
Yunhui Cui <yunhui.cui@nxp.com> |
armv8/ls2080a: configure PMU's PCTBENR to enable WDT The SP805-WDT module on LS2080A requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. The watchdog clock needs to be enabled first. Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
acb8f5e9 |
|
21-Apr-2016 |
Alison Wang <b18965@freescale.com> |
armv8: fsl-layerscape: Remove unnecessary flushing dcache As the issue about the stack will get corrupted when switching between the early and final mmu tables is fixed by commit 70e21b064, the workaround to flush dcache is unnecessary and should be removed. Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
3c1d218a |
|
04-Apr-2016 |
York Sun <york.sun@nxp.com> |
armv8: LS2080A: Consolidate LS2080A and LS2085A LS2080A is the primary SoC, and LS2085A is a personality with AIOP and DPAA DDR. The RDB and QDS boards support both personality. By detecting the SVR at runtime, a single image per board can support both SoCs. It gives users flexibility to swtich SoC without the need to reprogram the board. Signed-off-by: York Sun <york.sun@nxp.com> CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
c05016ab |
|
21-Mar-2016 |
Alexander Graf <agraf@csgraf.de> |
arm64: Fix layerscape mmu setup With commit 7985cdf we converted all systems except for the Layerscape SoCs to the generic descriptor table based page table setup. On the Layerscape SoCs however, we just provide an empty table stub and do the setup ourselves. To reserve enough memory for the tables, we need to override the default counting mechanism which would end up with an empty table because we have no maps. Fixes: 7985cdf Reported-by: York Sun <york.sun@nxp.com> CC: Alison Wang <alison.wang@nxp.com> CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Alexander Graf <agraf@suse.de> Tested-by: York Sun <york.sun@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
7985cdf7 |
|
03-Mar-2016 |
Alexander Graf <agraf@csgraf.de> |
arm64: Remove non-full-va map code By now the code to only have a single page table level with 64k page size and 42 bit address space is no longer used by any board in tree, so we can safely remove it. To clean up code, move the layerscape mmu code to the new defines, removing redundant field definitions. Signed-off-by: Alexander Graf <agraf@suse.de> |
#
c0492141 |
|
07-Dec-2015 |
York Sun <yorksun@freescale.com> |
armv8: fsl-layerscale: Rewrite reserving memory for MC and debug server MC and debug server are not board-specific. Move reserving memory to SoC file, using the new board_reserve_ram_top function. Reduce debug server memory by 2MB to make room for secure memory. In the system with MC and debug server, the top of u-boot memory is not the end of memory. PRAM is not used for this reservation. Signed-off-by: York Sun <yorksun@freescale.com> |
#
c107c0c0 |
|
04-Dec-2015 |
York Sun <yorksun@freescale.com> |
armv8: fsl-layerscape: Make DDR non secure in MMU tables DDR has been set as secure in MMU tables. Non-secure master such as SDHC DMA cannot access data correctly. Mixing secure and non- secure MMU entries requirs the MMU tables themselves in secure memory. This patch moves MMU tables into a secure DDR area. Early MMU tables are changed to set DDR as non-secure. A new table is added into final MMU tables so secure memory can have 2MB granuality. gd->secure_ram tracks the location of this secure memory. For ARMv8 SoCs, the RAM base is not zero and RAM is divided into several banks. gd->secure_ram needs to be maintained before using. This maintenance is board-specific, depending on the SoC and memory bank of the secure memory falls into. Signed-off-by: York Sun <yorksun@freescale.com> |
#
b4017364 |
|
04-Nov-2015 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
armv8: ls2085a: Add workaround of errata A009635 If the core runs at higher than x3 speed of the platform, there is possiblity about sev instruction to getting missed by other cores. This is because of SoC Run Control block may not able to sample the EVENTI(Sev) signals. Configure Run Control and EPU to periodically send out EVENTI signals to wake up A57 cores. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
d764129d |
|
04-Nov-2015 |
Alison Wang <b18965@freescale.com> |
armv8/layerscape: Update MMU table with execute-never bits For most device addresses excution shouldn't be allowed. Revise the MMU table to enforce execute-never bits. OCRAM, DDR and IFC are allowed for excution. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Alison Wang <alison.wang@freescale.com> Reported-by: Zhichun Hua <zhichun.hua@freescale.com> |
#
44937214 |
|
09-Nov-2015 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
armv8: LS2080A: Rename LS2085A to reflect LS2080A LS2080A is a prime personality of Freescale’s LS2085A. It is a non-AIOP personality without support of DP-DDR, L2 switch, 1588, PCIe endpoint etc. So renaming existing LS2085A code base to reflect LS2080A (Prime personality) Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> [York Sun: Dropped #ifdef in cpu.c for cpu_type_list] Reviewed-by: York Sun <yorksun@freescale.com> |
#
e8297341 |
|
26-Oct-2015 |
Shaohui Xie <Shaohui.Xie@freescale.com> |
armv8/ls1043a: Add Fman support Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
8281c58f |
|
26-Oct-2015 |
Mingkai Hu <Mingkai.Hu@freescale.com> |
armv8/fsl_lsch2: Add fsl_lsch2 SoC Freescale LayerScape with Chassis Generation 2 is a set of SoCs with ARMv8 cores and 2rd generation of Chassis. Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
9f3183d2 |
|
26-Oct-2015 |
Mingkai Hu <Mingkai.Hu@freescale.com> |
armv8/fsl_lsch3: Change arch to fsl-layerscape There are two LS series processors are built on ARMv8 Layersacpe architecture currently, LS2085A and LS1043A. They are based on ARMv8 core although use different chassis, so create fsl-layerscape to refactor the common code for the LS series processors which also paves the way for adding LS1043A platform. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
1d457dbb |
|
04-Dec-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_MAX_MEM_MAPPED to CFG Perform a simple rename of CONFIG_MAX_MEM_MAPPED to CFG_MAX_MEM_MAPPED Signed-off-by: Tom Rini <trini@konsulko.com> |
#
4fd9373b |
|
02-Dec-2022 |
Tom Rini <trini@konsulko.com> |
net: Remove more legacy functions Remove some of the board and arch specific non-DM_ETH helper code. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
ecc8d425 |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_PCI* to CFG_SYS_PCI* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_PCI and CONFIG_SYS_PCIE namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
8fd11135 |
|
25-Sep-2022 |
Sean Anderson <sean.anderson@seco.com> |
arm64: layerscape: Support SYSRESET CONFIG_SYSRESET provides its own implementation of reset_cpu. Disable our version when it is enabled. Signed-off-by: Sean Anderson <sean.anderson@seco.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> |
#
ce9c579e |
|
13-Jun-2022 |
Andre Przywara <andre.przywara@arm.com> |
armv8: always use current exception level for TCR_ELx access Currently get_tcr() takes an "el" parameter, to select the proper version of the TCR_ELx system register. This is problematic in case of the Apple M1, since it runs with HCR_EL2.E2H fixed to 1, so TCR_EL2 is actually using the TCR_EL1 layout, and we get the wrong version. For U-Boot's purposes the only sensible choice here is the current exception level, and indeed most callers treat it like that, so let's remove that parameter and read the current EL inside the function. This allows us to check for the E2H bit, and pretend it's EL1 in this case. There are two callers which don't care about the EL, and they pass 0, which looks wrong, but is irrelevant in these two cases, since we don't use the return value there. So the change cannot affect those two. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Mark Kettenis <kettenis@openbsd.org> Tested-by: Mark Kettenis <kettenis@openbsd.org> |
#
cda8f873 |
|
11-May-2022 |
Ye Li <ye.li@nxp.com> |
caam: Fix crash in case caam_jr_probe failed If probing caam_jr returns failure, the variable "dev" will not be initialized, so we can't use dev->name for the error print. Otherwise it will cause crash. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Gaurav Jain <gaurav.jain@nxp.com> |
#
cb14cc88 |
|
22-Apr-2022 |
Michael Walle <michael@walle.cc> |
armv8: layerscape: get rid of smc_call() There are two different implementations to do a secure monitor call: smc_call() and arm_smccc_smc(). The former is defined in fwcall.c and seems to be an ad-hoc implementation. The latter is imported from linux. smc_call() is also only available if CONFIG_ARMV8_PSCI is not defined. This makes it impossible to have both PSCI calls and PSCI implementation in one u-boot build. The layerscape SoC code decide at runtime via check_psci() if there is a PSCI support. Therefore, this is a prerequisite patch to add PSCI implementation support for the layerscape SoCs. Note, for the TFA part, this is only compile time tested with (ls1028ardb_tfa_defconfig). Signed-off-by: Michael Walle <michael@walle.cc> [Rebased] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
dfb6da55 |
|
05-Apr-2022 |
Marek Vasut <marex@denx.de> |
armv8: layerscape: env: Switch to arch_env_get_location() Implement arch_env_get_location() instead of env_get_location(), so that the env_get_location() can be implemented on board level and override the arch_env_get_location() architecture defaults. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Adam Ford <aford173@gmail.com> Cc: Fabio Estevam <festevam@denx.de> Cc: Marek Behún <marek.behun@nic.cz> Cc: Peng Fan <peng.fan@nxp.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefano Babic <sbabic@denx.de> Cc: Tim Harvey <tharvey@gateworks.com> Cc: Tom Rini <trini@konsulko.com> Cc: Tommaso Merciai <tomm.merciai@gmail.com> Cc: Vladimir Oltean <vladimir.oltean@nxp.com> |
#
8976556a |
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24-Mar-2022 |
Gaurav Jain <gaurav.jain@nxp.com> |
Layerscape: Enable Job ring driver model. LS(1021/1012/1028/1043/1046/1088/2088), LX2160, LX2162 platforms are enabled with JR driver model. removed sec_init() call from board files. sec is initialized based on job ring information processed from device tree. Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Michael Walle <michael@walle.cc> |
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f9147d63 |
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25-Feb-2022 |
Tom Rini <trini@konsulko.com> |
Convert CONFIG_CHIP_SELECTS_PER_CTRL to Kconfig This converts the following to Kconfig: CONFIG_CHIP_SELECTS_PER_CTRL Cc: Alison Wang <alison.wang@nxp.com> Cc: Pramod Kumar <pramod.kumar_1@nxp.com> Cc: Priyanka Jain <priyanka.jain@nxp.com> Cc: Rajesh Bhagat <rajesh.bhagat@nxp.com> Cc: Vladimir Oltean <olteanv@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
2f8a6db5 |
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14-Dec-2021 |
Tom Rini <trini@konsulko.com> |
Finish conversion of CONFIG_SYS_CLK_FREQ to Kconfig In order to finish moving this symbol to Kconfig for all platforms, we need to do a few more things. First, for all platforms that define this to a function, introduce CONFIG_DYNAMIC_SYS_CLK_FREQ, similar to CONFIG_DYNAMIC_DDR_CLK_FREQ and populate clock_legacy.h. This entails also switching all users from CONFIG_SYS_CLK_FREQ to get_board_sys_clk() and updating a few preprocessor tests. With that done, all platforms that define a value here can be converted to Kconfig, and a fall-back of zero is sufficiently safe to use (and what is used today in cases where code may or may not have this available). Make sure that code which calls this function includes <clock_legacy.h> to get the prototype. Signed-off-by: Tom Rini <trini@konsulko.com> |
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77b11f76 |
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18-Sep-2021 |
Vladimir Oltean <vladimir.oltean@nxp.com> |
net: replace the "xfi" phy-mode with "10gbase-r" As part of the effort of making U-Boot work with the same device tree as Linux, there is an issue with the "xfi" phy-mode. To be precise, in Linux there was a discussion (for those who have time to read: https://lore.kernel.org/netdev/1576768881-24971-2-git-send-email-madalin.bucur@oss.nxp.com/) which led to a patch: https://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next.git/commit/?id=c114574ebfdf42f826776f717c8056a00fa94881 TL;DR: "xfi" was standardized in Linux as "10gbase-r". This patch changes the relevant occurrences in U-Boot to use "10gbase-r" instead of "xfi" wherever applicable. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> |
#
84c2e044 |
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20-Apr-2021 |
Jiafei Pan <Jiafei.Pan@nxp.com> |
armv8: layerscape: add PSCI support for cpu release For cpu release command, check whether PSCI is supported firstly, if supported, use PSCI to kick off secondary cores, otherwise still use spin table. Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com> [Fixed checkpatch alignment CHECKs] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
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35b65dd8 |
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15-Dec-2020 |
Harald Seiler <hws@denx.de> |
reset: Remove addr parameter from reset_cpu() Historically, the reset_cpu() function had an `addr` parameter which was meant to pass in an address of the reset vector location, where the CPU should reset to. This feature is no longer used anywhere in U-Boot as all reset_cpu() implementations now ignore the passed value. Generic code has been added which always calls reset_cpu() with `0` which means this feature can no longer be used easily anyway. Over time, many implementations seem to have "misunderstood" the existence of this parameter as a way to customize/parameterize the reset (e.g. COLD vs WARM resets). As this is not properly supported, the code will almost always not do what it is intended to (because all call-sites just call reset_cpu() with 0). To avoid confusion and to clean up the codebase from unused left-overs of the past, remove the `addr` parameter entirely. Code which intends to support different kinds of resets should be rewritten as a sysreset driver instead. This transformation was done with the following coccinelle patch: @@ expression argvalue; @@ - reset_cpu(argvalue) + reset_cpu() @@ identifier argname; type argtype; @@ - reset_cpu(argtype argname) + reset_cpu(void) { ... } Signed-off-by: Harald Seiler <hws@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> |
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401d1c4f |
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30-Oct-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop asm/global_data.h from common header Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com> |
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3a187cff |
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29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
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c760095a |
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23-Oct-2020 |
Razvan Ionut Cirjan <razvanionut.cirjan@nxp.com> |
net: lx2160a.c: Update to set ECx_PMUX precedence As per hardware documentation, ECx_PMUX has precedence over SerDes protocol. For LX2160/LX2162 if DPMACs 17 and 18 are enabled as SGMII through SerDes protocol but ECx_PMUX configured them as RGMII, then the ports will be configured as RGMII and not SGMII. Signed-off-by: Razvan Ionut Cirjan <razvanionut.cirjan@nxp.com> [Rebased] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
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d31f3a1b |
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09-Sep-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2160a: fix reset sequence Make sure that SW_RST_REQ and RST_REQ_MSK are cleared before triggering hardware reset request. Signed-off-by: Thirupathaiah Annapureddy <thiruan@linux.microsoft.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
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b75d8dc5 |
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26-Jun-2020 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
treewide: convert bd_t to struct bd_info by coccinelle The Linux coding style guide (Documentation/process/coding-style.rst) clearly says: It's a **mistake** to use typedef for structures and pointers. Besides, using typedef for structures is annoying when you try to make headers self-contained. Let's say you have the following function declaration in a header: void foo(bd_t *bd); This is not self-contained since bd_t is not defined. To tell the compiler what 'bd_t' is, you need to include <asm/u-boot.h> #include <asm/u-boot.h> void foo(bd_t *bd); Then, the include direcective pulls in more bloat needlessly. If you use 'struct bd_info' instead, it is enough to put a forward declaration as follows: struct bd_info; void foo(struct bd_info *bd); Right, typedef'ing bd_t is a mistake. I used coccinelle to generate this commit. The semantic patch that makes this change is as follows: <smpl> @@ typedef bd_t; @@ -bd_t +struct bd_info </smpl> Signed-off-by: Masahiro Yamada <masahiroy@kernel.org> |
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25a5818f |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop asm/ptrace.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
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f7ae49fc |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
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90526e9f |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop net.h from common header Move this header out of the common header. Network support is used in quite a few places but it still does not warrant blanket inclusion. Note that this net.h header itself has quite a lot in it. It could be split into the driver-mode support, functions, structures, checksumming, etc. Signed-off-by: Simon Glass <sjg@chromium.org> |
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714497e3 |
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16-May-2020 |
Michael Walle <michael@walle.cc> |
efi_loader: round the memory area in efi_add_memory_map() Virtually all callers of this function do the rounding on their own. Some do it right, some don't. Instead of doing this in each caller, do the rounding in efi_add_memory_map(). Change the size parameter to bytes instead of pages and remove aligning and size calculation in all callers. There is no more need to make the original efi_add_memory_map() (which takes pages as size) available outside the module. Thus rename it to efi_add_memory_map_pg() and make it static to prevent further misuse outside the module. Signed-off-by: Michael Walle <michael@walle.cc> Add missing comma in sunxi_display.c. Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de> |
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6eb32a03 |
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23-Apr-2020 |
Madalin Bucur <madalin.bucur@oss.nxp.com> |
driver: net: fm: add DM ETH support Probe the FMan MACs based on the device tree while retaining the legacy code/functionality. One notable change introduced here is that, for DM_ETH, the name of the interfaces is corrected to the fmX-macY format, that avoids the referral to the MAC block names which were incorrect for FMan v3 devices (i.e. DTSEC, TGEC) and had weird formatting (i.e. FM1@DTSEC6, FM1@TGEC1). The legacy code is left unchanged in this respect. Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
6ebd4883 |
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27-Apr-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
fsl-layerscape: Add RESV_RAM check in resv_ram addr The initialization of gd->arch.resv_ram pointer should depend on if the RESV_RAM config is enabled. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Wasim Khan <wasim.khan@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
0d9d557d |
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10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
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db41d65a |
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28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move hang() to the same header as panic() At present panic() is in the vsprintf.h header file. That does not seem like an obvious choice for hang(), even though it relates to panic(). So let's put hang() in its own header. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Migrate a few more files] Signed-off-by: Tom Rini <trini@konsulko.com> |
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9b4a205f |
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28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move RAM-sizing functions to init.h These functions relate to memory init so move them into the init header. Signed-off-by: Simon Glass <sjg@chromium.org> |
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3499dd03 |
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27-Nov-2019 |
Alex Marginean <alexandru.marginean@nxp.com> |
ls1028a: Configure stream IDs for integrated PCI and fix up Linux DT Hardware comes out of reset with implicit values, but these are outside the accepted range for Layerscape gen 3 chassis spec used on LS1028A. Allocate different IDs and fix up Linux DT to use them. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
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b5981474 |
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14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some CPU functions out of common.h These functions belong in cpu_func.h since they do not use driver model. Move them over. Don't bother adding comments since these functions should be deleted. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
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68a6aa85 |
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14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move mii_init() function out of common.h This function belongs in mii.h so move it over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
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2189d5f1 |
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14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
Move strtomhz() to vsprintf.h At present this function sits in its own file but it does not really justify it. There are similar string functions in vsprintf.h, so move it there. Also add the missing function comment. Use the vsprintf.h include file explicitly where needed. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
812ff53c |
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30-Oct-2019 |
Pankaj Bansal <pankaj.bansal@nxp.com> |
fsl-layerscape: fix warning if no hwconfig is defined While getting the 'subarg' of 'hwconfig' env variable in config_core_prefetch(), if no hwconfig variable is defined, below warning is received: WARNING: Calling __hwconfig without a buffer and before environment is ready Fix this by checking 'hwconfig' env variable. If not found return without further processing. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Tested-by: Michael Walle <michael@walle.cc> |
#
28f9393b |
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17-Oct-2019 |
Mathew McBride <matt@traverse.com.au> |
fsl-layerscape: do not use layerscape EFI reset if PSCI used If the secure world reset handlers are used (via CONFIG_PSCI_RESET), then do not use the layerscape-specific implementation. Signed-off-by: Mathew McBride <matt@traverse.com.au> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
6ed69523 |
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18-Sep-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add more personalities support Add LS1027A, LS1018A and LS1017A personalities support to LS1028A SoC family. LS1028A is the prime personality of LS1028A SoC family. LS1027A is a lower funtionality version of QorIQ LS1028A which does not support the multimedia subsystems, such as LCD controller, GPU, and eDP PHY. The QorIQ LS1018A and LS1017A SoCs are single 64-bit Arm A72 core, low power versions of the QorIQ LS1028A and LS1027A SoCs respectively. Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
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0490cab5 |
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08-Aug-2019 |
Thomas Schaefer <thomas.schaefer@kontron.com> |
armv8: ls1028a: configure PMU's PCTBENR to enable WDT The SP805-WDT module on LS1028A requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. The watchdog clock needs to be enabled first. Signed-off-by: Thomas Schaefer <thomas.schaefer@kontron.com> Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
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f3998fdc |
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02-Aug-2019 |
Simon Glass <sjg@chromium.org> |
env: Rename environment.h to env_internal.h This file contains lots of internal details about the environment. Most code can include env.h instead, calling the functions there as needed. Rename this file and add a comment at the top to indicate its internal nature. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> [trini: Fixup apalis-tk1.c] Signed-off-by: Tom Rini <trini@konsulko.com> |
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3a7d5571 |
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01-Aug-2019 |
Simon Glass <sjg@chromium.org> |
env: Move env_get_f() to env.h Move this function over to the new header file. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
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d9532e80 |
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23-Apr-2019 |
Udit Agarwal <udit.agarwal@nxp.com> |
armv8: fsl-layerscape: Set env_loc to ENVL_NOWHERE with CONFIG_ENV_IS_NOWHERE. ENVL_NOWHERE is dependent on CONFIG_ENV_IS_NOWHERE and not on CONFIG_CHAIN_OF_TRUST so return ENVL_NOWHERE when CONFIG_ENV_IS_NOWHERE is enabled Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
d4ad111d |
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10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
059d9422 |
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08-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: lx2160a: add MMU table entries for PCIe The lx2160a have up to 6 PCIe controllers and have different address and size of PCIe region. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
8348e798 |
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08-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: layerscape: use PCIe address macro for precompile PCIe MMU entry Change to use PCIe address macro to determine if precompile the PCIe MMU table entry. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
10015025 |
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03-May-2019 |
Trevor Woerner <trevor@toganlabs.com> |
CONFIG_SPL_SYS_[DI]CACHE_OFF: add While converting CONFIG_SYS_[DI]CACHE_OFF to Kconfig, there are instances where these configuration items are conditional on SPL. This commit adds SPL variants of these configuration items, uses CONFIG_IS_ENABLED(), and updates the configurations as required. Acked-by: Alexey Brodkin <abrodkin@synopsys.com> Signed-off-by: Trevor Woerner <trevor@toganlabs.com> [trini: Make the default depend on the setting for full U-Boot, update more zynq hardware] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
2e53759d |
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29-Oct-2018 |
Pankaj Bansal <pankaj.bansal@nxp.com> |
armv8: fsl-layerscape: reorder rgmii dpmacs' enablement some dpmacs in armv8a based freescale layerscape SOCs can be configured via both serdes(sgmii, xfi, xlaui etc) bits and via EC*_PMUX(rgmii) bits in RCW. e.g. dpmac 17 and 18 in LX2160A can be configured as SGMII from serdes bits and as RGMII via EC1_PMUX/EC2_PMUX bits Now if a dpmac is enabled by serdes bits then it takes precedence over EC*_PMUX bits. i.e. in LX2160A if we select serdes protocol that configures dpmac17 as SGMII and set the EC1_PMUX as RGMII, then the dpmac is SGMII and not RGMII. Therefore, move the fsl_rgmii_init after fsl_serdes_init. in fsl_rgmii_init function of SOC, we will check if the dpmac is enabled or not? if it is (fsl_serdes_init has already enabled the dpmac), then don't enable it. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
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ec88ff80 |
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19-Dec-2018 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1043a: add SVR definitions for 23x23 package silicon LS1043A/LS1023A 23x23 package silicon has different SVR:VAR_PER. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
d23da2ae |
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26-Dec-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: fixes for TFABOOT framework Fixes for TFABOOT framework - update eMMC bootsrc to SD_MMC - Increase buffer size for mcinitcmd from 256 to 512 - Fix mcinitcmd and bootcmd for Secure Boot Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
4909b89e |
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29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
d6fdec21 |
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29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8:fsl-layerscape: Add support for Chassis 3.2 NXP layerscape architecture Chassis 3.2 builds upon chassis3 architecture with changes like DDR Memory map change, removal of IFC and support of upto 8 I2C controller. Patch add README.lsch3_2 and the above changes under macro CONFIG_NXP_LSCH3_2. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
56db948b |
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05-Nov-2018 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: Update parsing boot source Workaround of erratum A010539 clears the RCW source field in PORSR1 register, causing failure of detecting boot source using this method. Use SMC call if U-Boot runs at EL2. If SMC is not implemented or running at EL3, continue to read PORSR1 and presume QSPI as boot source if erratum workaround A010539 is enabled and RCW source is cleared. Signed-off-by: York Sun <york.sun@nxp.com> |
#
681d489e |
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05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: layerscape: add SMC calls for DDR size and bank info Adds SMC calls for getting DDR size and bank info for TFABOOT. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
2141d250 |
|
05-Nov-2018 |
Pankit Garg <pankit.garg@nxp.com> |
armv8: fsl-layerscape: bootcmd identification for TFABOOT Adds bootcmd identificaton on basis on boot source, valid in TFABOOT configuration. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> [YS: remove unnecessary braces] Reviewed-by: York Sun <york.sun@nxp.com> |
#
4c417384 |
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05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com> |
#
535d76a1 |
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05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: layerscape: Add TFABOOT support Adds TFABOOT support config option and add generic code to enable execution from DDR. Signed-off-by: York Sun <york.sun@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> |
#
e3506480 |
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05-Nov-2018 |
Pankit Garg <pankit.garg@nxp.com> |
armv8: fsl-layerscape: change tlb base from OCRAM to DDR in EL < 3 Change tlb base address from OCRAM to DDR when exception level is less than 3. Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
d171c707 |
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05-Nov-2018 |
York Sun <york.sun@nxp.com> |
move data structure out of cpu.h Move static definitions to cpu.c file, as it doesn't allow the cpu.h file to be included in multiple c files. Signed-off-by: York Sun <york.sun@nxp.com> |
#
9b5e6396 |
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30-Aug-2018 |
Stephen Warren <swarren@nvidia.com> |
efi_loader: simplify ifdefs Use CONFIG_IS_ENABLED(EFI_LOADER) to avoid explicitly checking CONFIG_SPL too. This simplifies the conditional. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Alexander Graf <agraf@suse.de> |
#
9cce5663 |
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16-Jul-2018 |
Joe Hershberger <joe.hershberger@ni.com> |
arm: Prevent redefinition error in fsl-layerscape The include/phy.h will start including dm.h, which pulls in linux/compat.h after the attempted redefinition in arch/arm/include/asm/armv8/mmu.h, so move this include to allow redefinition. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> |
#
83d290c5 |
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06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
482fc90c |
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06-Feb-2018 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
efi_loader: add missing EFI_RESET_PLATFORM_SPECIFIC EFI_RESET_PLATFORM_SPECIFIC is one of the values that can be used for the EFI service ResetSystem. The missing definition is added. The value has to handled in efi_reset_system(). Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Alexander Graf <agraf@suse.de> |
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22c793e6 |
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03-Mar-2018 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
efi_loader: exit status for efi_reset_system_init efi_reset_system_init provides the architecture or board specific initialization of the EFI subsystem. Errors should be caught and signalled by a return code. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Alexander Graf <agraf@suse.de> |
#
958b2ed5 |
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09-Jan-2018 |
Zhang Ying-22455 <ying.zhang22455@nxp.com> |
armv8/ls1088a: configure PMU's PCTBENR to enable WDT The SP805-WDT module on LS1088A requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. The watchdog clock needs to be enabled first. Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
44262327 |
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15-Dec-2017 |
Ahmed Mansour <ahmed.mansour@nxp.com> |
drivers/misc: Share qbman init between archs This patch adds changes necessary to move functionality present in PowerPC folders with ARM architectures that have DPAA1 QBMan hardware - Create new board/freescale/common/fsl_portals.c to house shared device tree fixups for DPAA1 devices with ARM and PowerPC cores - Add new header file to top includes directory to allow files in both architectures to grab the function prototypes - Port inhibit_portals() from PowerPC to ARM. This function is used in setup to disable interrupts on all QMan and BMan portals. It is needed because the interrupts are enabled by default for all portals including unused/uninitialised portals. When the kernel attempts to go to deep sleep the unused portals prevent it from doing so Signed-off-by: Ahmed Mansour <ahmed.mansour@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
a8f33034 |
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03-Dec-2017 |
Wenbin song <wenbin.song@nxp.com> |
armv8: ls1043a/ls2080a: check SoC by device ID Check LS1043A/LS2080a by device ID without using personality ID to determine revision number. This check applies to all various personalities of the same SoC family. Signed-off-by: Wenbin Song <wenbin.song@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
2db53cfe |
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09-Nov-2017 |
Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
armv8: fsl-layerscape: Add support of disabling core prefetch Instruction prefetch feature is by default enabled during core release. This patch add support of disabling instruction prefetch by setting core mask in PPA. Here each core mask bit represents a core and prefetch is disabled at the time of core release. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
7eb40f0f |
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28-Sep-2017 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: Avoid running dram_init_banksize again gd->ram_size is reduced in this function to reserve secure memory. Avoid running this function again to further reduce memory size. This fixes issue for SPL boot with PPA image loaded in which case secure memory is incorrectly allocated due to repeated calling. Signed-off-by: York Sun <york.sun@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
710d0cd7 |
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03-Oct-2017 |
Sumit Garg <sumit.garg@nxp.com> |
armv8: fsl-layerscape: Allocate Secure memory from first ddr region This change is required due to trusted OS (OP-TEE) not being position independent code, it requires compile time fixed base address. To take care of this it is assumed that all layerscape armv8 platforms has minimum 2G ddr in first region. So we can have fixed address space (66 MB -> (2MB for PPA + 64MB for trusted OS)) allocated from top of first 2G ddr region and compile trusted OS with this fixed base address. But one exception here is ls1012 where we have only 1G (rdb) or 512M (frdm) ddr memory. For those we can have different fixed compile time base addresses for trusted OS. Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
e9303a41 |
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07-Sep-2017 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: Fix MC reserved memory calculation In case high region memory doesn't have enough space for Management Complex (MC), the return value should indicate a failure so the caller can handle it accordingly. Signed-off-by: York Sun <york.sun@nxp.com> Reported-by: Ebony Zhu <ebony.zhu@nxp.com> |
#
17d066fc |
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31-Aug-2017 |
Ashish Kumar <Ashish.Kumar@nxp.com> |
armv8: fsl-layerscape: Support to add RGMII for ls1088aqds This patch adds support for RGMII protocol NXP's LDPAA2 support RGMII protocol. LS1088A is the first Soc supporting both RGMII and SGMII. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Amrita Kumari <amrita.kumari@nxp.com> Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
63b2316c |
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10-Aug-2017 |
Ashish Kumar <Ashish.Kumar@nxp.com> |
fsl-layerscape: Consolidate registers space defination for CCI-400 bus CoreLink Cache Coherent Interconnect (CCI) provides full cache coherency between two clusters of multi-core CPUs and I/O coherency for devices and I/O masters. This patch add new config option SYS_FSL_HAS_CCI400 and moves existing register space definaton of CCI-400 bus to fsl_immap to be shared. CONFIG_SYS_CCI400_ADDR is replaced with SYS_CCI400_OFFSET in Kconfig. Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> [YS: revised commit message, squashed patches for armv8 and armv7] Reviewed-by: York Sun <york.sun@nxp.com> |
#
6e2941d7 |
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17-May-2017 |
Simon Glass <sjg@chromium.org> |
common: freescale: Move arch-specific declarations The declarations should not be in common.h. Move them to the arch-specific headers. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Fixup thinko defined(FSL_LSCH3) -> defined(CONFIG_FSL_LSCH3)] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
399e2bb6 |
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15-May-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Make U-Boot EL2 safe When U-Boot boots from EL2, skip some lowlevel init code requiring EL3, including CCI-400/CCN-504, trust zone, GIC, etc. These initialization tasks are carried out before U-Boot runs. This applies to the RAM version image used for SPL boot if PPA is loaded first. Signed-off-by: York Sun <york.sun@nxp.com> |
#
1f55a938 |
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05-May-2017 |
Santan Kumar <santan.kumar@nxp.com> |
armv8: ls2080aqds: Add support for SD boot Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
e809e747 |
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27-Apr-2017 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: fsl-layerscape: Add NXP LS2081A, LS2041A SoC support The QorIQ LS2081A SoC has eight 64-bit ARM v8 Cortex A72 cores and is built on layerscape architecture. It is 40-pin derivative of LS2084A (non-AIOP personality of LS2088A). So feature-wise it is same as LS2084A. LS2041A is a 4-core personality of LS2081A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
026f30ec |
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18-Apr-2017 |
Yuantian Tang <andy.tang@nxp.com> |
arm: psci: make psci usable on single core socs PSCI can be used on both multiple and single core socs. Current implementation only allows PSCI to work on multiple core socs. This patch removes this restriction so that PSCI can work on single core socs as well. Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
4a3ab193 |
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27-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: ls2080a: Drop macro CONFIG_LS2080A Use CONFIG_ARCH_LS2080A instead. Signed-off-by: York Sun <york.sun@nxp.com> |
#
3eace37e |
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06-Apr-2017 |
Simon Glass <sjg@chromium.org> |
arm: freescale: Rename initdram() to fsl_initdram() This function name shadows a global name but is in fact different. This is very confusing. Rename it to help with the following refactoring. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
76b00aca |
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31-Mar-2017 |
Simon Glass <sjg@chromium.org> |
board_f: Drop setup_dram_config() wrapper By making dram_init_banksize() return an error code we can drop the wrapper. Adjust this and clean up all implementations. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
088454cd |
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31-Mar-2017 |
Simon Glass <sjg@chromium.org> |
board_f: Drop return value from initdram() At present we cannot use this function as an init sequence call without a wrapper, since it returns the RAM size. Adjust it to set the RAM size in global_data instead, and return 0 on success. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
52c41180 |
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31-Mar-2017 |
Simon Glass <sjg@chromium.org> |
board_f: Drop board_type parameter from initdram() It looks like only cm5200 and tqm8xx use this feature, so we don't really need it in generic code. Drop it and have the users access gd->board_type directly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
3d8553f0 |
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02-Mar-2017 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
pci: layerscape: add LS2088A series SoC pcie support The LS2088A series SoCs has different physical memory map address and CCSR registers address against LS2080A series SoCs. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
eea1cb77 |
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13-Feb-2017 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8/fsl-layerscape: Update erratum A009635 implementation Erratum A009635 is valid only for LS2080A SoC and its personality. Add SoC svr check. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
4961eafc |
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06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Update early MMU for DDR after initialization In early MMU table, DDR has to be mapped as device memory to avoid speculative access. After DDR is initialized, it needs to be updated to normal memory to allow code execution. To simplify the code, dram_init() is moved into a common file as a weak function. Signed-off-by: York Sun <york.sun@nxp.com> |
#
a045a0c3 |
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06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Fix the sequence of changing MMU table This patch follows the break-before-make process when making changes to MMU table. MMU is disabled before changing TTBR to avoid any potential race condition. Signed-off-by: York Sun <york.sun@nxp.com> |
#
24f55496 |
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06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Update MMU mapping with actual DDR size Update mapping with actual DDR size. Non-existing memory should not be mapped as "normal" memory to avoid speculative access. Signed-off-by: York Sun <york.sun@nxp.com> |
#
36cc0de0 |
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06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Rewrite memory reservation For ARMv8 Layerscape SoCs, secure memory and MC memorey are reserved at the end of DDR. DDR is spit into two or three banks. This patch reverts commit aabd7ddb and simplifies the calculation of reserved memory, and moves the code into common SoC file. Secure memory is carved out first. DDR bank size is reduced. Reserved memory is then allocated on the top of available memory. U-Boot still has access to reserved memory as data transferring is needed. Device tree is fixed with reduced memory size to hide the reserved memory from OS. The same region is reserved for efi_loader. Signed-off-by: York Sun <york.sun@nxp.com> |
#
daa92644 |
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16-Jan-2017 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
ARMv8/sec_firmware: relocated and renamed the config FSL_PPA_ARMV8_PSCI Moved the config FSL_PPA_ARMV8_PSCI from fsl-layerscape's Kconfig to Kconfig under armv8 and renamed it to SEC_FIRMWARE_ARMV8_PSCI. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
904110c7 |
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10-Jan-2017 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8/fsl-lsch2: refactor the clock system initialization Up to now, there are 3 kind of SoCs under Layerscape Chassis 2, like LS1043A, LS1046A and LS1012A. But the clocks tree has a lot of differences, for instance, the IP modules have different dividers to derive its clock from Platform PLL. And the core cluster PLL and platform PLL maybe have different reference clocks, such as LS1012A. Another problem is which clock/PLL should be described by sys_info->freq_systembus, it is confused in Layerscape Chissis 2. This patch is to bind the sys_info->freq_systembus to the Platform PLL, and handle the different divider of IP modules separately between different SoCs, and separate reference clocks of core cluster PLL and platform PLL. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
2d16a1a6 |
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07-Dec-2016 |
macro.wave.z@gmail.com <macro.wave.z@gmail.com> |
ARMv8: LS1043A: change macro CONFIG_ARMV8_PSCI definition NXP/Freescale uses macro CONFIG_ARMV8_PSCI to enable their private PSCI implementation in PPA firmware, but this macro naming too generic, so this patch replaces it with a specic one CONFIG_FSL_PPA_ARMV8_PSCI. And this macro CONFIG_ARMV8_PSCI will be used for a generic PSCI for ARMv8 which will be added in following patchs. Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
02fb2761 |
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20-Nov-2016 |
Shengzhou Liu <Shengzhou.Liu@nxp.com> |
fsl/ddr: Add erratum_a009942_check_cpo and clean related erratum - add additional function erratum_a009942_check_cpo to check if the board needs tuning CPO calibration for optimal setting. - move ERRATUM_A009942(with revision to check cpo_sample option) from fsl_ddr_gen4.c to ctrl_regs.c for reuse on all DDR4/DDR3 parts. - move ERRATUM_A008378 from fsl_ddr_gen4.c to ctrl_regs.c - remove obsolete ERRATUM_A004934 which is replaced with ERRATUM_A009942. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> [YS: Replaced CONFIG_QEMU_E500 with CONFIG_ARCH_QEMU_E500] Reviewed-by: York Sun <york.sun@nxp.com> |
#
e87c673c |
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16-Nov-2016 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8/fsl-lsch3: Update code to release secondary cores NXP ARMv8 SoC LS2080A release all secondary cores in one-go. But other new SoCs like LS2088A, LS1088A release secondary cores one by one. Update code to release secondary cores based on SoC SVR Add code to release cores one by one for non LS2080A SoCs Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> [YS: remove "inline" from declaration of initiator_type] Reviewed-by: York Sun <york.sun@nxp.com> |
#
f6b96ff6 |
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16-Nov-2016 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Use SVR based timer base address detection Timer controller base address has been changed from LS2080A SoC (and its personalities) to new SoCs like LS2088A, LS1088A. Use SVR based timer base address detection to avoid compile time #ifdef. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
f6a70b3a |
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16-Nov-2016 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add generic get_svr() in assembly Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
78d57842 |
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16-Nov-2016 |
Alexander Graf <agraf@csgraf.de> |
armv8: fsl-layerscape: Add support for efi_loader RTS reset When implementing efi loader support, we can expose runtime services for payloads. One such service is CPU reset. This patch implements RTS CPU reset support for layerscape systems. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: York Sun <york.sun@nxp.com> |
#
ef9a5fd8 |
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13-Sep-2016 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: Fix "cpu status" command The core position is not continuous for some SoCs. For example, valid cores may present at position 0, 1, 4, 5, 8, 9, etc. Some registers (including boot release register) only count existing cores. Current implementation of cpu_mask() complies with the continuous numbering. However, command "cpu status" queries the spin table with actual core position. Add functions to calculate core position from core number, to correctly calculate offsets. Tested on LS2080ARDB and LS1043ARDB. Signed-off-by: York Sun <york.sun@nxp.com> |
#
5d1a7a9d |
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13-Sep-2016 |
Wenbin Song <wenbin.song@nxp.com> |
armv8/fsl-layerscape: print SoC revsion number The exact SoC revsion number can be recognized from U-Boot log. Signed-off-by: Wenbin Song <wenbin.song@nxp.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
cbe7706a |
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26-Sep-2016 |
Tom Rini <trini@konsulko.com> |
Merge git://git.denx.de/u-boot-fsl-qoriq trini: Drop local memset() from examples/standalone/mem_to_mem_idma2intr.c Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
1221ce45 |
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20-Sep-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
treewide: replace #include <asm/errno.h> with <linux/errno.h> Now, arch/${ARCH}/include/asm/errno.h and include/linux/errno.h have the same content. (both just wrap <asm-generic/errno.h>) Replace all include directives for <asm/errno.h> with <linux/errno.h>. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> [trini: Fixup include/clk.] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
b63a9506 |
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03-Aug-2016 |
York Sun <york.sun@nxp.com> |
armv8: ls2080a: Remove debug server support Debug server feature has been dropped from roadmap. Signed-off-by: York Sun <york.sun@nxp.com> |
#
ed7a3943 |
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22-Jul-2016 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: mmu: Fix enabling MMU MMU bit in SCTLR needs to be set explicitly after tables are created. It isn't an issue for EL3 becuase this bit is already set by early MMU setup. But for other exception levels this bit was not set. Signed-off-by: York Sun <york.sun@nxp.com> |
#
79119a4d |
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05-Jul-2016 |
Alison Wang <b18965@freescale.com> |
armv8: fsl-layerscape: Add A72 core detection Add support to detect Cortex-A72 core for printing it out. The Initiator Version of A72 core should be 0x4. Signed-off-by: Alison Wang <alison.wang@nxp.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
032d5bb4 |
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28-Jun-2016 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
ARMv8/Layerscape: switch SMP method accordingly If the PSCI and PPA is ready, skip the fixup for spin-table and waking secondary cores. Otherwise, change SMP method to spin-table, and the device node of PSCI will be removed. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
85cdf38e |
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28-Jun-2016 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: fsl-layerscape: add i/d-cache enable function to enable_caches This function assume that the d-cache and MMU has been enabled earlier, so it just created MMU table in main memory. But the assumption is not always correct, for example, the early setup is done in EL3, while enable_caches() is called when the PE has turned into another EL. Define the function mmu_setup() for fsl-layerscape to cover the weak one. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
5ad5823d |
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24-Jun-2016 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Convert to use common MMU framework Drop platform code to create static MMU tables. Use common framework to create MMU tables on the run. Tested on LS2080ARDB with secure and non-secure ram scenarios. Signed-off-by: York Sun <york.sun@nxp.com> |
#
e61a7534 |
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24-Jun-2016 |
York Sun <york.sun@nxp.com> |
armv8: Move secure_ram variable out of generic global data Secure_ram variable was put in generic global data. But only ARMv8 uses this variable. Move it to ARM specific data structure. Signed-off-by: York Sun <york.sun@nxp.com> |
#
a10a31ec |
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18-Jun-2016 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of git://git.denx.de/u-boot-usb Signed-off-by: Tom Rini <trini@konsulko.com> Conflicts: arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
|
#
6fb522dc |
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12-Jun-2016 |
Sriram Dash <sriram.dash@nxp.com> |
arm64: fsl-layerscape: add get_svr and IS_SVR_REV helper Adds get_svr and IS_SVR_REV helpers for ARMv8 platforms, similar to PPC and ARMv7. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> |
#
a758177f |
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07-Jun-2016 |
Yunhui Cui <yunhui.cui@nxp.com> |
armv8/ls2080a: configure PMU's PCTBENR to enable WDT The SP805-WDT module on LS2080A requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. The watchdog clock needs to be enabled first. Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
acb8f5e9 |
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21-Apr-2016 |
Alison Wang <b18965@freescale.com> |
armv8: fsl-layerscape: Remove unnecessary flushing dcache As the issue about the stack will get corrupted when switching between the early and final mmu tables is fixed by commit 70e21b064, the workaround to flush dcache is unnecessary and should be removed. Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
3c1d218a |
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04-Apr-2016 |
York Sun <york.sun@nxp.com> |
armv8: LS2080A: Consolidate LS2080A and LS2085A LS2080A is the primary SoC, and LS2085A is a personality with AIOP and DPAA DDR. The RDB and QDS boards support both personality. By detecting the SVR at runtime, a single image per board can support both SoCs. It gives users flexibility to swtich SoC without the need to reprogram the board. Signed-off-by: York Sun <york.sun@nxp.com> CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
c05016ab |
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21-Mar-2016 |
Alexander Graf <agraf@csgraf.de> |
arm64: Fix layerscape mmu setup With commit 7985cdf we converted all systems except for the Layerscape SoCs to the generic descriptor table based page table setup. On the Layerscape SoCs however, we just provide an empty table stub and do the setup ourselves. To reserve enough memory for the tables, we need to override the default counting mechanism which would end up with an empty table because we have no maps. Fixes: 7985cdf Reported-by: York Sun <york.sun@nxp.com> CC: Alison Wang <alison.wang@nxp.com> CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Alexander Graf <agraf@suse.de> Tested-by: York Sun <york.sun@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
7985cdf7 |
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03-Mar-2016 |
Alexander Graf <agraf@csgraf.de> |
arm64: Remove non-full-va map code By now the code to only have a single page table level with 64k page size and 42 bit address space is no longer used by any board in tree, so we can safely remove it. To clean up code, move the layerscape mmu code to the new defines, removing redundant field definitions. Signed-off-by: Alexander Graf <agraf@suse.de> |
#
c0492141 |
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07-Dec-2015 |
York Sun <yorksun@freescale.com> |
armv8: fsl-layerscale: Rewrite reserving memory for MC and debug server MC and debug server are not board-specific. Move reserving memory to SoC file, using the new board_reserve_ram_top function. Reduce debug server memory by 2MB to make room for secure memory. In the system with MC and debug server, the top of u-boot memory is not the end of memory. PRAM is not used for this reservation. Signed-off-by: York Sun <yorksun@freescale.com> |
#
c107c0c0 |
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04-Dec-2015 |
York Sun <yorksun@freescale.com> |
armv8: fsl-layerscape: Make DDR non secure in MMU tables DDR has been set as secure in MMU tables. Non-secure master such as SDHC DMA cannot access data correctly. Mixing secure and non- secure MMU entries requirs the MMU tables themselves in secure memory. This patch moves MMU tables into a secure DDR area. Early MMU tables are changed to set DDR as non-secure. A new table is added into final MMU tables so secure memory can have 2MB granuality. gd->secure_ram tracks the location of this secure memory. For ARMv8 SoCs, the RAM base is not zero and RAM is divided into several banks. gd->secure_ram needs to be maintained before using. This maintenance is board-specific, depending on the SoC and memory bank of the secure memory falls into. Signed-off-by: York Sun <yorksun@freescale.com> |
#
b4017364 |
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04-Nov-2015 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
armv8: ls2085a: Add workaround of errata A009635 If the core runs at higher than x3 speed of the platform, there is possiblity about sev instruction to getting missed by other cores. This is because of SoC Run Control block may not able to sample the EVENTI(Sev) signals. Configure Run Control and EPU to periodically send out EVENTI signals to wake up A57 cores. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
d764129d |
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04-Nov-2015 |
Alison Wang <b18965@freescale.com> |
armv8/layerscape: Update MMU table with execute-never bits For most device addresses excution shouldn't be allowed. Revise the MMU table to enforce execute-never bits. OCRAM, DDR and IFC are allowed for excution. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Alison Wang <alison.wang@freescale.com> Reported-by: Zhichun Hua <zhichun.hua@freescale.com> |
#
44937214 |
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09-Nov-2015 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
armv8: LS2080A: Rename LS2085A to reflect LS2080A LS2080A is a prime personality of Freescale’s LS2085A. It is a non-AIOP personality without support of DP-DDR, L2 switch, 1588, PCIe endpoint etc. So renaming existing LS2085A code base to reflect LS2080A (Prime personality) Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> [York Sun: Dropped #ifdef in cpu.c for cpu_type_list] Reviewed-by: York Sun <yorksun@freescale.com> |
#
e8297341 |
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26-Oct-2015 |
Shaohui Xie <Shaohui.Xie@freescale.com> |
armv8/ls1043a: Add Fman support Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
8281c58f |
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26-Oct-2015 |
Mingkai Hu <Mingkai.Hu@freescale.com> |
armv8/fsl_lsch2: Add fsl_lsch2 SoC Freescale LayerScape with Chassis Generation 2 is a set of SoCs with ARMv8 cores and 2rd generation of Chassis. Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
9f3183d2 |
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26-Oct-2015 |
Mingkai Hu <Mingkai.Hu@freescale.com> |
armv8/fsl_lsch3: Change arch to fsl-layerscape There are two LS series processors are built on ARMv8 Layersacpe architecture currently, LS2085A and LS1043A. They are based on ARMv8 core although use different chassis, so create fsl-layerscape to refactor the common code for the LS series processors which also paves the way for adding LS1043A platform. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
6cc04547 |
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28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
8fd11135 |
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25-Sep-2022 |
Sean Anderson <sean.anderson@seco.com> |
arm64: layerscape: Support SYSRESET CONFIG_SYSRESET provides its own implementation of reset_cpu. Disable our version when it is enabled. Signed-off-by: Sean Anderson <sean.anderson@seco.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> |
#
ce9c579e |
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13-Jun-2022 |
Andre Przywara <andre.przywara@arm.com> |
armv8: always use current exception level for TCR_ELx access Currently get_tcr() takes an "el" parameter, to select the proper version of the TCR_ELx system register. This is problematic in case of the Apple M1, since it runs with HCR_EL2.E2H fixed to 1, so TCR_EL2 is actually using the TCR_EL1 layout, and we get the wrong version. For U-Boot's purposes the only sensible choice here is the current exception level, and indeed most callers treat it like that, so let's remove that parameter and read the current EL inside the function. This allows us to check for the E2H bit, and pretend it's EL1 in this case. There are two callers which don't care about the EL, and they pass 0, which looks wrong, but is irrelevant in these two cases, since we don't use the return value there. So the change cannot affect those two. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Mark Kettenis <kettenis@openbsd.org> Tested-by: Mark Kettenis <kettenis@openbsd.org> |
#
cda8f873 |
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11-May-2022 |
Ye Li <ye.li@nxp.com> |
caam: Fix crash in case caam_jr_probe failed If probing caam_jr returns failure, the variable "dev" will not be initialized, so we can't use dev->name for the error print. Otherwise it will cause crash. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Gaurav Jain <gaurav.jain@nxp.com> |
#
cb14cc88 |
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22-Apr-2022 |
Michael Walle <michael@walle.cc> |
armv8: layerscape: get rid of smc_call() There are two different implementations to do a secure monitor call: smc_call() and arm_smccc_smc(). The former is defined in fwcall.c and seems to be an ad-hoc implementation. The latter is imported from linux. smc_call() is also only available if CONFIG_ARMV8_PSCI is not defined. This makes it impossible to have both PSCI calls and PSCI implementation in one u-boot build. The layerscape SoC code decide at runtime via check_psci() if there is a PSCI support. Therefore, this is a prerequisite patch to add PSCI implementation support for the layerscape SoCs. Note, for the TFA part, this is only compile time tested with (ls1028ardb_tfa_defconfig). Signed-off-by: Michael Walle <michael@walle.cc> [Rebased] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
dfb6da55 |
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05-Apr-2022 |
Marek Vasut <marex@denx.de> |
armv8: layerscape: env: Switch to arch_env_get_location() Implement arch_env_get_location() instead of env_get_location(), so that the env_get_location() can be implemented on board level and override the arch_env_get_location() architecture defaults. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Adam Ford <aford173@gmail.com> Cc: Fabio Estevam <festevam@denx.de> Cc: Marek Behún <marek.behun@nic.cz> Cc: Peng Fan <peng.fan@nxp.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefano Babic <sbabic@denx.de> Cc: Tim Harvey <tharvey@gateworks.com> Cc: Tom Rini <trini@konsulko.com> Cc: Tommaso Merciai <tomm.merciai@gmail.com> Cc: Vladimir Oltean <vladimir.oltean@nxp.com> |
#
8976556a |
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24-Mar-2022 |
Gaurav Jain <gaurav.jain@nxp.com> |
Layerscape: Enable Job ring driver model. LS(1021/1012/1028/1043/1046/1088/2088), LX2160, LX2162 platforms are enabled with JR driver model. removed sec_init() call from board files. sec is initialized based on job ring information processed from device tree. Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Michael Walle <michael@walle.cc> |
#
f9147d63 |
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25-Feb-2022 |
Tom Rini <trini@konsulko.com> |
Convert CONFIG_CHIP_SELECTS_PER_CTRL to Kconfig This converts the following to Kconfig: CONFIG_CHIP_SELECTS_PER_CTRL Cc: Alison Wang <alison.wang@nxp.com> Cc: Pramod Kumar <pramod.kumar_1@nxp.com> Cc: Priyanka Jain <priyanka.jain@nxp.com> Cc: Rajesh Bhagat <rajesh.bhagat@nxp.com> Cc: Vladimir Oltean <olteanv@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
2f8a6db5 |
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14-Dec-2021 |
Tom Rini <trini@konsulko.com> |
Finish conversion of CONFIG_SYS_CLK_FREQ to Kconfig In order to finish moving this symbol to Kconfig for all platforms, we need to do a few more things. First, for all platforms that define this to a function, introduce CONFIG_DYNAMIC_SYS_CLK_FREQ, similar to CONFIG_DYNAMIC_DDR_CLK_FREQ and populate clock_legacy.h. This entails also switching all users from CONFIG_SYS_CLK_FREQ to get_board_sys_clk() and updating a few preprocessor tests. With that done, all platforms that define a value here can be converted to Kconfig, and a fall-back of zero is sufficiently safe to use (and what is used today in cases where code may or may not have this available). Make sure that code which calls this function includes <clock_legacy.h> to get the prototype. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
77b11f76 |
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18-Sep-2021 |
Vladimir Oltean <vladimir.oltean@nxp.com> |
net: replace the "xfi" phy-mode with "10gbase-r" As part of the effort of making U-Boot work with the same device tree as Linux, there is an issue with the "xfi" phy-mode. To be precise, in Linux there was a discussion (for those who have time to read: https://lore.kernel.org/netdev/1576768881-24971-2-git-send-email-madalin.bucur@oss.nxp.com/) which led to a patch: https://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next.git/commit/?id=c114574ebfdf42f826776f717c8056a00fa94881 TL;DR: "xfi" was standardized in Linux as "10gbase-r". This patch changes the relevant occurrences in U-Boot to use "10gbase-r" instead of "xfi" wherever applicable. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> |
#
84c2e044 |
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20-Apr-2021 |
Jiafei Pan <Jiafei.Pan@nxp.com> |
armv8: layerscape: add PSCI support for cpu release For cpu release command, check whether PSCI is supported firstly, if supported, use PSCI to kick off secondary cores, otherwise still use spin table. Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com> [Fixed checkpatch alignment CHECKs] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
35b65dd8 |
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15-Dec-2020 |
Harald Seiler <hws@denx.de> |
reset: Remove addr parameter from reset_cpu() Historically, the reset_cpu() function had an `addr` parameter which was meant to pass in an address of the reset vector location, where the CPU should reset to. This feature is no longer used anywhere in U-Boot as all reset_cpu() implementations now ignore the passed value. Generic code has been added which always calls reset_cpu() with `0` which means this feature can no longer be used easily anyway. Over time, many implementations seem to have "misunderstood" the existence of this parameter as a way to customize/parameterize the reset (e.g. COLD vs WARM resets). As this is not properly supported, the code will almost always not do what it is intended to (because all call-sites just call reset_cpu() with 0). To avoid confusion and to clean up the codebase from unused left-overs of the past, remove the `addr` parameter entirely. Code which intends to support different kinds of resets should be rewritten as a sysreset driver instead. This transformation was done with the following coccinelle patch: @@ expression argvalue; @@ - reset_cpu(argvalue) + reset_cpu() @@ identifier argname; type argtype; @@ - reset_cpu(argtype argname) + reset_cpu(void) { ... } Signed-off-by: Harald Seiler <hws@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
401d1c4f |
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30-Oct-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop asm/global_data.h from common header Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
3a187cff |
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29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
c760095a |
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23-Oct-2020 |
Razvan Ionut Cirjan <razvanionut.cirjan@nxp.com> |
net: lx2160a.c: Update to set ECx_PMUX precedence As per hardware documentation, ECx_PMUX has precedence over SerDes protocol. For LX2160/LX2162 if DPMACs 17 and 18 are enabled as SGMII through SerDes protocol but ECx_PMUX configured them as RGMII, then the ports will be configured as RGMII and not SGMII. Signed-off-by: Razvan Ionut Cirjan <razvanionut.cirjan@nxp.com> [Rebased] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
d31f3a1b |
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09-Sep-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2160a: fix reset sequence Make sure that SW_RST_REQ and RST_REQ_MSK are cleared before triggering hardware reset request. Signed-off-by: Thirupathaiah Annapureddy <thiruan@linux.microsoft.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
b75d8dc5 |
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26-Jun-2020 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
treewide: convert bd_t to struct bd_info by coccinelle The Linux coding style guide (Documentation/process/coding-style.rst) clearly says: It's a **mistake** to use typedef for structures and pointers. Besides, using typedef for structures is annoying when you try to make headers self-contained. Let's say you have the following function declaration in a header: void foo(bd_t *bd); This is not self-contained since bd_t is not defined. To tell the compiler what 'bd_t' is, you need to include <asm/u-boot.h> #include <asm/u-boot.h> void foo(bd_t *bd); Then, the include direcective pulls in more bloat needlessly. If you use 'struct bd_info' instead, it is enough to put a forward declaration as follows: struct bd_info; void foo(struct bd_info *bd); Right, typedef'ing bd_t is a mistake. I used coccinelle to generate this commit. The semantic patch that makes this change is as follows: <smpl> @@ typedef bd_t; @@ -bd_t +struct bd_info </smpl> Signed-off-by: Masahiro Yamada <masahiroy@kernel.org> |
#
25a5818f |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop asm/ptrace.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
f7ae49fc |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
90526e9f |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop net.h from common header Move this header out of the common header. Network support is used in quite a few places but it still does not warrant blanket inclusion. Note that this net.h header itself has quite a lot in it. It could be split into the driver-mode support, functions, structures, checksumming, etc. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
714497e3 |
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16-May-2020 |
Michael Walle <michael@walle.cc> |
efi_loader: round the memory area in efi_add_memory_map() Virtually all callers of this function do the rounding on their own. Some do it right, some don't. Instead of doing this in each caller, do the rounding in efi_add_memory_map(). Change the size parameter to bytes instead of pages and remove aligning and size calculation in all callers. There is no more need to make the original efi_add_memory_map() (which takes pages as size) available outside the module. Thus rename it to efi_add_memory_map_pg() and make it static to prevent further misuse outside the module. Signed-off-by: Michael Walle <michael@walle.cc> Add missing comma in sunxi_display.c. Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de> |
#
6eb32a03 |
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23-Apr-2020 |
Madalin Bucur <madalin.bucur@oss.nxp.com> |
driver: net: fm: add DM ETH support Probe the FMan MACs based on the device tree while retaining the legacy code/functionality. One notable change introduced here is that, for DM_ETH, the name of the interfaces is corrected to the fmX-macY format, that avoids the referral to the MAC block names which were incorrect for FMan v3 devices (i.e. DTSEC, TGEC) and had weird formatting (i.e. FM1@DTSEC6, FM1@TGEC1). The legacy code is left unchanged in this respect. Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
6ebd4883 |
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27-Apr-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
fsl-layerscape: Add RESV_RAM check in resv_ram addr The initialization of gd->arch.resv_ram pointer should depend on if the RESV_RAM config is enabled. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Wasim Khan <wasim.khan@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
0d9d557d |
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10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
db41d65a |
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28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move hang() to the same header as panic() At present panic() is in the vsprintf.h header file. That does not seem like an obvious choice for hang(), even though it relates to panic(). So let's put hang() in its own header. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Migrate a few more files] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
9b4a205f |
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28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move RAM-sizing functions to init.h These functions relate to memory init so move them into the init header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
3499dd03 |
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27-Nov-2019 |
Alex Marginean <alexandru.marginean@nxp.com> |
ls1028a: Configure stream IDs for integrated PCI and fix up Linux DT Hardware comes out of reset with implicit values, but these are outside the accepted range for Layerscape gen 3 chassis spec used on LS1028A. Allocate different IDs and fix up Linux DT to use them. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
b5981474 |
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14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some CPU functions out of common.h These functions belong in cpu_func.h since they do not use driver model. Move them over. Don't bother adding comments since these functions should be deleted. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
68a6aa85 |
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14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move mii_init() function out of common.h This function belongs in mii.h so move it over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
2189d5f1 |
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14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
Move strtomhz() to vsprintf.h At present this function sits in its own file but it does not really justify it. There are similar string functions in vsprintf.h, so move it there. Also add the missing function comment. Use the vsprintf.h include file explicitly where needed. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
812ff53c |
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30-Oct-2019 |
Pankaj Bansal <pankaj.bansal@nxp.com> |
fsl-layerscape: fix warning if no hwconfig is defined While getting the 'subarg' of 'hwconfig' env variable in config_core_prefetch(), if no hwconfig variable is defined, below warning is received: WARNING: Calling __hwconfig without a buffer and before environment is ready Fix this by checking 'hwconfig' env variable. If not found return without further processing. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Tested-by: Michael Walle <michael@walle.cc> |
#
28f9393b |
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17-Oct-2019 |
Mathew McBride <matt@traverse.com.au> |
fsl-layerscape: do not use layerscape EFI reset if PSCI used If the secure world reset handlers are used (via CONFIG_PSCI_RESET), then do not use the layerscape-specific implementation. Signed-off-by: Mathew McBride <matt@traverse.com.au> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
6ed69523 |
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18-Sep-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add more personalities support Add LS1027A, LS1018A and LS1017A personalities support to LS1028A SoC family. LS1028A is the prime personality of LS1028A SoC family. LS1027A is a lower funtionality version of QorIQ LS1028A which does not support the multimedia subsystems, such as LCD controller, GPU, and eDP PHY. The QorIQ LS1018A and LS1017A SoCs are single 64-bit Arm A72 core, low power versions of the QorIQ LS1028A and LS1027A SoCs respectively. Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
0490cab5 |
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08-Aug-2019 |
Thomas Schaefer <thomas.schaefer@kontron.com> |
armv8: ls1028a: configure PMU's PCTBENR to enable WDT The SP805-WDT module on LS1028A requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. The watchdog clock needs to be enabled first. Signed-off-by: Thomas Schaefer <thomas.schaefer@kontron.com> Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
f3998fdc |
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02-Aug-2019 |
Simon Glass <sjg@chromium.org> |
env: Rename environment.h to env_internal.h This file contains lots of internal details about the environment. Most code can include env.h instead, calling the functions there as needed. Rename this file and add a comment at the top to indicate its internal nature. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> [trini: Fixup apalis-tk1.c] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
3a7d5571 |
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01-Aug-2019 |
Simon Glass <sjg@chromium.org> |
env: Move env_get_f() to env.h Move this function over to the new header file. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
d9532e80 |
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23-Apr-2019 |
Udit Agarwal <udit.agarwal@nxp.com> |
armv8: fsl-layerscape: Set env_loc to ENVL_NOWHERE with CONFIG_ENV_IS_NOWHERE. ENVL_NOWHERE is dependent on CONFIG_ENV_IS_NOWHERE and not on CONFIG_CHAIN_OF_TRUST so return ENVL_NOWHERE when CONFIG_ENV_IS_NOWHERE is enabled Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
d4ad111d |
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10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
059d9422 |
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08-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: lx2160a: add MMU table entries for PCIe The lx2160a have up to 6 PCIe controllers and have different address and size of PCIe region. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
8348e798 |
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08-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: layerscape: use PCIe address macro for precompile PCIe MMU entry Change to use PCIe address macro to determine if precompile the PCIe MMU table entry. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
10015025 |
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03-May-2019 |
Trevor Woerner <trevor@toganlabs.com> |
CONFIG_SPL_SYS_[DI]CACHE_OFF: add While converting CONFIG_SYS_[DI]CACHE_OFF to Kconfig, there are instances where these configuration items are conditional on SPL. This commit adds SPL variants of these configuration items, uses CONFIG_IS_ENABLED(), and updates the configurations as required. Acked-by: Alexey Brodkin <abrodkin@synopsys.com> Signed-off-by: Trevor Woerner <trevor@toganlabs.com> [trini: Make the default depend on the setting for full U-Boot, update more zynq hardware] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
2e53759d |
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29-Oct-2018 |
Pankaj Bansal <pankaj.bansal@nxp.com> |
armv8: fsl-layerscape: reorder rgmii dpmacs' enablement some dpmacs in armv8a based freescale layerscape SOCs can be configured via both serdes(sgmii, xfi, xlaui etc) bits and via EC*_PMUX(rgmii) bits in RCW. e.g. dpmac 17 and 18 in LX2160A can be configured as SGMII from serdes bits and as RGMII via EC1_PMUX/EC2_PMUX bits Now if a dpmac is enabled by serdes bits then it takes precedence over EC*_PMUX bits. i.e. in LX2160A if we select serdes protocol that configures dpmac17 as SGMII and set the EC1_PMUX as RGMII, then the dpmac is SGMII and not RGMII. Therefore, move the fsl_rgmii_init after fsl_serdes_init. in fsl_rgmii_init function of SOC, we will check if the dpmac is enabled or not? if it is (fsl_serdes_init has already enabled the dpmac), then don't enable it. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
ec88ff80 |
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19-Dec-2018 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1043a: add SVR definitions for 23x23 package silicon LS1043A/LS1023A 23x23 package silicon has different SVR:VAR_PER. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
d23da2ae |
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26-Dec-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: fixes for TFABOOT framework Fixes for TFABOOT framework - update eMMC bootsrc to SD_MMC - Increase buffer size for mcinitcmd from 256 to 512 - Fix mcinitcmd and bootcmd for Secure Boot Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
4909b89e |
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29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
d6fdec21 |
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29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8:fsl-layerscape: Add support for Chassis 3.2 NXP layerscape architecture Chassis 3.2 builds upon chassis3 architecture with changes like DDR Memory map change, removal of IFC and support of upto 8 I2C controller. Patch add README.lsch3_2 and the above changes under macro CONFIG_NXP_LSCH3_2. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
56db948b |
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05-Nov-2018 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: Update parsing boot source Workaround of erratum A010539 clears the RCW source field in PORSR1 register, causing failure of detecting boot source using this method. Use SMC call if U-Boot runs at EL2. If SMC is not implemented or running at EL3, continue to read PORSR1 and presume QSPI as boot source if erratum workaround A010539 is enabled and RCW source is cleared. Signed-off-by: York Sun <york.sun@nxp.com> |
#
681d489e |
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05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: layerscape: add SMC calls for DDR size and bank info Adds SMC calls for getting DDR size and bank info for TFABOOT. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
2141d250 |
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05-Nov-2018 |
Pankit Garg <pankit.garg@nxp.com> |
armv8: fsl-layerscape: bootcmd identification for TFABOOT Adds bootcmd identificaton on basis on boot source, valid in TFABOOT configuration. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> [YS: remove unnecessary braces] Reviewed-by: York Sun <york.sun@nxp.com> |
#
4c417384 |
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05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com> |
#
535d76a1 |
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05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: layerscape: Add TFABOOT support Adds TFABOOT support config option and add generic code to enable execution from DDR. Signed-off-by: York Sun <york.sun@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> |
#
e3506480 |
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05-Nov-2018 |
Pankit Garg <pankit.garg@nxp.com> |
armv8: fsl-layerscape: change tlb base from OCRAM to DDR in EL < 3 Change tlb base address from OCRAM to DDR when exception level is less than 3. Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
d171c707 |
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05-Nov-2018 |
York Sun <york.sun@nxp.com> |
move data structure out of cpu.h Move static definitions to cpu.c file, as it doesn't allow the cpu.h file to be included in multiple c files. Signed-off-by: York Sun <york.sun@nxp.com> |
#
9b5e6396 |
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30-Aug-2018 |
Stephen Warren <swarren@nvidia.com> |
efi_loader: simplify ifdefs Use CONFIG_IS_ENABLED(EFI_LOADER) to avoid explicitly checking CONFIG_SPL too. This simplifies the conditional. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Alexander Graf <agraf@suse.de> |
#
9cce5663 |
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16-Jul-2018 |
Joe Hershberger <joe.hershberger@ni.com> |
arm: Prevent redefinition error in fsl-layerscape The include/phy.h will start including dm.h, which pulls in linux/compat.h after the attempted redefinition in arch/arm/include/asm/armv8/mmu.h, so move this include to allow redefinition. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> |
#
83d290c5 |
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06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
482fc90c |
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06-Feb-2018 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
efi_loader: add missing EFI_RESET_PLATFORM_SPECIFIC EFI_RESET_PLATFORM_SPECIFIC is one of the values that can be used for the EFI service ResetSystem. The missing definition is added. The value has to handled in efi_reset_system(). Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Alexander Graf <agraf@suse.de> |
#
22c793e6 |
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03-Mar-2018 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
efi_loader: exit status for efi_reset_system_init efi_reset_system_init provides the architecture or board specific initialization of the EFI subsystem. Errors should be caught and signalled by a return code. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Alexander Graf <agraf@suse.de> |
#
958b2ed5 |
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09-Jan-2018 |
Zhang Ying-22455 <ying.zhang22455@nxp.com> |
armv8/ls1088a: configure PMU's PCTBENR to enable WDT The SP805-WDT module on LS1088A requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. The watchdog clock needs to be enabled first. Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
44262327 |
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15-Dec-2017 |
Ahmed Mansour <ahmed.mansour@nxp.com> |
drivers/misc: Share qbman init between archs This patch adds changes necessary to move functionality present in PowerPC folders with ARM architectures that have DPAA1 QBMan hardware - Create new board/freescale/common/fsl_portals.c to house shared device tree fixups for DPAA1 devices with ARM and PowerPC cores - Add new header file to top includes directory to allow files in both architectures to grab the function prototypes - Port inhibit_portals() from PowerPC to ARM. This function is used in setup to disable interrupts on all QMan and BMan portals. It is needed because the interrupts are enabled by default for all portals including unused/uninitialised portals. When the kernel attempts to go to deep sleep the unused portals prevent it from doing so Signed-off-by: Ahmed Mansour <ahmed.mansour@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
a8f33034 |
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03-Dec-2017 |
Wenbin song <wenbin.song@nxp.com> |
armv8: ls1043a/ls2080a: check SoC by device ID Check LS1043A/LS2080a by device ID without using personality ID to determine revision number. This check applies to all various personalities of the same SoC family. Signed-off-by: Wenbin Song <wenbin.song@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
2db53cfe |
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09-Nov-2017 |
Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
armv8: fsl-layerscape: Add support of disabling core prefetch Instruction prefetch feature is by default enabled during core release. This patch add support of disabling instruction prefetch by setting core mask in PPA. Here each core mask bit represents a core and prefetch is disabled at the time of core release. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
7eb40f0f |
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28-Sep-2017 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: Avoid running dram_init_banksize again gd->ram_size is reduced in this function to reserve secure memory. Avoid running this function again to further reduce memory size. This fixes issue for SPL boot with PPA image loaded in which case secure memory is incorrectly allocated due to repeated calling. Signed-off-by: York Sun <york.sun@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
710d0cd7 |
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03-Oct-2017 |
Sumit Garg <sumit.garg@nxp.com> |
armv8: fsl-layerscape: Allocate Secure memory from first ddr region This change is required due to trusted OS (OP-TEE) not being position independent code, it requires compile time fixed base address. To take care of this it is assumed that all layerscape armv8 platforms has minimum 2G ddr in first region. So we can have fixed address space (66 MB -> (2MB for PPA + 64MB for trusted OS)) allocated from top of first 2G ddr region and compile trusted OS with this fixed base address. But one exception here is ls1012 where we have only 1G (rdb) or 512M (frdm) ddr memory. For those we can have different fixed compile time base addresses for trusted OS. Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
e9303a41 |
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07-Sep-2017 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: Fix MC reserved memory calculation In case high region memory doesn't have enough space for Management Complex (MC), the return value should indicate a failure so the caller can handle it accordingly. Signed-off-by: York Sun <york.sun@nxp.com> Reported-by: Ebony Zhu <ebony.zhu@nxp.com> |
#
17d066fc |
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31-Aug-2017 |
Ashish Kumar <Ashish.Kumar@nxp.com> |
armv8: fsl-layerscape: Support to add RGMII for ls1088aqds This patch adds support for RGMII protocol NXP's LDPAA2 support RGMII protocol. LS1088A is the first Soc supporting both RGMII and SGMII. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Amrita Kumari <amrita.kumari@nxp.com> Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
63b2316c |
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10-Aug-2017 |
Ashish Kumar <Ashish.Kumar@nxp.com> |
fsl-layerscape: Consolidate registers space defination for CCI-400 bus CoreLink Cache Coherent Interconnect (CCI) provides full cache coherency between two clusters of multi-core CPUs and I/O coherency for devices and I/O masters. This patch add new config option SYS_FSL_HAS_CCI400 and moves existing register space definaton of CCI-400 bus to fsl_immap to be shared. CONFIG_SYS_CCI400_ADDR is replaced with SYS_CCI400_OFFSET in Kconfig. Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> [YS: revised commit message, squashed patches for armv8 and armv7] Reviewed-by: York Sun <york.sun@nxp.com> |
#
6e2941d7 |
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17-May-2017 |
Simon Glass <sjg@chromium.org> |
common: freescale: Move arch-specific declarations The declarations should not be in common.h. Move them to the arch-specific headers. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Fixup thinko defined(FSL_LSCH3) -> defined(CONFIG_FSL_LSCH3)] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
399e2bb6 |
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15-May-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Make U-Boot EL2 safe When U-Boot boots from EL2, skip some lowlevel init code requiring EL3, including CCI-400/CCN-504, trust zone, GIC, etc. These initialization tasks are carried out before U-Boot runs. This applies to the RAM version image used for SPL boot if PPA is loaded first. Signed-off-by: York Sun <york.sun@nxp.com> |
#
1f55a938 |
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05-May-2017 |
Santan Kumar <santan.kumar@nxp.com> |
armv8: ls2080aqds: Add support for SD boot Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
e809e747 |
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27-Apr-2017 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: fsl-layerscape: Add NXP LS2081A, LS2041A SoC support The QorIQ LS2081A SoC has eight 64-bit ARM v8 Cortex A72 cores and is built on layerscape architecture. It is 40-pin derivative of LS2084A (non-AIOP personality of LS2088A). So feature-wise it is same as LS2084A. LS2041A is a 4-core personality of LS2081A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
026f30ec |
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18-Apr-2017 |
Yuantian Tang <andy.tang@nxp.com> |
arm: psci: make psci usable on single core socs PSCI can be used on both multiple and single core socs. Current implementation only allows PSCI to work on multiple core socs. This patch removes this restriction so that PSCI can work on single core socs as well. Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
4a3ab193 |
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27-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: ls2080a: Drop macro CONFIG_LS2080A Use CONFIG_ARCH_LS2080A instead. Signed-off-by: York Sun <york.sun@nxp.com> |
#
3eace37e |
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06-Apr-2017 |
Simon Glass <sjg@chromium.org> |
arm: freescale: Rename initdram() to fsl_initdram() This function name shadows a global name but is in fact different. This is very confusing. Rename it to help with the following refactoring. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
76b00aca |
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31-Mar-2017 |
Simon Glass <sjg@chromium.org> |
board_f: Drop setup_dram_config() wrapper By making dram_init_banksize() return an error code we can drop the wrapper. Adjust this and clean up all implementations. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
088454cd |
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31-Mar-2017 |
Simon Glass <sjg@chromium.org> |
board_f: Drop return value from initdram() At present we cannot use this function as an init sequence call without a wrapper, since it returns the RAM size. Adjust it to set the RAM size in global_data instead, and return 0 on success. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> |
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52c41180 |
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31-Mar-2017 |
Simon Glass <sjg@chromium.org> |
board_f: Drop board_type parameter from initdram() It looks like only cm5200 and tqm8xx use this feature, so we don't really need it in generic code. Drop it and have the users access gd->board_type directly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
3d8553f0 |
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02-Mar-2017 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
pci: layerscape: add LS2088A series SoC pcie support The LS2088A series SoCs has different physical memory map address and CCSR registers address against LS2080A series SoCs. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
eea1cb77 |
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13-Feb-2017 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8/fsl-layerscape: Update erratum A009635 implementation Erratum A009635 is valid only for LS2080A SoC and its personality. Add SoC svr check. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
4961eafc |
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06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Update early MMU for DDR after initialization In early MMU table, DDR has to be mapped as device memory to avoid speculative access. After DDR is initialized, it needs to be updated to normal memory to allow code execution. To simplify the code, dram_init() is moved into a common file as a weak function. Signed-off-by: York Sun <york.sun@nxp.com> |
#
a045a0c3 |
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06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Fix the sequence of changing MMU table This patch follows the break-before-make process when making changes to MMU table. MMU is disabled before changing TTBR to avoid any potential race condition. Signed-off-by: York Sun <york.sun@nxp.com> |
#
24f55496 |
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06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Update MMU mapping with actual DDR size Update mapping with actual DDR size. Non-existing memory should not be mapped as "normal" memory to avoid speculative access. Signed-off-by: York Sun <york.sun@nxp.com> |
#
36cc0de0 |
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06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Rewrite memory reservation For ARMv8 Layerscape SoCs, secure memory and MC memorey are reserved at the end of DDR. DDR is spit into two or three banks. This patch reverts commit aabd7ddb and simplifies the calculation of reserved memory, and moves the code into common SoC file. Secure memory is carved out first. DDR bank size is reduced. Reserved memory is then allocated on the top of available memory. U-Boot still has access to reserved memory as data transferring is needed. Device tree is fixed with reduced memory size to hide the reserved memory from OS. The same region is reserved for efi_loader. Signed-off-by: York Sun <york.sun@nxp.com> |
#
daa92644 |
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16-Jan-2017 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
ARMv8/sec_firmware: relocated and renamed the config FSL_PPA_ARMV8_PSCI Moved the config FSL_PPA_ARMV8_PSCI from fsl-layerscape's Kconfig to Kconfig under armv8 and renamed it to SEC_FIRMWARE_ARMV8_PSCI. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
904110c7 |
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10-Jan-2017 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8/fsl-lsch2: refactor the clock system initialization Up to now, there are 3 kind of SoCs under Layerscape Chassis 2, like LS1043A, LS1046A and LS1012A. But the clocks tree has a lot of differences, for instance, the IP modules have different dividers to derive its clock from Platform PLL. And the core cluster PLL and platform PLL maybe have different reference clocks, such as LS1012A. Another problem is which clock/PLL should be described by sys_info->freq_systembus, it is confused in Layerscape Chissis 2. This patch is to bind the sys_info->freq_systembus to the Platform PLL, and handle the different divider of IP modules separately between different SoCs, and separate reference clocks of core cluster PLL and platform PLL. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
2d16a1a6 |
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07-Dec-2016 |
macro.wave.z@gmail.com <macro.wave.z@gmail.com> |
ARMv8: LS1043A: change macro CONFIG_ARMV8_PSCI definition NXP/Freescale uses macro CONFIG_ARMV8_PSCI to enable their private PSCI implementation in PPA firmware, but this macro naming too generic, so this patch replaces it with a specic one CONFIG_FSL_PPA_ARMV8_PSCI. And this macro CONFIG_ARMV8_PSCI will be used for a generic PSCI for ARMv8 which will be added in following patchs. Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
02fb2761 |
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20-Nov-2016 |
Shengzhou Liu <Shengzhou.Liu@nxp.com> |
fsl/ddr: Add erratum_a009942_check_cpo and clean related erratum - add additional function erratum_a009942_check_cpo to check if the board needs tuning CPO calibration for optimal setting. - move ERRATUM_A009942(with revision to check cpo_sample option) from fsl_ddr_gen4.c to ctrl_regs.c for reuse on all DDR4/DDR3 parts. - move ERRATUM_A008378 from fsl_ddr_gen4.c to ctrl_regs.c - remove obsolete ERRATUM_A004934 which is replaced with ERRATUM_A009942. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> [YS: Replaced CONFIG_QEMU_E500 with CONFIG_ARCH_QEMU_E500] Reviewed-by: York Sun <york.sun@nxp.com> |
#
e87c673c |
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16-Nov-2016 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8/fsl-lsch3: Update code to release secondary cores NXP ARMv8 SoC LS2080A release all secondary cores in one-go. But other new SoCs like LS2088A, LS1088A release secondary cores one by one. Update code to release secondary cores based on SoC SVR Add code to release cores one by one for non LS2080A SoCs Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> [YS: remove "inline" from declaration of initiator_type] Reviewed-by: York Sun <york.sun@nxp.com> |
#
f6b96ff6 |
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16-Nov-2016 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Use SVR based timer base address detection Timer controller base address has been changed from LS2080A SoC (and its personalities) to new SoCs like LS2088A, LS1088A. Use SVR based timer base address detection to avoid compile time #ifdef. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
f6a70b3a |
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16-Nov-2016 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add generic get_svr() in assembly Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
78d57842 |
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16-Nov-2016 |
Alexander Graf <agraf@csgraf.de> |
armv8: fsl-layerscape: Add support for efi_loader RTS reset When implementing efi loader support, we can expose runtime services for payloads. One such service is CPU reset. This patch implements RTS CPU reset support for layerscape systems. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: York Sun <york.sun@nxp.com> |
#
ef9a5fd8 |
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13-Sep-2016 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: Fix "cpu status" command The core position is not continuous for some SoCs. For example, valid cores may present at position 0, 1, 4, 5, 8, 9, etc. Some registers (including boot release register) only count existing cores. Current implementation of cpu_mask() complies with the continuous numbering. However, command "cpu status" queries the spin table with actual core position. Add functions to calculate core position from core number, to correctly calculate offsets. Tested on LS2080ARDB and LS1043ARDB. Signed-off-by: York Sun <york.sun@nxp.com> |
#
5d1a7a9d |
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13-Sep-2016 |
Wenbin Song <wenbin.song@nxp.com> |
armv8/fsl-layerscape: print SoC revsion number The exact SoC revsion number can be recognized from U-Boot log. Signed-off-by: Wenbin Song <wenbin.song@nxp.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
cbe7706a |
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26-Sep-2016 |
Tom Rini <trini@konsulko.com> |
Merge git://git.denx.de/u-boot-fsl-qoriq trini: Drop local memset() from examples/standalone/mem_to_mem_idma2intr.c Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
1221ce45 |
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20-Sep-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
treewide: replace #include <asm/errno.h> with <linux/errno.h> Now, arch/${ARCH}/include/asm/errno.h and include/linux/errno.h have the same content. (both just wrap <asm-generic/errno.h>) Replace all include directives for <asm/errno.h> with <linux/errno.h>. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> [trini: Fixup include/clk.] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
b63a9506 |
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03-Aug-2016 |
York Sun <york.sun@nxp.com> |
armv8: ls2080a: Remove debug server support Debug server feature has been dropped from roadmap. Signed-off-by: York Sun <york.sun@nxp.com> |
#
ed7a3943 |
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22-Jul-2016 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: mmu: Fix enabling MMU MMU bit in SCTLR needs to be set explicitly after tables are created. It isn't an issue for EL3 becuase this bit is already set by early MMU setup. But for other exception levels this bit was not set. Signed-off-by: York Sun <york.sun@nxp.com> |
#
79119a4d |
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05-Jul-2016 |
Alison Wang <b18965@freescale.com> |
armv8: fsl-layerscape: Add A72 core detection Add support to detect Cortex-A72 core for printing it out. The Initiator Version of A72 core should be 0x4. Signed-off-by: Alison Wang <alison.wang@nxp.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
032d5bb4 |
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28-Jun-2016 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
ARMv8/Layerscape: switch SMP method accordingly If the PSCI and PPA is ready, skip the fixup for spin-table and waking secondary cores. Otherwise, change SMP method to spin-table, and the device node of PSCI will be removed. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
85cdf38e |
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28-Jun-2016 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: fsl-layerscape: add i/d-cache enable function to enable_caches This function assume that the d-cache and MMU has been enabled earlier, so it just created MMU table in main memory. But the assumption is not always correct, for example, the early setup is done in EL3, while enable_caches() is called when the PE has turned into another EL. Define the function mmu_setup() for fsl-layerscape to cover the weak one. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
5ad5823d |
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24-Jun-2016 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Convert to use common MMU framework Drop platform code to create static MMU tables. Use common framework to create MMU tables on the run. Tested on LS2080ARDB with secure and non-secure ram scenarios. Signed-off-by: York Sun <york.sun@nxp.com> |
#
e61a7534 |
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24-Jun-2016 |
York Sun <york.sun@nxp.com> |
armv8: Move secure_ram variable out of generic global data Secure_ram variable was put in generic global data. But only ARMv8 uses this variable. Move it to ARM specific data structure. Signed-off-by: York Sun <york.sun@nxp.com> |
#
a10a31ec |
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18-Jun-2016 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of git://git.denx.de/u-boot-usb Signed-off-by: Tom Rini <trini@konsulko.com> Conflicts: arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
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#
6fb522dc |
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12-Jun-2016 |
Sriram Dash <sriram.dash@nxp.com> |
arm64: fsl-layerscape: add get_svr and IS_SVR_REV helper Adds get_svr and IS_SVR_REV helpers for ARMv8 platforms, similar to PPC and ARMv7. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> |
#
a758177f |
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07-Jun-2016 |
Yunhui Cui <yunhui.cui@nxp.com> |
armv8/ls2080a: configure PMU's PCTBENR to enable WDT The SP805-WDT module on LS2080A requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. The watchdog clock needs to be enabled first. Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
acb8f5e9 |
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21-Apr-2016 |
Alison Wang <b18965@freescale.com> |
armv8: fsl-layerscape: Remove unnecessary flushing dcache As the issue about the stack will get corrupted when switching between the early and final mmu tables is fixed by commit 70e21b064, the workaround to flush dcache is unnecessary and should be removed. Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
3c1d218a |
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04-Apr-2016 |
York Sun <york.sun@nxp.com> |
armv8: LS2080A: Consolidate LS2080A and LS2085A LS2080A is the primary SoC, and LS2085A is a personality with AIOP and DPAA DDR. The RDB and QDS boards support both personality. By detecting the SVR at runtime, a single image per board can support both SoCs. It gives users flexibility to swtich SoC without the need to reprogram the board. Signed-off-by: York Sun <york.sun@nxp.com> CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
c05016ab |
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21-Mar-2016 |
Alexander Graf <agraf@csgraf.de> |
arm64: Fix layerscape mmu setup With commit 7985cdf we converted all systems except for the Layerscape SoCs to the generic descriptor table based page table setup. On the Layerscape SoCs however, we just provide an empty table stub and do the setup ourselves. To reserve enough memory for the tables, we need to override the default counting mechanism which would end up with an empty table because we have no maps. Fixes: 7985cdf Reported-by: York Sun <york.sun@nxp.com> CC: Alison Wang <alison.wang@nxp.com> CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Alexander Graf <agraf@suse.de> Tested-by: York Sun <york.sun@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
7985cdf7 |
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03-Mar-2016 |
Alexander Graf <agraf@csgraf.de> |
arm64: Remove non-full-va map code By now the code to only have a single page table level with 64k page size and 42 bit address space is no longer used by any board in tree, so we can safely remove it. To clean up code, move the layerscape mmu code to the new defines, removing redundant field definitions. Signed-off-by: Alexander Graf <agraf@suse.de> |
#
c0492141 |
|
07-Dec-2015 |
York Sun <yorksun@freescale.com> |
armv8: fsl-layerscale: Rewrite reserving memory for MC and debug server MC and debug server are not board-specific. Move reserving memory to SoC file, using the new board_reserve_ram_top function. Reduce debug server memory by 2MB to make room for secure memory. In the system with MC and debug server, the top of u-boot memory is not the end of memory. PRAM is not used for this reservation. Signed-off-by: York Sun <yorksun@freescale.com> |
#
c107c0c0 |
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04-Dec-2015 |
York Sun <yorksun@freescale.com> |
armv8: fsl-layerscape: Make DDR non secure in MMU tables DDR has been set as secure in MMU tables. Non-secure master such as SDHC DMA cannot access data correctly. Mixing secure and non- secure MMU entries requirs the MMU tables themselves in secure memory. This patch moves MMU tables into a secure DDR area. Early MMU tables are changed to set DDR as non-secure. A new table is added into final MMU tables so secure memory can have 2MB granuality. gd->secure_ram tracks the location of this secure memory. For ARMv8 SoCs, the RAM base is not zero and RAM is divided into several banks. gd->secure_ram needs to be maintained before using. This maintenance is board-specific, depending on the SoC and memory bank of the secure memory falls into. Signed-off-by: York Sun <yorksun@freescale.com> |
#
b4017364 |
|
04-Nov-2015 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
armv8: ls2085a: Add workaround of errata A009635 If the core runs at higher than x3 speed of the platform, there is possiblity about sev instruction to getting missed by other cores. This is because of SoC Run Control block may not able to sample the EVENTI(Sev) signals. Configure Run Control and EPU to periodically send out EVENTI signals to wake up A57 cores. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
d764129d |
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04-Nov-2015 |
Alison Wang <b18965@freescale.com> |
armv8/layerscape: Update MMU table with execute-never bits For most device addresses excution shouldn't be allowed. Revise the MMU table to enforce execute-never bits. OCRAM, DDR and IFC are allowed for excution. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Alison Wang <alison.wang@freescale.com> Reported-by: Zhichun Hua <zhichun.hua@freescale.com> |
#
44937214 |
|
09-Nov-2015 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
armv8: LS2080A: Rename LS2085A to reflect LS2080A LS2080A is a prime personality of Freescale’s LS2085A. It is a non-AIOP personality without support of DP-DDR, L2 switch, 1588, PCIe endpoint etc. So renaming existing LS2085A code base to reflect LS2080A (Prime personality) Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> [York Sun: Dropped #ifdef in cpu.c for cpu_type_list] Reviewed-by: York Sun <yorksun@freescale.com> |
#
e8297341 |
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26-Oct-2015 |
Shaohui Xie <Shaohui.Xie@freescale.com> |
armv8/ls1043a: Add Fman support Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
8281c58f |
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26-Oct-2015 |
Mingkai Hu <Mingkai.Hu@freescale.com> |
armv8/fsl_lsch2: Add fsl_lsch2 SoC Freescale LayerScape with Chassis Generation 2 is a set of SoCs with ARMv8 cores and 2rd generation of Chassis. Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
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9f3183d2 |
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26-Oct-2015 |
Mingkai Hu <Mingkai.Hu@freescale.com> |
armv8/fsl_lsch3: Change arch to fsl-layerscape There are two LS series processors are built on ARMv8 Layersacpe architecture currently, LS2085A and LS1043A. They are based on ARMv8 core although use different chassis, so create fsl-layerscape to refactor the common code for the LS series processors which also paves the way for adding LS1043A platform. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
8fd11135 |
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25-Sep-2022 |
Sean Anderson <sean.anderson@seco.com> |
arm64: layerscape: Support SYSRESET CONFIG_SYSRESET provides its own implementation of reset_cpu. Disable our version when it is enabled. Signed-off-by: Sean Anderson <sean.anderson@seco.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> |
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ce9c579e |
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13-Jun-2022 |
Andre Przywara <andre.przywara@arm.com> |
armv8: always use current exception level for TCR_ELx access Currently get_tcr() takes an "el" parameter, to select the proper version of the TCR_ELx system register. This is problematic in case of the Apple M1, since it runs with HCR_EL2.E2H fixed to 1, so TCR_EL2 is actually using the TCR_EL1 layout, and we get the wrong version. For U-Boot's purposes the only sensible choice here is the current exception level, and indeed most callers treat it like that, so let's remove that parameter and read the current EL inside the function. This allows us to check for the E2H bit, and pretend it's EL1 in this case. There are two callers which don't care about the EL, and they pass 0, which looks wrong, but is irrelevant in these two cases, since we don't use the return value there. So the change cannot affect those two. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Mark Kettenis <kettenis@openbsd.org> Tested-by: Mark Kettenis <kettenis@openbsd.org> |
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cda8f873 |
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11-May-2022 |
Ye Li <ye.li@nxp.com> |
caam: Fix crash in case caam_jr_probe failed If probing caam_jr returns failure, the variable "dev" will not be initialized, so we can't use dev->name for the error print. Otherwise it will cause crash. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Gaurav Jain <gaurav.jain@nxp.com> |
#
cb14cc88 |
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22-Apr-2022 |
Michael Walle <michael@walle.cc> |
armv8: layerscape: get rid of smc_call() There are two different implementations to do a secure monitor call: smc_call() and arm_smccc_smc(). The former is defined in fwcall.c and seems to be an ad-hoc implementation. The latter is imported from linux. smc_call() is also only available if CONFIG_ARMV8_PSCI is not defined. This makes it impossible to have both PSCI calls and PSCI implementation in one u-boot build. The layerscape SoC code decide at runtime via check_psci() if there is a PSCI support. Therefore, this is a prerequisite patch to add PSCI implementation support for the layerscape SoCs. Note, for the TFA part, this is only compile time tested with (ls1028ardb_tfa_defconfig). Signed-off-by: Michael Walle <michael@walle.cc> [Rebased] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
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dfb6da55 |
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05-Apr-2022 |
Marek Vasut <marex@denx.de> |
armv8: layerscape: env: Switch to arch_env_get_location() Implement arch_env_get_location() instead of env_get_location(), so that the env_get_location() can be implemented on board level and override the arch_env_get_location() architecture defaults. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Adam Ford <aford173@gmail.com> Cc: Fabio Estevam <festevam@denx.de> Cc: Marek Behún <marek.behun@nic.cz> Cc: Peng Fan <peng.fan@nxp.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefano Babic <sbabic@denx.de> Cc: Tim Harvey <tharvey@gateworks.com> Cc: Tom Rini <trini@konsulko.com> Cc: Tommaso Merciai <tomm.merciai@gmail.com> Cc: Vladimir Oltean <vladimir.oltean@nxp.com> |
#
8976556a |
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24-Mar-2022 |
Gaurav Jain <gaurav.jain@nxp.com> |
Layerscape: Enable Job ring driver model. LS(1021/1012/1028/1043/1046/1088/2088), LX2160, LX2162 platforms are enabled with JR driver model. removed sec_init() call from board files. sec is initialized based on job ring information processed from device tree. Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Michael Walle <michael@walle.cc> |
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f9147d63 |
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25-Feb-2022 |
Tom Rini <trini@konsulko.com> |
Convert CONFIG_CHIP_SELECTS_PER_CTRL to Kconfig This converts the following to Kconfig: CONFIG_CHIP_SELECTS_PER_CTRL Cc: Alison Wang <alison.wang@nxp.com> Cc: Pramod Kumar <pramod.kumar_1@nxp.com> Cc: Priyanka Jain <priyanka.jain@nxp.com> Cc: Rajesh Bhagat <rajesh.bhagat@nxp.com> Cc: Vladimir Oltean <olteanv@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com> |
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2f8a6db5 |
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14-Dec-2021 |
Tom Rini <trini@konsulko.com> |
Finish conversion of CONFIG_SYS_CLK_FREQ to Kconfig In order to finish moving this symbol to Kconfig for all platforms, we need to do a few more things. First, for all platforms that define this to a function, introduce CONFIG_DYNAMIC_SYS_CLK_FREQ, similar to CONFIG_DYNAMIC_DDR_CLK_FREQ and populate clock_legacy.h. This entails also switching all users from CONFIG_SYS_CLK_FREQ to get_board_sys_clk() and updating a few preprocessor tests. With that done, all platforms that define a value here can be converted to Kconfig, and a fall-back of zero is sufficiently safe to use (and what is used today in cases where code may or may not have this available). Make sure that code which calls this function includes <clock_legacy.h> to get the prototype. Signed-off-by: Tom Rini <trini@konsulko.com> |
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77b11f76 |
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18-Sep-2021 |
Vladimir Oltean <vladimir.oltean@nxp.com> |
net: replace the "xfi" phy-mode with "10gbase-r" As part of the effort of making U-Boot work with the same device tree as Linux, there is an issue with the "xfi" phy-mode. To be precise, in Linux there was a discussion (for those who have time to read: https://lore.kernel.org/netdev/1576768881-24971-2-git-send-email-madalin.bucur@oss.nxp.com/) which led to a patch: https://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next.git/commit/?id=c114574ebfdf42f826776f717c8056a00fa94881 TL;DR: "xfi" was standardized in Linux as "10gbase-r". This patch changes the relevant occurrences in U-Boot to use "10gbase-r" instead of "xfi" wherever applicable. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> |
#
84c2e044 |
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20-Apr-2021 |
Jiafei Pan <Jiafei.Pan@nxp.com> |
armv8: layerscape: add PSCI support for cpu release For cpu release command, check whether PSCI is supported firstly, if supported, use PSCI to kick off secondary cores, otherwise still use spin table. Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com> [Fixed checkpatch alignment CHECKs] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
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35b65dd8 |
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15-Dec-2020 |
Harald Seiler <hws@denx.de> |
reset: Remove addr parameter from reset_cpu() Historically, the reset_cpu() function had an `addr` parameter which was meant to pass in an address of the reset vector location, where the CPU should reset to. This feature is no longer used anywhere in U-Boot as all reset_cpu() implementations now ignore the passed value. Generic code has been added which always calls reset_cpu() with `0` which means this feature can no longer be used easily anyway. Over time, many implementations seem to have "misunderstood" the existence of this parameter as a way to customize/parameterize the reset (e.g. COLD vs WARM resets). As this is not properly supported, the code will almost always not do what it is intended to (because all call-sites just call reset_cpu() with 0). To avoid confusion and to clean up the codebase from unused left-overs of the past, remove the `addr` parameter entirely. Code which intends to support different kinds of resets should be rewritten as a sysreset driver instead. This transformation was done with the following coccinelle patch: @@ expression argvalue; @@ - reset_cpu(argvalue) + reset_cpu() @@ identifier argname; type argtype; @@ - reset_cpu(argtype argname) + reset_cpu(void) { ... } Signed-off-by: Harald Seiler <hws@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> |
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401d1c4f |
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30-Oct-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop asm/global_data.h from common header Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com> |
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3a187cff |
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29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
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c760095a |
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23-Oct-2020 |
Razvan Ionut Cirjan <razvanionut.cirjan@nxp.com> |
net: lx2160a.c: Update to set ECx_PMUX precedence As per hardware documentation, ECx_PMUX has precedence over SerDes protocol. For LX2160/LX2162 if DPMACs 17 and 18 are enabled as SGMII through SerDes protocol but ECx_PMUX configured them as RGMII, then the ports will be configured as RGMII and not SGMII. Signed-off-by: Razvan Ionut Cirjan <razvanionut.cirjan@nxp.com> [Rebased] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
d31f3a1b |
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09-Sep-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2160a: fix reset sequence Make sure that SW_RST_REQ and RST_REQ_MSK are cleared before triggering hardware reset request. Signed-off-by: Thirupathaiah Annapureddy <thiruan@linux.microsoft.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
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b75d8dc5 |
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26-Jun-2020 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
treewide: convert bd_t to struct bd_info by coccinelle The Linux coding style guide (Documentation/process/coding-style.rst) clearly says: It's a **mistake** to use typedef for structures and pointers. Besides, using typedef for structures is annoying when you try to make headers self-contained. Let's say you have the following function declaration in a header: void foo(bd_t *bd); This is not self-contained since bd_t is not defined. To tell the compiler what 'bd_t' is, you need to include <asm/u-boot.h> #include <asm/u-boot.h> void foo(bd_t *bd); Then, the include direcective pulls in more bloat needlessly. If you use 'struct bd_info' instead, it is enough to put a forward declaration as follows: struct bd_info; void foo(struct bd_info *bd); Right, typedef'ing bd_t is a mistake. I used coccinelle to generate this commit. The semantic patch that makes this change is as follows: <smpl> @@ typedef bd_t; @@ -bd_t +struct bd_info </smpl> Signed-off-by: Masahiro Yamada <masahiroy@kernel.org> |
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25a5818f |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop asm/ptrace.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
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f7ae49fc |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
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90526e9f |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop net.h from common header Move this header out of the common header. Network support is used in quite a few places but it still does not warrant blanket inclusion. Note that this net.h header itself has quite a lot in it. It could be split into the driver-mode support, functions, structures, checksumming, etc. Signed-off-by: Simon Glass <sjg@chromium.org> |
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714497e3 |
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16-May-2020 |
Michael Walle <michael@walle.cc> |
efi_loader: round the memory area in efi_add_memory_map() Virtually all callers of this function do the rounding on their own. Some do it right, some don't. Instead of doing this in each caller, do the rounding in efi_add_memory_map(). Change the size parameter to bytes instead of pages and remove aligning and size calculation in all callers. There is no more need to make the original efi_add_memory_map() (which takes pages as size) available outside the module. Thus rename it to efi_add_memory_map_pg() and make it static to prevent further misuse outside the module. Signed-off-by: Michael Walle <michael@walle.cc> Add missing comma in sunxi_display.c. Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de> |
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6eb32a03 |
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23-Apr-2020 |
Madalin Bucur <madalin.bucur@oss.nxp.com> |
driver: net: fm: add DM ETH support Probe the FMan MACs based on the device tree while retaining the legacy code/functionality. One notable change introduced here is that, for DM_ETH, the name of the interfaces is corrected to the fmX-macY format, that avoids the referral to the MAC block names which were incorrect for FMan v3 devices (i.e. DTSEC, TGEC) and had weird formatting (i.e. FM1@DTSEC6, FM1@TGEC1). The legacy code is left unchanged in this respect. Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
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6ebd4883 |
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27-Apr-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
fsl-layerscape: Add RESV_RAM check in resv_ram addr The initialization of gd->arch.resv_ram pointer should depend on if the RESV_RAM config is enabled. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Wasim Khan <wasim.khan@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
0d9d557d |
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10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
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db41d65a |
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28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move hang() to the same header as panic() At present panic() is in the vsprintf.h header file. That does not seem like an obvious choice for hang(), even though it relates to panic(). So let's put hang() in its own header. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Migrate a few more files] Signed-off-by: Tom Rini <trini@konsulko.com> |
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9b4a205f |
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28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move RAM-sizing functions to init.h These functions relate to memory init so move them into the init header. Signed-off-by: Simon Glass <sjg@chromium.org> |
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3499dd03 |
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27-Nov-2019 |
Alex Marginean <alexandru.marginean@nxp.com> |
ls1028a: Configure stream IDs for integrated PCI and fix up Linux DT Hardware comes out of reset with implicit values, but these are outside the accepted range for Layerscape gen 3 chassis spec used on LS1028A. Allocate different IDs and fix up Linux DT to use them. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
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b5981474 |
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14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some CPU functions out of common.h These functions belong in cpu_func.h since they do not use driver model. Move them over. Don't bother adding comments since these functions should be deleted. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
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68a6aa85 |
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14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move mii_init() function out of common.h This function belongs in mii.h so move it over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
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2189d5f1 |
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14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
Move strtomhz() to vsprintf.h At present this function sits in its own file but it does not really justify it. There are similar string functions in vsprintf.h, so move it there. Also add the missing function comment. Use the vsprintf.h include file explicitly where needed. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
812ff53c |
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30-Oct-2019 |
Pankaj Bansal <pankaj.bansal@nxp.com> |
fsl-layerscape: fix warning if no hwconfig is defined While getting the 'subarg' of 'hwconfig' env variable in config_core_prefetch(), if no hwconfig variable is defined, below warning is received: WARNING: Calling __hwconfig without a buffer and before environment is ready Fix this by checking 'hwconfig' env variable. If not found return without further processing. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Tested-by: Michael Walle <michael@walle.cc> |
#
28f9393b |
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17-Oct-2019 |
Mathew McBride <matt@traverse.com.au> |
fsl-layerscape: do not use layerscape EFI reset if PSCI used If the secure world reset handlers are used (via CONFIG_PSCI_RESET), then do not use the layerscape-specific implementation. Signed-off-by: Mathew McBride <matt@traverse.com.au> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
6ed69523 |
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18-Sep-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add more personalities support Add LS1027A, LS1018A and LS1017A personalities support to LS1028A SoC family. LS1028A is the prime personality of LS1028A SoC family. LS1027A is a lower funtionality version of QorIQ LS1028A which does not support the multimedia subsystems, such as LCD controller, GPU, and eDP PHY. The QorIQ LS1018A and LS1017A SoCs are single 64-bit Arm A72 core, low power versions of the QorIQ LS1028A and LS1027A SoCs respectively. Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
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0490cab5 |
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08-Aug-2019 |
Thomas Schaefer <thomas.schaefer@kontron.com> |
armv8: ls1028a: configure PMU's PCTBENR to enable WDT The SP805-WDT module on LS1028A requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. The watchdog clock needs to be enabled first. Signed-off-by: Thomas Schaefer <thomas.schaefer@kontron.com> Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
f3998fdc |
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02-Aug-2019 |
Simon Glass <sjg@chromium.org> |
env: Rename environment.h to env_internal.h This file contains lots of internal details about the environment. Most code can include env.h instead, calling the functions there as needed. Rename this file and add a comment at the top to indicate its internal nature. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> [trini: Fixup apalis-tk1.c] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
3a7d5571 |
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01-Aug-2019 |
Simon Glass <sjg@chromium.org> |
env: Move env_get_f() to env.h Move this function over to the new header file. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
d9532e80 |
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23-Apr-2019 |
Udit Agarwal <udit.agarwal@nxp.com> |
armv8: fsl-layerscape: Set env_loc to ENVL_NOWHERE with CONFIG_ENV_IS_NOWHERE. ENVL_NOWHERE is dependent on CONFIG_ENV_IS_NOWHERE and not on CONFIG_CHAIN_OF_TRUST so return ENVL_NOWHERE when CONFIG_ENV_IS_NOWHERE is enabled Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
d4ad111d |
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10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
059d9422 |
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08-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: lx2160a: add MMU table entries for PCIe The lx2160a have up to 6 PCIe controllers and have different address and size of PCIe region. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
8348e798 |
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08-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: layerscape: use PCIe address macro for precompile PCIe MMU entry Change to use PCIe address macro to determine if precompile the PCIe MMU table entry. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
10015025 |
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03-May-2019 |
Trevor Woerner <trevor@toganlabs.com> |
CONFIG_SPL_SYS_[DI]CACHE_OFF: add While converting CONFIG_SYS_[DI]CACHE_OFF to Kconfig, there are instances where these configuration items are conditional on SPL. This commit adds SPL variants of these configuration items, uses CONFIG_IS_ENABLED(), and updates the configurations as required. Acked-by: Alexey Brodkin <abrodkin@synopsys.com> Signed-off-by: Trevor Woerner <trevor@toganlabs.com> [trini: Make the default depend on the setting for full U-Boot, update more zynq hardware] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
2e53759d |
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29-Oct-2018 |
Pankaj Bansal <pankaj.bansal@nxp.com> |
armv8: fsl-layerscape: reorder rgmii dpmacs' enablement some dpmacs in armv8a based freescale layerscape SOCs can be configured via both serdes(sgmii, xfi, xlaui etc) bits and via EC*_PMUX(rgmii) bits in RCW. e.g. dpmac 17 and 18 in LX2160A can be configured as SGMII from serdes bits and as RGMII via EC1_PMUX/EC2_PMUX bits Now if a dpmac is enabled by serdes bits then it takes precedence over EC*_PMUX bits. i.e. in LX2160A if we select serdes protocol that configures dpmac17 as SGMII and set the EC1_PMUX as RGMII, then the dpmac is SGMII and not RGMII. Therefore, move the fsl_rgmii_init after fsl_serdes_init. in fsl_rgmii_init function of SOC, we will check if the dpmac is enabled or not? if it is (fsl_serdes_init has already enabled the dpmac), then don't enable it. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
ec88ff80 |
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19-Dec-2018 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1043a: add SVR definitions for 23x23 package silicon LS1043A/LS1023A 23x23 package silicon has different SVR:VAR_PER. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
d23da2ae |
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26-Dec-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: fixes for TFABOOT framework Fixes for TFABOOT framework - update eMMC bootsrc to SD_MMC - Increase buffer size for mcinitcmd from 256 to 512 - Fix mcinitcmd and bootcmd for Secure Boot Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
4909b89e |
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29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
d6fdec21 |
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29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8:fsl-layerscape: Add support for Chassis 3.2 NXP layerscape architecture Chassis 3.2 builds upon chassis3 architecture with changes like DDR Memory map change, removal of IFC and support of upto 8 I2C controller. Patch add README.lsch3_2 and the above changes under macro CONFIG_NXP_LSCH3_2. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
56db948b |
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05-Nov-2018 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: Update parsing boot source Workaround of erratum A010539 clears the RCW source field in PORSR1 register, causing failure of detecting boot source using this method. Use SMC call if U-Boot runs at EL2. If SMC is not implemented or running at EL3, continue to read PORSR1 and presume QSPI as boot source if erratum workaround A010539 is enabled and RCW source is cleared. Signed-off-by: York Sun <york.sun@nxp.com> |
#
681d489e |
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05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: layerscape: add SMC calls for DDR size and bank info Adds SMC calls for getting DDR size and bank info for TFABOOT. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
2141d250 |
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05-Nov-2018 |
Pankit Garg <pankit.garg@nxp.com> |
armv8: fsl-layerscape: bootcmd identification for TFABOOT Adds bootcmd identificaton on basis on boot source, valid in TFABOOT configuration. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> [YS: remove unnecessary braces] Reviewed-by: York Sun <york.sun@nxp.com> |
#
4c417384 |
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05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com> |
#
535d76a1 |
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05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: layerscape: Add TFABOOT support Adds TFABOOT support config option and add generic code to enable execution from DDR. Signed-off-by: York Sun <york.sun@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> |
#
e3506480 |
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05-Nov-2018 |
Pankit Garg <pankit.garg@nxp.com> |
armv8: fsl-layerscape: change tlb base from OCRAM to DDR in EL < 3 Change tlb base address from OCRAM to DDR when exception level is less than 3. Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
d171c707 |
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05-Nov-2018 |
York Sun <york.sun@nxp.com> |
move data structure out of cpu.h Move static definitions to cpu.c file, as it doesn't allow the cpu.h file to be included in multiple c files. Signed-off-by: York Sun <york.sun@nxp.com> |
#
9b5e6396 |
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30-Aug-2018 |
Stephen Warren <swarren@nvidia.com> |
efi_loader: simplify ifdefs Use CONFIG_IS_ENABLED(EFI_LOADER) to avoid explicitly checking CONFIG_SPL too. This simplifies the conditional. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Alexander Graf <agraf@suse.de> |
#
9cce5663 |
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16-Jul-2018 |
Joe Hershberger <joe.hershberger@ni.com> |
arm: Prevent redefinition error in fsl-layerscape The include/phy.h will start including dm.h, which pulls in linux/compat.h after the attempted redefinition in arch/arm/include/asm/armv8/mmu.h, so move this include to allow redefinition. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> |
#
83d290c5 |
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06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
482fc90c |
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06-Feb-2018 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
efi_loader: add missing EFI_RESET_PLATFORM_SPECIFIC EFI_RESET_PLATFORM_SPECIFIC is one of the values that can be used for the EFI service ResetSystem. The missing definition is added. The value has to handled in efi_reset_system(). Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Alexander Graf <agraf@suse.de> |
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22c793e6 |
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03-Mar-2018 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
efi_loader: exit status for efi_reset_system_init efi_reset_system_init provides the architecture or board specific initialization of the EFI subsystem. Errors should be caught and signalled by a return code. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Alexander Graf <agraf@suse.de> |
#
958b2ed5 |
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09-Jan-2018 |
Zhang Ying-22455 <ying.zhang22455@nxp.com> |
armv8/ls1088a: configure PMU's PCTBENR to enable WDT The SP805-WDT module on LS1088A requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. The watchdog clock needs to be enabled first. Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
44262327 |
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15-Dec-2017 |
Ahmed Mansour <ahmed.mansour@nxp.com> |
drivers/misc: Share qbman init between archs This patch adds changes necessary to move functionality present in PowerPC folders with ARM architectures that have DPAA1 QBMan hardware - Create new board/freescale/common/fsl_portals.c to house shared device tree fixups for DPAA1 devices with ARM and PowerPC cores - Add new header file to top includes directory to allow files in both architectures to grab the function prototypes - Port inhibit_portals() from PowerPC to ARM. This function is used in setup to disable interrupts on all QMan and BMan portals. It is needed because the interrupts are enabled by default for all portals including unused/uninitialised portals. When the kernel attempts to go to deep sleep the unused portals prevent it from doing so Signed-off-by: Ahmed Mansour <ahmed.mansour@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
a8f33034 |
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03-Dec-2017 |
Wenbin song <wenbin.song@nxp.com> |
armv8: ls1043a/ls2080a: check SoC by device ID Check LS1043A/LS2080a by device ID without using personality ID to determine revision number. This check applies to all various personalities of the same SoC family. Signed-off-by: Wenbin Song <wenbin.song@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
2db53cfe |
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09-Nov-2017 |
Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
armv8: fsl-layerscape: Add support of disabling core prefetch Instruction prefetch feature is by default enabled during core release. This patch add support of disabling instruction prefetch by setting core mask in PPA. Here each core mask bit represents a core and prefetch is disabled at the time of core release. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
7eb40f0f |
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28-Sep-2017 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: Avoid running dram_init_banksize again gd->ram_size is reduced in this function to reserve secure memory. Avoid running this function again to further reduce memory size. This fixes issue for SPL boot with PPA image loaded in which case secure memory is incorrectly allocated due to repeated calling. Signed-off-by: York Sun <york.sun@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
710d0cd7 |
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03-Oct-2017 |
Sumit Garg <sumit.garg@nxp.com> |
armv8: fsl-layerscape: Allocate Secure memory from first ddr region This change is required due to trusted OS (OP-TEE) not being position independent code, it requires compile time fixed base address. To take care of this it is assumed that all layerscape armv8 platforms has minimum 2G ddr in first region. So we can have fixed address space (66 MB -> (2MB for PPA + 64MB for trusted OS)) allocated from top of first 2G ddr region and compile trusted OS with this fixed base address. But one exception here is ls1012 where we have only 1G (rdb) or 512M (frdm) ddr memory. For those we can have different fixed compile time base addresses for trusted OS. Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
e9303a41 |
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07-Sep-2017 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: Fix MC reserved memory calculation In case high region memory doesn't have enough space for Management Complex (MC), the return value should indicate a failure so the caller can handle it accordingly. Signed-off-by: York Sun <york.sun@nxp.com> Reported-by: Ebony Zhu <ebony.zhu@nxp.com> |
#
17d066fc |
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31-Aug-2017 |
Ashish Kumar <Ashish.Kumar@nxp.com> |
armv8: fsl-layerscape: Support to add RGMII for ls1088aqds This patch adds support for RGMII protocol NXP's LDPAA2 support RGMII protocol. LS1088A is the first Soc supporting both RGMII and SGMII. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Amrita Kumari <amrita.kumari@nxp.com> Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
63b2316c |
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10-Aug-2017 |
Ashish Kumar <Ashish.Kumar@nxp.com> |
fsl-layerscape: Consolidate registers space defination for CCI-400 bus CoreLink Cache Coherent Interconnect (CCI) provides full cache coherency between two clusters of multi-core CPUs and I/O coherency for devices and I/O masters. This patch add new config option SYS_FSL_HAS_CCI400 and moves existing register space definaton of CCI-400 bus to fsl_immap to be shared. CONFIG_SYS_CCI400_ADDR is replaced with SYS_CCI400_OFFSET in Kconfig. Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> [YS: revised commit message, squashed patches for armv8 and armv7] Reviewed-by: York Sun <york.sun@nxp.com> |
#
6e2941d7 |
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17-May-2017 |
Simon Glass <sjg@chromium.org> |
common: freescale: Move arch-specific declarations The declarations should not be in common.h. Move them to the arch-specific headers. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Fixup thinko defined(FSL_LSCH3) -> defined(CONFIG_FSL_LSCH3)] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
399e2bb6 |
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15-May-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Make U-Boot EL2 safe When U-Boot boots from EL2, skip some lowlevel init code requiring EL3, including CCI-400/CCN-504, trust zone, GIC, etc. These initialization tasks are carried out before U-Boot runs. This applies to the RAM version image used for SPL boot if PPA is loaded first. Signed-off-by: York Sun <york.sun@nxp.com> |
#
1f55a938 |
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05-May-2017 |
Santan Kumar <santan.kumar@nxp.com> |
armv8: ls2080aqds: Add support for SD boot Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
e809e747 |
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27-Apr-2017 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: fsl-layerscape: Add NXP LS2081A, LS2041A SoC support The QorIQ LS2081A SoC has eight 64-bit ARM v8 Cortex A72 cores and is built on layerscape architecture. It is 40-pin derivative of LS2084A (non-AIOP personality of LS2088A). So feature-wise it is same as LS2084A. LS2041A is a 4-core personality of LS2081A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
026f30ec |
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18-Apr-2017 |
Yuantian Tang <andy.tang@nxp.com> |
arm: psci: make psci usable on single core socs PSCI can be used on both multiple and single core socs. Current implementation only allows PSCI to work on multiple core socs. This patch removes this restriction so that PSCI can work on single core socs as well. Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
4a3ab193 |
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27-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: ls2080a: Drop macro CONFIG_LS2080A Use CONFIG_ARCH_LS2080A instead. Signed-off-by: York Sun <york.sun@nxp.com> |
#
3eace37e |
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06-Apr-2017 |
Simon Glass <sjg@chromium.org> |
arm: freescale: Rename initdram() to fsl_initdram() This function name shadows a global name but is in fact different. This is very confusing. Rename it to help with the following refactoring. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
76b00aca |
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31-Mar-2017 |
Simon Glass <sjg@chromium.org> |
board_f: Drop setup_dram_config() wrapper By making dram_init_banksize() return an error code we can drop the wrapper. Adjust this and clean up all implementations. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
088454cd |
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31-Mar-2017 |
Simon Glass <sjg@chromium.org> |
board_f: Drop return value from initdram() At present we cannot use this function as an init sequence call without a wrapper, since it returns the RAM size. Adjust it to set the RAM size in global_data instead, and return 0 on success. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
52c41180 |
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31-Mar-2017 |
Simon Glass <sjg@chromium.org> |
board_f: Drop board_type parameter from initdram() It looks like only cm5200 and tqm8xx use this feature, so we don't really need it in generic code. Drop it and have the users access gd->board_type directly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
3d8553f0 |
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02-Mar-2017 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
pci: layerscape: add LS2088A series SoC pcie support The LS2088A series SoCs has different physical memory map address and CCSR registers address against LS2080A series SoCs. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
eea1cb77 |
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13-Feb-2017 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8/fsl-layerscape: Update erratum A009635 implementation Erratum A009635 is valid only for LS2080A SoC and its personality. Add SoC svr check. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
4961eafc |
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06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Update early MMU for DDR after initialization In early MMU table, DDR has to be mapped as device memory to avoid speculative access. After DDR is initialized, it needs to be updated to normal memory to allow code execution. To simplify the code, dram_init() is moved into a common file as a weak function. Signed-off-by: York Sun <york.sun@nxp.com> |
#
a045a0c3 |
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06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Fix the sequence of changing MMU table This patch follows the break-before-make process when making changes to MMU table. MMU is disabled before changing TTBR to avoid any potential race condition. Signed-off-by: York Sun <york.sun@nxp.com> |
#
24f55496 |
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06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Update MMU mapping with actual DDR size Update mapping with actual DDR size. Non-existing memory should not be mapped as "normal" memory to avoid speculative access. Signed-off-by: York Sun <york.sun@nxp.com> |
#
36cc0de0 |
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06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Rewrite memory reservation For ARMv8 Layerscape SoCs, secure memory and MC memorey are reserved at the end of DDR. DDR is spit into two or three banks. This patch reverts commit aabd7ddb and simplifies the calculation of reserved memory, and moves the code into common SoC file. Secure memory is carved out first. DDR bank size is reduced. Reserved memory is then allocated on the top of available memory. U-Boot still has access to reserved memory as data transferring is needed. Device tree is fixed with reduced memory size to hide the reserved memory from OS. The same region is reserved for efi_loader. Signed-off-by: York Sun <york.sun@nxp.com> |
#
daa92644 |
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16-Jan-2017 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
ARMv8/sec_firmware: relocated and renamed the config FSL_PPA_ARMV8_PSCI Moved the config FSL_PPA_ARMV8_PSCI from fsl-layerscape's Kconfig to Kconfig under armv8 and renamed it to SEC_FIRMWARE_ARMV8_PSCI. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
904110c7 |
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10-Jan-2017 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8/fsl-lsch2: refactor the clock system initialization Up to now, there are 3 kind of SoCs under Layerscape Chassis 2, like LS1043A, LS1046A and LS1012A. But the clocks tree has a lot of differences, for instance, the IP modules have different dividers to derive its clock from Platform PLL. And the core cluster PLL and platform PLL maybe have different reference clocks, such as LS1012A. Another problem is which clock/PLL should be described by sys_info->freq_systembus, it is confused in Layerscape Chissis 2. This patch is to bind the sys_info->freq_systembus to the Platform PLL, and handle the different divider of IP modules separately between different SoCs, and separate reference clocks of core cluster PLL and platform PLL. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
2d16a1a6 |
|
07-Dec-2016 |
macro.wave.z@gmail.com <macro.wave.z@gmail.com> |
ARMv8: LS1043A: change macro CONFIG_ARMV8_PSCI definition NXP/Freescale uses macro CONFIG_ARMV8_PSCI to enable their private PSCI implementation in PPA firmware, but this macro naming too generic, so this patch replaces it with a specic one CONFIG_FSL_PPA_ARMV8_PSCI. And this macro CONFIG_ARMV8_PSCI will be used for a generic PSCI for ARMv8 which will be added in following patchs. Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
02fb2761 |
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20-Nov-2016 |
Shengzhou Liu <Shengzhou.Liu@nxp.com> |
fsl/ddr: Add erratum_a009942_check_cpo and clean related erratum - add additional function erratum_a009942_check_cpo to check if the board needs tuning CPO calibration for optimal setting. - move ERRATUM_A009942(with revision to check cpo_sample option) from fsl_ddr_gen4.c to ctrl_regs.c for reuse on all DDR4/DDR3 parts. - move ERRATUM_A008378 from fsl_ddr_gen4.c to ctrl_regs.c - remove obsolete ERRATUM_A004934 which is replaced with ERRATUM_A009942. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> [YS: Replaced CONFIG_QEMU_E500 with CONFIG_ARCH_QEMU_E500] Reviewed-by: York Sun <york.sun@nxp.com> |
#
e87c673c |
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16-Nov-2016 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8/fsl-lsch3: Update code to release secondary cores NXP ARMv8 SoC LS2080A release all secondary cores in one-go. But other new SoCs like LS2088A, LS1088A release secondary cores one by one. Update code to release secondary cores based on SoC SVR Add code to release cores one by one for non LS2080A SoCs Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> [YS: remove "inline" from declaration of initiator_type] Reviewed-by: York Sun <york.sun@nxp.com> |
#
f6b96ff6 |
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16-Nov-2016 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Use SVR based timer base address detection Timer controller base address has been changed from LS2080A SoC (and its personalities) to new SoCs like LS2088A, LS1088A. Use SVR based timer base address detection to avoid compile time #ifdef. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
f6a70b3a |
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16-Nov-2016 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add generic get_svr() in assembly Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
78d57842 |
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16-Nov-2016 |
Alexander Graf <agraf@csgraf.de> |
armv8: fsl-layerscape: Add support for efi_loader RTS reset When implementing efi loader support, we can expose runtime services for payloads. One such service is CPU reset. This patch implements RTS CPU reset support for layerscape systems. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: York Sun <york.sun@nxp.com> |
#
ef9a5fd8 |
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13-Sep-2016 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: Fix "cpu status" command The core position is not continuous for some SoCs. For example, valid cores may present at position 0, 1, 4, 5, 8, 9, etc. Some registers (including boot release register) only count existing cores. Current implementation of cpu_mask() complies with the continuous numbering. However, command "cpu status" queries the spin table with actual core position. Add functions to calculate core position from core number, to correctly calculate offsets. Tested on LS2080ARDB and LS1043ARDB. Signed-off-by: York Sun <york.sun@nxp.com> |
#
5d1a7a9d |
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13-Sep-2016 |
Wenbin Song <wenbin.song@nxp.com> |
armv8/fsl-layerscape: print SoC revsion number The exact SoC revsion number can be recognized from U-Boot log. Signed-off-by: Wenbin Song <wenbin.song@nxp.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
cbe7706a |
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26-Sep-2016 |
Tom Rini <trini@konsulko.com> |
Merge git://git.denx.de/u-boot-fsl-qoriq trini: Drop local memset() from examples/standalone/mem_to_mem_idma2intr.c Signed-off-by: Tom Rini <trini@konsulko.com>
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#
1221ce45 |
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20-Sep-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
treewide: replace #include <asm/errno.h> with <linux/errno.h> Now, arch/${ARCH}/include/asm/errno.h and include/linux/errno.h have the same content. (both just wrap <asm-generic/errno.h>) Replace all include directives for <asm/errno.h> with <linux/errno.h>. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> [trini: Fixup include/clk.] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
b63a9506 |
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03-Aug-2016 |
York Sun <york.sun@nxp.com> |
armv8: ls2080a: Remove debug server support Debug server feature has been dropped from roadmap. Signed-off-by: York Sun <york.sun@nxp.com> |
#
ed7a3943 |
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22-Jul-2016 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: mmu: Fix enabling MMU MMU bit in SCTLR needs to be set explicitly after tables are created. It isn't an issue for EL3 becuase this bit is already set by early MMU setup. But for other exception levels this bit was not set. Signed-off-by: York Sun <york.sun@nxp.com> |
#
79119a4d |
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05-Jul-2016 |
Alison Wang <b18965@freescale.com> |
armv8: fsl-layerscape: Add A72 core detection Add support to detect Cortex-A72 core for printing it out. The Initiator Version of A72 core should be 0x4. Signed-off-by: Alison Wang <alison.wang@nxp.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
032d5bb4 |
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28-Jun-2016 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
ARMv8/Layerscape: switch SMP method accordingly If the PSCI and PPA is ready, skip the fixup for spin-table and waking secondary cores. Otherwise, change SMP method to spin-table, and the device node of PSCI will be removed. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
85cdf38e |
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28-Jun-2016 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: fsl-layerscape: add i/d-cache enable function to enable_caches This function assume that the d-cache and MMU has been enabled earlier, so it just created MMU table in main memory. But the assumption is not always correct, for example, the early setup is done in EL3, while enable_caches() is called when the PE has turned into another EL. Define the function mmu_setup() for fsl-layerscape to cover the weak one. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
5ad5823d |
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24-Jun-2016 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Convert to use common MMU framework Drop platform code to create static MMU tables. Use common framework to create MMU tables on the run. Tested on LS2080ARDB with secure and non-secure ram scenarios. Signed-off-by: York Sun <york.sun@nxp.com> |
#
e61a7534 |
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24-Jun-2016 |
York Sun <york.sun@nxp.com> |
armv8: Move secure_ram variable out of generic global data Secure_ram variable was put in generic global data. But only ARMv8 uses this variable. Move it to ARM specific data structure. Signed-off-by: York Sun <york.sun@nxp.com> |
#
a10a31ec |
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18-Jun-2016 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of git://git.denx.de/u-boot-usb Signed-off-by: Tom Rini <trini@konsulko.com> Conflicts: arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
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#
6fb522dc |
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12-Jun-2016 |
Sriram Dash <sriram.dash@nxp.com> |
arm64: fsl-layerscape: add get_svr and IS_SVR_REV helper Adds get_svr and IS_SVR_REV helpers for ARMv8 platforms, similar to PPC and ARMv7. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> |
#
a758177f |
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07-Jun-2016 |
Yunhui Cui <yunhui.cui@nxp.com> |
armv8/ls2080a: configure PMU's PCTBENR to enable WDT The SP805-WDT module on LS2080A requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. The watchdog clock needs to be enabled first. Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
acb8f5e9 |
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21-Apr-2016 |
Alison Wang <b18965@freescale.com> |
armv8: fsl-layerscape: Remove unnecessary flushing dcache As the issue about the stack will get corrupted when switching between the early and final mmu tables is fixed by commit 70e21b064, the workaround to flush dcache is unnecessary and should be removed. Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
3c1d218a |
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04-Apr-2016 |
York Sun <york.sun@nxp.com> |
armv8: LS2080A: Consolidate LS2080A and LS2085A LS2080A is the primary SoC, and LS2085A is a personality with AIOP and DPAA DDR. The RDB and QDS boards support both personality. By detecting the SVR at runtime, a single image per board can support both SoCs. It gives users flexibility to swtich SoC without the need to reprogram the board. Signed-off-by: York Sun <york.sun@nxp.com> CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
c05016ab |
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21-Mar-2016 |
Alexander Graf <agraf@csgraf.de> |
arm64: Fix layerscape mmu setup With commit 7985cdf we converted all systems except for the Layerscape SoCs to the generic descriptor table based page table setup. On the Layerscape SoCs however, we just provide an empty table stub and do the setup ourselves. To reserve enough memory for the tables, we need to override the default counting mechanism which would end up with an empty table because we have no maps. Fixes: 7985cdf Reported-by: York Sun <york.sun@nxp.com> CC: Alison Wang <alison.wang@nxp.com> CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Alexander Graf <agraf@suse.de> Tested-by: York Sun <york.sun@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
7985cdf7 |
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03-Mar-2016 |
Alexander Graf <agraf@csgraf.de> |
arm64: Remove non-full-va map code By now the code to only have a single page table level with 64k page size and 42 bit address space is no longer used by any board in tree, so we can safely remove it. To clean up code, move the layerscape mmu code to the new defines, removing redundant field definitions. Signed-off-by: Alexander Graf <agraf@suse.de> |
#
c0492141 |
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07-Dec-2015 |
York Sun <yorksun@freescale.com> |
armv8: fsl-layerscale: Rewrite reserving memory for MC and debug server MC and debug server are not board-specific. Move reserving memory to SoC file, using the new board_reserve_ram_top function. Reduce debug server memory by 2MB to make room for secure memory. In the system with MC and debug server, the top of u-boot memory is not the end of memory. PRAM is not used for this reservation. Signed-off-by: York Sun <yorksun@freescale.com> |
#
c107c0c0 |
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04-Dec-2015 |
York Sun <yorksun@freescale.com> |
armv8: fsl-layerscape: Make DDR non secure in MMU tables DDR has been set as secure in MMU tables. Non-secure master such as SDHC DMA cannot access data correctly. Mixing secure and non- secure MMU entries requirs the MMU tables themselves in secure memory. This patch moves MMU tables into a secure DDR area. Early MMU tables are changed to set DDR as non-secure. A new table is added into final MMU tables so secure memory can have 2MB granuality. gd->secure_ram tracks the location of this secure memory. For ARMv8 SoCs, the RAM base is not zero and RAM is divided into several banks. gd->secure_ram needs to be maintained before using. This maintenance is board-specific, depending on the SoC and memory bank of the secure memory falls into. Signed-off-by: York Sun <yorksun@freescale.com> |
#
b4017364 |
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04-Nov-2015 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
armv8: ls2085a: Add workaround of errata A009635 If the core runs at higher than x3 speed of the platform, there is possiblity about sev instruction to getting missed by other cores. This is because of SoC Run Control block may not able to sample the EVENTI(Sev) signals. Configure Run Control and EPU to periodically send out EVENTI signals to wake up A57 cores. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
d764129d |
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04-Nov-2015 |
Alison Wang <b18965@freescale.com> |
armv8/layerscape: Update MMU table with execute-never bits For most device addresses excution shouldn't be allowed. Revise the MMU table to enforce execute-never bits. OCRAM, DDR and IFC are allowed for excution. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Alison Wang <alison.wang@freescale.com> Reported-by: Zhichun Hua <zhichun.hua@freescale.com> |
#
44937214 |
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09-Nov-2015 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
armv8: LS2080A: Rename LS2085A to reflect LS2080A LS2080A is a prime personality of Freescale’s LS2085A. It is a non-AIOP personality without support of DP-DDR, L2 switch, 1588, PCIe endpoint etc. So renaming existing LS2085A code base to reflect LS2080A (Prime personality) Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> [York Sun: Dropped #ifdef in cpu.c for cpu_type_list] Reviewed-by: York Sun <yorksun@freescale.com> |
#
e8297341 |
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26-Oct-2015 |
Shaohui Xie <Shaohui.Xie@freescale.com> |
armv8/ls1043a: Add Fman support Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
8281c58f |
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26-Oct-2015 |
Mingkai Hu <Mingkai.Hu@freescale.com> |
armv8/fsl_lsch2: Add fsl_lsch2 SoC Freescale LayerScape with Chassis Generation 2 is a set of SoCs with ARMv8 cores and 2rd generation of Chassis. Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
9f3183d2 |
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26-Oct-2015 |
Mingkai Hu <Mingkai.Hu@freescale.com> |
armv8/fsl_lsch3: Change arch to fsl-layerscape There are two LS series processors are built on ARMv8 Layersacpe architecture currently, LS2085A and LS1043A. They are based on ARMv8 core although use different chassis, so create fsl-layerscape to refactor the common code for the LS series processors which also paves the way for adding LS1043A platform. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
ce9c579e |
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13-Jun-2022 |
Andre Przywara <andre.przywara@arm.com> |
armv8: always use current exception level for TCR_ELx access Currently get_tcr() takes an "el" parameter, to select the proper version of the TCR_ELx system register. This is problematic in case of the Apple M1, since it runs with HCR_EL2.E2H fixed to 1, so TCR_EL2 is actually using the TCR_EL1 layout, and we get the wrong version. For U-Boot's purposes the only sensible choice here is the current exception level, and indeed most callers treat it like that, so let's remove that parameter and read the current EL inside the function. This allows us to check for the E2H bit, and pretend it's EL1 in this case. There are two callers which don't care about the EL, and they pass 0, which looks wrong, but is irrelevant in these two cases, since we don't use the return value there. So the change cannot affect those two. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Mark Kettenis <kettenis@openbsd.org> Tested-by: Mark Kettenis <kettenis@openbsd.org> |
#
cda8f873 |
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11-May-2022 |
Ye Li <ye.li@nxp.com> |
caam: Fix crash in case caam_jr_probe failed If probing caam_jr returns failure, the variable "dev" will not be initialized, so we can't use dev->name for the error print. Otherwise it will cause crash. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Gaurav Jain <gaurav.jain@nxp.com> |
#
cb14cc88 |
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22-Apr-2022 |
Michael Walle <michael@walle.cc> |
armv8: layerscape: get rid of smc_call() There are two different implementations to do a secure monitor call: smc_call() and arm_smccc_smc(). The former is defined in fwcall.c and seems to be an ad-hoc implementation. The latter is imported from linux. smc_call() is also only available if CONFIG_ARMV8_PSCI is not defined. This makes it impossible to have both PSCI calls and PSCI implementation in one u-boot build. The layerscape SoC code decide at runtime via check_psci() if there is a PSCI support. Therefore, this is a prerequisite patch to add PSCI implementation support for the layerscape SoCs. Note, for the TFA part, this is only compile time tested with (ls1028ardb_tfa_defconfig). Signed-off-by: Michael Walle <michael@walle.cc> [Rebased] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
dfb6da55 |
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05-Apr-2022 |
Marek Vasut <marex@denx.de> |
armv8: layerscape: env: Switch to arch_env_get_location() Implement arch_env_get_location() instead of env_get_location(), so that the env_get_location() can be implemented on board level and override the arch_env_get_location() architecture defaults. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Adam Ford <aford173@gmail.com> Cc: Fabio Estevam <festevam@denx.de> Cc: Marek Behún <marek.behun@nic.cz> Cc: Peng Fan <peng.fan@nxp.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefano Babic <sbabic@denx.de> Cc: Tim Harvey <tharvey@gateworks.com> Cc: Tom Rini <trini@konsulko.com> Cc: Tommaso Merciai <tomm.merciai@gmail.com> Cc: Vladimir Oltean <vladimir.oltean@nxp.com> |
#
8976556a |
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24-Mar-2022 |
Gaurav Jain <gaurav.jain@nxp.com> |
Layerscape: Enable Job ring driver model. LS(1021/1012/1028/1043/1046/1088/2088), LX2160, LX2162 platforms are enabled with JR driver model. removed sec_init() call from board files. sec is initialized based on job ring information processed from device tree. Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Michael Walle <michael@walle.cc> |
#
f9147d63 |
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25-Feb-2022 |
Tom Rini <trini@konsulko.com> |
Convert CONFIG_CHIP_SELECTS_PER_CTRL to Kconfig This converts the following to Kconfig: CONFIG_CHIP_SELECTS_PER_CTRL Cc: Alison Wang <alison.wang@nxp.com> Cc: Pramod Kumar <pramod.kumar_1@nxp.com> Cc: Priyanka Jain <priyanka.jain@nxp.com> Cc: Rajesh Bhagat <rajesh.bhagat@nxp.com> Cc: Vladimir Oltean <olteanv@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
2f8a6db5 |
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14-Dec-2021 |
Tom Rini <trini@konsulko.com> |
Finish conversion of CONFIG_SYS_CLK_FREQ to Kconfig In order to finish moving this symbol to Kconfig for all platforms, we need to do a few more things. First, for all platforms that define this to a function, introduce CONFIG_DYNAMIC_SYS_CLK_FREQ, similar to CONFIG_DYNAMIC_DDR_CLK_FREQ and populate clock_legacy.h. This entails also switching all users from CONFIG_SYS_CLK_FREQ to get_board_sys_clk() and updating a few preprocessor tests. With that done, all platforms that define a value here can be converted to Kconfig, and a fall-back of zero is sufficiently safe to use (and what is used today in cases where code may or may not have this available). Make sure that code which calls this function includes <clock_legacy.h> to get the prototype. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
77b11f76 |
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18-Sep-2021 |
Vladimir Oltean <vladimir.oltean@nxp.com> |
net: replace the "xfi" phy-mode with "10gbase-r" As part of the effort of making U-Boot work with the same device tree as Linux, there is an issue with the "xfi" phy-mode. To be precise, in Linux there was a discussion (for those who have time to read: https://lore.kernel.org/netdev/1576768881-24971-2-git-send-email-madalin.bucur@oss.nxp.com/) which led to a patch: https://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next.git/commit/?id=c114574ebfdf42f826776f717c8056a00fa94881 TL;DR: "xfi" was standardized in Linux as "10gbase-r". This patch changes the relevant occurrences in U-Boot to use "10gbase-r" instead of "xfi" wherever applicable. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> |
#
84c2e044 |
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20-Apr-2021 |
Jiafei Pan <Jiafei.Pan@nxp.com> |
armv8: layerscape: add PSCI support for cpu release For cpu release command, check whether PSCI is supported firstly, if supported, use PSCI to kick off secondary cores, otherwise still use spin table. Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com> [Fixed checkpatch alignment CHECKs] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
35b65dd8 |
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15-Dec-2020 |
Harald Seiler <hws@denx.de> |
reset: Remove addr parameter from reset_cpu() Historically, the reset_cpu() function had an `addr` parameter which was meant to pass in an address of the reset vector location, where the CPU should reset to. This feature is no longer used anywhere in U-Boot as all reset_cpu() implementations now ignore the passed value. Generic code has been added which always calls reset_cpu() with `0` which means this feature can no longer be used easily anyway. Over time, many implementations seem to have "misunderstood" the existence of this parameter as a way to customize/parameterize the reset (e.g. COLD vs WARM resets). As this is not properly supported, the code will almost always not do what it is intended to (because all call-sites just call reset_cpu() with 0). To avoid confusion and to clean up the codebase from unused left-overs of the past, remove the `addr` parameter entirely. Code which intends to support different kinds of resets should be rewritten as a sysreset driver instead. This transformation was done with the following coccinelle patch: @@ expression argvalue; @@ - reset_cpu(argvalue) + reset_cpu() @@ identifier argname; type argtype; @@ - reset_cpu(argtype argname) + reset_cpu(void) { ... } Signed-off-by: Harald Seiler <hws@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
401d1c4f |
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30-Oct-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop asm/global_data.h from common header Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
3a187cff |
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29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
c760095a |
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23-Oct-2020 |
Razvan Ionut Cirjan <razvanionut.cirjan@nxp.com> |
net: lx2160a.c: Update to set ECx_PMUX precedence As per hardware documentation, ECx_PMUX has precedence over SerDes protocol. For LX2160/LX2162 if DPMACs 17 and 18 are enabled as SGMII through SerDes protocol but ECx_PMUX configured them as RGMII, then the ports will be configured as RGMII and not SGMII. Signed-off-by: Razvan Ionut Cirjan <razvanionut.cirjan@nxp.com> [Rebased] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
d31f3a1b |
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09-Sep-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2160a: fix reset sequence Make sure that SW_RST_REQ and RST_REQ_MSK are cleared before triggering hardware reset request. Signed-off-by: Thirupathaiah Annapureddy <thiruan@linux.microsoft.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
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b75d8dc5 |
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26-Jun-2020 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
treewide: convert bd_t to struct bd_info by coccinelle The Linux coding style guide (Documentation/process/coding-style.rst) clearly says: It's a **mistake** to use typedef for structures and pointers. Besides, using typedef for structures is annoying when you try to make headers self-contained. Let's say you have the following function declaration in a header: void foo(bd_t *bd); This is not self-contained since bd_t is not defined. To tell the compiler what 'bd_t' is, you need to include <asm/u-boot.h> #include <asm/u-boot.h> void foo(bd_t *bd); Then, the include direcective pulls in more bloat needlessly. If you use 'struct bd_info' instead, it is enough to put a forward declaration as follows: struct bd_info; void foo(struct bd_info *bd); Right, typedef'ing bd_t is a mistake. I used coccinelle to generate this commit. The semantic patch that makes this change is as follows: <smpl> @@ typedef bd_t; @@ -bd_t +struct bd_info </smpl> Signed-off-by: Masahiro Yamada <masahiroy@kernel.org> |
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25a5818f |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop asm/ptrace.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
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f7ae49fc |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
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90526e9f |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop net.h from common header Move this header out of the common header. Network support is used in quite a few places but it still does not warrant blanket inclusion. Note that this net.h header itself has quite a lot in it. It could be split into the driver-mode support, functions, structures, checksumming, etc. Signed-off-by: Simon Glass <sjg@chromium.org> |
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714497e3 |
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16-May-2020 |
Michael Walle <michael@walle.cc> |
efi_loader: round the memory area in efi_add_memory_map() Virtually all callers of this function do the rounding on their own. Some do it right, some don't. Instead of doing this in each caller, do the rounding in efi_add_memory_map(). Change the size parameter to bytes instead of pages and remove aligning and size calculation in all callers. There is no more need to make the original efi_add_memory_map() (which takes pages as size) available outside the module. Thus rename it to efi_add_memory_map_pg() and make it static to prevent further misuse outside the module. Signed-off-by: Michael Walle <michael@walle.cc> Add missing comma in sunxi_display.c. Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de> |
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6eb32a03 |
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23-Apr-2020 |
Madalin Bucur <madalin.bucur@oss.nxp.com> |
driver: net: fm: add DM ETH support Probe the FMan MACs based on the device tree while retaining the legacy code/functionality. One notable change introduced here is that, for DM_ETH, the name of the interfaces is corrected to the fmX-macY format, that avoids the referral to the MAC block names which were incorrect for FMan v3 devices (i.e. DTSEC, TGEC) and had weird formatting (i.e. FM1@DTSEC6, FM1@TGEC1). The legacy code is left unchanged in this respect. Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
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6ebd4883 |
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27-Apr-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
fsl-layerscape: Add RESV_RAM check in resv_ram addr The initialization of gd->arch.resv_ram pointer should depend on if the RESV_RAM config is enabled. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Wasim Khan <wasim.khan@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
0d9d557d |
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10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
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db41d65a |
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28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move hang() to the same header as panic() At present panic() is in the vsprintf.h header file. That does not seem like an obvious choice for hang(), even though it relates to panic(). So let's put hang() in its own header. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Migrate a few more files] Signed-off-by: Tom Rini <trini@konsulko.com> |
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9b4a205f |
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28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move RAM-sizing functions to init.h These functions relate to memory init so move them into the init header. Signed-off-by: Simon Glass <sjg@chromium.org> |
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3499dd03 |
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27-Nov-2019 |
Alex Marginean <alexandru.marginean@nxp.com> |
ls1028a: Configure stream IDs for integrated PCI and fix up Linux DT Hardware comes out of reset with implicit values, but these are outside the accepted range for Layerscape gen 3 chassis spec used on LS1028A. Allocate different IDs and fix up Linux DT to use them. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
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b5981474 |
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14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some CPU functions out of common.h These functions belong in cpu_func.h since they do not use driver model. Move them over. Don't bother adding comments since these functions should be deleted. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
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68a6aa85 |
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14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move mii_init() function out of common.h This function belongs in mii.h so move it over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
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2189d5f1 |
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14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
Move strtomhz() to vsprintf.h At present this function sits in its own file but it does not really justify it. There are similar string functions in vsprintf.h, so move it there. Also add the missing function comment. Use the vsprintf.h include file explicitly where needed. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
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812ff53c |
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30-Oct-2019 |
Pankaj Bansal <pankaj.bansal@nxp.com> |
fsl-layerscape: fix warning if no hwconfig is defined While getting the 'subarg' of 'hwconfig' env variable in config_core_prefetch(), if no hwconfig variable is defined, below warning is received: WARNING: Calling __hwconfig without a buffer and before environment is ready Fix this by checking 'hwconfig' env variable. If not found return without further processing. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Tested-by: Michael Walle <michael@walle.cc> |
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28f9393b |
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17-Oct-2019 |
Mathew McBride <matt@traverse.com.au> |
fsl-layerscape: do not use layerscape EFI reset if PSCI used If the secure world reset handlers are used (via CONFIG_PSCI_RESET), then do not use the layerscape-specific implementation. Signed-off-by: Mathew McBride <matt@traverse.com.au> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
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6ed69523 |
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18-Sep-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add more personalities support Add LS1027A, LS1018A and LS1017A personalities support to LS1028A SoC family. LS1028A is the prime personality of LS1028A SoC family. LS1027A is a lower funtionality version of QorIQ LS1028A which does not support the multimedia subsystems, such as LCD controller, GPU, and eDP PHY. The QorIQ LS1018A and LS1017A SoCs are single 64-bit Arm A72 core, low power versions of the QorIQ LS1028A and LS1027A SoCs respectively. Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
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0490cab5 |
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08-Aug-2019 |
Thomas Schaefer <thomas.schaefer@kontron.com> |
armv8: ls1028a: configure PMU's PCTBENR to enable WDT The SP805-WDT module on LS1028A requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. The watchdog clock needs to be enabled first. Signed-off-by: Thomas Schaefer <thomas.schaefer@kontron.com> Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
f3998fdc |
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02-Aug-2019 |
Simon Glass <sjg@chromium.org> |
env: Rename environment.h to env_internal.h This file contains lots of internal details about the environment. Most code can include env.h instead, calling the functions there as needed. Rename this file and add a comment at the top to indicate its internal nature. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> [trini: Fixup apalis-tk1.c] Signed-off-by: Tom Rini <trini@konsulko.com> |
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3a7d5571 |
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01-Aug-2019 |
Simon Glass <sjg@chromium.org> |
env: Move env_get_f() to env.h Move this function over to the new header file. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
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d9532e80 |
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23-Apr-2019 |
Udit Agarwal <udit.agarwal@nxp.com> |
armv8: fsl-layerscape: Set env_loc to ENVL_NOWHERE with CONFIG_ENV_IS_NOWHERE. ENVL_NOWHERE is dependent on CONFIG_ENV_IS_NOWHERE and not on CONFIG_CHAIN_OF_TRUST so return ENVL_NOWHERE when CONFIG_ENV_IS_NOWHERE is enabled Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
d4ad111d |
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10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
059d9422 |
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08-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: lx2160a: add MMU table entries for PCIe The lx2160a have up to 6 PCIe controllers and have different address and size of PCIe region. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
8348e798 |
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08-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: layerscape: use PCIe address macro for precompile PCIe MMU entry Change to use PCIe address macro to determine if precompile the PCIe MMU table entry. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
10015025 |
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03-May-2019 |
Trevor Woerner <trevor@toganlabs.com> |
CONFIG_SPL_SYS_[DI]CACHE_OFF: add While converting CONFIG_SYS_[DI]CACHE_OFF to Kconfig, there are instances where these configuration items are conditional on SPL. This commit adds SPL variants of these configuration items, uses CONFIG_IS_ENABLED(), and updates the configurations as required. Acked-by: Alexey Brodkin <abrodkin@synopsys.com> Signed-off-by: Trevor Woerner <trevor@toganlabs.com> [trini: Make the default depend on the setting for full U-Boot, update more zynq hardware] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
2e53759d |
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29-Oct-2018 |
Pankaj Bansal <pankaj.bansal@nxp.com> |
armv8: fsl-layerscape: reorder rgmii dpmacs' enablement some dpmacs in armv8a based freescale layerscape SOCs can be configured via both serdes(sgmii, xfi, xlaui etc) bits and via EC*_PMUX(rgmii) bits in RCW. e.g. dpmac 17 and 18 in LX2160A can be configured as SGMII from serdes bits and as RGMII via EC1_PMUX/EC2_PMUX bits Now if a dpmac is enabled by serdes bits then it takes precedence over EC*_PMUX bits. i.e. in LX2160A if we select serdes protocol that configures dpmac17 as SGMII and set the EC1_PMUX as RGMII, then the dpmac is SGMII and not RGMII. Therefore, move the fsl_rgmii_init after fsl_serdes_init. in fsl_rgmii_init function of SOC, we will check if the dpmac is enabled or not? if it is (fsl_serdes_init has already enabled the dpmac), then don't enable it. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
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ec88ff80 |
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19-Dec-2018 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1043a: add SVR definitions for 23x23 package silicon LS1043A/LS1023A 23x23 package silicon has different SVR:VAR_PER. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
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d23da2ae |
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26-Dec-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: fixes for TFABOOT framework Fixes for TFABOOT framework - update eMMC bootsrc to SD_MMC - Increase buffer size for mcinitcmd from 256 to 512 - Fix mcinitcmd and bootcmd for Secure Boot Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
4909b89e |
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29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
d6fdec21 |
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29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8:fsl-layerscape: Add support for Chassis 3.2 NXP layerscape architecture Chassis 3.2 builds upon chassis3 architecture with changes like DDR Memory map change, removal of IFC and support of upto 8 I2C controller. Patch add README.lsch3_2 and the above changes under macro CONFIG_NXP_LSCH3_2. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
56db948b |
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05-Nov-2018 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: Update parsing boot source Workaround of erratum A010539 clears the RCW source field in PORSR1 register, causing failure of detecting boot source using this method. Use SMC call if U-Boot runs at EL2. If SMC is not implemented or running at EL3, continue to read PORSR1 and presume QSPI as boot source if erratum workaround A010539 is enabled and RCW source is cleared. Signed-off-by: York Sun <york.sun@nxp.com> |
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681d489e |
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05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: layerscape: add SMC calls for DDR size and bank info Adds SMC calls for getting DDR size and bank info for TFABOOT. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
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2141d250 |
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05-Nov-2018 |
Pankit Garg <pankit.garg@nxp.com> |
armv8: fsl-layerscape: bootcmd identification for TFABOOT Adds bootcmd identificaton on basis on boot source, valid in TFABOOT configuration. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> [YS: remove unnecessary braces] Reviewed-by: York Sun <york.sun@nxp.com> |
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4c417384 |
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05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com> |
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535d76a1 |
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05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: layerscape: Add TFABOOT support Adds TFABOOT support config option and add generic code to enable execution from DDR. Signed-off-by: York Sun <york.sun@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> |
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e3506480 |
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05-Nov-2018 |
Pankit Garg <pankit.garg@nxp.com> |
armv8: fsl-layerscape: change tlb base from OCRAM to DDR in EL < 3 Change tlb base address from OCRAM to DDR when exception level is less than 3. Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
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d171c707 |
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05-Nov-2018 |
York Sun <york.sun@nxp.com> |
move data structure out of cpu.h Move static definitions to cpu.c file, as it doesn't allow the cpu.h file to be included in multiple c files. Signed-off-by: York Sun <york.sun@nxp.com> |
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9b5e6396 |
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30-Aug-2018 |
Stephen Warren <swarren@nvidia.com> |
efi_loader: simplify ifdefs Use CONFIG_IS_ENABLED(EFI_LOADER) to avoid explicitly checking CONFIG_SPL too. This simplifies the conditional. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Alexander Graf <agraf@suse.de> |
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9cce5663 |
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16-Jul-2018 |
Joe Hershberger <joe.hershberger@ni.com> |
arm: Prevent redefinition error in fsl-layerscape The include/phy.h will start including dm.h, which pulls in linux/compat.h after the attempted redefinition in arch/arm/include/asm/armv8/mmu.h, so move this include to allow redefinition. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> |
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83d290c5 |
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06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
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482fc90c |
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06-Feb-2018 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
efi_loader: add missing EFI_RESET_PLATFORM_SPECIFIC EFI_RESET_PLATFORM_SPECIFIC is one of the values that can be used for the EFI service ResetSystem. The missing definition is added. The value has to handled in efi_reset_system(). Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Alexander Graf <agraf@suse.de> |
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22c793e6 |
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03-Mar-2018 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
efi_loader: exit status for efi_reset_system_init efi_reset_system_init provides the architecture or board specific initialization of the EFI subsystem. Errors should be caught and signalled by a return code. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Alexander Graf <agraf@suse.de> |
#
958b2ed5 |
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09-Jan-2018 |
Zhang Ying-22455 <ying.zhang22455@nxp.com> |
armv8/ls1088a: configure PMU's PCTBENR to enable WDT The SP805-WDT module on LS1088A requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. The watchdog clock needs to be enabled first. Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
44262327 |
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15-Dec-2017 |
Ahmed Mansour <ahmed.mansour@nxp.com> |
drivers/misc: Share qbman init between archs This patch adds changes necessary to move functionality present in PowerPC folders with ARM architectures that have DPAA1 QBMan hardware - Create new board/freescale/common/fsl_portals.c to house shared device tree fixups for DPAA1 devices with ARM and PowerPC cores - Add new header file to top includes directory to allow files in both architectures to grab the function prototypes - Port inhibit_portals() from PowerPC to ARM. This function is used in setup to disable interrupts on all QMan and BMan portals. It is needed because the interrupts are enabled by default for all portals including unused/uninitialised portals. When the kernel attempts to go to deep sleep the unused portals prevent it from doing so Signed-off-by: Ahmed Mansour <ahmed.mansour@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
a8f33034 |
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03-Dec-2017 |
Wenbin song <wenbin.song@nxp.com> |
armv8: ls1043a/ls2080a: check SoC by device ID Check LS1043A/LS2080a by device ID without using personality ID to determine revision number. This check applies to all various personalities of the same SoC family. Signed-off-by: Wenbin Song <wenbin.song@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
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2db53cfe |
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09-Nov-2017 |
Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
armv8: fsl-layerscape: Add support of disabling core prefetch Instruction prefetch feature is by default enabled during core release. This patch add support of disabling instruction prefetch by setting core mask in PPA. Here each core mask bit represents a core and prefetch is disabled at the time of core release. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
7eb40f0f |
|
28-Sep-2017 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: Avoid running dram_init_banksize again gd->ram_size is reduced in this function to reserve secure memory. Avoid running this function again to further reduce memory size. This fixes issue for SPL boot with PPA image loaded in which case secure memory is incorrectly allocated due to repeated calling. Signed-off-by: York Sun <york.sun@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
710d0cd7 |
|
03-Oct-2017 |
Sumit Garg <sumit.garg@nxp.com> |
armv8: fsl-layerscape: Allocate Secure memory from first ddr region This change is required due to trusted OS (OP-TEE) not being position independent code, it requires compile time fixed base address. To take care of this it is assumed that all layerscape armv8 platforms has minimum 2G ddr in first region. So we can have fixed address space (66 MB -> (2MB for PPA + 64MB for trusted OS)) allocated from top of first 2G ddr region and compile trusted OS with this fixed base address. But one exception here is ls1012 where we have only 1G (rdb) or 512M (frdm) ddr memory. For those we can have different fixed compile time base addresses for trusted OS. Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
e9303a41 |
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07-Sep-2017 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: Fix MC reserved memory calculation In case high region memory doesn't have enough space for Management Complex (MC), the return value should indicate a failure so the caller can handle it accordingly. Signed-off-by: York Sun <york.sun@nxp.com> Reported-by: Ebony Zhu <ebony.zhu@nxp.com> |
#
17d066fc |
|
31-Aug-2017 |
Ashish Kumar <Ashish.Kumar@nxp.com> |
armv8: fsl-layerscape: Support to add RGMII for ls1088aqds This patch adds support for RGMII protocol NXP's LDPAA2 support RGMII protocol. LS1088A is the first Soc supporting both RGMII and SGMII. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Amrita Kumari <amrita.kumari@nxp.com> Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
63b2316c |
|
10-Aug-2017 |
Ashish Kumar <Ashish.Kumar@nxp.com> |
fsl-layerscape: Consolidate registers space defination for CCI-400 bus CoreLink Cache Coherent Interconnect (CCI) provides full cache coherency between two clusters of multi-core CPUs and I/O coherency for devices and I/O masters. This patch add new config option SYS_FSL_HAS_CCI400 and moves existing register space definaton of CCI-400 bus to fsl_immap to be shared. CONFIG_SYS_CCI400_ADDR is replaced with SYS_CCI400_OFFSET in Kconfig. Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> [YS: revised commit message, squashed patches for armv8 and armv7] Reviewed-by: York Sun <york.sun@nxp.com> |
#
6e2941d7 |
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17-May-2017 |
Simon Glass <sjg@chromium.org> |
common: freescale: Move arch-specific declarations The declarations should not be in common.h. Move them to the arch-specific headers. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Fixup thinko defined(FSL_LSCH3) -> defined(CONFIG_FSL_LSCH3)] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
399e2bb6 |
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15-May-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Make U-Boot EL2 safe When U-Boot boots from EL2, skip some lowlevel init code requiring EL3, including CCI-400/CCN-504, trust zone, GIC, etc. These initialization tasks are carried out before U-Boot runs. This applies to the RAM version image used for SPL boot if PPA is loaded first. Signed-off-by: York Sun <york.sun@nxp.com> |
#
1f55a938 |
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05-May-2017 |
Santan Kumar <santan.kumar@nxp.com> |
armv8: ls2080aqds: Add support for SD boot Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
e809e747 |
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27-Apr-2017 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: fsl-layerscape: Add NXP LS2081A, LS2041A SoC support The QorIQ LS2081A SoC has eight 64-bit ARM v8 Cortex A72 cores and is built on layerscape architecture. It is 40-pin derivative of LS2084A (non-AIOP personality of LS2088A). So feature-wise it is same as LS2084A. LS2041A is a 4-core personality of LS2081A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
026f30ec |
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18-Apr-2017 |
Yuantian Tang <andy.tang@nxp.com> |
arm: psci: make psci usable on single core socs PSCI can be used on both multiple and single core socs. Current implementation only allows PSCI to work on multiple core socs. This patch removes this restriction so that PSCI can work on single core socs as well. Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
4a3ab193 |
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27-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: ls2080a: Drop macro CONFIG_LS2080A Use CONFIG_ARCH_LS2080A instead. Signed-off-by: York Sun <york.sun@nxp.com> |
#
3eace37e |
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06-Apr-2017 |
Simon Glass <sjg@chromium.org> |
arm: freescale: Rename initdram() to fsl_initdram() This function name shadows a global name but is in fact different. This is very confusing. Rename it to help with the following refactoring. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
76b00aca |
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31-Mar-2017 |
Simon Glass <sjg@chromium.org> |
board_f: Drop setup_dram_config() wrapper By making dram_init_banksize() return an error code we can drop the wrapper. Adjust this and clean up all implementations. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
088454cd |
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31-Mar-2017 |
Simon Glass <sjg@chromium.org> |
board_f: Drop return value from initdram() At present we cannot use this function as an init sequence call without a wrapper, since it returns the RAM size. Adjust it to set the RAM size in global_data instead, and return 0 on success. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
52c41180 |
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31-Mar-2017 |
Simon Glass <sjg@chromium.org> |
board_f: Drop board_type parameter from initdram() It looks like only cm5200 and tqm8xx use this feature, so we don't really need it in generic code. Drop it and have the users access gd->board_type directly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
3d8553f0 |
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02-Mar-2017 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
pci: layerscape: add LS2088A series SoC pcie support The LS2088A series SoCs has different physical memory map address and CCSR registers address against LS2080A series SoCs. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
eea1cb77 |
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13-Feb-2017 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8/fsl-layerscape: Update erratum A009635 implementation Erratum A009635 is valid only for LS2080A SoC and its personality. Add SoC svr check. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
4961eafc |
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06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Update early MMU for DDR after initialization In early MMU table, DDR has to be mapped as device memory to avoid speculative access. After DDR is initialized, it needs to be updated to normal memory to allow code execution. To simplify the code, dram_init() is moved into a common file as a weak function. Signed-off-by: York Sun <york.sun@nxp.com> |
#
a045a0c3 |
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06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Fix the sequence of changing MMU table This patch follows the break-before-make process when making changes to MMU table. MMU is disabled before changing TTBR to avoid any potential race condition. Signed-off-by: York Sun <york.sun@nxp.com> |
#
24f55496 |
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06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Update MMU mapping with actual DDR size Update mapping with actual DDR size. Non-existing memory should not be mapped as "normal" memory to avoid speculative access. Signed-off-by: York Sun <york.sun@nxp.com> |
#
36cc0de0 |
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06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Rewrite memory reservation For ARMv8 Layerscape SoCs, secure memory and MC memorey are reserved at the end of DDR. DDR is spit into two or three banks. This patch reverts commit aabd7ddb and simplifies the calculation of reserved memory, and moves the code into common SoC file. Secure memory is carved out first. DDR bank size is reduced. Reserved memory is then allocated on the top of available memory. U-Boot still has access to reserved memory as data transferring is needed. Device tree is fixed with reduced memory size to hide the reserved memory from OS. The same region is reserved for efi_loader. Signed-off-by: York Sun <york.sun@nxp.com> |
#
daa92644 |
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16-Jan-2017 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
ARMv8/sec_firmware: relocated and renamed the config FSL_PPA_ARMV8_PSCI Moved the config FSL_PPA_ARMV8_PSCI from fsl-layerscape's Kconfig to Kconfig under armv8 and renamed it to SEC_FIRMWARE_ARMV8_PSCI. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
904110c7 |
|
10-Jan-2017 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8/fsl-lsch2: refactor the clock system initialization Up to now, there are 3 kind of SoCs under Layerscape Chassis 2, like LS1043A, LS1046A and LS1012A. But the clocks tree has a lot of differences, for instance, the IP modules have different dividers to derive its clock from Platform PLL. And the core cluster PLL and platform PLL maybe have different reference clocks, such as LS1012A. Another problem is which clock/PLL should be described by sys_info->freq_systembus, it is confused in Layerscape Chissis 2. This patch is to bind the sys_info->freq_systembus to the Platform PLL, and handle the different divider of IP modules separately between different SoCs, and separate reference clocks of core cluster PLL and platform PLL. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
2d16a1a6 |
|
07-Dec-2016 |
macro.wave.z@gmail.com <macro.wave.z@gmail.com> |
ARMv8: LS1043A: change macro CONFIG_ARMV8_PSCI definition NXP/Freescale uses macro CONFIG_ARMV8_PSCI to enable their private PSCI implementation in PPA firmware, but this macro naming too generic, so this patch replaces it with a specic one CONFIG_FSL_PPA_ARMV8_PSCI. And this macro CONFIG_ARMV8_PSCI will be used for a generic PSCI for ARMv8 which will be added in following patchs. Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
02fb2761 |
|
20-Nov-2016 |
Shengzhou Liu <Shengzhou.Liu@nxp.com> |
fsl/ddr: Add erratum_a009942_check_cpo and clean related erratum - add additional function erratum_a009942_check_cpo to check if the board needs tuning CPO calibration for optimal setting. - move ERRATUM_A009942(with revision to check cpo_sample option) from fsl_ddr_gen4.c to ctrl_regs.c for reuse on all DDR4/DDR3 parts. - move ERRATUM_A008378 from fsl_ddr_gen4.c to ctrl_regs.c - remove obsolete ERRATUM_A004934 which is replaced with ERRATUM_A009942. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> [YS: Replaced CONFIG_QEMU_E500 with CONFIG_ARCH_QEMU_E500] Reviewed-by: York Sun <york.sun@nxp.com> |
#
e87c673c |
|
16-Nov-2016 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8/fsl-lsch3: Update code to release secondary cores NXP ARMv8 SoC LS2080A release all secondary cores in one-go. But other new SoCs like LS2088A, LS1088A release secondary cores one by one. Update code to release secondary cores based on SoC SVR Add code to release cores one by one for non LS2080A SoCs Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> [YS: remove "inline" from declaration of initiator_type] Reviewed-by: York Sun <york.sun@nxp.com> |
#
f6b96ff6 |
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16-Nov-2016 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Use SVR based timer base address detection Timer controller base address has been changed from LS2080A SoC (and its personalities) to new SoCs like LS2088A, LS1088A. Use SVR based timer base address detection to avoid compile time #ifdef. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
f6a70b3a |
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16-Nov-2016 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add generic get_svr() in assembly Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
78d57842 |
|
16-Nov-2016 |
Alexander Graf <agraf@csgraf.de> |
armv8: fsl-layerscape: Add support for efi_loader RTS reset When implementing efi loader support, we can expose runtime services for payloads. One such service is CPU reset. This patch implements RTS CPU reset support for layerscape systems. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: York Sun <york.sun@nxp.com> |
#
ef9a5fd8 |
|
13-Sep-2016 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: Fix "cpu status" command The core position is not continuous for some SoCs. For example, valid cores may present at position 0, 1, 4, 5, 8, 9, etc. Some registers (including boot release register) only count existing cores. Current implementation of cpu_mask() complies with the continuous numbering. However, command "cpu status" queries the spin table with actual core position. Add functions to calculate core position from core number, to correctly calculate offsets. Tested on LS2080ARDB and LS1043ARDB. Signed-off-by: York Sun <york.sun@nxp.com> |
#
5d1a7a9d |
|
13-Sep-2016 |
Wenbin Song <wenbin.song@nxp.com> |
armv8/fsl-layerscape: print SoC revsion number The exact SoC revsion number can be recognized from U-Boot log. Signed-off-by: Wenbin Song <wenbin.song@nxp.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
cbe7706a |
|
26-Sep-2016 |
Tom Rini <trini@konsulko.com> |
Merge git://git.denx.de/u-boot-fsl-qoriq trini: Drop local memset() from examples/standalone/mem_to_mem_idma2intr.c Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
1221ce45 |
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20-Sep-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
treewide: replace #include <asm/errno.h> with <linux/errno.h> Now, arch/${ARCH}/include/asm/errno.h and include/linux/errno.h have the same content. (both just wrap <asm-generic/errno.h>) Replace all include directives for <asm/errno.h> with <linux/errno.h>. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> [trini: Fixup include/clk.] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
b63a9506 |
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03-Aug-2016 |
York Sun <york.sun@nxp.com> |
armv8: ls2080a: Remove debug server support Debug server feature has been dropped from roadmap. Signed-off-by: York Sun <york.sun@nxp.com> |
#
ed7a3943 |
|
22-Jul-2016 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: mmu: Fix enabling MMU MMU bit in SCTLR needs to be set explicitly after tables are created. It isn't an issue for EL3 becuase this bit is already set by early MMU setup. But for other exception levels this bit was not set. Signed-off-by: York Sun <york.sun@nxp.com> |
#
79119a4d |
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05-Jul-2016 |
Alison Wang <b18965@freescale.com> |
armv8: fsl-layerscape: Add A72 core detection Add support to detect Cortex-A72 core for printing it out. The Initiator Version of A72 core should be 0x4. Signed-off-by: Alison Wang <alison.wang@nxp.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
032d5bb4 |
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28-Jun-2016 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
ARMv8/Layerscape: switch SMP method accordingly If the PSCI and PPA is ready, skip the fixup for spin-table and waking secondary cores. Otherwise, change SMP method to spin-table, and the device node of PSCI will be removed. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
85cdf38e |
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28-Jun-2016 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: fsl-layerscape: add i/d-cache enable function to enable_caches This function assume that the d-cache and MMU has been enabled earlier, so it just created MMU table in main memory. But the assumption is not always correct, for example, the early setup is done in EL3, while enable_caches() is called when the PE has turned into another EL. Define the function mmu_setup() for fsl-layerscape to cover the weak one. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
5ad5823d |
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24-Jun-2016 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Convert to use common MMU framework Drop platform code to create static MMU tables. Use common framework to create MMU tables on the run. Tested on LS2080ARDB with secure and non-secure ram scenarios. Signed-off-by: York Sun <york.sun@nxp.com> |
#
e61a7534 |
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24-Jun-2016 |
York Sun <york.sun@nxp.com> |
armv8: Move secure_ram variable out of generic global data Secure_ram variable was put in generic global data. But only ARMv8 uses this variable. Move it to ARM specific data structure. Signed-off-by: York Sun <york.sun@nxp.com> |
#
a10a31ec |
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18-Jun-2016 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of git://git.denx.de/u-boot-usb Signed-off-by: Tom Rini <trini@konsulko.com> Conflicts: arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
|
#
6fb522dc |
|
12-Jun-2016 |
Sriram Dash <sriram.dash@nxp.com> |
arm64: fsl-layerscape: add get_svr and IS_SVR_REV helper Adds get_svr and IS_SVR_REV helpers for ARMv8 platforms, similar to PPC and ARMv7. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> |
#
a758177f |
|
07-Jun-2016 |
Yunhui Cui <yunhui.cui@nxp.com> |
armv8/ls2080a: configure PMU's PCTBENR to enable WDT The SP805-WDT module on LS2080A requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. The watchdog clock needs to be enabled first. Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
acb8f5e9 |
|
21-Apr-2016 |
Alison Wang <b18965@freescale.com> |
armv8: fsl-layerscape: Remove unnecessary flushing dcache As the issue about the stack will get corrupted when switching between the early and final mmu tables is fixed by commit 70e21b064, the workaround to flush dcache is unnecessary and should be removed. Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
3c1d218a |
|
04-Apr-2016 |
York Sun <york.sun@nxp.com> |
armv8: LS2080A: Consolidate LS2080A and LS2085A LS2080A is the primary SoC, and LS2085A is a personality with AIOP and DPAA DDR. The RDB and QDS boards support both personality. By detecting the SVR at runtime, a single image per board can support both SoCs. It gives users flexibility to swtich SoC without the need to reprogram the board. Signed-off-by: York Sun <york.sun@nxp.com> CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
c05016ab |
|
21-Mar-2016 |
Alexander Graf <agraf@csgraf.de> |
arm64: Fix layerscape mmu setup With commit 7985cdf we converted all systems except for the Layerscape SoCs to the generic descriptor table based page table setup. On the Layerscape SoCs however, we just provide an empty table stub and do the setup ourselves. To reserve enough memory for the tables, we need to override the default counting mechanism which would end up with an empty table because we have no maps. Fixes: 7985cdf Reported-by: York Sun <york.sun@nxp.com> CC: Alison Wang <alison.wang@nxp.com> CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Alexander Graf <agraf@suse.de> Tested-by: York Sun <york.sun@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
7985cdf7 |
|
03-Mar-2016 |
Alexander Graf <agraf@csgraf.de> |
arm64: Remove non-full-va map code By now the code to only have a single page table level with 64k page size and 42 bit address space is no longer used by any board in tree, so we can safely remove it. To clean up code, move the layerscape mmu code to the new defines, removing redundant field definitions. Signed-off-by: Alexander Graf <agraf@suse.de> |
#
c0492141 |
|
07-Dec-2015 |
York Sun <yorksun@freescale.com> |
armv8: fsl-layerscale: Rewrite reserving memory for MC and debug server MC and debug server are not board-specific. Move reserving memory to SoC file, using the new board_reserve_ram_top function. Reduce debug server memory by 2MB to make room for secure memory. In the system with MC and debug server, the top of u-boot memory is not the end of memory. PRAM is not used for this reservation. Signed-off-by: York Sun <yorksun@freescale.com> |
#
c107c0c0 |
|
04-Dec-2015 |
York Sun <yorksun@freescale.com> |
armv8: fsl-layerscape: Make DDR non secure in MMU tables DDR has been set as secure in MMU tables. Non-secure master such as SDHC DMA cannot access data correctly. Mixing secure and non- secure MMU entries requirs the MMU tables themselves in secure memory. This patch moves MMU tables into a secure DDR area. Early MMU tables are changed to set DDR as non-secure. A new table is added into final MMU tables so secure memory can have 2MB granuality. gd->secure_ram tracks the location of this secure memory. For ARMv8 SoCs, the RAM base is not zero and RAM is divided into several banks. gd->secure_ram needs to be maintained before using. This maintenance is board-specific, depending on the SoC and memory bank of the secure memory falls into. Signed-off-by: York Sun <yorksun@freescale.com> |
#
b4017364 |
|
04-Nov-2015 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
armv8: ls2085a: Add workaround of errata A009635 If the core runs at higher than x3 speed of the platform, there is possiblity about sev instruction to getting missed by other cores. This is because of SoC Run Control block may not able to sample the EVENTI(Sev) signals. Configure Run Control and EPU to periodically send out EVENTI signals to wake up A57 cores. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
d764129d |
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04-Nov-2015 |
Alison Wang <b18965@freescale.com> |
armv8/layerscape: Update MMU table with execute-never bits For most device addresses excution shouldn't be allowed. Revise the MMU table to enforce execute-never bits. OCRAM, DDR and IFC are allowed for excution. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Alison Wang <alison.wang@freescale.com> Reported-by: Zhichun Hua <zhichun.hua@freescale.com> |
#
44937214 |
|
09-Nov-2015 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
armv8: LS2080A: Rename LS2085A to reflect LS2080A LS2080A is a prime personality of Freescale’s LS2085A. It is a non-AIOP personality without support of DP-DDR, L2 switch, 1588, PCIe endpoint etc. So renaming existing LS2085A code base to reflect LS2080A (Prime personality) Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> [York Sun: Dropped #ifdef in cpu.c for cpu_type_list] Reviewed-by: York Sun <yorksun@freescale.com> |
#
e8297341 |
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26-Oct-2015 |
Shaohui Xie <Shaohui.Xie@freescale.com> |
armv8/ls1043a: Add Fman support Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
8281c58f |
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26-Oct-2015 |
Mingkai Hu <Mingkai.Hu@freescale.com> |
armv8/fsl_lsch2: Add fsl_lsch2 SoC Freescale LayerScape with Chassis Generation 2 is a set of SoCs with ARMv8 cores and 2rd generation of Chassis. Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
9f3183d2 |
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26-Oct-2015 |
Mingkai Hu <Mingkai.Hu@freescale.com> |
armv8/fsl_lsch3: Change arch to fsl-layerscape There are two LS series processors are built on ARMv8 Layersacpe architecture currently, LS2085A and LS1043A. They are based on ARMv8 core although use different chassis, so create fsl-layerscape to refactor the common code for the LS series processors which also paves the way for adding LS1043A platform. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
cda8f873 |
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11-May-2022 |
Ye Li <ye.li@nxp.com> |
caam: Fix crash in case caam_jr_probe failed If probing caam_jr returns failure, the variable "dev" will not be initialized, so we can't use dev->name for the error print. Otherwise it will cause crash. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Gaurav Jain <gaurav.jain@nxp.com> |
#
cb14cc88 |
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22-Apr-2022 |
Michael Walle <michael@walle.cc> |
armv8: layerscape: get rid of smc_call() There are two different implementations to do a secure monitor call: smc_call() and arm_smccc_smc(). The former is defined in fwcall.c and seems to be an ad-hoc implementation. The latter is imported from linux. smc_call() is also only available if CONFIG_ARMV8_PSCI is not defined. This makes it impossible to have both PSCI calls and PSCI implementation in one u-boot build. The layerscape SoC code decide at runtime via check_psci() if there is a PSCI support. Therefore, this is a prerequisite patch to add PSCI implementation support for the layerscape SoCs. Note, for the TFA part, this is only compile time tested with (ls1028ardb_tfa_defconfig). Signed-off-by: Michael Walle <michael@walle.cc> [Rebased] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
dfb6da55 |
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05-Apr-2022 |
Marek Vasut <marex@denx.de> |
armv8: layerscape: env: Switch to arch_env_get_location() Implement arch_env_get_location() instead of env_get_location(), so that the env_get_location() can be implemented on board level and override the arch_env_get_location() architecture defaults. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Adam Ford <aford173@gmail.com> Cc: Fabio Estevam <festevam@denx.de> Cc: Marek Behún <marek.behun@nic.cz> Cc: Peng Fan <peng.fan@nxp.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefano Babic <sbabic@denx.de> Cc: Tim Harvey <tharvey@gateworks.com> Cc: Tom Rini <trini@konsulko.com> Cc: Tommaso Merciai <tomm.merciai@gmail.com> Cc: Vladimir Oltean <vladimir.oltean@nxp.com> |
#
8976556a |
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24-Mar-2022 |
Gaurav Jain <gaurav.jain@nxp.com> |
Layerscape: Enable Job ring driver model. LS(1021/1012/1028/1043/1046/1088/2088), LX2160, LX2162 platforms are enabled with JR driver model. removed sec_init() call from board files. sec is initialized based on job ring information processed from device tree. Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Michael Walle <michael@walle.cc> |
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f9147d63 |
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25-Feb-2022 |
Tom Rini <trini@konsulko.com> |
Convert CONFIG_CHIP_SELECTS_PER_CTRL to Kconfig This converts the following to Kconfig: CONFIG_CHIP_SELECTS_PER_CTRL Cc: Alison Wang <alison.wang@nxp.com> Cc: Pramod Kumar <pramod.kumar_1@nxp.com> Cc: Priyanka Jain <priyanka.jain@nxp.com> Cc: Rajesh Bhagat <rajesh.bhagat@nxp.com> Cc: Vladimir Oltean <olteanv@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
2f8a6db5 |
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14-Dec-2021 |
Tom Rini <trini@konsulko.com> |
Finish conversion of CONFIG_SYS_CLK_FREQ to Kconfig In order to finish moving this symbol to Kconfig for all platforms, we need to do a few more things. First, for all platforms that define this to a function, introduce CONFIG_DYNAMIC_SYS_CLK_FREQ, similar to CONFIG_DYNAMIC_DDR_CLK_FREQ and populate clock_legacy.h. This entails also switching all users from CONFIG_SYS_CLK_FREQ to get_board_sys_clk() and updating a few preprocessor tests. With that done, all platforms that define a value here can be converted to Kconfig, and a fall-back of zero is sufficiently safe to use (and what is used today in cases where code may or may not have this available). Make sure that code which calls this function includes <clock_legacy.h> to get the prototype. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
77b11f76 |
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18-Sep-2021 |
Vladimir Oltean <vladimir.oltean@nxp.com> |
net: replace the "xfi" phy-mode with "10gbase-r" As part of the effort of making U-Boot work with the same device tree as Linux, there is an issue with the "xfi" phy-mode. To be precise, in Linux there was a discussion (for those who have time to read: https://lore.kernel.org/netdev/1576768881-24971-2-git-send-email-madalin.bucur@oss.nxp.com/) which led to a patch: https://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next.git/commit/?id=c114574ebfdf42f826776f717c8056a00fa94881 TL;DR: "xfi" was standardized in Linux as "10gbase-r". This patch changes the relevant occurrences in U-Boot to use "10gbase-r" instead of "xfi" wherever applicable. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> |
#
84c2e044 |
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20-Apr-2021 |
Jiafei Pan <Jiafei.Pan@nxp.com> |
armv8: layerscape: add PSCI support for cpu release For cpu release command, check whether PSCI is supported firstly, if supported, use PSCI to kick off secondary cores, otherwise still use spin table. Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com> [Fixed checkpatch alignment CHECKs] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
35b65dd8 |
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15-Dec-2020 |
Harald Seiler <hws@denx.de> |
reset: Remove addr parameter from reset_cpu() Historically, the reset_cpu() function had an `addr` parameter which was meant to pass in an address of the reset vector location, where the CPU should reset to. This feature is no longer used anywhere in U-Boot as all reset_cpu() implementations now ignore the passed value. Generic code has been added which always calls reset_cpu() with `0` which means this feature can no longer be used easily anyway. Over time, many implementations seem to have "misunderstood" the existence of this parameter as a way to customize/parameterize the reset (e.g. COLD vs WARM resets). As this is not properly supported, the code will almost always not do what it is intended to (because all call-sites just call reset_cpu() with 0). To avoid confusion and to clean up the codebase from unused left-overs of the past, remove the `addr` parameter entirely. Code which intends to support different kinds of resets should be rewritten as a sysreset driver instead. This transformation was done with the following coccinelle patch: @@ expression argvalue; @@ - reset_cpu(argvalue) + reset_cpu() @@ identifier argname; type argtype; @@ - reset_cpu(argtype argname) + reset_cpu(void) { ... } Signed-off-by: Harald Seiler <hws@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
401d1c4f |
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30-Oct-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop asm/global_data.h from common header Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
3a187cff |
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29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
c760095a |
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23-Oct-2020 |
Razvan Ionut Cirjan <razvanionut.cirjan@nxp.com> |
net: lx2160a.c: Update to set ECx_PMUX precedence As per hardware documentation, ECx_PMUX has precedence over SerDes protocol. For LX2160/LX2162 if DPMACs 17 and 18 are enabled as SGMII through SerDes protocol but ECx_PMUX configured them as RGMII, then the ports will be configured as RGMII and not SGMII. Signed-off-by: Razvan Ionut Cirjan <razvanionut.cirjan@nxp.com> [Rebased] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
d31f3a1b |
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09-Sep-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2160a: fix reset sequence Make sure that SW_RST_REQ and RST_REQ_MSK are cleared before triggering hardware reset request. Signed-off-by: Thirupathaiah Annapureddy <thiruan@linux.microsoft.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
b75d8dc5 |
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26-Jun-2020 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
treewide: convert bd_t to struct bd_info by coccinelle The Linux coding style guide (Documentation/process/coding-style.rst) clearly says: It's a **mistake** to use typedef for structures and pointers. Besides, using typedef for structures is annoying when you try to make headers self-contained. Let's say you have the following function declaration in a header: void foo(bd_t *bd); This is not self-contained since bd_t is not defined. To tell the compiler what 'bd_t' is, you need to include <asm/u-boot.h> #include <asm/u-boot.h> void foo(bd_t *bd); Then, the include direcective pulls in more bloat needlessly. If you use 'struct bd_info' instead, it is enough to put a forward declaration as follows: struct bd_info; void foo(struct bd_info *bd); Right, typedef'ing bd_t is a mistake. I used coccinelle to generate this commit. The semantic patch that makes this change is as follows: <smpl> @@ typedef bd_t; @@ -bd_t +struct bd_info </smpl> Signed-off-by: Masahiro Yamada <masahiroy@kernel.org> |
#
25a5818f |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop asm/ptrace.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
f7ae49fc |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
90526e9f |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop net.h from common header Move this header out of the common header. Network support is used in quite a few places but it still does not warrant blanket inclusion. Note that this net.h header itself has quite a lot in it. It could be split into the driver-mode support, functions, structures, checksumming, etc. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
714497e3 |
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16-May-2020 |
Michael Walle <michael@walle.cc> |
efi_loader: round the memory area in efi_add_memory_map() Virtually all callers of this function do the rounding on their own. Some do it right, some don't. Instead of doing this in each caller, do the rounding in efi_add_memory_map(). Change the size parameter to bytes instead of pages and remove aligning and size calculation in all callers. There is no more need to make the original efi_add_memory_map() (which takes pages as size) available outside the module. Thus rename it to efi_add_memory_map_pg() and make it static to prevent further misuse outside the module. Signed-off-by: Michael Walle <michael@walle.cc> Add missing comma in sunxi_display.c. Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de> |
#
6eb32a03 |
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23-Apr-2020 |
Madalin Bucur <madalin.bucur@oss.nxp.com> |
driver: net: fm: add DM ETH support Probe the FMan MACs based on the device tree while retaining the legacy code/functionality. One notable change introduced here is that, for DM_ETH, the name of the interfaces is corrected to the fmX-macY format, that avoids the referral to the MAC block names which were incorrect for FMan v3 devices (i.e. DTSEC, TGEC) and had weird formatting (i.e. FM1@DTSEC6, FM1@TGEC1). The legacy code is left unchanged in this respect. Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
6ebd4883 |
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27-Apr-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
fsl-layerscape: Add RESV_RAM check in resv_ram addr The initialization of gd->arch.resv_ram pointer should depend on if the RESV_RAM config is enabled. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Wasim Khan <wasim.khan@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
0d9d557d |
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10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
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db41d65a |
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28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move hang() to the same header as panic() At present panic() is in the vsprintf.h header file. That does not seem like an obvious choice for hang(), even though it relates to panic(). So let's put hang() in its own header. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Migrate a few more files] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
9b4a205f |
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28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move RAM-sizing functions to init.h These functions relate to memory init so move them into the init header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
3499dd03 |
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27-Nov-2019 |
Alex Marginean <alexandru.marginean@nxp.com> |
ls1028a: Configure stream IDs for integrated PCI and fix up Linux DT Hardware comes out of reset with implicit values, but these are outside the accepted range for Layerscape gen 3 chassis spec used on LS1028A. Allocate different IDs and fix up Linux DT to use them. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
b5981474 |
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14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some CPU functions out of common.h These functions belong in cpu_func.h since they do not use driver model. Move them over. Don't bother adding comments since these functions should be deleted. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
68a6aa85 |
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14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move mii_init() function out of common.h This function belongs in mii.h so move it over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
2189d5f1 |
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14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
Move strtomhz() to vsprintf.h At present this function sits in its own file but it does not really justify it. There are similar string functions in vsprintf.h, so move it there. Also add the missing function comment. Use the vsprintf.h include file explicitly where needed. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
812ff53c |
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30-Oct-2019 |
Pankaj Bansal <pankaj.bansal@nxp.com> |
fsl-layerscape: fix warning if no hwconfig is defined While getting the 'subarg' of 'hwconfig' env variable in config_core_prefetch(), if no hwconfig variable is defined, below warning is received: WARNING: Calling __hwconfig without a buffer and before environment is ready Fix this by checking 'hwconfig' env variable. If not found return without further processing. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Tested-by: Michael Walle <michael@walle.cc> |
#
28f9393b |
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17-Oct-2019 |
Mathew McBride <matt@traverse.com.au> |
fsl-layerscape: do not use layerscape EFI reset if PSCI used If the secure world reset handlers are used (via CONFIG_PSCI_RESET), then do not use the layerscape-specific implementation. Signed-off-by: Mathew McBride <matt@traverse.com.au> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
6ed69523 |
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18-Sep-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add more personalities support Add LS1027A, LS1018A and LS1017A personalities support to LS1028A SoC family. LS1028A is the prime personality of LS1028A SoC family. LS1027A is a lower funtionality version of QorIQ LS1028A which does not support the multimedia subsystems, such as LCD controller, GPU, and eDP PHY. The QorIQ LS1018A and LS1017A SoCs are single 64-bit Arm A72 core, low power versions of the QorIQ LS1028A and LS1027A SoCs respectively. Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
0490cab5 |
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08-Aug-2019 |
Thomas Schaefer <thomas.schaefer@kontron.com> |
armv8: ls1028a: configure PMU's PCTBENR to enable WDT The SP805-WDT module on LS1028A requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. The watchdog clock needs to be enabled first. Signed-off-by: Thomas Schaefer <thomas.schaefer@kontron.com> Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
f3998fdc |
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02-Aug-2019 |
Simon Glass <sjg@chromium.org> |
env: Rename environment.h to env_internal.h This file contains lots of internal details about the environment. Most code can include env.h instead, calling the functions there as needed. Rename this file and add a comment at the top to indicate its internal nature. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> [trini: Fixup apalis-tk1.c] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
3a7d5571 |
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01-Aug-2019 |
Simon Glass <sjg@chromium.org> |
env: Move env_get_f() to env.h Move this function over to the new header file. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
d9532e80 |
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23-Apr-2019 |
Udit Agarwal <udit.agarwal@nxp.com> |
armv8: fsl-layerscape: Set env_loc to ENVL_NOWHERE with CONFIG_ENV_IS_NOWHERE. ENVL_NOWHERE is dependent on CONFIG_ENV_IS_NOWHERE and not on CONFIG_CHAIN_OF_TRUST so return ENVL_NOWHERE when CONFIG_ENV_IS_NOWHERE is enabled Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
d4ad111d |
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10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
059d9422 |
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08-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: lx2160a: add MMU table entries for PCIe The lx2160a have up to 6 PCIe controllers and have different address and size of PCIe region. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
8348e798 |
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08-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: layerscape: use PCIe address macro for precompile PCIe MMU entry Change to use PCIe address macro to determine if precompile the PCIe MMU table entry. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
10015025 |
|
03-May-2019 |
Trevor Woerner <trevor@toganlabs.com> |
CONFIG_SPL_SYS_[DI]CACHE_OFF: add While converting CONFIG_SYS_[DI]CACHE_OFF to Kconfig, there are instances where these configuration items are conditional on SPL. This commit adds SPL variants of these configuration items, uses CONFIG_IS_ENABLED(), and updates the configurations as required. Acked-by: Alexey Brodkin <abrodkin@synopsys.com> Signed-off-by: Trevor Woerner <trevor@toganlabs.com> [trini: Make the default depend on the setting for full U-Boot, update more zynq hardware] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
2e53759d |
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29-Oct-2018 |
Pankaj Bansal <pankaj.bansal@nxp.com> |
armv8: fsl-layerscape: reorder rgmii dpmacs' enablement some dpmacs in armv8a based freescale layerscape SOCs can be configured via both serdes(sgmii, xfi, xlaui etc) bits and via EC*_PMUX(rgmii) bits in RCW. e.g. dpmac 17 and 18 in LX2160A can be configured as SGMII from serdes bits and as RGMII via EC1_PMUX/EC2_PMUX bits Now if a dpmac is enabled by serdes bits then it takes precedence over EC*_PMUX bits. i.e. in LX2160A if we select serdes protocol that configures dpmac17 as SGMII and set the EC1_PMUX as RGMII, then the dpmac is SGMII and not RGMII. Therefore, move the fsl_rgmii_init after fsl_serdes_init. in fsl_rgmii_init function of SOC, we will check if the dpmac is enabled or not? if it is (fsl_serdes_init has already enabled the dpmac), then don't enable it. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
ec88ff80 |
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19-Dec-2018 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1043a: add SVR definitions for 23x23 package silicon LS1043A/LS1023A 23x23 package silicon has different SVR:VAR_PER. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
d23da2ae |
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26-Dec-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: fixes for TFABOOT framework Fixes for TFABOOT framework - update eMMC bootsrc to SD_MMC - Increase buffer size for mcinitcmd from 256 to 512 - Fix mcinitcmd and bootcmd for Secure Boot Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
4909b89e |
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29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
d6fdec21 |
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29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8:fsl-layerscape: Add support for Chassis 3.2 NXP layerscape architecture Chassis 3.2 builds upon chassis3 architecture with changes like DDR Memory map change, removal of IFC and support of upto 8 I2C controller. Patch add README.lsch3_2 and the above changes under macro CONFIG_NXP_LSCH3_2. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
56db948b |
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05-Nov-2018 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: Update parsing boot source Workaround of erratum A010539 clears the RCW source field in PORSR1 register, causing failure of detecting boot source using this method. Use SMC call if U-Boot runs at EL2. If SMC is not implemented or running at EL3, continue to read PORSR1 and presume QSPI as boot source if erratum workaround A010539 is enabled and RCW source is cleared. Signed-off-by: York Sun <york.sun@nxp.com> |
#
681d489e |
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05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: layerscape: add SMC calls for DDR size and bank info Adds SMC calls for getting DDR size and bank info for TFABOOT. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
2141d250 |
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05-Nov-2018 |
Pankit Garg <pankit.garg@nxp.com> |
armv8: fsl-layerscape: bootcmd identification for TFABOOT Adds bootcmd identificaton on basis on boot source, valid in TFABOOT configuration. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> [YS: remove unnecessary braces] Reviewed-by: York Sun <york.sun@nxp.com> |
#
4c417384 |
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05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com> |
#
535d76a1 |
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05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: layerscape: Add TFABOOT support Adds TFABOOT support config option and add generic code to enable execution from DDR. Signed-off-by: York Sun <york.sun@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> |
#
e3506480 |
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05-Nov-2018 |
Pankit Garg <pankit.garg@nxp.com> |
armv8: fsl-layerscape: change tlb base from OCRAM to DDR in EL < 3 Change tlb base address from OCRAM to DDR when exception level is less than 3. Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
d171c707 |
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05-Nov-2018 |
York Sun <york.sun@nxp.com> |
move data structure out of cpu.h Move static definitions to cpu.c file, as it doesn't allow the cpu.h file to be included in multiple c files. Signed-off-by: York Sun <york.sun@nxp.com> |
#
9b5e6396 |
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30-Aug-2018 |
Stephen Warren <swarren@nvidia.com> |
efi_loader: simplify ifdefs Use CONFIG_IS_ENABLED(EFI_LOADER) to avoid explicitly checking CONFIG_SPL too. This simplifies the conditional. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Alexander Graf <agraf@suse.de> |
#
9cce5663 |
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16-Jul-2018 |
Joe Hershberger <joe.hershberger@ni.com> |
arm: Prevent redefinition error in fsl-layerscape The include/phy.h will start including dm.h, which pulls in linux/compat.h after the attempted redefinition in arch/arm/include/asm/armv8/mmu.h, so move this include to allow redefinition. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> |
#
83d290c5 |
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06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
482fc90c |
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06-Feb-2018 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
efi_loader: add missing EFI_RESET_PLATFORM_SPECIFIC EFI_RESET_PLATFORM_SPECIFIC is one of the values that can be used for the EFI service ResetSystem. The missing definition is added. The value has to handled in efi_reset_system(). Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Alexander Graf <agraf@suse.de> |
#
22c793e6 |
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03-Mar-2018 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
efi_loader: exit status for efi_reset_system_init efi_reset_system_init provides the architecture or board specific initialization of the EFI subsystem. Errors should be caught and signalled by a return code. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Alexander Graf <agraf@suse.de> |
#
958b2ed5 |
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09-Jan-2018 |
Zhang Ying-22455 <ying.zhang22455@nxp.com> |
armv8/ls1088a: configure PMU's PCTBENR to enable WDT The SP805-WDT module on LS1088A requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. The watchdog clock needs to be enabled first. Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
44262327 |
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15-Dec-2017 |
Ahmed Mansour <ahmed.mansour@nxp.com> |
drivers/misc: Share qbman init between archs This patch adds changes necessary to move functionality present in PowerPC folders with ARM architectures that have DPAA1 QBMan hardware - Create new board/freescale/common/fsl_portals.c to house shared device tree fixups for DPAA1 devices with ARM and PowerPC cores - Add new header file to top includes directory to allow files in both architectures to grab the function prototypes - Port inhibit_portals() from PowerPC to ARM. This function is used in setup to disable interrupts on all QMan and BMan portals. It is needed because the interrupts are enabled by default for all portals including unused/uninitialised portals. When the kernel attempts to go to deep sleep the unused portals prevent it from doing so Signed-off-by: Ahmed Mansour <ahmed.mansour@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
a8f33034 |
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03-Dec-2017 |
Wenbin song <wenbin.song@nxp.com> |
armv8: ls1043a/ls2080a: check SoC by device ID Check LS1043A/LS2080a by device ID without using personality ID to determine revision number. This check applies to all various personalities of the same SoC family. Signed-off-by: Wenbin Song <wenbin.song@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
2db53cfe |
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09-Nov-2017 |
Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
armv8: fsl-layerscape: Add support of disabling core prefetch Instruction prefetch feature is by default enabled during core release. This patch add support of disabling instruction prefetch by setting core mask in PPA. Here each core mask bit represents a core and prefetch is disabled at the time of core release. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
7eb40f0f |
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28-Sep-2017 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: Avoid running dram_init_banksize again gd->ram_size is reduced in this function to reserve secure memory. Avoid running this function again to further reduce memory size. This fixes issue for SPL boot with PPA image loaded in which case secure memory is incorrectly allocated due to repeated calling. Signed-off-by: York Sun <york.sun@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
710d0cd7 |
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03-Oct-2017 |
Sumit Garg <sumit.garg@nxp.com> |
armv8: fsl-layerscape: Allocate Secure memory from first ddr region This change is required due to trusted OS (OP-TEE) not being position independent code, it requires compile time fixed base address. To take care of this it is assumed that all layerscape armv8 platforms has minimum 2G ddr in first region. So we can have fixed address space (66 MB -> (2MB for PPA + 64MB for trusted OS)) allocated from top of first 2G ddr region and compile trusted OS with this fixed base address. But one exception here is ls1012 where we have only 1G (rdb) or 512M (frdm) ddr memory. For those we can have different fixed compile time base addresses for trusted OS. Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
e9303a41 |
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07-Sep-2017 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: Fix MC reserved memory calculation In case high region memory doesn't have enough space for Management Complex (MC), the return value should indicate a failure so the caller can handle it accordingly. Signed-off-by: York Sun <york.sun@nxp.com> Reported-by: Ebony Zhu <ebony.zhu@nxp.com> |
#
17d066fc |
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31-Aug-2017 |
Ashish Kumar <Ashish.Kumar@nxp.com> |
armv8: fsl-layerscape: Support to add RGMII for ls1088aqds This patch adds support for RGMII protocol NXP's LDPAA2 support RGMII protocol. LS1088A is the first Soc supporting both RGMII and SGMII. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Amrita Kumari <amrita.kumari@nxp.com> Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
63b2316c |
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10-Aug-2017 |
Ashish Kumar <Ashish.Kumar@nxp.com> |
fsl-layerscape: Consolidate registers space defination for CCI-400 bus CoreLink Cache Coherent Interconnect (CCI) provides full cache coherency between two clusters of multi-core CPUs and I/O coherency for devices and I/O masters. This patch add new config option SYS_FSL_HAS_CCI400 and moves existing register space definaton of CCI-400 bus to fsl_immap to be shared. CONFIG_SYS_CCI400_ADDR is replaced with SYS_CCI400_OFFSET in Kconfig. Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> [YS: revised commit message, squashed patches for armv8 and armv7] Reviewed-by: York Sun <york.sun@nxp.com> |
#
6e2941d7 |
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17-May-2017 |
Simon Glass <sjg@chromium.org> |
common: freescale: Move arch-specific declarations The declarations should not be in common.h. Move them to the arch-specific headers. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Fixup thinko defined(FSL_LSCH3) -> defined(CONFIG_FSL_LSCH3)] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
399e2bb6 |
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15-May-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Make U-Boot EL2 safe When U-Boot boots from EL2, skip some lowlevel init code requiring EL3, including CCI-400/CCN-504, trust zone, GIC, etc. These initialization tasks are carried out before U-Boot runs. This applies to the RAM version image used for SPL boot if PPA is loaded first. Signed-off-by: York Sun <york.sun@nxp.com> |
#
1f55a938 |
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05-May-2017 |
Santan Kumar <santan.kumar@nxp.com> |
armv8: ls2080aqds: Add support for SD boot Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
e809e747 |
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27-Apr-2017 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: fsl-layerscape: Add NXP LS2081A, LS2041A SoC support The QorIQ LS2081A SoC has eight 64-bit ARM v8 Cortex A72 cores and is built on layerscape architecture. It is 40-pin derivative of LS2084A (non-AIOP personality of LS2088A). So feature-wise it is same as LS2084A. LS2041A is a 4-core personality of LS2081A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
026f30ec |
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18-Apr-2017 |
Yuantian Tang <andy.tang@nxp.com> |
arm: psci: make psci usable on single core socs PSCI can be used on both multiple and single core socs. Current implementation only allows PSCI to work on multiple core socs. This patch removes this restriction so that PSCI can work on single core socs as well. Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
4a3ab193 |
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27-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: ls2080a: Drop macro CONFIG_LS2080A Use CONFIG_ARCH_LS2080A instead. Signed-off-by: York Sun <york.sun@nxp.com> |
#
3eace37e |
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06-Apr-2017 |
Simon Glass <sjg@chromium.org> |
arm: freescale: Rename initdram() to fsl_initdram() This function name shadows a global name but is in fact different. This is very confusing. Rename it to help with the following refactoring. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
76b00aca |
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31-Mar-2017 |
Simon Glass <sjg@chromium.org> |
board_f: Drop setup_dram_config() wrapper By making dram_init_banksize() return an error code we can drop the wrapper. Adjust this and clean up all implementations. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
088454cd |
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31-Mar-2017 |
Simon Glass <sjg@chromium.org> |
board_f: Drop return value from initdram() At present we cannot use this function as an init sequence call without a wrapper, since it returns the RAM size. Adjust it to set the RAM size in global_data instead, and return 0 on success. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
52c41180 |
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31-Mar-2017 |
Simon Glass <sjg@chromium.org> |
board_f: Drop board_type parameter from initdram() It looks like only cm5200 and tqm8xx use this feature, so we don't really need it in generic code. Drop it and have the users access gd->board_type directly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
3d8553f0 |
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02-Mar-2017 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
pci: layerscape: add LS2088A series SoC pcie support The LS2088A series SoCs has different physical memory map address and CCSR registers address against LS2080A series SoCs. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
eea1cb77 |
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13-Feb-2017 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8/fsl-layerscape: Update erratum A009635 implementation Erratum A009635 is valid only for LS2080A SoC and its personality. Add SoC svr check. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
4961eafc |
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06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Update early MMU for DDR after initialization In early MMU table, DDR has to be mapped as device memory to avoid speculative access. After DDR is initialized, it needs to be updated to normal memory to allow code execution. To simplify the code, dram_init() is moved into a common file as a weak function. Signed-off-by: York Sun <york.sun@nxp.com> |
#
a045a0c3 |
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06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Fix the sequence of changing MMU table This patch follows the break-before-make process when making changes to MMU table. MMU is disabled before changing TTBR to avoid any potential race condition. Signed-off-by: York Sun <york.sun@nxp.com> |
#
24f55496 |
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06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Update MMU mapping with actual DDR size Update mapping with actual DDR size. Non-existing memory should not be mapped as "normal" memory to avoid speculative access. Signed-off-by: York Sun <york.sun@nxp.com> |
#
36cc0de0 |
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06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Rewrite memory reservation For ARMv8 Layerscape SoCs, secure memory and MC memorey are reserved at the end of DDR. DDR is spit into two or three banks. This patch reverts commit aabd7ddb and simplifies the calculation of reserved memory, and moves the code into common SoC file. Secure memory is carved out first. DDR bank size is reduced. Reserved memory is then allocated on the top of available memory. U-Boot still has access to reserved memory as data transferring is needed. Device tree is fixed with reduced memory size to hide the reserved memory from OS. The same region is reserved for efi_loader. Signed-off-by: York Sun <york.sun@nxp.com> |
#
daa92644 |
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16-Jan-2017 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
ARMv8/sec_firmware: relocated and renamed the config FSL_PPA_ARMV8_PSCI Moved the config FSL_PPA_ARMV8_PSCI from fsl-layerscape's Kconfig to Kconfig under armv8 and renamed it to SEC_FIRMWARE_ARMV8_PSCI. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
904110c7 |
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10-Jan-2017 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8/fsl-lsch2: refactor the clock system initialization Up to now, there are 3 kind of SoCs under Layerscape Chassis 2, like LS1043A, LS1046A and LS1012A. But the clocks tree has a lot of differences, for instance, the IP modules have different dividers to derive its clock from Platform PLL. And the core cluster PLL and platform PLL maybe have different reference clocks, such as LS1012A. Another problem is which clock/PLL should be described by sys_info->freq_systembus, it is confused in Layerscape Chissis 2. This patch is to bind the sys_info->freq_systembus to the Platform PLL, and handle the different divider of IP modules separately between different SoCs, and separate reference clocks of core cluster PLL and platform PLL. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
2d16a1a6 |
|
07-Dec-2016 |
macro.wave.z@gmail.com <macro.wave.z@gmail.com> |
ARMv8: LS1043A: change macro CONFIG_ARMV8_PSCI definition NXP/Freescale uses macro CONFIG_ARMV8_PSCI to enable their private PSCI implementation in PPA firmware, but this macro naming too generic, so this patch replaces it with a specic one CONFIG_FSL_PPA_ARMV8_PSCI. And this macro CONFIG_ARMV8_PSCI will be used for a generic PSCI for ARMv8 which will be added in following patchs. Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
02fb2761 |
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20-Nov-2016 |
Shengzhou Liu <Shengzhou.Liu@nxp.com> |
fsl/ddr: Add erratum_a009942_check_cpo and clean related erratum - add additional function erratum_a009942_check_cpo to check if the board needs tuning CPO calibration for optimal setting. - move ERRATUM_A009942(with revision to check cpo_sample option) from fsl_ddr_gen4.c to ctrl_regs.c for reuse on all DDR4/DDR3 parts. - move ERRATUM_A008378 from fsl_ddr_gen4.c to ctrl_regs.c - remove obsolete ERRATUM_A004934 which is replaced with ERRATUM_A009942. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> [YS: Replaced CONFIG_QEMU_E500 with CONFIG_ARCH_QEMU_E500] Reviewed-by: York Sun <york.sun@nxp.com> |
#
e87c673c |
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16-Nov-2016 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8/fsl-lsch3: Update code to release secondary cores NXP ARMv8 SoC LS2080A release all secondary cores in one-go. But other new SoCs like LS2088A, LS1088A release secondary cores one by one. Update code to release secondary cores based on SoC SVR Add code to release cores one by one for non LS2080A SoCs Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> [YS: remove "inline" from declaration of initiator_type] Reviewed-by: York Sun <york.sun@nxp.com> |
#
f6b96ff6 |
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16-Nov-2016 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Use SVR based timer base address detection Timer controller base address has been changed from LS2080A SoC (and its personalities) to new SoCs like LS2088A, LS1088A. Use SVR based timer base address detection to avoid compile time #ifdef. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
f6a70b3a |
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16-Nov-2016 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add generic get_svr() in assembly Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
78d57842 |
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16-Nov-2016 |
Alexander Graf <agraf@csgraf.de> |
armv8: fsl-layerscape: Add support for efi_loader RTS reset When implementing efi loader support, we can expose runtime services for payloads. One such service is CPU reset. This patch implements RTS CPU reset support for layerscape systems. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: York Sun <york.sun@nxp.com> |
#
ef9a5fd8 |
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13-Sep-2016 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: Fix "cpu status" command The core position is not continuous for some SoCs. For example, valid cores may present at position 0, 1, 4, 5, 8, 9, etc. Some registers (including boot release register) only count existing cores. Current implementation of cpu_mask() complies with the continuous numbering. However, command "cpu status" queries the spin table with actual core position. Add functions to calculate core position from core number, to correctly calculate offsets. Tested on LS2080ARDB and LS1043ARDB. Signed-off-by: York Sun <york.sun@nxp.com> |
#
5d1a7a9d |
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13-Sep-2016 |
Wenbin Song <wenbin.song@nxp.com> |
armv8/fsl-layerscape: print SoC revsion number The exact SoC revsion number can be recognized from U-Boot log. Signed-off-by: Wenbin Song <wenbin.song@nxp.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
cbe7706a |
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26-Sep-2016 |
Tom Rini <trini@konsulko.com> |
Merge git://git.denx.de/u-boot-fsl-qoriq trini: Drop local memset() from examples/standalone/mem_to_mem_idma2intr.c Signed-off-by: Tom Rini <trini@konsulko.com>
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#
1221ce45 |
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20-Sep-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
treewide: replace #include <asm/errno.h> with <linux/errno.h> Now, arch/${ARCH}/include/asm/errno.h and include/linux/errno.h have the same content. (both just wrap <asm-generic/errno.h>) Replace all include directives for <asm/errno.h> with <linux/errno.h>. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> [trini: Fixup include/clk.] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
b63a9506 |
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03-Aug-2016 |
York Sun <york.sun@nxp.com> |
armv8: ls2080a: Remove debug server support Debug server feature has been dropped from roadmap. Signed-off-by: York Sun <york.sun@nxp.com> |
#
ed7a3943 |
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22-Jul-2016 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: mmu: Fix enabling MMU MMU bit in SCTLR needs to be set explicitly after tables are created. It isn't an issue for EL3 becuase this bit is already set by early MMU setup. But for other exception levels this bit was not set. Signed-off-by: York Sun <york.sun@nxp.com> |
#
79119a4d |
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05-Jul-2016 |
Alison Wang <b18965@freescale.com> |
armv8: fsl-layerscape: Add A72 core detection Add support to detect Cortex-A72 core for printing it out. The Initiator Version of A72 core should be 0x4. Signed-off-by: Alison Wang <alison.wang@nxp.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
032d5bb4 |
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28-Jun-2016 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
ARMv8/Layerscape: switch SMP method accordingly If the PSCI and PPA is ready, skip the fixup for spin-table and waking secondary cores. Otherwise, change SMP method to spin-table, and the device node of PSCI will be removed. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
85cdf38e |
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28-Jun-2016 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: fsl-layerscape: add i/d-cache enable function to enable_caches This function assume that the d-cache and MMU has been enabled earlier, so it just created MMU table in main memory. But the assumption is not always correct, for example, the early setup is done in EL3, while enable_caches() is called when the PE has turned into another EL. Define the function mmu_setup() for fsl-layerscape to cover the weak one. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
5ad5823d |
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24-Jun-2016 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Convert to use common MMU framework Drop platform code to create static MMU tables. Use common framework to create MMU tables on the run. Tested on LS2080ARDB with secure and non-secure ram scenarios. Signed-off-by: York Sun <york.sun@nxp.com> |
#
e61a7534 |
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24-Jun-2016 |
York Sun <york.sun@nxp.com> |
armv8: Move secure_ram variable out of generic global data Secure_ram variable was put in generic global data. But only ARMv8 uses this variable. Move it to ARM specific data structure. Signed-off-by: York Sun <york.sun@nxp.com> |
#
a10a31ec |
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18-Jun-2016 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of git://git.denx.de/u-boot-usb Signed-off-by: Tom Rini <trini@konsulko.com> Conflicts: arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
|
#
6fb522dc |
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12-Jun-2016 |
Sriram Dash <sriram.dash@nxp.com> |
arm64: fsl-layerscape: add get_svr and IS_SVR_REV helper Adds get_svr and IS_SVR_REV helpers for ARMv8 platforms, similar to PPC and ARMv7. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> |
#
a758177f |
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07-Jun-2016 |
Yunhui Cui <yunhui.cui@nxp.com> |
armv8/ls2080a: configure PMU's PCTBENR to enable WDT The SP805-WDT module on LS2080A requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. The watchdog clock needs to be enabled first. Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
acb8f5e9 |
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21-Apr-2016 |
Alison Wang <b18965@freescale.com> |
armv8: fsl-layerscape: Remove unnecessary flushing dcache As the issue about the stack will get corrupted when switching between the early and final mmu tables is fixed by commit 70e21b064, the workaround to flush dcache is unnecessary and should be removed. Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
3c1d218a |
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04-Apr-2016 |
York Sun <york.sun@nxp.com> |
armv8: LS2080A: Consolidate LS2080A and LS2085A LS2080A is the primary SoC, and LS2085A is a personality with AIOP and DPAA DDR. The RDB and QDS boards support both personality. By detecting the SVR at runtime, a single image per board can support both SoCs. It gives users flexibility to swtich SoC without the need to reprogram the board. Signed-off-by: York Sun <york.sun@nxp.com> CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
c05016ab |
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21-Mar-2016 |
Alexander Graf <agraf@csgraf.de> |
arm64: Fix layerscape mmu setup With commit 7985cdf we converted all systems except for the Layerscape SoCs to the generic descriptor table based page table setup. On the Layerscape SoCs however, we just provide an empty table stub and do the setup ourselves. To reserve enough memory for the tables, we need to override the default counting mechanism which would end up with an empty table because we have no maps. Fixes: 7985cdf Reported-by: York Sun <york.sun@nxp.com> CC: Alison Wang <alison.wang@nxp.com> CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Alexander Graf <agraf@suse.de> Tested-by: York Sun <york.sun@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
7985cdf7 |
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03-Mar-2016 |
Alexander Graf <agraf@csgraf.de> |
arm64: Remove non-full-va map code By now the code to only have a single page table level with 64k page size and 42 bit address space is no longer used by any board in tree, so we can safely remove it. To clean up code, move the layerscape mmu code to the new defines, removing redundant field definitions. Signed-off-by: Alexander Graf <agraf@suse.de> |
#
c0492141 |
|
07-Dec-2015 |
York Sun <yorksun@freescale.com> |
armv8: fsl-layerscale: Rewrite reserving memory for MC and debug server MC and debug server are not board-specific. Move reserving memory to SoC file, using the new board_reserve_ram_top function. Reduce debug server memory by 2MB to make room for secure memory. In the system with MC and debug server, the top of u-boot memory is not the end of memory. PRAM is not used for this reservation. Signed-off-by: York Sun <yorksun@freescale.com> |
#
c107c0c0 |
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04-Dec-2015 |
York Sun <yorksun@freescale.com> |
armv8: fsl-layerscape: Make DDR non secure in MMU tables DDR has been set as secure in MMU tables. Non-secure master such as SDHC DMA cannot access data correctly. Mixing secure and non- secure MMU entries requirs the MMU tables themselves in secure memory. This patch moves MMU tables into a secure DDR area. Early MMU tables are changed to set DDR as non-secure. A new table is added into final MMU tables so secure memory can have 2MB granuality. gd->secure_ram tracks the location of this secure memory. For ARMv8 SoCs, the RAM base is not zero and RAM is divided into several banks. gd->secure_ram needs to be maintained before using. This maintenance is board-specific, depending on the SoC and memory bank of the secure memory falls into. Signed-off-by: York Sun <yorksun@freescale.com> |
#
b4017364 |
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04-Nov-2015 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
armv8: ls2085a: Add workaround of errata A009635 If the core runs at higher than x3 speed of the platform, there is possiblity about sev instruction to getting missed by other cores. This is because of SoC Run Control block may not able to sample the EVENTI(Sev) signals. Configure Run Control and EPU to periodically send out EVENTI signals to wake up A57 cores. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
d764129d |
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04-Nov-2015 |
Alison Wang <b18965@freescale.com> |
armv8/layerscape: Update MMU table with execute-never bits For most device addresses excution shouldn't be allowed. Revise the MMU table to enforce execute-never bits. OCRAM, DDR and IFC are allowed for excution. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Alison Wang <alison.wang@freescale.com> Reported-by: Zhichun Hua <zhichun.hua@freescale.com> |
#
44937214 |
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09-Nov-2015 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
armv8: LS2080A: Rename LS2085A to reflect LS2080A LS2080A is a prime personality of Freescale’s LS2085A. It is a non-AIOP personality without support of DP-DDR, L2 switch, 1588, PCIe endpoint etc. So renaming existing LS2085A code base to reflect LS2080A (Prime personality) Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> [York Sun: Dropped #ifdef in cpu.c for cpu_type_list] Reviewed-by: York Sun <yorksun@freescale.com> |
#
e8297341 |
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26-Oct-2015 |
Shaohui Xie <Shaohui.Xie@freescale.com> |
armv8/ls1043a: Add Fman support Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
8281c58f |
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26-Oct-2015 |
Mingkai Hu <Mingkai.Hu@freescale.com> |
armv8/fsl_lsch2: Add fsl_lsch2 SoC Freescale LayerScape with Chassis Generation 2 is a set of SoCs with ARMv8 cores and 2rd generation of Chassis. Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
9f3183d2 |
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26-Oct-2015 |
Mingkai Hu <Mingkai.Hu@freescale.com> |
armv8/fsl_lsch3: Change arch to fsl-layerscape There are two LS series processors are built on ARMv8 Layersacpe architecture currently, LS2085A and LS1043A. They are based on ARMv8 core although use different chassis, so create fsl-layerscape to refactor the common code for the LS series processors which also paves the way for adding LS1043A platform. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
cb14cc88 |
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22-Apr-2022 |
Michael Walle <michael@walle.cc> |
armv8: layerscape: get rid of smc_call() There are two different implementations to do a secure monitor call: smc_call() and arm_smccc_smc(). The former is defined in fwcall.c and seems to be an ad-hoc implementation. The latter is imported from linux. smc_call() is also only available if CONFIG_ARMV8_PSCI is not defined. This makes it impossible to have both PSCI calls and PSCI implementation in one u-boot build. The layerscape SoC code decide at runtime via check_psci() if there is a PSCI support. Therefore, this is a prerequisite patch to add PSCI implementation support for the layerscape SoCs. Note, for the TFA part, this is only compile time tested with (ls1028ardb_tfa_defconfig). Signed-off-by: Michael Walle <michael@walle.cc> [Rebased] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
dfb6da55 |
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05-Apr-2022 |
Marek Vasut <marex@denx.de> |
armv8: layerscape: env: Switch to arch_env_get_location() Implement arch_env_get_location() instead of env_get_location(), so that the env_get_location() can be implemented on board level and override the arch_env_get_location() architecture defaults. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Adam Ford <aford173@gmail.com> Cc: Fabio Estevam <festevam@denx.de> Cc: Marek Behún <marek.behun@nic.cz> Cc: Peng Fan <peng.fan@nxp.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefano Babic <sbabic@denx.de> Cc: Tim Harvey <tharvey@gateworks.com> Cc: Tom Rini <trini@konsulko.com> Cc: Tommaso Merciai <tomm.merciai@gmail.com> Cc: Vladimir Oltean <vladimir.oltean@nxp.com> |
#
8976556a |
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24-Mar-2022 |
Gaurav Jain <gaurav.jain@nxp.com> |
Layerscape: Enable Job ring driver model. LS(1021/1012/1028/1043/1046/1088/2088), LX2160, LX2162 platforms are enabled with JR driver model. removed sec_init() call from board files. sec is initialized based on job ring information processed from device tree. Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Michael Walle <michael@walle.cc> |
#
f9147d63 |
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25-Feb-2022 |
Tom Rini <trini@konsulko.com> |
Convert CONFIG_CHIP_SELECTS_PER_CTRL to Kconfig This converts the following to Kconfig: CONFIG_CHIP_SELECTS_PER_CTRL Cc: Alison Wang <alison.wang@nxp.com> Cc: Pramod Kumar <pramod.kumar_1@nxp.com> Cc: Priyanka Jain <priyanka.jain@nxp.com> Cc: Rajesh Bhagat <rajesh.bhagat@nxp.com> Cc: Vladimir Oltean <olteanv@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
2f8a6db5 |
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14-Dec-2021 |
Tom Rini <trini@konsulko.com> |
Finish conversion of CONFIG_SYS_CLK_FREQ to Kconfig In order to finish moving this symbol to Kconfig for all platforms, we need to do a few more things. First, for all platforms that define this to a function, introduce CONFIG_DYNAMIC_SYS_CLK_FREQ, similar to CONFIG_DYNAMIC_DDR_CLK_FREQ and populate clock_legacy.h. This entails also switching all users from CONFIG_SYS_CLK_FREQ to get_board_sys_clk() and updating a few preprocessor tests. With that done, all platforms that define a value here can be converted to Kconfig, and a fall-back of zero is sufficiently safe to use (and what is used today in cases where code may or may not have this available). Make sure that code which calls this function includes <clock_legacy.h> to get the prototype. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
77b11f76 |
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18-Sep-2021 |
Vladimir Oltean <vladimir.oltean@nxp.com> |
net: replace the "xfi" phy-mode with "10gbase-r" As part of the effort of making U-Boot work with the same device tree as Linux, there is an issue with the "xfi" phy-mode. To be precise, in Linux there was a discussion (for those who have time to read: https://lore.kernel.org/netdev/1576768881-24971-2-git-send-email-madalin.bucur@oss.nxp.com/) which led to a patch: https://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next.git/commit/?id=c114574ebfdf42f826776f717c8056a00fa94881 TL;DR: "xfi" was standardized in Linux as "10gbase-r". This patch changes the relevant occurrences in U-Boot to use "10gbase-r" instead of "xfi" wherever applicable. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> |
#
84c2e044 |
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20-Apr-2021 |
Jiafei Pan <Jiafei.Pan@nxp.com> |
armv8: layerscape: add PSCI support for cpu release For cpu release command, check whether PSCI is supported firstly, if supported, use PSCI to kick off secondary cores, otherwise still use spin table. Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com> [Fixed checkpatch alignment CHECKs] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
35b65dd8 |
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15-Dec-2020 |
Harald Seiler <hws@denx.de> |
reset: Remove addr parameter from reset_cpu() Historically, the reset_cpu() function had an `addr` parameter which was meant to pass in an address of the reset vector location, where the CPU should reset to. This feature is no longer used anywhere in U-Boot as all reset_cpu() implementations now ignore the passed value. Generic code has been added which always calls reset_cpu() with `0` which means this feature can no longer be used easily anyway. Over time, many implementations seem to have "misunderstood" the existence of this parameter as a way to customize/parameterize the reset (e.g. COLD vs WARM resets). As this is not properly supported, the code will almost always not do what it is intended to (because all call-sites just call reset_cpu() with 0). To avoid confusion and to clean up the codebase from unused left-overs of the past, remove the `addr` parameter entirely. Code which intends to support different kinds of resets should be rewritten as a sysreset driver instead. This transformation was done with the following coccinelle patch: @@ expression argvalue; @@ - reset_cpu(argvalue) + reset_cpu() @@ identifier argname; type argtype; @@ - reset_cpu(argtype argname) + reset_cpu(void) { ... } Signed-off-by: Harald Seiler <hws@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
401d1c4f |
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30-Oct-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop asm/global_data.h from common header Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
3a187cff |
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29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
c760095a |
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23-Oct-2020 |
Razvan Ionut Cirjan <razvanionut.cirjan@nxp.com> |
net: lx2160a.c: Update to set ECx_PMUX precedence As per hardware documentation, ECx_PMUX has precedence over SerDes protocol. For LX2160/LX2162 if DPMACs 17 and 18 are enabled as SGMII through SerDes protocol but ECx_PMUX configured them as RGMII, then the ports will be configured as RGMII and not SGMII. Signed-off-by: Razvan Ionut Cirjan <razvanionut.cirjan@nxp.com> [Rebased] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
d31f3a1b |
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09-Sep-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2160a: fix reset sequence Make sure that SW_RST_REQ and RST_REQ_MSK are cleared before triggering hardware reset request. Signed-off-by: Thirupathaiah Annapureddy <thiruan@linux.microsoft.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
b75d8dc5 |
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26-Jun-2020 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
treewide: convert bd_t to struct bd_info by coccinelle The Linux coding style guide (Documentation/process/coding-style.rst) clearly says: It's a **mistake** to use typedef for structures and pointers. Besides, using typedef for structures is annoying when you try to make headers self-contained. Let's say you have the following function declaration in a header: void foo(bd_t *bd); This is not self-contained since bd_t is not defined. To tell the compiler what 'bd_t' is, you need to include <asm/u-boot.h> #include <asm/u-boot.h> void foo(bd_t *bd); Then, the include direcective pulls in more bloat needlessly. If you use 'struct bd_info' instead, it is enough to put a forward declaration as follows: struct bd_info; void foo(struct bd_info *bd); Right, typedef'ing bd_t is a mistake. I used coccinelle to generate this commit. The semantic patch that makes this change is as follows: <smpl> @@ typedef bd_t; @@ -bd_t +struct bd_info </smpl> Signed-off-by: Masahiro Yamada <masahiroy@kernel.org> |
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25a5818f |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop asm/ptrace.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
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f7ae49fc |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
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90526e9f |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop net.h from common header Move this header out of the common header. Network support is used in quite a few places but it still does not warrant blanket inclusion. Note that this net.h header itself has quite a lot in it. It could be split into the driver-mode support, functions, structures, checksumming, etc. Signed-off-by: Simon Glass <sjg@chromium.org> |
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714497e3 |
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16-May-2020 |
Michael Walle <michael@walle.cc> |
efi_loader: round the memory area in efi_add_memory_map() Virtually all callers of this function do the rounding on their own. Some do it right, some don't. Instead of doing this in each caller, do the rounding in efi_add_memory_map(). Change the size parameter to bytes instead of pages and remove aligning and size calculation in all callers. There is no more need to make the original efi_add_memory_map() (which takes pages as size) available outside the module. Thus rename it to efi_add_memory_map_pg() and make it static to prevent further misuse outside the module. Signed-off-by: Michael Walle <michael@walle.cc> Add missing comma in sunxi_display.c. Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de> |
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6eb32a03 |
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23-Apr-2020 |
Madalin Bucur <madalin.bucur@oss.nxp.com> |
driver: net: fm: add DM ETH support Probe the FMan MACs based on the device tree while retaining the legacy code/functionality. One notable change introduced here is that, for DM_ETH, the name of the interfaces is corrected to the fmX-macY format, that avoids the referral to the MAC block names which were incorrect for FMan v3 devices (i.e. DTSEC, TGEC) and had weird formatting (i.e. FM1@DTSEC6, FM1@TGEC1). The legacy code is left unchanged in this respect. Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
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6ebd4883 |
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27-Apr-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
fsl-layerscape: Add RESV_RAM check in resv_ram addr The initialization of gd->arch.resv_ram pointer should depend on if the RESV_RAM config is enabled. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Wasim Khan <wasim.khan@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
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0d9d557d |
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10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
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db41d65a |
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28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move hang() to the same header as panic() At present panic() is in the vsprintf.h header file. That does not seem like an obvious choice for hang(), even though it relates to panic(). So let's put hang() in its own header. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Migrate a few more files] Signed-off-by: Tom Rini <trini@konsulko.com> |
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9b4a205f |
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28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move RAM-sizing functions to init.h These functions relate to memory init so move them into the init header. Signed-off-by: Simon Glass <sjg@chromium.org> |
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3499dd03 |
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27-Nov-2019 |
Alex Marginean <alexandru.marginean@nxp.com> |
ls1028a: Configure stream IDs for integrated PCI and fix up Linux DT Hardware comes out of reset with implicit values, but these are outside the accepted range for Layerscape gen 3 chassis spec used on LS1028A. Allocate different IDs and fix up Linux DT to use them. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
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b5981474 |
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14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some CPU functions out of common.h These functions belong in cpu_func.h since they do not use driver model. Move them over. Don't bother adding comments since these functions should be deleted. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
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68a6aa85 |
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14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move mii_init() function out of common.h This function belongs in mii.h so move it over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
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2189d5f1 |
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14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
Move strtomhz() to vsprintf.h At present this function sits in its own file but it does not really justify it. There are similar string functions in vsprintf.h, so move it there. Also add the missing function comment. Use the vsprintf.h include file explicitly where needed. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
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812ff53c |
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30-Oct-2019 |
Pankaj Bansal <pankaj.bansal@nxp.com> |
fsl-layerscape: fix warning if no hwconfig is defined While getting the 'subarg' of 'hwconfig' env variable in config_core_prefetch(), if no hwconfig variable is defined, below warning is received: WARNING: Calling __hwconfig without a buffer and before environment is ready Fix this by checking 'hwconfig' env variable. If not found return without further processing. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Tested-by: Michael Walle <michael@walle.cc> |
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28f9393b |
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17-Oct-2019 |
Mathew McBride <matt@traverse.com.au> |
fsl-layerscape: do not use layerscape EFI reset if PSCI used If the secure world reset handlers are used (via CONFIG_PSCI_RESET), then do not use the layerscape-specific implementation. Signed-off-by: Mathew McBride <matt@traverse.com.au> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
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6ed69523 |
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18-Sep-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add more personalities support Add LS1027A, LS1018A and LS1017A personalities support to LS1028A SoC family. LS1028A is the prime personality of LS1028A SoC family. LS1027A is a lower funtionality version of QorIQ LS1028A which does not support the multimedia subsystems, such as LCD controller, GPU, and eDP PHY. The QorIQ LS1018A and LS1017A SoCs are single 64-bit Arm A72 core, low power versions of the QorIQ LS1028A and LS1027A SoCs respectively. Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
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0490cab5 |
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08-Aug-2019 |
Thomas Schaefer <thomas.schaefer@kontron.com> |
armv8: ls1028a: configure PMU's PCTBENR to enable WDT The SP805-WDT module on LS1028A requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. The watchdog clock needs to be enabled first. Signed-off-by: Thomas Schaefer <thomas.schaefer@kontron.com> Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
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f3998fdc |
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02-Aug-2019 |
Simon Glass <sjg@chromium.org> |
env: Rename environment.h to env_internal.h This file contains lots of internal details about the environment. Most code can include env.h instead, calling the functions there as needed. Rename this file and add a comment at the top to indicate its internal nature. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> [trini: Fixup apalis-tk1.c] Signed-off-by: Tom Rini <trini@konsulko.com> |
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3a7d5571 |
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01-Aug-2019 |
Simon Glass <sjg@chromium.org> |
env: Move env_get_f() to env.h Move this function over to the new header file. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
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d9532e80 |
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23-Apr-2019 |
Udit Agarwal <udit.agarwal@nxp.com> |
armv8: fsl-layerscape: Set env_loc to ENVL_NOWHERE with CONFIG_ENV_IS_NOWHERE. ENVL_NOWHERE is dependent on CONFIG_ENV_IS_NOWHERE and not on CONFIG_CHAIN_OF_TRUST so return ENVL_NOWHERE when CONFIG_ENV_IS_NOWHERE is enabled Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
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d4ad111d |
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10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
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059d9422 |
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08-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: lx2160a: add MMU table entries for PCIe The lx2160a have up to 6 PCIe controllers and have different address and size of PCIe region. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
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8348e798 |
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08-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: layerscape: use PCIe address macro for precompile PCIe MMU entry Change to use PCIe address macro to determine if precompile the PCIe MMU table entry. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
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10015025 |
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03-May-2019 |
Trevor Woerner <trevor@toganlabs.com> |
CONFIG_SPL_SYS_[DI]CACHE_OFF: add While converting CONFIG_SYS_[DI]CACHE_OFF to Kconfig, there are instances where these configuration items are conditional on SPL. This commit adds SPL variants of these configuration items, uses CONFIG_IS_ENABLED(), and updates the configurations as required. Acked-by: Alexey Brodkin <abrodkin@synopsys.com> Signed-off-by: Trevor Woerner <trevor@toganlabs.com> [trini: Make the default depend on the setting for full U-Boot, update more zynq hardware] Signed-off-by: Tom Rini <trini@konsulko.com> |
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2e53759d |
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29-Oct-2018 |
Pankaj Bansal <pankaj.bansal@nxp.com> |
armv8: fsl-layerscape: reorder rgmii dpmacs' enablement some dpmacs in armv8a based freescale layerscape SOCs can be configured via both serdes(sgmii, xfi, xlaui etc) bits and via EC*_PMUX(rgmii) bits in RCW. e.g. dpmac 17 and 18 in LX2160A can be configured as SGMII from serdes bits and as RGMII via EC1_PMUX/EC2_PMUX bits Now if a dpmac is enabled by serdes bits then it takes precedence over EC*_PMUX bits. i.e. in LX2160A if we select serdes protocol that configures dpmac17 as SGMII and set the EC1_PMUX as RGMII, then the dpmac is SGMII and not RGMII. Therefore, move the fsl_rgmii_init after fsl_serdes_init. in fsl_rgmii_init function of SOC, we will check if the dpmac is enabled or not? if it is (fsl_serdes_init has already enabled the dpmac), then don't enable it. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
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ec88ff80 |
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19-Dec-2018 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1043a: add SVR definitions for 23x23 package silicon LS1043A/LS1023A 23x23 package silicon has different SVR:VAR_PER. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
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d23da2ae |
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26-Dec-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: fixes for TFABOOT framework Fixes for TFABOOT framework - update eMMC bootsrc to SD_MMC - Increase buffer size for mcinitcmd from 256 to 512 - Fix mcinitcmd and bootcmd for Secure Boot Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
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4909b89e |
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29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
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d6fdec21 |
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29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8:fsl-layerscape: Add support for Chassis 3.2 NXP layerscape architecture Chassis 3.2 builds upon chassis3 architecture with changes like DDR Memory map change, removal of IFC and support of upto 8 I2C controller. Patch add README.lsch3_2 and the above changes under macro CONFIG_NXP_LSCH3_2. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
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56db948b |
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05-Nov-2018 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: Update parsing boot source Workaround of erratum A010539 clears the RCW source field in PORSR1 register, causing failure of detecting boot source using this method. Use SMC call if U-Boot runs at EL2. If SMC is not implemented or running at EL3, continue to read PORSR1 and presume QSPI as boot source if erratum workaround A010539 is enabled and RCW source is cleared. Signed-off-by: York Sun <york.sun@nxp.com> |
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681d489e |
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05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: layerscape: add SMC calls for DDR size and bank info Adds SMC calls for getting DDR size and bank info for TFABOOT. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
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2141d250 |
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05-Nov-2018 |
Pankit Garg <pankit.garg@nxp.com> |
armv8: fsl-layerscape: bootcmd identification for TFABOOT Adds bootcmd identificaton on basis on boot source, valid in TFABOOT configuration. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> [YS: remove unnecessary braces] Reviewed-by: York Sun <york.sun@nxp.com> |
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4c417384 |
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05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com> |
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535d76a1 |
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05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: layerscape: Add TFABOOT support Adds TFABOOT support config option and add generic code to enable execution from DDR. Signed-off-by: York Sun <york.sun@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> |
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e3506480 |
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05-Nov-2018 |
Pankit Garg <pankit.garg@nxp.com> |
armv8: fsl-layerscape: change tlb base from OCRAM to DDR in EL < 3 Change tlb base address from OCRAM to DDR when exception level is less than 3. Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
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d171c707 |
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05-Nov-2018 |
York Sun <york.sun@nxp.com> |
move data structure out of cpu.h Move static definitions to cpu.c file, as it doesn't allow the cpu.h file to be included in multiple c files. Signed-off-by: York Sun <york.sun@nxp.com> |
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9b5e6396 |
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30-Aug-2018 |
Stephen Warren <swarren@nvidia.com> |
efi_loader: simplify ifdefs Use CONFIG_IS_ENABLED(EFI_LOADER) to avoid explicitly checking CONFIG_SPL too. This simplifies the conditional. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Alexander Graf <agraf@suse.de> |
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9cce5663 |
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16-Jul-2018 |
Joe Hershberger <joe.hershberger@ni.com> |
arm: Prevent redefinition error in fsl-layerscape The include/phy.h will start including dm.h, which pulls in linux/compat.h after the attempted redefinition in arch/arm/include/asm/armv8/mmu.h, so move this include to allow redefinition. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> |
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83d290c5 |
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06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
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482fc90c |
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06-Feb-2018 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
efi_loader: add missing EFI_RESET_PLATFORM_SPECIFIC EFI_RESET_PLATFORM_SPECIFIC is one of the values that can be used for the EFI service ResetSystem. The missing definition is added. The value has to handled in efi_reset_system(). Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Alexander Graf <agraf@suse.de> |
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22c793e6 |
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03-Mar-2018 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
efi_loader: exit status for efi_reset_system_init efi_reset_system_init provides the architecture or board specific initialization of the EFI subsystem. Errors should be caught and signalled by a return code. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Alexander Graf <agraf@suse.de> |
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958b2ed5 |
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09-Jan-2018 |
Zhang Ying-22455 <ying.zhang22455@nxp.com> |
armv8/ls1088a: configure PMU's PCTBENR to enable WDT The SP805-WDT module on LS1088A requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. The watchdog clock needs to be enabled first. Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
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44262327 |
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15-Dec-2017 |
Ahmed Mansour <ahmed.mansour@nxp.com> |
drivers/misc: Share qbman init between archs This patch adds changes necessary to move functionality present in PowerPC folders with ARM architectures that have DPAA1 QBMan hardware - Create new board/freescale/common/fsl_portals.c to house shared device tree fixups for DPAA1 devices with ARM and PowerPC cores - Add new header file to top includes directory to allow files in both architectures to grab the function prototypes - Port inhibit_portals() from PowerPC to ARM. This function is used in setup to disable interrupts on all QMan and BMan portals. It is needed because the interrupts are enabled by default for all portals including unused/uninitialised portals. When the kernel attempts to go to deep sleep the unused portals prevent it from doing so Signed-off-by: Ahmed Mansour <ahmed.mansour@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
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a8f33034 |
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03-Dec-2017 |
Wenbin song <wenbin.song@nxp.com> |
armv8: ls1043a/ls2080a: check SoC by device ID Check LS1043A/LS2080a by device ID without using personality ID to determine revision number. This check applies to all various personalities of the same SoC family. Signed-off-by: Wenbin Song <wenbin.song@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
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2db53cfe |
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09-Nov-2017 |
Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
armv8: fsl-layerscape: Add support of disabling core prefetch Instruction prefetch feature is by default enabled during core release. This patch add support of disabling instruction prefetch by setting core mask in PPA. Here each core mask bit represents a core and prefetch is disabled at the time of core release. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
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7eb40f0f |
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28-Sep-2017 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: Avoid running dram_init_banksize again gd->ram_size is reduced in this function to reserve secure memory. Avoid running this function again to further reduce memory size. This fixes issue for SPL boot with PPA image loaded in which case secure memory is incorrectly allocated due to repeated calling. Signed-off-by: York Sun <york.sun@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
710d0cd7 |
|
03-Oct-2017 |
Sumit Garg <sumit.garg@nxp.com> |
armv8: fsl-layerscape: Allocate Secure memory from first ddr region This change is required due to trusted OS (OP-TEE) not being position independent code, it requires compile time fixed base address. To take care of this it is assumed that all layerscape armv8 platforms has minimum 2G ddr in first region. So we can have fixed address space (66 MB -> (2MB for PPA + 64MB for trusted OS)) allocated from top of first 2G ddr region and compile trusted OS with this fixed base address. But one exception here is ls1012 where we have only 1G (rdb) or 512M (frdm) ddr memory. For those we can have different fixed compile time base addresses for trusted OS. Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
e9303a41 |
|
07-Sep-2017 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: Fix MC reserved memory calculation In case high region memory doesn't have enough space for Management Complex (MC), the return value should indicate a failure so the caller can handle it accordingly. Signed-off-by: York Sun <york.sun@nxp.com> Reported-by: Ebony Zhu <ebony.zhu@nxp.com> |
#
17d066fc |
|
31-Aug-2017 |
Ashish Kumar <Ashish.Kumar@nxp.com> |
armv8: fsl-layerscape: Support to add RGMII for ls1088aqds This patch adds support for RGMII protocol NXP's LDPAA2 support RGMII protocol. LS1088A is the first Soc supporting both RGMII and SGMII. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Amrita Kumari <amrita.kumari@nxp.com> Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
63b2316c |
|
10-Aug-2017 |
Ashish Kumar <Ashish.Kumar@nxp.com> |
fsl-layerscape: Consolidate registers space defination for CCI-400 bus CoreLink Cache Coherent Interconnect (CCI) provides full cache coherency between two clusters of multi-core CPUs and I/O coherency for devices and I/O masters. This patch add new config option SYS_FSL_HAS_CCI400 and moves existing register space definaton of CCI-400 bus to fsl_immap to be shared. CONFIG_SYS_CCI400_ADDR is replaced with SYS_CCI400_OFFSET in Kconfig. Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> [YS: revised commit message, squashed patches for armv8 and armv7] Reviewed-by: York Sun <york.sun@nxp.com> |
#
6e2941d7 |
|
17-May-2017 |
Simon Glass <sjg@chromium.org> |
common: freescale: Move arch-specific declarations The declarations should not be in common.h. Move them to the arch-specific headers. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Fixup thinko defined(FSL_LSCH3) -> defined(CONFIG_FSL_LSCH3)] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
399e2bb6 |
|
15-May-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Make U-Boot EL2 safe When U-Boot boots from EL2, skip some lowlevel init code requiring EL3, including CCI-400/CCN-504, trust zone, GIC, etc. These initialization tasks are carried out before U-Boot runs. This applies to the RAM version image used for SPL boot if PPA is loaded first. Signed-off-by: York Sun <york.sun@nxp.com> |
#
1f55a938 |
|
05-May-2017 |
Santan Kumar <santan.kumar@nxp.com> |
armv8: ls2080aqds: Add support for SD boot Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
e809e747 |
|
27-Apr-2017 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: fsl-layerscape: Add NXP LS2081A, LS2041A SoC support The QorIQ LS2081A SoC has eight 64-bit ARM v8 Cortex A72 cores and is built on layerscape architecture. It is 40-pin derivative of LS2084A (non-AIOP personality of LS2088A). So feature-wise it is same as LS2084A. LS2041A is a 4-core personality of LS2081A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
026f30ec |
|
18-Apr-2017 |
Yuantian Tang <andy.tang@nxp.com> |
arm: psci: make psci usable on single core socs PSCI can be used on both multiple and single core socs. Current implementation only allows PSCI to work on multiple core socs. This patch removes this restriction so that PSCI can work on single core socs as well. Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
4a3ab193 |
|
27-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: ls2080a: Drop macro CONFIG_LS2080A Use CONFIG_ARCH_LS2080A instead. Signed-off-by: York Sun <york.sun@nxp.com> |
#
3eace37e |
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06-Apr-2017 |
Simon Glass <sjg@chromium.org> |
arm: freescale: Rename initdram() to fsl_initdram() This function name shadows a global name but is in fact different. This is very confusing. Rename it to help with the following refactoring. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
76b00aca |
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31-Mar-2017 |
Simon Glass <sjg@chromium.org> |
board_f: Drop setup_dram_config() wrapper By making dram_init_banksize() return an error code we can drop the wrapper. Adjust this and clean up all implementations. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
088454cd |
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31-Mar-2017 |
Simon Glass <sjg@chromium.org> |
board_f: Drop return value from initdram() At present we cannot use this function as an init sequence call without a wrapper, since it returns the RAM size. Adjust it to set the RAM size in global_data instead, and return 0 on success. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
52c41180 |
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31-Mar-2017 |
Simon Glass <sjg@chromium.org> |
board_f: Drop board_type parameter from initdram() It looks like only cm5200 and tqm8xx use this feature, so we don't really need it in generic code. Drop it and have the users access gd->board_type directly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
3d8553f0 |
|
02-Mar-2017 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
pci: layerscape: add LS2088A series SoC pcie support The LS2088A series SoCs has different physical memory map address and CCSR registers address against LS2080A series SoCs. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
eea1cb77 |
|
13-Feb-2017 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8/fsl-layerscape: Update erratum A009635 implementation Erratum A009635 is valid only for LS2080A SoC and its personality. Add SoC svr check. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
4961eafc |
|
06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Update early MMU for DDR after initialization In early MMU table, DDR has to be mapped as device memory to avoid speculative access. After DDR is initialized, it needs to be updated to normal memory to allow code execution. To simplify the code, dram_init() is moved into a common file as a weak function. Signed-off-by: York Sun <york.sun@nxp.com> |
#
a045a0c3 |
|
06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Fix the sequence of changing MMU table This patch follows the break-before-make process when making changes to MMU table. MMU is disabled before changing TTBR to avoid any potential race condition. Signed-off-by: York Sun <york.sun@nxp.com> |
#
24f55496 |
|
06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Update MMU mapping with actual DDR size Update mapping with actual DDR size. Non-existing memory should not be mapped as "normal" memory to avoid speculative access. Signed-off-by: York Sun <york.sun@nxp.com> |
#
36cc0de0 |
|
06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Rewrite memory reservation For ARMv8 Layerscape SoCs, secure memory and MC memorey are reserved at the end of DDR. DDR is spit into two or three banks. This patch reverts commit aabd7ddb and simplifies the calculation of reserved memory, and moves the code into common SoC file. Secure memory is carved out first. DDR bank size is reduced. Reserved memory is then allocated on the top of available memory. U-Boot still has access to reserved memory as data transferring is needed. Device tree is fixed with reduced memory size to hide the reserved memory from OS. The same region is reserved for efi_loader. Signed-off-by: York Sun <york.sun@nxp.com> |
#
daa92644 |
|
16-Jan-2017 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
ARMv8/sec_firmware: relocated and renamed the config FSL_PPA_ARMV8_PSCI Moved the config FSL_PPA_ARMV8_PSCI from fsl-layerscape's Kconfig to Kconfig under armv8 and renamed it to SEC_FIRMWARE_ARMV8_PSCI. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
904110c7 |
|
10-Jan-2017 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8/fsl-lsch2: refactor the clock system initialization Up to now, there are 3 kind of SoCs under Layerscape Chassis 2, like LS1043A, LS1046A and LS1012A. But the clocks tree has a lot of differences, for instance, the IP modules have different dividers to derive its clock from Platform PLL. And the core cluster PLL and platform PLL maybe have different reference clocks, such as LS1012A. Another problem is which clock/PLL should be described by sys_info->freq_systembus, it is confused in Layerscape Chissis 2. This patch is to bind the sys_info->freq_systembus to the Platform PLL, and handle the different divider of IP modules separately between different SoCs, and separate reference clocks of core cluster PLL and platform PLL. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
2d16a1a6 |
|
07-Dec-2016 |
macro.wave.z@gmail.com <macro.wave.z@gmail.com> |
ARMv8: LS1043A: change macro CONFIG_ARMV8_PSCI definition NXP/Freescale uses macro CONFIG_ARMV8_PSCI to enable their private PSCI implementation in PPA firmware, but this macro naming too generic, so this patch replaces it with a specic one CONFIG_FSL_PPA_ARMV8_PSCI. And this macro CONFIG_ARMV8_PSCI will be used for a generic PSCI for ARMv8 which will be added in following patchs. Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
02fb2761 |
|
20-Nov-2016 |
Shengzhou Liu <Shengzhou.Liu@nxp.com> |
fsl/ddr: Add erratum_a009942_check_cpo and clean related erratum - add additional function erratum_a009942_check_cpo to check if the board needs tuning CPO calibration for optimal setting. - move ERRATUM_A009942(with revision to check cpo_sample option) from fsl_ddr_gen4.c to ctrl_regs.c for reuse on all DDR4/DDR3 parts. - move ERRATUM_A008378 from fsl_ddr_gen4.c to ctrl_regs.c - remove obsolete ERRATUM_A004934 which is replaced with ERRATUM_A009942. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> [YS: Replaced CONFIG_QEMU_E500 with CONFIG_ARCH_QEMU_E500] Reviewed-by: York Sun <york.sun@nxp.com> |
#
e87c673c |
|
16-Nov-2016 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8/fsl-lsch3: Update code to release secondary cores NXP ARMv8 SoC LS2080A release all secondary cores in one-go. But other new SoCs like LS2088A, LS1088A release secondary cores one by one. Update code to release secondary cores based on SoC SVR Add code to release cores one by one for non LS2080A SoCs Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> [YS: remove "inline" from declaration of initiator_type] Reviewed-by: York Sun <york.sun@nxp.com> |
#
f6b96ff6 |
|
16-Nov-2016 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Use SVR based timer base address detection Timer controller base address has been changed from LS2080A SoC (and its personalities) to new SoCs like LS2088A, LS1088A. Use SVR based timer base address detection to avoid compile time #ifdef. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
f6a70b3a |
|
16-Nov-2016 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add generic get_svr() in assembly Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
78d57842 |
|
16-Nov-2016 |
Alexander Graf <agraf@csgraf.de> |
armv8: fsl-layerscape: Add support for efi_loader RTS reset When implementing efi loader support, we can expose runtime services for payloads. One such service is CPU reset. This patch implements RTS CPU reset support for layerscape systems. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: York Sun <york.sun@nxp.com> |
#
ef9a5fd8 |
|
13-Sep-2016 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: Fix "cpu status" command The core position is not continuous for some SoCs. For example, valid cores may present at position 0, 1, 4, 5, 8, 9, etc. Some registers (including boot release register) only count existing cores. Current implementation of cpu_mask() complies with the continuous numbering. However, command "cpu status" queries the spin table with actual core position. Add functions to calculate core position from core number, to correctly calculate offsets. Tested on LS2080ARDB and LS1043ARDB. Signed-off-by: York Sun <york.sun@nxp.com> |
#
5d1a7a9d |
|
13-Sep-2016 |
Wenbin Song <wenbin.song@nxp.com> |
armv8/fsl-layerscape: print SoC revsion number The exact SoC revsion number can be recognized from U-Boot log. Signed-off-by: Wenbin Song <wenbin.song@nxp.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
cbe7706a |
|
26-Sep-2016 |
Tom Rini <trini@konsulko.com> |
Merge git://git.denx.de/u-boot-fsl-qoriq trini: Drop local memset() from examples/standalone/mem_to_mem_idma2intr.c Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
1221ce45 |
|
20-Sep-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
treewide: replace #include <asm/errno.h> with <linux/errno.h> Now, arch/${ARCH}/include/asm/errno.h and include/linux/errno.h have the same content. (both just wrap <asm-generic/errno.h>) Replace all include directives for <asm/errno.h> with <linux/errno.h>. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> [trini: Fixup include/clk.] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
b63a9506 |
|
03-Aug-2016 |
York Sun <york.sun@nxp.com> |
armv8: ls2080a: Remove debug server support Debug server feature has been dropped from roadmap. Signed-off-by: York Sun <york.sun@nxp.com> |
#
ed7a3943 |
|
22-Jul-2016 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: mmu: Fix enabling MMU MMU bit in SCTLR needs to be set explicitly after tables are created. It isn't an issue for EL3 becuase this bit is already set by early MMU setup. But for other exception levels this bit was not set. Signed-off-by: York Sun <york.sun@nxp.com> |
#
79119a4d |
|
05-Jul-2016 |
Alison Wang <b18965@freescale.com> |
armv8: fsl-layerscape: Add A72 core detection Add support to detect Cortex-A72 core for printing it out. The Initiator Version of A72 core should be 0x4. Signed-off-by: Alison Wang <alison.wang@nxp.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
032d5bb4 |
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28-Jun-2016 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
ARMv8/Layerscape: switch SMP method accordingly If the PSCI and PPA is ready, skip the fixup for spin-table and waking secondary cores. Otherwise, change SMP method to spin-table, and the device node of PSCI will be removed. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
85cdf38e |
|
28-Jun-2016 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: fsl-layerscape: add i/d-cache enable function to enable_caches This function assume that the d-cache and MMU has been enabled earlier, so it just created MMU table in main memory. But the assumption is not always correct, for example, the early setup is done in EL3, while enable_caches() is called when the PE has turned into another EL. Define the function mmu_setup() for fsl-layerscape to cover the weak one. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
5ad5823d |
|
24-Jun-2016 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Convert to use common MMU framework Drop platform code to create static MMU tables. Use common framework to create MMU tables on the run. Tested on LS2080ARDB with secure and non-secure ram scenarios. Signed-off-by: York Sun <york.sun@nxp.com> |
#
e61a7534 |
|
24-Jun-2016 |
York Sun <york.sun@nxp.com> |
armv8: Move secure_ram variable out of generic global data Secure_ram variable was put in generic global data. But only ARMv8 uses this variable. Move it to ARM specific data structure. Signed-off-by: York Sun <york.sun@nxp.com> |
#
a10a31ec |
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18-Jun-2016 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of git://git.denx.de/u-boot-usb Signed-off-by: Tom Rini <trini@konsulko.com> Conflicts: arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
|
#
6fb522dc |
|
12-Jun-2016 |
Sriram Dash <sriram.dash@nxp.com> |
arm64: fsl-layerscape: add get_svr and IS_SVR_REV helper Adds get_svr and IS_SVR_REV helpers for ARMv8 platforms, similar to PPC and ARMv7. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> |
#
a758177f |
|
07-Jun-2016 |
Yunhui Cui <yunhui.cui@nxp.com> |
armv8/ls2080a: configure PMU's PCTBENR to enable WDT The SP805-WDT module on LS2080A requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. The watchdog clock needs to be enabled first. Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
acb8f5e9 |
|
21-Apr-2016 |
Alison Wang <b18965@freescale.com> |
armv8: fsl-layerscape: Remove unnecessary flushing dcache As the issue about the stack will get corrupted when switching between the early and final mmu tables is fixed by commit 70e21b064, the workaround to flush dcache is unnecessary and should be removed. Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
3c1d218a |
|
04-Apr-2016 |
York Sun <york.sun@nxp.com> |
armv8: LS2080A: Consolidate LS2080A and LS2085A LS2080A is the primary SoC, and LS2085A is a personality with AIOP and DPAA DDR. The RDB and QDS boards support both personality. By detecting the SVR at runtime, a single image per board can support both SoCs. It gives users flexibility to swtich SoC without the need to reprogram the board. Signed-off-by: York Sun <york.sun@nxp.com> CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
c05016ab |
|
21-Mar-2016 |
Alexander Graf <agraf@csgraf.de> |
arm64: Fix layerscape mmu setup With commit 7985cdf we converted all systems except for the Layerscape SoCs to the generic descriptor table based page table setup. On the Layerscape SoCs however, we just provide an empty table stub and do the setup ourselves. To reserve enough memory for the tables, we need to override the default counting mechanism which would end up with an empty table because we have no maps. Fixes: 7985cdf Reported-by: York Sun <york.sun@nxp.com> CC: Alison Wang <alison.wang@nxp.com> CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Alexander Graf <agraf@suse.de> Tested-by: York Sun <york.sun@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
7985cdf7 |
|
03-Mar-2016 |
Alexander Graf <agraf@csgraf.de> |
arm64: Remove non-full-va map code By now the code to only have a single page table level with 64k page size and 42 bit address space is no longer used by any board in tree, so we can safely remove it. To clean up code, move the layerscape mmu code to the new defines, removing redundant field definitions. Signed-off-by: Alexander Graf <agraf@suse.de> |
#
c0492141 |
|
07-Dec-2015 |
York Sun <yorksun@freescale.com> |
armv8: fsl-layerscale: Rewrite reserving memory for MC and debug server MC and debug server are not board-specific. Move reserving memory to SoC file, using the new board_reserve_ram_top function. Reduce debug server memory by 2MB to make room for secure memory. In the system with MC and debug server, the top of u-boot memory is not the end of memory. PRAM is not used for this reservation. Signed-off-by: York Sun <yorksun@freescale.com> |
#
c107c0c0 |
|
04-Dec-2015 |
York Sun <yorksun@freescale.com> |
armv8: fsl-layerscape: Make DDR non secure in MMU tables DDR has been set as secure in MMU tables. Non-secure master such as SDHC DMA cannot access data correctly. Mixing secure and non- secure MMU entries requirs the MMU tables themselves in secure memory. This patch moves MMU tables into a secure DDR area. Early MMU tables are changed to set DDR as non-secure. A new table is added into final MMU tables so secure memory can have 2MB granuality. gd->secure_ram tracks the location of this secure memory. For ARMv8 SoCs, the RAM base is not zero and RAM is divided into several banks. gd->secure_ram needs to be maintained before using. This maintenance is board-specific, depending on the SoC and memory bank of the secure memory falls into. Signed-off-by: York Sun <yorksun@freescale.com> |
#
b4017364 |
|
04-Nov-2015 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
armv8: ls2085a: Add workaround of errata A009635 If the core runs at higher than x3 speed of the platform, there is possiblity about sev instruction to getting missed by other cores. This is because of SoC Run Control block may not able to sample the EVENTI(Sev) signals. Configure Run Control and EPU to periodically send out EVENTI signals to wake up A57 cores. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
d764129d |
|
04-Nov-2015 |
Alison Wang <b18965@freescale.com> |
armv8/layerscape: Update MMU table with execute-never bits For most device addresses excution shouldn't be allowed. Revise the MMU table to enforce execute-never bits. OCRAM, DDR and IFC are allowed for excution. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Alison Wang <alison.wang@freescale.com> Reported-by: Zhichun Hua <zhichun.hua@freescale.com> |
#
44937214 |
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09-Nov-2015 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
armv8: LS2080A: Rename LS2085A to reflect LS2080A LS2080A is a prime personality of Freescale’s LS2085A. It is a non-AIOP personality without support of DP-DDR, L2 switch, 1588, PCIe endpoint etc. So renaming existing LS2085A code base to reflect LS2080A (Prime personality) Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> [York Sun: Dropped #ifdef in cpu.c for cpu_type_list] Reviewed-by: York Sun <yorksun@freescale.com> |
#
e8297341 |
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26-Oct-2015 |
Shaohui Xie <Shaohui.Xie@freescale.com> |
armv8/ls1043a: Add Fman support Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
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8281c58f |
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26-Oct-2015 |
Mingkai Hu <Mingkai.Hu@freescale.com> |
armv8/fsl_lsch2: Add fsl_lsch2 SoC Freescale LayerScape with Chassis Generation 2 is a set of SoCs with ARMv8 cores and 2rd generation of Chassis. Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
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9f3183d2 |
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26-Oct-2015 |
Mingkai Hu <Mingkai.Hu@freescale.com> |
armv8/fsl_lsch3: Change arch to fsl-layerscape There are two LS series processors are built on ARMv8 Layersacpe architecture currently, LS2085A and LS1043A. They are based on ARMv8 core although use different chassis, so create fsl-layerscape to refactor the common code for the LS series processors which also paves the way for adding LS1043A platform. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
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dfb6da55 |
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05-Apr-2022 |
Marek Vasut <marex@denx.de> |
armv8: layerscape: env: Switch to arch_env_get_location() Implement arch_env_get_location() instead of env_get_location(), so that the env_get_location() can be implemented on board level and override the arch_env_get_location() architecture defaults. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Adam Ford <aford173@gmail.com> Cc: Fabio Estevam <festevam@denx.de> Cc: Marek Behún <marek.behun@nic.cz> Cc: Peng Fan <peng.fan@nxp.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefano Babic <sbabic@denx.de> Cc: Tim Harvey <tharvey@gateworks.com> Cc: Tom Rini <trini@konsulko.com> Cc: Tommaso Merciai <tomm.merciai@gmail.com> Cc: Vladimir Oltean <vladimir.oltean@nxp.com> |
#
8976556a |
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24-Mar-2022 |
Gaurav Jain <gaurav.jain@nxp.com> |
Layerscape: Enable Job ring driver model. LS(1021/1012/1028/1043/1046/1088/2088), LX2160, LX2162 platforms are enabled with JR driver model. removed sec_init() call from board files. sec is initialized based on job ring information processed from device tree. Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Michael Walle <michael@walle.cc> |
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f9147d63 |
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25-Feb-2022 |
Tom Rini <trini@konsulko.com> |
Convert CONFIG_CHIP_SELECTS_PER_CTRL to Kconfig This converts the following to Kconfig: CONFIG_CHIP_SELECTS_PER_CTRL Cc: Alison Wang <alison.wang@nxp.com> Cc: Pramod Kumar <pramod.kumar_1@nxp.com> Cc: Priyanka Jain <priyanka.jain@nxp.com> Cc: Rajesh Bhagat <rajesh.bhagat@nxp.com> Cc: Vladimir Oltean <olteanv@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com> |
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2f8a6db5 |
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14-Dec-2021 |
Tom Rini <trini@konsulko.com> |
Finish conversion of CONFIG_SYS_CLK_FREQ to Kconfig In order to finish moving this symbol to Kconfig for all platforms, we need to do a few more things. First, for all platforms that define this to a function, introduce CONFIG_DYNAMIC_SYS_CLK_FREQ, similar to CONFIG_DYNAMIC_DDR_CLK_FREQ and populate clock_legacy.h. This entails also switching all users from CONFIG_SYS_CLK_FREQ to get_board_sys_clk() and updating a few preprocessor tests. With that done, all platforms that define a value here can be converted to Kconfig, and a fall-back of zero is sufficiently safe to use (and what is used today in cases where code may or may not have this available). Make sure that code which calls this function includes <clock_legacy.h> to get the prototype. Signed-off-by: Tom Rini <trini@konsulko.com> |
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77b11f76 |
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18-Sep-2021 |
Vladimir Oltean <vladimir.oltean@nxp.com> |
net: replace the "xfi" phy-mode with "10gbase-r" As part of the effort of making U-Boot work with the same device tree as Linux, there is an issue with the "xfi" phy-mode. To be precise, in Linux there was a discussion (for those who have time to read: https://lore.kernel.org/netdev/1576768881-24971-2-git-send-email-madalin.bucur@oss.nxp.com/) which led to a patch: https://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next.git/commit/?id=c114574ebfdf42f826776f717c8056a00fa94881 TL;DR: "xfi" was standardized in Linux as "10gbase-r". This patch changes the relevant occurrences in U-Boot to use "10gbase-r" instead of "xfi" wherever applicable. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> |
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84c2e044 |
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20-Apr-2021 |
Jiafei Pan <Jiafei.Pan@nxp.com> |
armv8: layerscape: add PSCI support for cpu release For cpu release command, check whether PSCI is supported firstly, if supported, use PSCI to kick off secondary cores, otherwise still use spin table. Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com> [Fixed checkpatch alignment CHECKs] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
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35b65dd8 |
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15-Dec-2020 |
Harald Seiler <hws@denx.de> |
reset: Remove addr parameter from reset_cpu() Historically, the reset_cpu() function had an `addr` parameter which was meant to pass in an address of the reset vector location, where the CPU should reset to. This feature is no longer used anywhere in U-Boot as all reset_cpu() implementations now ignore the passed value. Generic code has been added which always calls reset_cpu() with `0` which means this feature can no longer be used easily anyway. Over time, many implementations seem to have "misunderstood" the existence of this parameter as a way to customize/parameterize the reset (e.g. COLD vs WARM resets). As this is not properly supported, the code will almost always not do what it is intended to (because all call-sites just call reset_cpu() with 0). To avoid confusion and to clean up the codebase from unused left-overs of the past, remove the `addr` parameter entirely. Code which intends to support different kinds of resets should be rewritten as a sysreset driver instead. This transformation was done with the following coccinelle patch: @@ expression argvalue; @@ - reset_cpu(argvalue) + reset_cpu() @@ identifier argname; type argtype; @@ - reset_cpu(argtype argname) + reset_cpu(void) { ... } Signed-off-by: Harald Seiler <hws@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> |
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401d1c4f |
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30-Oct-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop asm/global_data.h from common header Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com> |
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3a187cff |
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29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
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c760095a |
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23-Oct-2020 |
Razvan Ionut Cirjan <razvanionut.cirjan@nxp.com> |
net: lx2160a.c: Update to set ECx_PMUX precedence As per hardware documentation, ECx_PMUX has precedence over SerDes protocol. For LX2160/LX2162 if DPMACs 17 and 18 are enabled as SGMII through SerDes protocol but ECx_PMUX configured them as RGMII, then the ports will be configured as RGMII and not SGMII. Signed-off-by: Razvan Ionut Cirjan <razvanionut.cirjan@nxp.com> [Rebased] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
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d31f3a1b |
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09-Sep-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2160a: fix reset sequence Make sure that SW_RST_REQ and RST_REQ_MSK are cleared before triggering hardware reset request. Signed-off-by: Thirupathaiah Annapureddy <thiruan@linux.microsoft.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
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b75d8dc5 |
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26-Jun-2020 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
treewide: convert bd_t to struct bd_info by coccinelle The Linux coding style guide (Documentation/process/coding-style.rst) clearly says: It's a **mistake** to use typedef for structures and pointers. Besides, using typedef for structures is annoying when you try to make headers self-contained. Let's say you have the following function declaration in a header: void foo(bd_t *bd); This is not self-contained since bd_t is not defined. To tell the compiler what 'bd_t' is, you need to include <asm/u-boot.h> #include <asm/u-boot.h> void foo(bd_t *bd); Then, the include direcective pulls in more bloat needlessly. If you use 'struct bd_info' instead, it is enough to put a forward declaration as follows: struct bd_info; void foo(struct bd_info *bd); Right, typedef'ing bd_t is a mistake. I used coccinelle to generate this commit. The semantic patch that makes this change is as follows: <smpl> @@ typedef bd_t; @@ -bd_t +struct bd_info </smpl> Signed-off-by: Masahiro Yamada <masahiroy@kernel.org> |
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25a5818f |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop asm/ptrace.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
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f7ae49fc |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
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90526e9f |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop net.h from common header Move this header out of the common header. Network support is used in quite a few places but it still does not warrant blanket inclusion. Note that this net.h header itself has quite a lot in it. It could be split into the driver-mode support, functions, structures, checksumming, etc. Signed-off-by: Simon Glass <sjg@chromium.org> |
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714497e3 |
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16-May-2020 |
Michael Walle <michael@walle.cc> |
efi_loader: round the memory area in efi_add_memory_map() Virtually all callers of this function do the rounding on their own. Some do it right, some don't. Instead of doing this in each caller, do the rounding in efi_add_memory_map(). Change the size parameter to bytes instead of pages and remove aligning and size calculation in all callers. There is no more need to make the original efi_add_memory_map() (which takes pages as size) available outside the module. Thus rename it to efi_add_memory_map_pg() and make it static to prevent further misuse outside the module. Signed-off-by: Michael Walle <michael@walle.cc> Add missing comma in sunxi_display.c. Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de> |
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6eb32a03 |
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23-Apr-2020 |
Madalin Bucur <madalin.bucur@oss.nxp.com> |
driver: net: fm: add DM ETH support Probe the FMan MACs based on the device tree while retaining the legacy code/functionality. One notable change introduced here is that, for DM_ETH, the name of the interfaces is corrected to the fmX-macY format, that avoids the referral to the MAC block names which were incorrect for FMan v3 devices (i.e. DTSEC, TGEC) and had weird formatting (i.e. FM1@DTSEC6, FM1@TGEC1). The legacy code is left unchanged in this respect. Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
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6ebd4883 |
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27-Apr-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
fsl-layerscape: Add RESV_RAM check in resv_ram addr The initialization of gd->arch.resv_ram pointer should depend on if the RESV_RAM config is enabled. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Wasim Khan <wasim.khan@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
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0d9d557d |
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10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
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db41d65a |
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28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move hang() to the same header as panic() At present panic() is in the vsprintf.h header file. That does not seem like an obvious choice for hang(), even though it relates to panic(). So let's put hang() in its own header. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Migrate a few more files] Signed-off-by: Tom Rini <trini@konsulko.com> |
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9b4a205f |
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28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move RAM-sizing functions to init.h These functions relate to memory init so move them into the init header. Signed-off-by: Simon Glass <sjg@chromium.org> |
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3499dd03 |
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27-Nov-2019 |
Alex Marginean <alexandru.marginean@nxp.com> |
ls1028a: Configure stream IDs for integrated PCI and fix up Linux DT Hardware comes out of reset with implicit values, but these are outside the accepted range for Layerscape gen 3 chassis spec used on LS1028A. Allocate different IDs and fix up Linux DT to use them. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
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b5981474 |
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14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some CPU functions out of common.h These functions belong in cpu_func.h since they do not use driver model. Move them over. Don't bother adding comments since these functions should be deleted. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
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68a6aa85 |
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14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move mii_init() function out of common.h This function belongs in mii.h so move it over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
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2189d5f1 |
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14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
Move strtomhz() to vsprintf.h At present this function sits in its own file but it does not really justify it. There are similar string functions in vsprintf.h, so move it there. Also add the missing function comment. Use the vsprintf.h include file explicitly where needed. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
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812ff53c |
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30-Oct-2019 |
Pankaj Bansal <pankaj.bansal@nxp.com> |
fsl-layerscape: fix warning if no hwconfig is defined While getting the 'subarg' of 'hwconfig' env variable in config_core_prefetch(), if no hwconfig variable is defined, below warning is received: WARNING: Calling __hwconfig without a buffer and before environment is ready Fix this by checking 'hwconfig' env variable. If not found return without further processing. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Tested-by: Michael Walle <michael@walle.cc> |
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28f9393b |
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17-Oct-2019 |
Mathew McBride <matt@traverse.com.au> |
fsl-layerscape: do not use layerscape EFI reset if PSCI used If the secure world reset handlers are used (via CONFIG_PSCI_RESET), then do not use the layerscape-specific implementation. Signed-off-by: Mathew McBride <matt@traverse.com.au> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
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6ed69523 |
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18-Sep-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add more personalities support Add LS1027A, LS1018A and LS1017A personalities support to LS1028A SoC family. LS1028A is the prime personality of LS1028A SoC family. LS1027A is a lower funtionality version of QorIQ LS1028A which does not support the multimedia subsystems, such as LCD controller, GPU, and eDP PHY. The QorIQ LS1018A and LS1017A SoCs are single 64-bit Arm A72 core, low power versions of the QorIQ LS1028A and LS1027A SoCs respectively. Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
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0490cab5 |
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08-Aug-2019 |
Thomas Schaefer <thomas.schaefer@kontron.com> |
armv8: ls1028a: configure PMU's PCTBENR to enable WDT The SP805-WDT module on LS1028A requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. The watchdog clock needs to be enabled first. Signed-off-by: Thomas Schaefer <thomas.schaefer@kontron.com> Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
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f3998fdc |
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02-Aug-2019 |
Simon Glass <sjg@chromium.org> |
env: Rename environment.h to env_internal.h This file contains lots of internal details about the environment. Most code can include env.h instead, calling the functions there as needed. Rename this file and add a comment at the top to indicate its internal nature. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> [trini: Fixup apalis-tk1.c] Signed-off-by: Tom Rini <trini@konsulko.com> |
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3a7d5571 |
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01-Aug-2019 |
Simon Glass <sjg@chromium.org> |
env: Move env_get_f() to env.h Move this function over to the new header file. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
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d9532e80 |
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23-Apr-2019 |
Udit Agarwal <udit.agarwal@nxp.com> |
armv8: fsl-layerscape: Set env_loc to ENVL_NOWHERE with CONFIG_ENV_IS_NOWHERE. ENVL_NOWHERE is dependent on CONFIG_ENV_IS_NOWHERE and not on CONFIG_CHAIN_OF_TRUST so return ENVL_NOWHERE when CONFIG_ENV_IS_NOWHERE is enabled Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
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d4ad111d |
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10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
059d9422 |
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08-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: lx2160a: add MMU table entries for PCIe The lx2160a have up to 6 PCIe controllers and have different address and size of PCIe region. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
8348e798 |
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08-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: layerscape: use PCIe address macro for precompile PCIe MMU entry Change to use PCIe address macro to determine if precompile the PCIe MMU table entry. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
10015025 |
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03-May-2019 |
Trevor Woerner <trevor@toganlabs.com> |
CONFIG_SPL_SYS_[DI]CACHE_OFF: add While converting CONFIG_SYS_[DI]CACHE_OFF to Kconfig, there are instances where these configuration items are conditional on SPL. This commit adds SPL variants of these configuration items, uses CONFIG_IS_ENABLED(), and updates the configurations as required. Acked-by: Alexey Brodkin <abrodkin@synopsys.com> Signed-off-by: Trevor Woerner <trevor@toganlabs.com> [trini: Make the default depend on the setting for full U-Boot, update more zynq hardware] Signed-off-by: Tom Rini <trini@konsulko.com> |
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2e53759d |
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29-Oct-2018 |
Pankaj Bansal <pankaj.bansal@nxp.com> |
armv8: fsl-layerscape: reorder rgmii dpmacs' enablement some dpmacs in armv8a based freescale layerscape SOCs can be configured via both serdes(sgmii, xfi, xlaui etc) bits and via EC*_PMUX(rgmii) bits in RCW. e.g. dpmac 17 and 18 in LX2160A can be configured as SGMII from serdes bits and as RGMII via EC1_PMUX/EC2_PMUX bits Now if a dpmac is enabled by serdes bits then it takes precedence over EC*_PMUX bits. i.e. in LX2160A if we select serdes protocol that configures dpmac17 as SGMII and set the EC1_PMUX as RGMII, then the dpmac is SGMII and not RGMII. Therefore, move the fsl_rgmii_init after fsl_serdes_init. in fsl_rgmii_init function of SOC, we will check if the dpmac is enabled or not? if it is (fsl_serdes_init has already enabled the dpmac), then don't enable it. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
ec88ff80 |
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19-Dec-2018 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1043a: add SVR definitions for 23x23 package silicon LS1043A/LS1023A 23x23 package silicon has different SVR:VAR_PER. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
d23da2ae |
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26-Dec-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: fixes for TFABOOT framework Fixes for TFABOOT framework - update eMMC bootsrc to SD_MMC - Increase buffer size for mcinitcmd from 256 to 512 - Fix mcinitcmd and bootcmd for Secure Boot Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
4909b89e |
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29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
d6fdec21 |
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29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8:fsl-layerscape: Add support for Chassis 3.2 NXP layerscape architecture Chassis 3.2 builds upon chassis3 architecture with changes like DDR Memory map change, removal of IFC and support of upto 8 I2C controller. Patch add README.lsch3_2 and the above changes under macro CONFIG_NXP_LSCH3_2. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
56db948b |
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05-Nov-2018 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: Update parsing boot source Workaround of erratum A010539 clears the RCW source field in PORSR1 register, causing failure of detecting boot source using this method. Use SMC call if U-Boot runs at EL2. If SMC is not implemented or running at EL3, continue to read PORSR1 and presume QSPI as boot source if erratum workaround A010539 is enabled and RCW source is cleared. Signed-off-by: York Sun <york.sun@nxp.com> |
#
681d489e |
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05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: layerscape: add SMC calls for DDR size and bank info Adds SMC calls for getting DDR size and bank info for TFABOOT. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
2141d250 |
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05-Nov-2018 |
Pankit Garg <pankit.garg@nxp.com> |
armv8: fsl-layerscape: bootcmd identification for TFABOOT Adds bootcmd identificaton on basis on boot source, valid in TFABOOT configuration. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> [YS: remove unnecessary braces] Reviewed-by: York Sun <york.sun@nxp.com> |
#
4c417384 |
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05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com> |
#
535d76a1 |
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05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: layerscape: Add TFABOOT support Adds TFABOOT support config option and add generic code to enable execution from DDR. Signed-off-by: York Sun <york.sun@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> |
#
e3506480 |
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05-Nov-2018 |
Pankit Garg <pankit.garg@nxp.com> |
armv8: fsl-layerscape: change tlb base from OCRAM to DDR in EL < 3 Change tlb base address from OCRAM to DDR when exception level is less than 3. Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
d171c707 |
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05-Nov-2018 |
York Sun <york.sun@nxp.com> |
move data structure out of cpu.h Move static definitions to cpu.c file, as it doesn't allow the cpu.h file to be included in multiple c files. Signed-off-by: York Sun <york.sun@nxp.com> |
#
9b5e6396 |
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30-Aug-2018 |
Stephen Warren <swarren@nvidia.com> |
efi_loader: simplify ifdefs Use CONFIG_IS_ENABLED(EFI_LOADER) to avoid explicitly checking CONFIG_SPL too. This simplifies the conditional. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Alexander Graf <agraf@suse.de> |
#
9cce5663 |
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16-Jul-2018 |
Joe Hershberger <joe.hershberger@ni.com> |
arm: Prevent redefinition error in fsl-layerscape The include/phy.h will start including dm.h, which pulls in linux/compat.h after the attempted redefinition in arch/arm/include/asm/armv8/mmu.h, so move this include to allow redefinition. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> |
#
83d290c5 |
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06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
482fc90c |
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06-Feb-2018 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
efi_loader: add missing EFI_RESET_PLATFORM_SPECIFIC EFI_RESET_PLATFORM_SPECIFIC is one of the values that can be used for the EFI service ResetSystem. The missing definition is added. The value has to handled in efi_reset_system(). Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Alexander Graf <agraf@suse.de> |
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22c793e6 |
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03-Mar-2018 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
efi_loader: exit status for efi_reset_system_init efi_reset_system_init provides the architecture or board specific initialization of the EFI subsystem. Errors should be caught and signalled by a return code. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Alexander Graf <agraf@suse.de> |
#
958b2ed5 |
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09-Jan-2018 |
Zhang Ying-22455 <ying.zhang22455@nxp.com> |
armv8/ls1088a: configure PMU's PCTBENR to enable WDT The SP805-WDT module on LS1088A requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. The watchdog clock needs to be enabled first. Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
44262327 |
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15-Dec-2017 |
Ahmed Mansour <ahmed.mansour@nxp.com> |
drivers/misc: Share qbman init between archs This patch adds changes necessary to move functionality present in PowerPC folders with ARM architectures that have DPAA1 QBMan hardware - Create new board/freescale/common/fsl_portals.c to house shared device tree fixups for DPAA1 devices with ARM and PowerPC cores - Add new header file to top includes directory to allow files in both architectures to grab the function prototypes - Port inhibit_portals() from PowerPC to ARM. This function is used in setup to disable interrupts on all QMan and BMan portals. It is needed because the interrupts are enabled by default for all portals including unused/uninitialised portals. When the kernel attempts to go to deep sleep the unused portals prevent it from doing so Signed-off-by: Ahmed Mansour <ahmed.mansour@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
a8f33034 |
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03-Dec-2017 |
Wenbin song <wenbin.song@nxp.com> |
armv8: ls1043a/ls2080a: check SoC by device ID Check LS1043A/LS2080a by device ID without using personality ID to determine revision number. This check applies to all various personalities of the same SoC family. Signed-off-by: Wenbin Song <wenbin.song@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
2db53cfe |
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09-Nov-2017 |
Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
armv8: fsl-layerscape: Add support of disabling core prefetch Instruction prefetch feature is by default enabled during core release. This patch add support of disabling instruction prefetch by setting core mask in PPA. Here each core mask bit represents a core and prefetch is disabled at the time of core release. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
7eb40f0f |
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28-Sep-2017 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: Avoid running dram_init_banksize again gd->ram_size is reduced in this function to reserve secure memory. Avoid running this function again to further reduce memory size. This fixes issue for SPL boot with PPA image loaded in which case secure memory is incorrectly allocated due to repeated calling. Signed-off-by: York Sun <york.sun@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
710d0cd7 |
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03-Oct-2017 |
Sumit Garg <sumit.garg@nxp.com> |
armv8: fsl-layerscape: Allocate Secure memory from first ddr region This change is required due to trusted OS (OP-TEE) not being position independent code, it requires compile time fixed base address. To take care of this it is assumed that all layerscape armv8 platforms has minimum 2G ddr in first region. So we can have fixed address space (66 MB -> (2MB for PPA + 64MB for trusted OS)) allocated from top of first 2G ddr region and compile trusted OS with this fixed base address. But one exception here is ls1012 where we have only 1G (rdb) or 512M (frdm) ddr memory. For those we can have different fixed compile time base addresses for trusted OS. Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
e9303a41 |
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07-Sep-2017 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: Fix MC reserved memory calculation In case high region memory doesn't have enough space for Management Complex (MC), the return value should indicate a failure so the caller can handle it accordingly. Signed-off-by: York Sun <york.sun@nxp.com> Reported-by: Ebony Zhu <ebony.zhu@nxp.com> |
#
17d066fc |
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31-Aug-2017 |
Ashish Kumar <Ashish.Kumar@nxp.com> |
armv8: fsl-layerscape: Support to add RGMII for ls1088aqds This patch adds support for RGMII protocol NXP's LDPAA2 support RGMII protocol. LS1088A is the first Soc supporting both RGMII and SGMII. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Amrita Kumari <amrita.kumari@nxp.com> Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
63b2316c |
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10-Aug-2017 |
Ashish Kumar <Ashish.Kumar@nxp.com> |
fsl-layerscape: Consolidate registers space defination for CCI-400 bus CoreLink Cache Coherent Interconnect (CCI) provides full cache coherency between two clusters of multi-core CPUs and I/O coherency for devices and I/O masters. This patch add new config option SYS_FSL_HAS_CCI400 and moves existing register space definaton of CCI-400 bus to fsl_immap to be shared. CONFIG_SYS_CCI400_ADDR is replaced with SYS_CCI400_OFFSET in Kconfig. Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> [YS: revised commit message, squashed patches for armv8 and armv7] Reviewed-by: York Sun <york.sun@nxp.com> |
#
6e2941d7 |
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17-May-2017 |
Simon Glass <sjg@chromium.org> |
common: freescale: Move arch-specific declarations The declarations should not be in common.h. Move them to the arch-specific headers. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Fixup thinko defined(FSL_LSCH3) -> defined(CONFIG_FSL_LSCH3)] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
399e2bb6 |
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15-May-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Make U-Boot EL2 safe When U-Boot boots from EL2, skip some lowlevel init code requiring EL3, including CCI-400/CCN-504, trust zone, GIC, etc. These initialization tasks are carried out before U-Boot runs. This applies to the RAM version image used for SPL boot if PPA is loaded first. Signed-off-by: York Sun <york.sun@nxp.com> |
#
1f55a938 |
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05-May-2017 |
Santan Kumar <santan.kumar@nxp.com> |
armv8: ls2080aqds: Add support for SD boot Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
e809e747 |
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27-Apr-2017 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: fsl-layerscape: Add NXP LS2081A, LS2041A SoC support The QorIQ LS2081A SoC has eight 64-bit ARM v8 Cortex A72 cores and is built on layerscape architecture. It is 40-pin derivative of LS2084A (non-AIOP personality of LS2088A). So feature-wise it is same as LS2084A. LS2041A is a 4-core personality of LS2081A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
026f30ec |
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18-Apr-2017 |
Yuantian Tang <andy.tang@nxp.com> |
arm: psci: make psci usable on single core socs PSCI can be used on both multiple and single core socs. Current implementation only allows PSCI to work on multiple core socs. This patch removes this restriction so that PSCI can work on single core socs as well. Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
4a3ab193 |
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27-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: ls2080a: Drop macro CONFIG_LS2080A Use CONFIG_ARCH_LS2080A instead. Signed-off-by: York Sun <york.sun@nxp.com> |
#
3eace37e |
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06-Apr-2017 |
Simon Glass <sjg@chromium.org> |
arm: freescale: Rename initdram() to fsl_initdram() This function name shadows a global name but is in fact different. This is very confusing. Rename it to help with the following refactoring. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
76b00aca |
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31-Mar-2017 |
Simon Glass <sjg@chromium.org> |
board_f: Drop setup_dram_config() wrapper By making dram_init_banksize() return an error code we can drop the wrapper. Adjust this and clean up all implementations. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
088454cd |
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31-Mar-2017 |
Simon Glass <sjg@chromium.org> |
board_f: Drop return value from initdram() At present we cannot use this function as an init sequence call without a wrapper, since it returns the RAM size. Adjust it to set the RAM size in global_data instead, and return 0 on success. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
52c41180 |
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31-Mar-2017 |
Simon Glass <sjg@chromium.org> |
board_f: Drop board_type parameter from initdram() It looks like only cm5200 and tqm8xx use this feature, so we don't really need it in generic code. Drop it and have the users access gd->board_type directly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
3d8553f0 |
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02-Mar-2017 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
pci: layerscape: add LS2088A series SoC pcie support The LS2088A series SoCs has different physical memory map address and CCSR registers address against LS2080A series SoCs. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
eea1cb77 |
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13-Feb-2017 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8/fsl-layerscape: Update erratum A009635 implementation Erratum A009635 is valid only for LS2080A SoC and its personality. Add SoC svr check. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
4961eafc |
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06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Update early MMU for DDR after initialization In early MMU table, DDR has to be mapped as device memory to avoid speculative access. After DDR is initialized, it needs to be updated to normal memory to allow code execution. To simplify the code, dram_init() is moved into a common file as a weak function. Signed-off-by: York Sun <york.sun@nxp.com> |
#
a045a0c3 |
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06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Fix the sequence of changing MMU table This patch follows the break-before-make process when making changes to MMU table. MMU is disabled before changing TTBR to avoid any potential race condition. Signed-off-by: York Sun <york.sun@nxp.com> |
#
24f55496 |
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06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Update MMU mapping with actual DDR size Update mapping with actual DDR size. Non-existing memory should not be mapped as "normal" memory to avoid speculative access. Signed-off-by: York Sun <york.sun@nxp.com> |
#
36cc0de0 |
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06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Rewrite memory reservation For ARMv8 Layerscape SoCs, secure memory and MC memorey are reserved at the end of DDR. DDR is spit into two or three banks. This patch reverts commit aabd7ddb and simplifies the calculation of reserved memory, and moves the code into common SoC file. Secure memory is carved out first. DDR bank size is reduced. Reserved memory is then allocated on the top of available memory. U-Boot still has access to reserved memory as data transferring is needed. Device tree is fixed with reduced memory size to hide the reserved memory from OS. The same region is reserved for efi_loader. Signed-off-by: York Sun <york.sun@nxp.com> |
#
daa92644 |
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16-Jan-2017 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
ARMv8/sec_firmware: relocated and renamed the config FSL_PPA_ARMV8_PSCI Moved the config FSL_PPA_ARMV8_PSCI from fsl-layerscape's Kconfig to Kconfig under armv8 and renamed it to SEC_FIRMWARE_ARMV8_PSCI. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
904110c7 |
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10-Jan-2017 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8/fsl-lsch2: refactor the clock system initialization Up to now, there are 3 kind of SoCs under Layerscape Chassis 2, like LS1043A, LS1046A and LS1012A. But the clocks tree has a lot of differences, for instance, the IP modules have different dividers to derive its clock from Platform PLL. And the core cluster PLL and platform PLL maybe have different reference clocks, such as LS1012A. Another problem is which clock/PLL should be described by sys_info->freq_systembus, it is confused in Layerscape Chissis 2. This patch is to bind the sys_info->freq_systembus to the Platform PLL, and handle the different divider of IP modules separately between different SoCs, and separate reference clocks of core cluster PLL and platform PLL. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
2d16a1a6 |
|
07-Dec-2016 |
macro.wave.z@gmail.com <macro.wave.z@gmail.com> |
ARMv8: LS1043A: change macro CONFIG_ARMV8_PSCI definition NXP/Freescale uses macro CONFIG_ARMV8_PSCI to enable their private PSCI implementation in PPA firmware, but this macro naming too generic, so this patch replaces it with a specic one CONFIG_FSL_PPA_ARMV8_PSCI. And this macro CONFIG_ARMV8_PSCI will be used for a generic PSCI for ARMv8 which will be added in following patchs. Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
02fb2761 |
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20-Nov-2016 |
Shengzhou Liu <Shengzhou.Liu@nxp.com> |
fsl/ddr: Add erratum_a009942_check_cpo and clean related erratum - add additional function erratum_a009942_check_cpo to check if the board needs tuning CPO calibration for optimal setting. - move ERRATUM_A009942(with revision to check cpo_sample option) from fsl_ddr_gen4.c to ctrl_regs.c for reuse on all DDR4/DDR3 parts. - move ERRATUM_A008378 from fsl_ddr_gen4.c to ctrl_regs.c - remove obsolete ERRATUM_A004934 which is replaced with ERRATUM_A009942. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> [YS: Replaced CONFIG_QEMU_E500 with CONFIG_ARCH_QEMU_E500] Reviewed-by: York Sun <york.sun@nxp.com> |
#
e87c673c |
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16-Nov-2016 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8/fsl-lsch3: Update code to release secondary cores NXP ARMv8 SoC LS2080A release all secondary cores in one-go. But other new SoCs like LS2088A, LS1088A release secondary cores one by one. Update code to release secondary cores based on SoC SVR Add code to release cores one by one for non LS2080A SoCs Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> [YS: remove "inline" from declaration of initiator_type] Reviewed-by: York Sun <york.sun@nxp.com> |
#
f6b96ff6 |
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16-Nov-2016 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Use SVR based timer base address detection Timer controller base address has been changed from LS2080A SoC (and its personalities) to new SoCs like LS2088A, LS1088A. Use SVR based timer base address detection to avoid compile time #ifdef. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
f6a70b3a |
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16-Nov-2016 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add generic get_svr() in assembly Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
78d57842 |
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16-Nov-2016 |
Alexander Graf <agraf@csgraf.de> |
armv8: fsl-layerscape: Add support for efi_loader RTS reset When implementing efi loader support, we can expose runtime services for payloads. One such service is CPU reset. This patch implements RTS CPU reset support for layerscape systems. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: York Sun <york.sun@nxp.com> |
#
ef9a5fd8 |
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13-Sep-2016 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: Fix "cpu status" command The core position is not continuous for some SoCs. For example, valid cores may present at position 0, 1, 4, 5, 8, 9, etc. Some registers (including boot release register) only count existing cores. Current implementation of cpu_mask() complies with the continuous numbering. However, command "cpu status" queries the spin table with actual core position. Add functions to calculate core position from core number, to correctly calculate offsets. Tested on LS2080ARDB and LS1043ARDB. Signed-off-by: York Sun <york.sun@nxp.com> |
#
5d1a7a9d |
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13-Sep-2016 |
Wenbin Song <wenbin.song@nxp.com> |
armv8/fsl-layerscape: print SoC revsion number The exact SoC revsion number can be recognized from U-Boot log. Signed-off-by: Wenbin Song <wenbin.song@nxp.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
cbe7706a |
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26-Sep-2016 |
Tom Rini <trini@konsulko.com> |
Merge git://git.denx.de/u-boot-fsl-qoriq trini: Drop local memset() from examples/standalone/mem_to_mem_idma2intr.c Signed-off-by: Tom Rini <trini@konsulko.com>
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#
1221ce45 |
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20-Sep-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
treewide: replace #include <asm/errno.h> with <linux/errno.h> Now, arch/${ARCH}/include/asm/errno.h and include/linux/errno.h have the same content. (both just wrap <asm-generic/errno.h>) Replace all include directives for <asm/errno.h> with <linux/errno.h>. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> [trini: Fixup include/clk.] Signed-off-by: Tom Rini <trini@konsulko.com> |
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b63a9506 |
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03-Aug-2016 |
York Sun <york.sun@nxp.com> |
armv8: ls2080a: Remove debug server support Debug server feature has been dropped from roadmap. Signed-off-by: York Sun <york.sun@nxp.com> |
#
ed7a3943 |
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22-Jul-2016 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: mmu: Fix enabling MMU MMU bit in SCTLR needs to be set explicitly after tables are created. It isn't an issue for EL3 becuase this bit is already set by early MMU setup. But for other exception levels this bit was not set. Signed-off-by: York Sun <york.sun@nxp.com> |
#
79119a4d |
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05-Jul-2016 |
Alison Wang <b18965@freescale.com> |
armv8: fsl-layerscape: Add A72 core detection Add support to detect Cortex-A72 core for printing it out. The Initiator Version of A72 core should be 0x4. Signed-off-by: Alison Wang <alison.wang@nxp.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
032d5bb4 |
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28-Jun-2016 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
ARMv8/Layerscape: switch SMP method accordingly If the PSCI and PPA is ready, skip the fixup for spin-table and waking secondary cores. Otherwise, change SMP method to spin-table, and the device node of PSCI will be removed. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
85cdf38e |
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28-Jun-2016 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: fsl-layerscape: add i/d-cache enable function to enable_caches This function assume that the d-cache and MMU has been enabled earlier, so it just created MMU table in main memory. But the assumption is not always correct, for example, the early setup is done in EL3, while enable_caches() is called when the PE has turned into another EL. Define the function mmu_setup() for fsl-layerscape to cover the weak one. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
5ad5823d |
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24-Jun-2016 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Convert to use common MMU framework Drop platform code to create static MMU tables. Use common framework to create MMU tables on the run. Tested on LS2080ARDB with secure and non-secure ram scenarios. Signed-off-by: York Sun <york.sun@nxp.com> |
#
e61a7534 |
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24-Jun-2016 |
York Sun <york.sun@nxp.com> |
armv8: Move secure_ram variable out of generic global data Secure_ram variable was put in generic global data. But only ARMv8 uses this variable. Move it to ARM specific data structure. Signed-off-by: York Sun <york.sun@nxp.com> |
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a10a31ec |
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18-Jun-2016 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of git://git.denx.de/u-boot-usb Signed-off-by: Tom Rini <trini@konsulko.com> Conflicts: arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
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#
6fb522dc |
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12-Jun-2016 |
Sriram Dash <sriram.dash@nxp.com> |
arm64: fsl-layerscape: add get_svr and IS_SVR_REV helper Adds get_svr and IS_SVR_REV helpers for ARMv8 platforms, similar to PPC and ARMv7. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> |
#
a758177f |
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07-Jun-2016 |
Yunhui Cui <yunhui.cui@nxp.com> |
armv8/ls2080a: configure PMU's PCTBENR to enable WDT The SP805-WDT module on LS2080A requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. The watchdog clock needs to be enabled first. Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
acb8f5e9 |
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21-Apr-2016 |
Alison Wang <b18965@freescale.com> |
armv8: fsl-layerscape: Remove unnecessary flushing dcache As the issue about the stack will get corrupted when switching between the early and final mmu tables is fixed by commit 70e21b064, the workaround to flush dcache is unnecessary and should be removed. Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
3c1d218a |
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04-Apr-2016 |
York Sun <york.sun@nxp.com> |
armv8: LS2080A: Consolidate LS2080A and LS2085A LS2080A is the primary SoC, and LS2085A is a personality with AIOP and DPAA DDR. The RDB and QDS boards support both personality. By detecting the SVR at runtime, a single image per board can support both SoCs. It gives users flexibility to swtich SoC without the need to reprogram the board. Signed-off-by: York Sun <york.sun@nxp.com> CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
c05016ab |
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21-Mar-2016 |
Alexander Graf <agraf@csgraf.de> |
arm64: Fix layerscape mmu setup With commit 7985cdf we converted all systems except for the Layerscape SoCs to the generic descriptor table based page table setup. On the Layerscape SoCs however, we just provide an empty table stub and do the setup ourselves. To reserve enough memory for the tables, we need to override the default counting mechanism which would end up with an empty table because we have no maps. Fixes: 7985cdf Reported-by: York Sun <york.sun@nxp.com> CC: Alison Wang <alison.wang@nxp.com> CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Alexander Graf <agraf@suse.de> Tested-by: York Sun <york.sun@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
7985cdf7 |
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03-Mar-2016 |
Alexander Graf <agraf@csgraf.de> |
arm64: Remove non-full-va map code By now the code to only have a single page table level with 64k page size and 42 bit address space is no longer used by any board in tree, so we can safely remove it. To clean up code, move the layerscape mmu code to the new defines, removing redundant field definitions. Signed-off-by: Alexander Graf <agraf@suse.de> |
#
c0492141 |
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07-Dec-2015 |
York Sun <yorksun@freescale.com> |
armv8: fsl-layerscale: Rewrite reserving memory for MC and debug server MC and debug server are not board-specific. Move reserving memory to SoC file, using the new board_reserve_ram_top function. Reduce debug server memory by 2MB to make room for secure memory. In the system with MC and debug server, the top of u-boot memory is not the end of memory. PRAM is not used for this reservation. Signed-off-by: York Sun <yorksun@freescale.com> |
#
c107c0c0 |
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04-Dec-2015 |
York Sun <yorksun@freescale.com> |
armv8: fsl-layerscape: Make DDR non secure in MMU tables DDR has been set as secure in MMU tables. Non-secure master such as SDHC DMA cannot access data correctly. Mixing secure and non- secure MMU entries requirs the MMU tables themselves in secure memory. This patch moves MMU tables into a secure DDR area. Early MMU tables are changed to set DDR as non-secure. A new table is added into final MMU tables so secure memory can have 2MB granuality. gd->secure_ram tracks the location of this secure memory. For ARMv8 SoCs, the RAM base is not zero and RAM is divided into several banks. gd->secure_ram needs to be maintained before using. This maintenance is board-specific, depending on the SoC and memory bank of the secure memory falls into. Signed-off-by: York Sun <yorksun@freescale.com> |
#
b4017364 |
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04-Nov-2015 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
armv8: ls2085a: Add workaround of errata A009635 If the core runs at higher than x3 speed of the platform, there is possiblity about sev instruction to getting missed by other cores. This is because of SoC Run Control block may not able to sample the EVENTI(Sev) signals. Configure Run Control and EPU to periodically send out EVENTI signals to wake up A57 cores. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
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d764129d |
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04-Nov-2015 |
Alison Wang <b18965@freescale.com> |
armv8/layerscape: Update MMU table with execute-never bits For most device addresses excution shouldn't be allowed. Revise the MMU table to enforce execute-never bits. OCRAM, DDR and IFC are allowed for excution. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Alison Wang <alison.wang@freescale.com> Reported-by: Zhichun Hua <zhichun.hua@freescale.com> |
#
44937214 |
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09-Nov-2015 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
armv8: LS2080A: Rename LS2085A to reflect LS2080A LS2080A is a prime personality of Freescale’s LS2085A. It is a non-AIOP personality without support of DP-DDR, L2 switch, 1588, PCIe endpoint etc. So renaming existing LS2085A code base to reflect LS2080A (Prime personality) Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> [York Sun: Dropped #ifdef in cpu.c for cpu_type_list] Reviewed-by: York Sun <yorksun@freescale.com> |
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e8297341 |
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26-Oct-2015 |
Shaohui Xie <Shaohui.Xie@freescale.com> |
armv8/ls1043a: Add Fman support Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
8281c58f |
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26-Oct-2015 |
Mingkai Hu <Mingkai.Hu@freescale.com> |
armv8/fsl_lsch2: Add fsl_lsch2 SoC Freescale LayerScape with Chassis Generation 2 is a set of SoCs with ARMv8 cores and 2rd generation of Chassis. Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
9f3183d2 |
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26-Oct-2015 |
Mingkai Hu <Mingkai.Hu@freescale.com> |
armv8/fsl_lsch3: Change arch to fsl-layerscape There are two LS series processors are built on ARMv8 Layersacpe architecture currently, LS2085A and LS1043A. They are based on ARMv8 core although use different chassis, so create fsl-layerscape to refactor the common code for the LS series processors which also paves the way for adding LS1043A platform. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
8976556a |
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24-Mar-2022 |
Gaurav Jain <gaurav.jain@nxp.com> |
Layerscape: Enable Job ring driver model. LS(1021/1012/1028/1043/1046/1088/2088), LX2160, LX2162 platforms are enabled with JR driver model. removed sec_init() call from board files. sec is initialized based on job ring information processed from device tree. Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Michael Walle <michael@walle.cc> |
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f9147d63 |
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25-Feb-2022 |
Tom Rini <trini@konsulko.com> |
Convert CONFIG_CHIP_SELECTS_PER_CTRL to Kconfig This converts the following to Kconfig: CONFIG_CHIP_SELECTS_PER_CTRL Cc: Alison Wang <alison.wang@nxp.com> Cc: Pramod Kumar <pramod.kumar_1@nxp.com> Cc: Priyanka Jain <priyanka.jain@nxp.com> Cc: Rajesh Bhagat <rajesh.bhagat@nxp.com> Cc: Vladimir Oltean <olteanv@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com> |
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2f8a6db5 |
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14-Dec-2021 |
Tom Rini <trini@konsulko.com> |
Finish conversion of CONFIG_SYS_CLK_FREQ to Kconfig In order to finish moving this symbol to Kconfig for all platforms, we need to do a few more things. First, for all platforms that define this to a function, introduce CONFIG_DYNAMIC_SYS_CLK_FREQ, similar to CONFIG_DYNAMIC_DDR_CLK_FREQ and populate clock_legacy.h. This entails also switching all users from CONFIG_SYS_CLK_FREQ to get_board_sys_clk() and updating a few preprocessor tests. With that done, all platforms that define a value here can be converted to Kconfig, and a fall-back of zero is sufficiently safe to use (and what is used today in cases where code may or may not have this available). Make sure that code which calls this function includes <clock_legacy.h> to get the prototype. Signed-off-by: Tom Rini <trini@konsulko.com> |
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77b11f76 |
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18-Sep-2021 |
Vladimir Oltean <vladimir.oltean@nxp.com> |
net: replace the "xfi" phy-mode with "10gbase-r" As part of the effort of making U-Boot work with the same device tree as Linux, there is an issue with the "xfi" phy-mode. To be precise, in Linux there was a discussion (for those who have time to read: https://lore.kernel.org/netdev/1576768881-24971-2-git-send-email-madalin.bucur@oss.nxp.com/) which led to a patch: https://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next.git/commit/?id=c114574ebfdf42f826776f717c8056a00fa94881 TL;DR: "xfi" was standardized in Linux as "10gbase-r". This patch changes the relevant occurrences in U-Boot to use "10gbase-r" instead of "xfi" wherever applicable. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> |
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84c2e044 |
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20-Apr-2021 |
Jiafei Pan <Jiafei.Pan@nxp.com> |
armv8: layerscape: add PSCI support for cpu release For cpu release command, check whether PSCI is supported firstly, if supported, use PSCI to kick off secondary cores, otherwise still use spin table. Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com> [Fixed checkpatch alignment CHECKs] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
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35b65dd8 |
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15-Dec-2020 |
Harald Seiler <hws@denx.de> |
reset: Remove addr parameter from reset_cpu() Historically, the reset_cpu() function had an `addr` parameter which was meant to pass in an address of the reset vector location, where the CPU should reset to. This feature is no longer used anywhere in U-Boot as all reset_cpu() implementations now ignore the passed value. Generic code has been added which always calls reset_cpu() with `0` which means this feature can no longer be used easily anyway. Over time, many implementations seem to have "misunderstood" the existence of this parameter as a way to customize/parameterize the reset (e.g. COLD vs WARM resets). As this is not properly supported, the code will almost always not do what it is intended to (because all call-sites just call reset_cpu() with 0). To avoid confusion and to clean up the codebase from unused left-overs of the past, remove the `addr` parameter entirely. Code which intends to support different kinds of resets should be rewritten as a sysreset driver instead. This transformation was done with the following coccinelle patch: @@ expression argvalue; @@ - reset_cpu(argvalue) + reset_cpu() @@ identifier argname; type argtype; @@ - reset_cpu(argtype argname) + reset_cpu(void) { ... } Signed-off-by: Harald Seiler <hws@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
401d1c4f |
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30-Oct-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop asm/global_data.h from common header Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
3a187cff |
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29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
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c760095a |
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23-Oct-2020 |
Razvan Ionut Cirjan <razvanionut.cirjan@nxp.com> |
net: lx2160a.c: Update to set ECx_PMUX precedence As per hardware documentation, ECx_PMUX has precedence over SerDes protocol. For LX2160/LX2162 if DPMACs 17 and 18 are enabled as SGMII through SerDes protocol but ECx_PMUX configured them as RGMII, then the ports will be configured as RGMII and not SGMII. Signed-off-by: Razvan Ionut Cirjan <razvanionut.cirjan@nxp.com> [Rebased] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
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d31f3a1b |
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09-Sep-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2160a: fix reset sequence Make sure that SW_RST_REQ and RST_REQ_MSK are cleared before triggering hardware reset request. Signed-off-by: Thirupathaiah Annapureddy <thiruan@linux.microsoft.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
b75d8dc5 |
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26-Jun-2020 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
treewide: convert bd_t to struct bd_info by coccinelle The Linux coding style guide (Documentation/process/coding-style.rst) clearly says: It's a **mistake** to use typedef for structures and pointers. Besides, using typedef for structures is annoying when you try to make headers self-contained. Let's say you have the following function declaration in a header: void foo(bd_t *bd); This is not self-contained since bd_t is not defined. To tell the compiler what 'bd_t' is, you need to include <asm/u-boot.h> #include <asm/u-boot.h> void foo(bd_t *bd); Then, the include direcective pulls in more bloat needlessly. If you use 'struct bd_info' instead, it is enough to put a forward declaration as follows: struct bd_info; void foo(struct bd_info *bd); Right, typedef'ing bd_t is a mistake. I used coccinelle to generate this commit. The semantic patch that makes this change is as follows: <smpl> @@ typedef bd_t; @@ -bd_t +struct bd_info </smpl> Signed-off-by: Masahiro Yamada <masahiroy@kernel.org> |
#
25a5818f |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop asm/ptrace.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
f7ae49fc |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
90526e9f |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop net.h from common header Move this header out of the common header. Network support is used in quite a few places but it still does not warrant blanket inclusion. Note that this net.h header itself has quite a lot in it. It could be split into the driver-mode support, functions, structures, checksumming, etc. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
714497e3 |
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16-May-2020 |
Michael Walle <michael@walle.cc> |
efi_loader: round the memory area in efi_add_memory_map() Virtually all callers of this function do the rounding on their own. Some do it right, some don't. Instead of doing this in each caller, do the rounding in efi_add_memory_map(). Change the size parameter to bytes instead of pages and remove aligning and size calculation in all callers. There is no more need to make the original efi_add_memory_map() (which takes pages as size) available outside the module. Thus rename it to efi_add_memory_map_pg() and make it static to prevent further misuse outside the module. Signed-off-by: Michael Walle <michael@walle.cc> Add missing comma in sunxi_display.c. Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de> |
#
6eb32a03 |
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23-Apr-2020 |
Madalin Bucur <madalin.bucur@oss.nxp.com> |
driver: net: fm: add DM ETH support Probe the FMan MACs based on the device tree while retaining the legacy code/functionality. One notable change introduced here is that, for DM_ETH, the name of the interfaces is corrected to the fmX-macY format, that avoids the referral to the MAC block names which were incorrect for FMan v3 devices (i.e. DTSEC, TGEC) and had weird formatting (i.e. FM1@DTSEC6, FM1@TGEC1). The legacy code is left unchanged in this respect. Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
6ebd4883 |
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27-Apr-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
fsl-layerscape: Add RESV_RAM check in resv_ram addr The initialization of gd->arch.resv_ram pointer should depend on if the RESV_RAM config is enabled. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Wasim Khan <wasim.khan@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
0d9d557d |
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10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
db41d65a |
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28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move hang() to the same header as panic() At present panic() is in the vsprintf.h header file. That does not seem like an obvious choice for hang(), even though it relates to panic(). So let's put hang() in its own header. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Migrate a few more files] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
9b4a205f |
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28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move RAM-sizing functions to init.h These functions relate to memory init so move them into the init header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
3499dd03 |
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27-Nov-2019 |
Alex Marginean <alexandru.marginean@nxp.com> |
ls1028a: Configure stream IDs for integrated PCI and fix up Linux DT Hardware comes out of reset with implicit values, but these are outside the accepted range for Layerscape gen 3 chassis spec used on LS1028A. Allocate different IDs and fix up Linux DT to use them. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
b5981474 |
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14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some CPU functions out of common.h These functions belong in cpu_func.h since they do not use driver model. Move them over. Don't bother adding comments since these functions should be deleted. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
68a6aa85 |
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14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move mii_init() function out of common.h This function belongs in mii.h so move it over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
2189d5f1 |
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14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
Move strtomhz() to vsprintf.h At present this function sits in its own file but it does not really justify it. There are similar string functions in vsprintf.h, so move it there. Also add the missing function comment. Use the vsprintf.h include file explicitly where needed. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
812ff53c |
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30-Oct-2019 |
Pankaj Bansal <pankaj.bansal@nxp.com> |
fsl-layerscape: fix warning if no hwconfig is defined While getting the 'subarg' of 'hwconfig' env variable in config_core_prefetch(), if no hwconfig variable is defined, below warning is received: WARNING: Calling __hwconfig without a buffer and before environment is ready Fix this by checking 'hwconfig' env variable. If not found return without further processing. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Tested-by: Michael Walle <michael@walle.cc> |
#
28f9393b |
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17-Oct-2019 |
Mathew McBride <matt@traverse.com.au> |
fsl-layerscape: do not use layerscape EFI reset if PSCI used If the secure world reset handlers are used (via CONFIG_PSCI_RESET), then do not use the layerscape-specific implementation. Signed-off-by: Mathew McBride <matt@traverse.com.au> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
6ed69523 |
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18-Sep-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add more personalities support Add LS1027A, LS1018A and LS1017A personalities support to LS1028A SoC family. LS1028A is the prime personality of LS1028A SoC family. LS1027A is a lower funtionality version of QorIQ LS1028A which does not support the multimedia subsystems, such as LCD controller, GPU, and eDP PHY. The QorIQ LS1018A and LS1017A SoCs are single 64-bit Arm A72 core, low power versions of the QorIQ LS1028A and LS1027A SoCs respectively. Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
0490cab5 |
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08-Aug-2019 |
Thomas Schaefer <thomas.schaefer@kontron.com> |
armv8: ls1028a: configure PMU's PCTBENR to enable WDT The SP805-WDT module on LS1028A requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. The watchdog clock needs to be enabled first. Signed-off-by: Thomas Schaefer <thomas.schaefer@kontron.com> Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
f3998fdc |
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02-Aug-2019 |
Simon Glass <sjg@chromium.org> |
env: Rename environment.h to env_internal.h This file contains lots of internal details about the environment. Most code can include env.h instead, calling the functions there as needed. Rename this file and add a comment at the top to indicate its internal nature. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> [trini: Fixup apalis-tk1.c] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
3a7d5571 |
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01-Aug-2019 |
Simon Glass <sjg@chromium.org> |
env: Move env_get_f() to env.h Move this function over to the new header file. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
d9532e80 |
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23-Apr-2019 |
Udit Agarwal <udit.agarwal@nxp.com> |
armv8: fsl-layerscape: Set env_loc to ENVL_NOWHERE with CONFIG_ENV_IS_NOWHERE. ENVL_NOWHERE is dependent on CONFIG_ENV_IS_NOWHERE and not on CONFIG_CHAIN_OF_TRUST so return ENVL_NOWHERE when CONFIG_ENV_IS_NOWHERE is enabled Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
d4ad111d |
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10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
059d9422 |
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08-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: lx2160a: add MMU table entries for PCIe The lx2160a have up to 6 PCIe controllers and have different address and size of PCIe region. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
8348e798 |
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08-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: layerscape: use PCIe address macro for precompile PCIe MMU entry Change to use PCIe address macro to determine if precompile the PCIe MMU table entry. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
10015025 |
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03-May-2019 |
Trevor Woerner <trevor@toganlabs.com> |
CONFIG_SPL_SYS_[DI]CACHE_OFF: add While converting CONFIG_SYS_[DI]CACHE_OFF to Kconfig, there are instances where these configuration items are conditional on SPL. This commit adds SPL variants of these configuration items, uses CONFIG_IS_ENABLED(), and updates the configurations as required. Acked-by: Alexey Brodkin <abrodkin@synopsys.com> Signed-off-by: Trevor Woerner <trevor@toganlabs.com> [trini: Make the default depend on the setting for full U-Boot, update more zynq hardware] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
2e53759d |
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29-Oct-2018 |
Pankaj Bansal <pankaj.bansal@nxp.com> |
armv8: fsl-layerscape: reorder rgmii dpmacs' enablement some dpmacs in armv8a based freescale layerscape SOCs can be configured via both serdes(sgmii, xfi, xlaui etc) bits and via EC*_PMUX(rgmii) bits in RCW. e.g. dpmac 17 and 18 in LX2160A can be configured as SGMII from serdes bits and as RGMII via EC1_PMUX/EC2_PMUX bits Now if a dpmac is enabled by serdes bits then it takes precedence over EC*_PMUX bits. i.e. in LX2160A if we select serdes protocol that configures dpmac17 as SGMII and set the EC1_PMUX as RGMII, then the dpmac is SGMII and not RGMII. Therefore, move the fsl_rgmii_init after fsl_serdes_init. in fsl_rgmii_init function of SOC, we will check if the dpmac is enabled or not? if it is (fsl_serdes_init has already enabled the dpmac), then don't enable it. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
ec88ff80 |
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19-Dec-2018 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1043a: add SVR definitions for 23x23 package silicon LS1043A/LS1023A 23x23 package silicon has different SVR:VAR_PER. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
d23da2ae |
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26-Dec-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: fixes for TFABOOT framework Fixes for TFABOOT framework - update eMMC bootsrc to SD_MMC - Increase buffer size for mcinitcmd from 256 to 512 - Fix mcinitcmd and bootcmd for Secure Boot Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
4909b89e |
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29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
d6fdec21 |
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29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8:fsl-layerscape: Add support for Chassis 3.2 NXP layerscape architecture Chassis 3.2 builds upon chassis3 architecture with changes like DDR Memory map change, removal of IFC and support of upto 8 I2C controller. Patch add README.lsch3_2 and the above changes under macro CONFIG_NXP_LSCH3_2. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
56db948b |
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05-Nov-2018 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: Update parsing boot source Workaround of erratum A010539 clears the RCW source field in PORSR1 register, causing failure of detecting boot source using this method. Use SMC call if U-Boot runs at EL2. If SMC is not implemented or running at EL3, continue to read PORSR1 and presume QSPI as boot source if erratum workaround A010539 is enabled and RCW source is cleared. Signed-off-by: York Sun <york.sun@nxp.com> |
#
681d489e |
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05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: layerscape: add SMC calls for DDR size and bank info Adds SMC calls for getting DDR size and bank info for TFABOOT. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
2141d250 |
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05-Nov-2018 |
Pankit Garg <pankit.garg@nxp.com> |
armv8: fsl-layerscape: bootcmd identification for TFABOOT Adds bootcmd identificaton on basis on boot source, valid in TFABOOT configuration. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> [YS: remove unnecessary braces] Reviewed-by: York Sun <york.sun@nxp.com> |
#
4c417384 |
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05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com> |
#
535d76a1 |
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05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: layerscape: Add TFABOOT support Adds TFABOOT support config option and add generic code to enable execution from DDR. Signed-off-by: York Sun <york.sun@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> |
#
e3506480 |
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05-Nov-2018 |
Pankit Garg <pankit.garg@nxp.com> |
armv8: fsl-layerscape: change tlb base from OCRAM to DDR in EL < 3 Change tlb base address from OCRAM to DDR when exception level is less than 3. Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
d171c707 |
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05-Nov-2018 |
York Sun <york.sun@nxp.com> |
move data structure out of cpu.h Move static definitions to cpu.c file, as it doesn't allow the cpu.h file to be included in multiple c files. Signed-off-by: York Sun <york.sun@nxp.com> |
#
9b5e6396 |
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30-Aug-2018 |
Stephen Warren <swarren@nvidia.com> |
efi_loader: simplify ifdefs Use CONFIG_IS_ENABLED(EFI_LOADER) to avoid explicitly checking CONFIG_SPL too. This simplifies the conditional. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Alexander Graf <agraf@suse.de> |
#
9cce5663 |
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16-Jul-2018 |
Joe Hershberger <joe.hershberger@ni.com> |
arm: Prevent redefinition error in fsl-layerscape The include/phy.h will start including dm.h, which pulls in linux/compat.h after the attempted redefinition in arch/arm/include/asm/armv8/mmu.h, so move this include to allow redefinition. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> |
#
83d290c5 |
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06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
482fc90c |
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06-Feb-2018 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
efi_loader: add missing EFI_RESET_PLATFORM_SPECIFIC EFI_RESET_PLATFORM_SPECIFIC is one of the values that can be used for the EFI service ResetSystem. The missing definition is added. The value has to handled in efi_reset_system(). Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Alexander Graf <agraf@suse.de> |
#
22c793e6 |
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03-Mar-2018 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
efi_loader: exit status for efi_reset_system_init efi_reset_system_init provides the architecture or board specific initialization of the EFI subsystem. Errors should be caught and signalled by a return code. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Alexander Graf <agraf@suse.de> |
#
958b2ed5 |
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09-Jan-2018 |
Zhang Ying-22455 <ying.zhang22455@nxp.com> |
armv8/ls1088a: configure PMU's PCTBENR to enable WDT The SP805-WDT module on LS1088A requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. The watchdog clock needs to be enabled first. Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
44262327 |
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15-Dec-2017 |
Ahmed Mansour <ahmed.mansour@nxp.com> |
drivers/misc: Share qbman init between archs This patch adds changes necessary to move functionality present in PowerPC folders with ARM architectures that have DPAA1 QBMan hardware - Create new board/freescale/common/fsl_portals.c to house shared device tree fixups for DPAA1 devices with ARM and PowerPC cores - Add new header file to top includes directory to allow files in both architectures to grab the function prototypes - Port inhibit_portals() from PowerPC to ARM. This function is used in setup to disable interrupts on all QMan and BMan portals. It is needed because the interrupts are enabled by default for all portals including unused/uninitialised portals. When the kernel attempts to go to deep sleep the unused portals prevent it from doing so Signed-off-by: Ahmed Mansour <ahmed.mansour@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
a8f33034 |
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03-Dec-2017 |
Wenbin song <wenbin.song@nxp.com> |
armv8: ls1043a/ls2080a: check SoC by device ID Check LS1043A/LS2080a by device ID without using personality ID to determine revision number. This check applies to all various personalities of the same SoC family. Signed-off-by: Wenbin Song <wenbin.song@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
2db53cfe |
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09-Nov-2017 |
Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
armv8: fsl-layerscape: Add support of disabling core prefetch Instruction prefetch feature is by default enabled during core release. This patch add support of disabling instruction prefetch by setting core mask in PPA. Here each core mask bit represents a core and prefetch is disabled at the time of core release. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
7eb40f0f |
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28-Sep-2017 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: Avoid running dram_init_banksize again gd->ram_size is reduced in this function to reserve secure memory. Avoid running this function again to further reduce memory size. This fixes issue for SPL boot with PPA image loaded in which case secure memory is incorrectly allocated due to repeated calling. Signed-off-by: York Sun <york.sun@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
710d0cd7 |
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03-Oct-2017 |
Sumit Garg <sumit.garg@nxp.com> |
armv8: fsl-layerscape: Allocate Secure memory from first ddr region This change is required due to trusted OS (OP-TEE) not being position independent code, it requires compile time fixed base address. To take care of this it is assumed that all layerscape armv8 platforms has minimum 2G ddr in first region. So we can have fixed address space (66 MB -> (2MB for PPA + 64MB for trusted OS)) allocated from top of first 2G ddr region and compile trusted OS with this fixed base address. But one exception here is ls1012 where we have only 1G (rdb) or 512M (frdm) ddr memory. For those we can have different fixed compile time base addresses for trusted OS. Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
e9303a41 |
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07-Sep-2017 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: Fix MC reserved memory calculation In case high region memory doesn't have enough space for Management Complex (MC), the return value should indicate a failure so the caller can handle it accordingly. Signed-off-by: York Sun <york.sun@nxp.com> Reported-by: Ebony Zhu <ebony.zhu@nxp.com> |
#
17d066fc |
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31-Aug-2017 |
Ashish Kumar <Ashish.Kumar@nxp.com> |
armv8: fsl-layerscape: Support to add RGMII for ls1088aqds This patch adds support for RGMII protocol NXP's LDPAA2 support RGMII protocol. LS1088A is the first Soc supporting both RGMII and SGMII. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Amrita Kumari <amrita.kumari@nxp.com> Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
63b2316c |
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10-Aug-2017 |
Ashish Kumar <Ashish.Kumar@nxp.com> |
fsl-layerscape: Consolidate registers space defination for CCI-400 bus CoreLink Cache Coherent Interconnect (CCI) provides full cache coherency between two clusters of multi-core CPUs and I/O coherency for devices and I/O masters. This patch add new config option SYS_FSL_HAS_CCI400 and moves existing register space definaton of CCI-400 bus to fsl_immap to be shared. CONFIG_SYS_CCI400_ADDR is replaced with SYS_CCI400_OFFSET in Kconfig. Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> [YS: revised commit message, squashed patches for armv8 and armv7] Reviewed-by: York Sun <york.sun@nxp.com> |
#
6e2941d7 |
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17-May-2017 |
Simon Glass <sjg@chromium.org> |
common: freescale: Move arch-specific declarations The declarations should not be in common.h. Move them to the arch-specific headers. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Fixup thinko defined(FSL_LSCH3) -> defined(CONFIG_FSL_LSCH3)] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
399e2bb6 |
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15-May-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Make U-Boot EL2 safe When U-Boot boots from EL2, skip some lowlevel init code requiring EL3, including CCI-400/CCN-504, trust zone, GIC, etc. These initialization tasks are carried out before U-Boot runs. This applies to the RAM version image used for SPL boot if PPA is loaded first. Signed-off-by: York Sun <york.sun@nxp.com> |
#
1f55a938 |
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05-May-2017 |
Santan Kumar <santan.kumar@nxp.com> |
armv8: ls2080aqds: Add support for SD boot Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
e809e747 |
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27-Apr-2017 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: fsl-layerscape: Add NXP LS2081A, LS2041A SoC support The QorIQ LS2081A SoC has eight 64-bit ARM v8 Cortex A72 cores and is built on layerscape architecture. It is 40-pin derivative of LS2084A (non-AIOP personality of LS2088A). So feature-wise it is same as LS2084A. LS2041A is a 4-core personality of LS2081A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
026f30ec |
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18-Apr-2017 |
Yuantian Tang <andy.tang@nxp.com> |
arm: psci: make psci usable on single core socs PSCI can be used on both multiple and single core socs. Current implementation only allows PSCI to work on multiple core socs. This patch removes this restriction so that PSCI can work on single core socs as well. Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
4a3ab193 |
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27-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: ls2080a: Drop macro CONFIG_LS2080A Use CONFIG_ARCH_LS2080A instead. Signed-off-by: York Sun <york.sun@nxp.com> |
#
3eace37e |
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06-Apr-2017 |
Simon Glass <sjg@chromium.org> |
arm: freescale: Rename initdram() to fsl_initdram() This function name shadows a global name but is in fact different. This is very confusing. Rename it to help with the following refactoring. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
76b00aca |
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31-Mar-2017 |
Simon Glass <sjg@chromium.org> |
board_f: Drop setup_dram_config() wrapper By making dram_init_banksize() return an error code we can drop the wrapper. Adjust this and clean up all implementations. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
088454cd |
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31-Mar-2017 |
Simon Glass <sjg@chromium.org> |
board_f: Drop return value from initdram() At present we cannot use this function as an init sequence call without a wrapper, since it returns the RAM size. Adjust it to set the RAM size in global_data instead, and return 0 on success. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> |
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52c41180 |
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31-Mar-2017 |
Simon Glass <sjg@chromium.org> |
board_f: Drop board_type parameter from initdram() It looks like only cm5200 and tqm8xx use this feature, so we don't really need it in generic code. Drop it and have the users access gd->board_type directly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
3d8553f0 |
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02-Mar-2017 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
pci: layerscape: add LS2088A series SoC pcie support The LS2088A series SoCs has different physical memory map address and CCSR registers address against LS2080A series SoCs. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
eea1cb77 |
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13-Feb-2017 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8/fsl-layerscape: Update erratum A009635 implementation Erratum A009635 is valid only for LS2080A SoC and its personality. Add SoC svr check. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
4961eafc |
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06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Update early MMU for DDR after initialization In early MMU table, DDR has to be mapped as device memory to avoid speculative access. After DDR is initialized, it needs to be updated to normal memory to allow code execution. To simplify the code, dram_init() is moved into a common file as a weak function. Signed-off-by: York Sun <york.sun@nxp.com> |
#
a045a0c3 |
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06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Fix the sequence of changing MMU table This patch follows the break-before-make process when making changes to MMU table. MMU is disabled before changing TTBR to avoid any potential race condition. Signed-off-by: York Sun <york.sun@nxp.com> |
#
24f55496 |
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06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Update MMU mapping with actual DDR size Update mapping with actual DDR size. Non-existing memory should not be mapped as "normal" memory to avoid speculative access. Signed-off-by: York Sun <york.sun@nxp.com> |
#
36cc0de0 |
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06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Rewrite memory reservation For ARMv8 Layerscape SoCs, secure memory and MC memorey are reserved at the end of DDR. DDR is spit into two or three banks. This patch reverts commit aabd7ddb and simplifies the calculation of reserved memory, and moves the code into common SoC file. Secure memory is carved out first. DDR bank size is reduced. Reserved memory is then allocated on the top of available memory. U-Boot still has access to reserved memory as data transferring is needed. Device tree is fixed with reduced memory size to hide the reserved memory from OS. The same region is reserved for efi_loader. Signed-off-by: York Sun <york.sun@nxp.com> |
#
daa92644 |
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16-Jan-2017 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
ARMv8/sec_firmware: relocated and renamed the config FSL_PPA_ARMV8_PSCI Moved the config FSL_PPA_ARMV8_PSCI from fsl-layerscape's Kconfig to Kconfig under armv8 and renamed it to SEC_FIRMWARE_ARMV8_PSCI. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
904110c7 |
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10-Jan-2017 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8/fsl-lsch2: refactor the clock system initialization Up to now, there are 3 kind of SoCs under Layerscape Chassis 2, like LS1043A, LS1046A and LS1012A. But the clocks tree has a lot of differences, for instance, the IP modules have different dividers to derive its clock from Platform PLL. And the core cluster PLL and platform PLL maybe have different reference clocks, such as LS1012A. Another problem is which clock/PLL should be described by sys_info->freq_systembus, it is confused in Layerscape Chissis 2. This patch is to bind the sys_info->freq_systembus to the Platform PLL, and handle the different divider of IP modules separately between different SoCs, and separate reference clocks of core cluster PLL and platform PLL. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
2d16a1a6 |
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07-Dec-2016 |
macro.wave.z@gmail.com <macro.wave.z@gmail.com> |
ARMv8: LS1043A: change macro CONFIG_ARMV8_PSCI definition NXP/Freescale uses macro CONFIG_ARMV8_PSCI to enable their private PSCI implementation in PPA firmware, but this macro naming too generic, so this patch replaces it with a specic one CONFIG_FSL_PPA_ARMV8_PSCI. And this macro CONFIG_ARMV8_PSCI will be used for a generic PSCI for ARMv8 which will be added in following patchs. Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
02fb2761 |
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20-Nov-2016 |
Shengzhou Liu <Shengzhou.Liu@nxp.com> |
fsl/ddr: Add erratum_a009942_check_cpo and clean related erratum - add additional function erratum_a009942_check_cpo to check if the board needs tuning CPO calibration for optimal setting. - move ERRATUM_A009942(with revision to check cpo_sample option) from fsl_ddr_gen4.c to ctrl_regs.c for reuse on all DDR4/DDR3 parts. - move ERRATUM_A008378 from fsl_ddr_gen4.c to ctrl_regs.c - remove obsolete ERRATUM_A004934 which is replaced with ERRATUM_A009942. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> [YS: Replaced CONFIG_QEMU_E500 with CONFIG_ARCH_QEMU_E500] Reviewed-by: York Sun <york.sun@nxp.com> |
#
e87c673c |
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16-Nov-2016 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8/fsl-lsch3: Update code to release secondary cores NXP ARMv8 SoC LS2080A release all secondary cores in one-go. But other new SoCs like LS2088A, LS1088A release secondary cores one by one. Update code to release secondary cores based on SoC SVR Add code to release cores one by one for non LS2080A SoCs Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> [YS: remove "inline" from declaration of initiator_type] Reviewed-by: York Sun <york.sun@nxp.com> |
#
f6b96ff6 |
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16-Nov-2016 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Use SVR based timer base address detection Timer controller base address has been changed from LS2080A SoC (and its personalities) to new SoCs like LS2088A, LS1088A. Use SVR based timer base address detection to avoid compile time #ifdef. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
f6a70b3a |
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16-Nov-2016 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add generic get_svr() in assembly Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
78d57842 |
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16-Nov-2016 |
Alexander Graf <agraf@csgraf.de> |
armv8: fsl-layerscape: Add support for efi_loader RTS reset When implementing efi loader support, we can expose runtime services for payloads. One such service is CPU reset. This patch implements RTS CPU reset support for layerscape systems. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: York Sun <york.sun@nxp.com> |
#
ef9a5fd8 |
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13-Sep-2016 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: Fix "cpu status" command The core position is not continuous for some SoCs. For example, valid cores may present at position 0, 1, 4, 5, 8, 9, etc. Some registers (including boot release register) only count existing cores. Current implementation of cpu_mask() complies with the continuous numbering. However, command "cpu status" queries the spin table with actual core position. Add functions to calculate core position from core number, to correctly calculate offsets. Tested on LS2080ARDB and LS1043ARDB. Signed-off-by: York Sun <york.sun@nxp.com> |
#
5d1a7a9d |
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13-Sep-2016 |
Wenbin Song <wenbin.song@nxp.com> |
armv8/fsl-layerscape: print SoC revsion number The exact SoC revsion number can be recognized from U-Boot log. Signed-off-by: Wenbin Song <wenbin.song@nxp.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
cbe7706a |
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26-Sep-2016 |
Tom Rini <trini@konsulko.com> |
Merge git://git.denx.de/u-boot-fsl-qoriq trini: Drop local memset() from examples/standalone/mem_to_mem_idma2intr.c Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
1221ce45 |
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20-Sep-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
treewide: replace #include <asm/errno.h> with <linux/errno.h> Now, arch/${ARCH}/include/asm/errno.h and include/linux/errno.h have the same content. (both just wrap <asm-generic/errno.h>) Replace all include directives for <asm/errno.h> with <linux/errno.h>. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> [trini: Fixup include/clk.] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
b63a9506 |
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03-Aug-2016 |
York Sun <york.sun@nxp.com> |
armv8: ls2080a: Remove debug server support Debug server feature has been dropped from roadmap. Signed-off-by: York Sun <york.sun@nxp.com> |
#
ed7a3943 |
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22-Jul-2016 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: mmu: Fix enabling MMU MMU bit in SCTLR needs to be set explicitly after tables are created. It isn't an issue for EL3 becuase this bit is already set by early MMU setup. But for other exception levels this bit was not set. Signed-off-by: York Sun <york.sun@nxp.com> |
#
79119a4d |
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05-Jul-2016 |
Alison Wang <b18965@freescale.com> |
armv8: fsl-layerscape: Add A72 core detection Add support to detect Cortex-A72 core for printing it out. The Initiator Version of A72 core should be 0x4. Signed-off-by: Alison Wang <alison.wang@nxp.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
032d5bb4 |
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28-Jun-2016 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
ARMv8/Layerscape: switch SMP method accordingly If the PSCI and PPA is ready, skip the fixup for spin-table and waking secondary cores. Otherwise, change SMP method to spin-table, and the device node of PSCI will be removed. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
85cdf38e |
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28-Jun-2016 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: fsl-layerscape: add i/d-cache enable function to enable_caches This function assume that the d-cache and MMU has been enabled earlier, so it just created MMU table in main memory. But the assumption is not always correct, for example, the early setup is done in EL3, while enable_caches() is called when the PE has turned into another EL. Define the function mmu_setup() for fsl-layerscape to cover the weak one. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
5ad5823d |
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24-Jun-2016 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Convert to use common MMU framework Drop platform code to create static MMU tables. Use common framework to create MMU tables on the run. Tested on LS2080ARDB with secure and non-secure ram scenarios. Signed-off-by: York Sun <york.sun@nxp.com> |
#
e61a7534 |
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24-Jun-2016 |
York Sun <york.sun@nxp.com> |
armv8: Move secure_ram variable out of generic global data Secure_ram variable was put in generic global data. But only ARMv8 uses this variable. Move it to ARM specific data structure. Signed-off-by: York Sun <york.sun@nxp.com> |
#
a10a31ec |
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18-Jun-2016 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of git://git.denx.de/u-boot-usb Signed-off-by: Tom Rini <trini@konsulko.com> Conflicts: arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
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#
6fb522dc |
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12-Jun-2016 |
Sriram Dash <sriram.dash@nxp.com> |
arm64: fsl-layerscape: add get_svr and IS_SVR_REV helper Adds get_svr and IS_SVR_REV helpers for ARMv8 platforms, similar to PPC and ARMv7. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> |
#
a758177f |
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07-Jun-2016 |
Yunhui Cui <yunhui.cui@nxp.com> |
armv8/ls2080a: configure PMU's PCTBENR to enable WDT The SP805-WDT module on LS2080A requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. The watchdog clock needs to be enabled first. Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
acb8f5e9 |
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21-Apr-2016 |
Alison Wang <b18965@freescale.com> |
armv8: fsl-layerscape: Remove unnecessary flushing dcache As the issue about the stack will get corrupted when switching between the early and final mmu tables is fixed by commit 70e21b064, the workaround to flush dcache is unnecessary and should be removed. Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
3c1d218a |
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04-Apr-2016 |
York Sun <york.sun@nxp.com> |
armv8: LS2080A: Consolidate LS2080A and LS2085A LS2080A is the primary SoC, and LS2085A is a personality with AIOP and DPAA DDR. The RDB and QDS boards support both personality. By detecting the SVR at runtime, a single image per board can support both SoCs. It gives users flexibility to swtich SoC without the need to reprogram the board. Signed-off-by: York Sun <york.sun@nxp.com> CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
c05016ab |
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21-Mar-2016 |
Alexander Graf <agraf@csgraf.de> |
arm64: Fix layerscape mmu setup With commit 7985cdf we converted all systems except for the Layerscape SoCs to the generic descriptor table based page table setup. On the Layerscape SoCs however, we just provide an empty table stub and do the setup ourselves. To reserve enough memory for the tables, we need to override the default counting mechanism which would end up with an empty table because we have no maps. Fixes: 7985cdf Reported-by: York Sun <york.sun@nxp.com> CC: Alison Wang <alison.wang@nxp.com> CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Alexander Graf <agraf@suse.de> Tested-by: York Sun <york.sun@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
7985cdf7 |
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03-Mar-2016 |
Alexander Graf <agraf@csgraf.de> |
arm64: Remove non-full-va map code By now the code to only have a single page table level with 64k page size and 42 bit address space is no longer used by any board in tree, so we can safely remove it. To clean up code, move the layerscape mmu code to the new defines, removing redundant field definitions. Signed-off-by: Alexander Graf <agraf@suse.de> |
#
c0492141 |
|
07-Dec-2015 |
York Sun <yorksun@freescale.com> |
armv8: fsl-layerscale: Rewrite reserving memory for MC and debug server MC and debug server are not board-specific. Move reserving memory to SoC file, using the new board_reserve_ram_top function. Reduce debug server memory by 2MB to make room for secure memory. In the system with MC and debug server, the top of u-boot memory is not the end of memory. PRAM is not used for this reservation. Signed-off-by: York Sun <yorksun@freescale.com> |
#
c107c0c0 |
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04-Dec-2015 |
York Sun <yorksun@freescale.com> |
armv8: fsl-layerscape: Make DDR non secure in MMU tables DDR has been set as secure in MMU tables. Non-secure master such as SDHC DMA cannot access data correctly. Mixing secure and non- secure MMU entries requirs the MMU tables themselves in secure memory. This patch moves MMU tables into a secure DDR area. Early MMU tables are changed to set DDR as non-secure. A new table is added into final MMU tables so secure memory can have 2MB granuality. gd->secure_ram tracks the location of this secure memory. For ARMv8 SoCs, the RAM base is not zero and RAM is divided into several banks. gd->secure_ram needs to be maintained before using. This maintenance is board-specific, depending on the SoC and memory bank of the secure memory falls into. Signed-off-by: York Sun <yorksun@freescale.com> |
#
b4017364 |
|
04-Nov-2015 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
armv8: ls2085a: Add workaround of errata A009635 If the core runs at higher than x3 speed of the platform, there is possiblity about sev instruction to getting missed by other cores. This is because of SoC Run Control block may not able to sample the EVENTI(Sev) signals. Configure Run Control and EPU to periodically send out EVENTI signals to wake up A57 cores. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
d764129d |
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04-Nov-2015 |
Alison Wang <b18965@freescale.com> |
armv8/layerscape: Update MMU table with execute-never bits For most device addresses excution shouldn't be allowed. Revise the MMU table to enforce execute-never bits. OCRAM, DDR and IFC are allowed for excution. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Alison Wang <alison.wang@freescale.com> Reported-by: Zhichun Hua <zhichun.hua@freescale.com> |
#
44937214 |
|
09-Nov-2015 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
armv8: LS2080A: Rename LS2085A to reflect LS2080A LS2080A is a prime personality of Freescale’s LS2085A. It is a non-AIOP personality without support of DP-DDR, L2 switch, 1588, PCIe endpoint etc. So renaming existing LS2085A code base to reflect LS2080A (Prime personality) Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> [York Sun: Dropped #ifdef in cpu.c for cpu_type_list] Reviewed-by: York Sun <yorksun@freescale.com> |
#
e8297341 |
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26-Oct-2015 |
Shaohui Xie <Shaohui.Xie@freescale.com> |
armv8/ls1043a: Add Fman support Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
8281c58f |
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26-Oct-2015 |
Mingkai Hu <Mingkai.Hu@freescale.com> |
armv8/fsl_lsch2: Add fsl_lsch2 SoC Freescale LayerScape with Chassis Generation 2 is a set of SoCs with ARMv8 cores and 2rd generation of Chassis. Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
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9f3183d2 |
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26-Oct-2015 |
Mingkai Hu <Mingkai.Hu@freescale.com> |
armv8/fsl_lsch3: Change arch to fsl-layerscape There are two LS series processors are built on ARMv8 Layersacpe architecture currently, LS2085A and LS1043A. They are based on ARMv8 core although use different chassis, so create fsl-layerscape to refactor the common code for the LS series processors which also paves the way for adding LS1043A platform. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
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f9147d63 |
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25-Feb-2022 |
Tom Rini <trini@konsulko.com> |
Convert CONFIG_CHIP_SELECTS_PER_CTRL to Kconfig This converts the following to Kconfig: CONFIG_CHIP_SELECTS_PER_CTRL Cc: Alison Wang <alison.wang@nxp.com> Cc: Pramod Kumar <pramod.kumar_1@nxp.com> Cc: Priyanka Jain <priyanka.jain@nxp.com> Cc: Rajesh Bhagat <rajesh.bhagat@nxp.com> Cc: Vladimir Oltean <olteanv@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com> |
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2f8a6db5 |
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14-Dec-2021 |
Tom Rini <trini@konsulko.com> |
Finish conversion of CONFIG_SYS_CLK_FREQ to Kconfig In order to finish moving this symbol to Kconfig for all platforms, we need to do a few more things. First, for all platforms that define this to a function, introduce CONFIG_DYNAMIC_SYS_CLK_FREQ, similar to CONFIG_DYNAMIC_DDR_CLK_FREQ and populate clock_legacy.h. This entails also switching all users from CONFIG_SYS_CLK_FREQ to get_board_sys_clk() and updating a few preprocessor tests. With that done, all platforms that define a value here can be converted to Kconfig, and a fall-back of zero is sufficiently safe to use (and what is used today in cases where code may or may not have this available). Make sure that code which calls this function includes <clock_legacy.h> to get the prototype. Signed-off-by: Tom Rini <trini@konsulko.com> |
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77b11f76 |
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18-Sep-2021 |
Vladimir Oltean <vladimir.oltean@nxp.com> |
net: replace the "xfi" phy-mode with "10gbase-r" As part of the effort of making U-Boot work with the same device tree as Linux, there is an issue with the "xfi" phy-mode. To be precise, in Linux there was a discussion (for those who have time to read: https://lore.kernel.org/netdev/1576768881-24971-2-git-send-email-madalin.bucur@oss.nxp.com/) which led to a patch: https://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next.git/commit/?id=c114574ebfdf42f826776f717c8056a00fa94881 TL;DR: "xfi" was standardized in Linux as "10gbase-r". This patch changes the relevant occurrences in U-Boot to use "10gbase-r" instead of "xfi" wherever applicable. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> |
#
84c2e044 |
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20-Apr-2021 |
Jiafei Pan <Jiafei.Pan@nxp.com> |
armv8: layerscape: add PSCI support for cpu release For cpu release command, check whether PSCI is supported firstly, if supported, use PSCI to kick off secondary cores, otherwise still use spin table. Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com> [Fixed checkpatch alignment CHECKs] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
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35b65dd8 |
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15-Dec-2020 |
Harald Seiler <hws@denx.de> |
reset: Remove addr parameter from reset_cpu() Historically, the reset_cpu() function had an `addr` parameter which was meant to pass in an address of the reset vector location, where the CPU should reset to. This feature is no longer used anywhere in U-Boot as all reset_cpu() implementations now ignore the passed value. Generic code has been added which always calls reset_cpu() with `0` which means this feature can no longer be used easily anyway. Over time, many implementations seem to have "misunderstood" the existence of this parameter as a way to customize/parameterize the reset (e.g. COLD vs WARM resets). As this is not properly supported, the code will almost always not do what it is intended to (because all call-sites just call reset_cpu() with 0). To avoid confusion and to clean up the codebase from unused left-overs of the past, remove the `addr` parameter entirely. Code which intends to support different kinds of resets should be rewritten as a sysreset driver instead. This transformation was done with the following coccinelle patch: @@ expression argvalue; @@ - reset_cpu(argvalue) + reset_cpu() @@ identifier argname; type argtype; @@ - reset_cpu(argtype argname) + reset_cpu(void) { ... } Signed-off-by: Harald Seiler <hws@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> |
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401d1c4f |
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30-Oct-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop asm/global_data.h from common header Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com> |
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3a187cff |
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29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
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c760095a |
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23-Oct-2020 |
Razvan Ionut Cirjan <razvanionut.cirjan@nxp.com> |
net: lx2160a.c: Update to set ECx_PMUX precedence As per hardware documentation, ECx_PMUX has precedence over SerDes protocol. For LX2160/LX2162 if DPMACs 17 and 18 are enabled as SGMII through SerDes protocol but ECx_PMUX configured them as RGMII, then the ports will be configured as RGMII and not SGMII. Signed-off-by: Razvan Ionut Cirjan <razvanionut.cirjan@nxp.com> [Rebased] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
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d31f3a1b |
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09-Sep-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2160a: fix reset sequence Make sure that SW_RST_REQ and RST_REQ_MSK are cleared before triggering hardware reset request. Signed-off-by: Thirupathaiah Annapureddy <thiruan@linux.microsoft.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
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b75d8dc5 |
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26-Jun-2020 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
treewide: convert bd_t to struct bd_info by coccinelle The Linux coding style guide (Documentation/process/coding-style.rst) clearly says: It's a **mistake** to use typedef for structures and pointers. Besides, using typedef for structures is annoying when you try to make headers self-contained. Let's say you have the following function declaration in a header: void foo(bd_t *bd); This is not self-contained since bd_t is not defined. To tell the compiler what 'bd_t' is, you need to include <asm/u-boot.h> #include <asm/u-boot.h> void foo(bd_t *bd); Then, the include direcective pulls in more bloat needlessly. If you use 'struct bd_info' instead, it is enough to put a forward declaration as follows: struct bd_info; void foo(struct bd_info *bd); Right, typedef'ing bd_t is a mistake. I used coccinelle to generate this commit. The semantic patch that makes this change is as follows: <smpl> @@ typedef bd_t; @@ -bd_t +struct bd_info </smpl> Signed-off-by: Masahiro Yamada <masahiroy@kernel.org> |
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25a5818f |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop asm/ptrace.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
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f7ae49fc |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
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90526e9f |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop net.h from common header Move this header out of the common header. Network support is used in quite a few places but it still does not warrant blanket inclusion. Note that this net.h header itself has quite a lot in it. It could be split into the driver-mode support, functions, structures, checksumming, etc. Signed-off-by: Simon Glass <sjg@chromium.org> |
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714497e3 |
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16-May-2020 |
Michael Walle <michael@walle.cc> |
efi_loader: round the memory area in efi_add_memory_map() Virtually all callers of this function do the rounding on their own. Some do it right, some don't. Instead of doing this in each caller, do the rounding in efi_add_memory_map(). Change the size parameter to bytes instead of pages and remove aligning and size calculation in all callers. There is no more need to make the original efi_add_memory_map() (which takes pages as size) available outside the module. Thus rename it to efi_add_memory_map_pg() and make it static to prevent further misuse outside the module. Signed-off-by: Michael Walle <michael@walle.cc> Add missing comma in sunxi_display.c. Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de> |
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6eb32a03 |
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23-Apr-2020 |
Madalin Bucur <madalin.bucur@oss.nxp.com> |
driver: net: fm: add DM ETH support Probe the FMan MACs based on the device tree while retaining the legacy code/functionality. One notable change introduced here is that, for DM_ETH, the name of the interfaces is corrected to the fmX-macY format, that avoids the referral to the MAC block names which were incorrect for FMan v3 devices (i.e. DTSEC, TGEC) and had weird formatting (i.e. FM1@DTSEC6, FM1@TGEC1). The legacy code is left unchanged in this respect. Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
6ebd4883 |
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27-Apr-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
fsl-layerscape: Add RESV_RAM check in resv_ram addr The initialization of gd->arch.resv_ram pointer should depend on if the RESV_RAM config is enabled. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Wasim Khan <wasim.khan@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
0d9d557d |
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10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
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db41d65a |
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28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move hang() to the same header as panic() At present panic() is in the vsprintf.h header file. That does not seem like an obvious choice for hang(), even though it relates to panic(). So let's put hang() in its own header. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Migrate a few more files] Signed-off-by: Tom Rini <trini@konsulko.com> |
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9b4a205f |
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28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move RAM-sizing functions to init.h These functions relate to memory init so move them into the init header. Signed-off-by: Simon Glass <sjg@chromium.org> |
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3499dd03 |
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27-Nov-2019 |
Alex Marginean <alexandru.marginean@nxp.com> |
ls1028a: Configure stream IDs for integrated PCI and fix up Linux DT Hardware comes out of reset with implicit values, but these are outside the accepted range for Layerscape gen 3 chassis spec used on LS1028A. Allocate different IDs and fix up Linux DT to use them. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
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b5981474 |
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14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some CPU functions out of common.h These functions belong in cpu_func.h since they do not use driver model. Move them over. Don't bother adding comments since these functions should be deleted. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
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68a6aa85 |
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14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move mii_init() function out of common.h This function belongs in mii.h so move it over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
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2189d5f1 |
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14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
Move strtomhz() to vsprintf.h At present this function sits in its own file but it does not really justify it. There are similar string functions in vsprintf.h, so move it there. Also add the missing function comment. Use the vsprintf.h include file explicitly where needed. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
812ff53c |
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30-Oct-2019 |
Pankaj Bansal <pankaj.bansal@nxp.com> |
fsl-layerscape: fix warning if no hwconfig is defined While getting the 'subarg' of 'hwconfig' env variable in config_core_prefetch(), if no hwconfig variable is defined, below warning is received: WARNING: Calling __hwconfig without a buffer and before environment is ready Fix this by checking 'hwconfig' env variable. If not found return without further processing. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Tested-by: Michael Walle <michael@walle.cc> |
#
28f9393b |
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17-Oct-2019 |
Mathew McBride <matt@traverse.com.au> |
fsl-layerscape: do not use layerscape EFI reset if PSCI used If the secure world reset handlers are used (via CONFIG_PSCI_RESET), then do not use the layerscape-specific implementation. Signed-off-by: Mathew McBride <matt@traverse.com.au> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
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6ed69523 |
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18-Sep-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add more personalities support Add LS1027A, LS1018A and LS1017A personalities support to LS1028A SoC family. LS1028A is the prime personality of LS1028A SoC family. LS1027A is a lower funtionality version of QorIQ LS1028A which does not support the multimedia subsystems, such as LCD controller, GPU, and eDP PHY. The QorIQ LS1018A and LS1017A SoCs are single 64-bit Arm A72 core, low power versions of the QorIQ LS1028A and LS1027A SoCs respectively. Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
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0490cab5 |
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08-Aug-2019 |
Thomas Schaefer <thomas.schaefer@kontron.com> |
armv8: ls1028a: configure PMU's PCTBENR to enable WDT The SP805-WDT module on LS1028A requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. The watchdog clock needs to be enabled first. Signed-off-by: Thomas Schaefer <thomas.schaefer@kontron.com> Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
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f3998fdc |
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02-Aug-2019 |
Simon Glass <sjg@chromium.org> |
env: Rename environment.h to env_internal.h This file contains lots of internal details about the environment. Most code can include env.h instead, calling the functions there as needed. Rename this file and add a comment at the top to indicate its internal nature. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> [trini: Fixup apalis-tk1.c] Signed-off-by: Tom Rini <trini@konsulko.com> |
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3a7d5571 |
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01-Aug-2019 |
Simon Glass <sjg@chromium.org> |
env: Move env_get_f() to env.h Move this function over to the new header file. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
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d9532e80 |
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23-Apr-2019 |
Udit Agarwal <udit.agarwal@nxp.com> |
armv8: fsl-layerscape: Set env_loc to ENVL_NOWHERE with CONFIG_ENV_IS_NOWHERE. ENVL_NOWHERE is dependent on CONFIG_ENV_IS_NOWHERE and not on CONFIG_CHAIN_OF_TRUST so return ENVL_NOWHERE when CONFIG_ENV_IS_NOWHERE is enabled Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
d4ad111d |
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10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
059d9422 |
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08-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: lx2160a: add MMU table entries for PCIe The lx2160a have up to 6 PCIe controllers and have different address and size of PCIe region. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
8348e798 |
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08-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: layerscape: use PCIe address macro for precompile PCIe MMU entry Change to use PCIe address macro to determine if precompile the PCIe MMU table entry. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
10015025 |
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03-May-2019 |
Trevor Woerner <trevor@toganlabs.com> |
CONFIG_SPL_SYS_[DI]CACHE_OFF: add While converting CONFIG_SYS_[DI]CACHE_OFF to Kconfig, there are instances where these configuration items are conditional on SPL. This commit adds SPL variants of these configuration items, uses CONFIG_IS_ENABLED(), and updates the configurations as required. Acked-by: Alexey Brodkin <abrodkin@synopsys.com> Signed-off-by: Trevor Woerner <trevor@toganlabs.com> [trini: Make the default depend on the setting for full U-Boot, update more zynq hardware] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
2e53759d |
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29-Oct-2018 |
Pankaj Bansal <pankaj.bansal@nxp.com> |
armv8: fsl-layerscape: reorder rgmii dpmacs' enablement some dpmacs in armv8a based freescale layerscape SOCs can be configured via both serdes(sgmii, xfi, xlaui etc) bits and via EC*_PMUX(rgmii) bits in RCW. e.g. dpmac 17 and 18 in LX2160A can be configured as SGMII from serdes bits and as RGMII via EC1_PMUX/EC2_PMUX bits Now if a dpmac is enabled by serdes bits then it takes precedence over EC*_PMUX bits. i.e. in LX2160A if we select serdes protocol that configures dpmac17 as SGMII and set the EC1_PMUX as RGMII, then the dpmac is SGMII and not RGMII. Therefore, move the fsl_rgmii_init after fsl_serdes_init. in fsl_rgmii_init function of SOC, we will check if the dpmac is enabled or not? if it is (fsl_serdes_init has already enabled the dpmac), then don't enable it. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
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ec88ff80 |
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19-Dec-2018 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1043a: add SVR definitions for 23x23 package silicon LS1043A/LS1023A 23x23 package silicon has different SVR:VAR_PER. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
d23da2ae |
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26-Dec-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: fixes for TFABOOT framework Fixes for TFABOOT framework - update eMMC bootsrc to SD_MMC - Increase buffer size for mcinitcmd from 256 to 512 - Fix mcinitcmd and bootcmd for Secure Boot Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
4909b89e |
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29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
d6fdec21 |
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29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8:fsl-layerscape: Add support for Chassis 3.2 NXP layerscape architecture Chassis 3.2 builds upon chassis3 architecture with changes like DDR Memory map change, removal of IFC and support of upto 8 I2C controller. Patch add README.lsch3_2 and the above changes under macro CONFIG_NXP_LSCH3_2. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
56db948b |
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05-Nov-2018 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: Update parsing boot source Workaround of erratum A010539 clears the RCW source field in PORSR1 register, causing failure of detecting boot source using this method. Use SMC call if U-Boot runs at EL2. If SMC is not implemented or running at EL3, continue to read PORSR1 and presume QSPI as boot source if erratum workaround A010539 is enabled and RCW source is cleared. Signed-off-by: York Sun <york.sun@nxp.com> |
#
681d489e |
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05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: layerscape: add SMC calls for DDR size and bank info Adds SMC calls for getting DDR size and bank info for TFABOOT. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
2141d250 |
|
05-Nov-2018 |
Pankit Garg <pankit.garg@nxp.com> |
armv8: fsl-layerscape: bootcmd identification for TFABOOT Adds bootcmd identificaton on basis on boot source, valid in TFABOOT configuration. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> [YS: remove unnecessary braces] Reviewed-by: York Sun <york.sun@nxp.com> |
#
4c417384 |
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05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com> |
#
535d76a1 |
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05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: layerscape: Add TFABOOT support Adds TFABOOT support config option and add generic code to enable execution from DDR. Signed-off-by: York Sun <york.sun@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> |
#
e3506480 |
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05-Nov-2018 |
Pankit Garg <pankit.garg@nxp.com> |
armv8: fsl-layerscape: change tlb base from OCRAM to DDR in EL < 3 Change tlb base address from OCRAM to DDR when exception level is less than 3. Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
d171c707 |
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05-Nov-2018 |
York Sun <york.sun@nxp.com> |
move data structure out of cpu.h Move static definitions to cpu.c file, as it doesn't allow the cpu.h file to be included in multiple c files. Signed-off-by: York Sun <york.sun@nxp.com> |
#
9b5e6396 |
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30-Aug-2018 |
Stephen Warren <swarren@nvidia.com> |
efi_loader: simplify ifdefs Use CONFIG_IS_ENABLED(EFI_LOADER) to avoid explicitly checking CONFIG_SPL too. This simplifies the conditional. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Alexander Graf <agraf@suse.de> |
#
9cce5663 |
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16-Jul-2018 |
Joe Hershberger <joe.hershberger@ni.com> |
arm: Prevent redefinition error in fsl-layerscape The include/phy.h will start including dm.h, which pulls in linux/compat.h after the attempted redefinition in arch/arm/include/asm/armv8/mmu.h, so move this include to allow redefinition. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> |
#
83d290c5 |
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06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
482fc90c |
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06-Feb-2018 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
efi_loader: add missing EFI_RESET_PLATFORM_SPECIFIC EFI_RESET_PLATFORM_SPECIFIC is one of the values that can be used for the EFI service ResetSystem. The missing definition is added. The value has to handled in efi_reset_system(). Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Alexander Graf <agraf@suse.de> |
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22c793e6 |
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03-Mar-2018 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
efi_loader: exit status for efi_reset_system_init efi_reset_system_init provides the architecture or board specific initialization of the EFI subsystem. Errors should be caught and signalled by a return code. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Alexander Graf <agraf@suse.de> |
#
958b2ed5 |
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09-Jan-2018 |
Zhang Ying-22455 <ying.zhang22455@nxp.com> |
armv8/ls1088a: configure PMU's PCTBENR to enable WDT The SP805-WDT module on LS1088A requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. The watchdog clock needs to be enabled first. Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
44262327 |
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15-Dec-2017 |
Ahmed Mansour <ahmed.mansour@nxp.com> |
drivers/misc: Share qbman init between archs This patch adds changes necessary to move functionality present in PowerPC folders with ARM architectures that have DPAA1 QBMan hardware - Create new board/freescale/common/fsl_portals.c to house shared device tree fixups for DPAA1 devices with ARM and PowerPC cores - Add new header file to top includes directory to allow files in both architectures to grab the function prototypes - Port inhibit_portals() from PowerPC to ARM. This function is used in setup to disable interrupts on all QMan and BMan portals. It is needed because the interrupts are enabled by default for all portals including unused/uninitialised portals. When the kernel attempts to go to deep sleep the unused portals prevent it from doing so Signed-off-by: Ahmed Mansour <ahmed.mansour@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
a8f33034 |
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03-Dec-2017 |
Wenbin song <wenbin.song@nxp.com> |
armv8: ls1043a/ls2080a: check SoC by device ID Check LS1043A/LS2080a by device ID without using personality ID to determine revision number. This check applies to all various personalities of the same SoC family. Signed-off-by: Wenbin Song <wenbin.song@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
2db53cfe |
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09-Nov-2017 |
Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
armv8: fsl-layerscape: Add support of disabling core prefetch Instruction prefetch feature is by default enabled during core release. This patch add support of disabling instruction prefetch by setting core mask in PPA. Here each core mask bit represents a core and prefetch is disabled at the time of core release. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
7eb40f0f |
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28-Sep-2017 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: Avoid running dram_init_banksize again gd->ram_size is reduced in this function to reserve secure memory. Avoid running this function again to further reduce memory size. This fixes issue for SPL boot with PPA image loaded in which case secure memory is incorrectly allocated due to repeated calling. Signed-off-by: York Sun <york.sun@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
710d0cd7 |
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03-Oct-2017 |
Sumit Garg <sumit.garg@nxp.com> |
armv8: fsl-layerscape: Allocate Secure memory from first ddr region This change is required due to trusted OS (OP-TEE) not being position independent code, it requires compile time fixed base address. To take care of this it is assumed that all layerscape armv8 platforms has minimum 2G ddr in first region. So we can have fixed address space (66 MB -> (2MB for PPA + 64MB for trusted OS)) allocated from top of first 2G ddr region and compile trusted OS with this fixed base address. But one exception here is ls1012 where we have only 1G (rdb) or 512M (frdm) ddr memory. For those we can have different fixed compile time base addresses for trusted OS. Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
e9303a41 |
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07-Sep-2017 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: Fix MC reserved memory calculation In case high region memory doesn't have enough space for Management Complex (MC), the return value should indicate a failure so the caller can handle it accordingly. Signed-off-by: York Sun <york.sun@nxp.com> Reported-by: Ebony Zhu <ebony.zhu@nxp.com> |
#
17d066fc |
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31-Aug-2017 |
Ashish Kumar <Ashish.Kumar@nxp.com> |
armv8: fsl-layerscape: Support to add RGMII for ls1088aqds This patch adds support for RGMII protocol NXP's LDPAA2 support RGMII protocol. LS1088A is the first Soc supporting both RGMII and SGMII. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Amrita Kumari <amrita.kumari@nxp.com> Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
63b2316c |
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10-Aug-2017 |
Ashish Kumar <Ashish.Kumar@nxp.com> |
fsl-layerscape: Consolidate registers space defination for CCI-400 bus CoreLink Cache Coherent Interconnect (CCI) provides full cache coherency between two clusters of multi-core CPUs and I/O coherency for devices and I/O masters. This patch add new config option SYS_FSL_HAS_CCI400 and moves existing register space definaton of CCI-400 bus to fsl_immap to be shared. CONFIG_SYS_CCI400_ADDR is replaced with SYS_CCI400_OFFSET in Kconfig. Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> [YS: revised commit message, squashed patches for armv8 and armv7] Reviewed-by: York Sun <york.sun@nxp.com> |
#
6e2941d7 |
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17-May-2017 |
Simon Glass <sjg@chromium.org> |
common: freescale: Move arch-specific declarations The declarations should not be in common.h. Move them to the arch-specific headers. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Fixup thinko defined(FSL_LSCH3) -> defined(CONFIG_FSL_LSCH3)] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
399e2bb6 |
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15-May-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Make U-Boot EL2 safe When U-Boot boots from EL2, skip some lowlevel init code requiring EL3, including CCI-400/CCN-504, trust zone, GIC, etc. These initialization tasks are carried out before U-Boot runs. This applies to the RAM version image used for SPL boot if PPA is loaded first. Signed-off-by: York Sun <york.sun@nxp.com> |
#
1f55a938 |
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05-May-2017 |
Santan Kumar <santan.kumar@nxp.com> |
armv8: ls2080aqds: Add support for SD boot Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
e809e747 |
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27-Apr-2017 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: fsl-layerscape: Add NXP LS2081A, LS2041A SoC support The QorIQ LS2081A SoC has eight 64-bit ARM v8 Cortex A72 cores and is built on layerscape architecture. It is 40-pin derivative of LS2084A (non-AIOP personality of LS2088A). So feature-wise it is same as LS2084A. LS2041A is a 4-core personality of LS2081A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
026f30ec |
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18-Apr-2017 |
Yuantian Tang <andy.tang@nxp.com> |
arm: psci: make psci usable on single core socs PSCI can be used on both multiple and single core socs. Current implementation only allows PSCI to work on multiple core socs. This patch removes this restriction so that PSCI can work on single core socs as well. Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
4a3ab193 |
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27-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: ls2080a: Drop macro CONFIG_LS2080A Use CONFIG_ARCH_LS2080A instead. Signed-off-by: York Sun <york.sun@nxp.com> |
#
3eace37e |
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06-Apr-2017 |
Simon Glass <sjg@chromium.org> |
arm: freescale: Rename initdram() to fsl_initdram() This function name shadows a global name but is in fact different. This is very confusing. Rename it to help with the following refactoring. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
76b00aca |
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31-Mar-2017 |
Simon Glass <sjg@chromium.org> |
board_f: Drop setup_dram_config() wrapper By making dram_init_banksize() return an error code we can drop the wrapper. Adjust this and clean up all implementations. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
088454cd |
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31-Mar-2017 |
Simon Glass <sjg@chromium.org> |
board_f: Drop return value from initdram() At present we cannot use this function as an init sequence call without a wrapper, since it returns the RAM size. Adjust it to set the RAM size in global_data instead, and return 0 on success. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
52c41180 |
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31-Mar-2017 |
Simon Glass <sjg@chromium.org> |
board_f: Drop board_type parameter from initdram() It looks like only cm5200 and tqm8xx use this feature, so we don't really need it in generic code. Drop it and have the users access gd->board_type directly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
3d8553f0 |
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02-Mar-2017 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
pci: layerscape: add LS2088A series SoC pcie support The LS2088A series SoCs has different physical memory map address and CCSR registers address against LS2080A series SoCs. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
eea1cb77 |
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13-Feb-2017 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8/fsl-layerscape: Update erratum A009635 implementation Erratum A009635 is valid only for LS2080A SoC and its personality. Add SoC svr check. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
4961eafc |
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06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Update early MMU for DDR after initialization In early MMU table, DDR has to be mapped as device memory to avoid speculative access. After DDR is initialized, it needs to be updated to normal memory to allow code execution. To simplify the code, dram_init() is moved into a common file as a weak function. Signed-off-by: York Sun <york.sun@nxp.com> |
#
a045a0c3 |
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06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Fix the sequence of changing MMU table This patch follows the break-before-make process when making changes to MMU table. MMU is disabled before changing TTBR to avoid any potential race condition. Signed-off-by: York Sun <york.sun@nxp.com> |
#
24f55496 |
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06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Update MMU mapping with actual DDR size Update mapping with actual DDR size. Non-existing memory should not be mapped as "normal" memory to avoid speculative access. Signed-off-by: York Sun <york.sun@nxp.com> |
#
36cc0de0 |
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06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Rewrite memory reservation For ARMv8 Layerscape SoCs, secure memory and MC memorey are reserved at the end of DDR. DDR is spit into two or three banks. This patch reverts commit aabd7ddb and simplifies the calculation of reserved memory, and moves the code into common SoC file. Secure memory is carved out first. DDR bank size is reduced. Reserved memory is then allocated on the top of available memory. U-Boot still has access to reserved memory as data transferring is needed. Device tree is fixed with reduced memory size to hide the reserved memory from OS. The same region is reserved for efi_loader. Signed-off-by: York Sun <york.sun@nxp.com> |
#
daa92644 |
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16-Jan-2017 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
ARMv8/sec_firmware: relocated and renamed the config FSL_PPA_ARMV8_PSCI Moved the config FSL_PPA_ARMV8_PSCI from fsl-layerscape's Kconfig to Kconfig under armv8 and renamed it to SEC_FIRMWARE_ARMV8_PSCI. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
904110c7 |
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10-Jan-2017 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8/fsl-lsch2: refactor the clock system initialization Up to now, there are 3 kind of SoCs under Layerscape Chassis 2, like LS1043A, LS1046A and LS1012A. But the clocks tree has a lot of differences, for instance, the IP modules have different dividers to derive its clock from Platform PLL. And the core cluster PLL and platform PLL maybe have different reference clocks, such as LS1012A. Another problem is which clock/PLL should be described by sys_info->freq_systembus, it is confused in Layerscape Chissis 2. This patch is to bind the sys_info->freq_systembus to the Platform PLL, and handle the different divider of IP modules separately between different SoCs, and separate reference clocks of core cluster PLL and platform PLL. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
2d16a1a6 |
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07-Dec-2016 |
macro.wave.z@gmail.com <macro.wave.z@gmail.com> |
ARMv8: LS1043A: change macro CONFIG_ARMV8_PSCI definition NXP/Freescale uses macro CONFIG_ARMV8_PSCI to enable their private PSCI implementation in PPA firmware, but this macro naming too generic, so this patch replaces it with a specic one CONFIG_FSL_PPA_ARMV8_PSCI. And this macro CONFIG_ARMV8_PSCI will be used for a generic PSCI for ARMv8 which will be added in following patchs. Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
02fb2761 |
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20-Nov-2016 |
Shengzhou Liu <Shengzhou.Liu@nxp.com> |
fsl/ddr: Add erratum_a009942_check_cpo and clean related erratum - add additional function erratum_a009942_check_cpo to check if the board needs tuning CPO calibration for optimal setting. - move ERRATUM_A009942(with revision to check cpo_sample option) from fsl_ddr_gen4.c to ctrl_regs.c for reuse on all DDR4/DDR3 parts. - move ERRATUM_A008378 from fsl_ddr_gen4.c to ctrl_regs.c - remove obsolete ERRATUM_A004934 which is replaced with ERRATUM_A009942. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> [YS: Replaced CONFIG_QEMU_E500 with CONFIG_ARCH_QEMU_E500] Reviewed-by: York Sun <york.sun@nxp.com> |
#
e87c673c |
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16-Nov-2016 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8/fsl-lsch3: Update code to release secondary cores NXP ARMv8 SoC LS2080A release all secondary cores in one-go. But other new SoCs like LS2088A, LS1088A release secondary cores one by one. Update code to release secondary cores based on SoC SVR Add code to release cores one by one for non LS2080A SoCs Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> [YS: remove "inline" from declaration of initiator_type] Reviewed-by: York Sun <york.sun@nxp.com> |
#
f6b96ff6 |
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16-Nov-2016 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Use SVR based timer base address detection Timer controller base address has been changed from LS2080A SoC (and its personalities) to new SoCs like LS2088A, LS1088A. Use SVR based timer base address detection to avoid compile time #ifdef. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
f6a70b3a |
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16-Nov-2016 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add generic get_svr() in assembly Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
78d57842 |
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16-Nov-2016 |
Alexander Graf <agraf@csgraf.de> |
armv8: fsl-layerscape: Add support for efi_loader RTS reset When implementing efi loader support, we can expose runtime services for payloads. One such service is CPU reset. This patch implements RTS CPU reset support for layerscape systems. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: York Sun <york.sun@nxp.com> |
#
ef9a5fd8 |
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13-Sep-2016 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: Fix "cpu status" command The core position is not continuous for some SoCs. For example, valid cores may present at position 0, 1, 4, 5, 8, 9, etc. Some registers (including boot release register) only count existing cores. Current implementation of cpu_mask() complies with the continuous numbering. However, command "cpu status" queries the spin table with actual core position. Add functions to calculate core position from core number, to correctly calculate offsets. Tested on LS2080ARDB and LS1043ARDB. Signed-off-by: York Sun <york.sun@nxp.com> |
#
5d1a7a9d |
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13-Sep-2016 |
Wenbin Song <wenbin.song@nxp.com> |
armv8/fsl-layerscape: print SoC revsion number The exact SoC revsion number can be recognized from U-Boot log. Signed-off-by: Wenbin Song <wenbin.song@nxp.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
cbe7706a |
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26-Sep-2016 |
Tom Rini <trini@konsulko.com> |
Merge git://git.denx.de/u-boot-fsl-qoriq trini: Drop local memset() from examples/standalone/mem_to_mem_idma2intr.c Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
1221ce45 |
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20-Sep-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
treewide: replace #include <asm/errno.h> with <linux/errno.h> Now, arch/${ARCH}/include/asm/errno.h and include/linux/errno.h have the same content. (both just wrap <asm-generic/errno.h>) Replace all include directives for <asm/errno.h> with <linux/errno.h>. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> [trini: Fixup include/clk.] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
b63a9506 |
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03-Aug-2016 |
York Sun <york.sun@nxp.com> |
armv8: ls2080a: Remove debug server support Debug server feature has been dropped from roadmap. Signed-off-by: York Sun <york.sun@nxp.com> |
#
ed7a3943 |
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22-Jul-2016 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: mmu: Fix enabling MMU MMU bit in SCTLR needs to be set explicitly after tables are created. It isn't an issue for EL3 becuase this bit is already set by early MMU setup. But for other exception levels this bit was not set. Signed-off-by: York Sun <york.sun@nxp.com> |
#
79119a4d |
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05-Jul-2016 |
Alison Wang <b18965@freescale.com> |
armv8: fsl-layerscape: Add A72 core detection Add support to detect Cortex-A72 core for printing it out. The Initiator Version of A72 core should be 0x4. Signed-off-by: Alison Wang <alison.wang@nxp.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
032d5bb4 |
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28-Jun-2016 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
ARMv8/Layerscape: switch SMP method accordingly If the PSCI and PPA is ready, skip the fixup for spin-table and waking secondary cores. Otherwise, change SMP method to spin-table, and the device node of PSCI will be removed. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
85cdf38e |
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28-Jun-2016 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: fsl-layerscape: add i/d-cache enable function to enable_caches This function assume that the d-cache and MMU has been enabled earlier, so it just created MMU table in main memory. But the assumption is not always correct, for example, the early setup is done in EL3, while enable_caches() is called when the PE has turned into another EL. Define the function mmu_setup() for fsl-layerscape to cover the weak one. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
5ad5823d |
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24-Jun-2016 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Convert to use common MMU framework Drop platform code to create static MMU tables. Use common framework to create MMU tables on the run. Tested on LS2080ARDB with secure and non-secure ram scenarios. Signed-off-by: York Sun <york.sun@nxp.com> |
#
e61a7534 |
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24-Jun-2016 |
York Sun <york.sun@nxp.com> |
armv8: Move secure_ram variable out of generic global data Secure_ram variable was put in generic global data. But only ARMv8 uses this variable. Move it to ARM specific data structure. Signed-off-by: York Sun <york.sun@nxp.com> |
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a10a31ec |
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18-Jun-2016 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of git://git.denx.de/u-boot-usb Signed-off-by: Tom Rini <trini@konsulko.com> Conflicts: arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
|
#
6fb522dc |
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12-Jun-2016 |
Sriram Dash <sriram.dash@nxp.com> |
arm64: fsl-layerscape: add get_svr and IS_SVR_REV helper Adds get_svr and IS_SVR_REV helpers for ARMv8 platforms, similar to PPC and ARMv7. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> |
#
a758177f |
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07-Jun-2016 |
Yunhui Cui <yunhui.cui@nxp.com> |
armv8/ls2080a: configure PMU's PCTBENR to enable WDT The SP805-WDT module on LS2080A requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. The watchdog clock needs to be enabled first. Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
acb8f5e9 |
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21-Apr-2016 |
Alison Wang <b18965@freescale.com> |
armv8: fsl-layerscape: Remove unnecessary flushing dcache As the issue about the stack will get corrupted when switching between the early and final mmu tables is fixed by commit 70e21b064, the workaround to flush dcache is unnecessary and should be removed. Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
3c1d218a |
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04-Apr-2016 |
York Sun <york.sun@nxp.com> |
armv8: LS2080A: Consolidate LS2080A and LS2085A LS2080A is the primary SoC, and LS2085A is a personality with AIOP and DPAA DDR. The RDB and QDS boards support both personality. By detecting the SVR at runtime, a single image per board can support both SoCs. It gives users flexibility to swtich SoC without the need to reprogram the board. Signed-off-by: York Sun <york.sun@nxp.com> CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
c05016ab |
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21-Mar-2016 |
Alexander Graf <agraf@csgraf.de> |
arm64: Fix layerscape mmu setup With commit 7985cdf we converted all systems except for the Layerscape SoCs to the generic descriptor table based page table setup. On the Layerscape SoCs however, we just provide an empty table stub and do the setup ourselves. To reserve enough memory for the tables, we need to override the default counting mechanism which would end up with an empty table because we have no maps. Fixes: 7985cdf Reported-by: York Sun <york.sun@nxp.com> CC: Alison Wang <alison.wang@nxp.com> CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Alexander Graf <agraf@suse.de> Tested-by: York Sun <york.sun@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
7985cdf7 |
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03-Mar-2016 |
Alexander Graf <agraf@csgraf.de> |
arm64: Remove non-full-va map code By now the code to only have a single page table level with 64k page size and 42 bit address space is no longer used by any board in tree, so we can safely remove it. To clean up code, move the layerscape mmu code to the new defines, removing redundant field definitions. Signed-off-by: Alexander Graf <agraf@suse.de> |
#
c0492141 |
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07-Dec-2015 |
York Sun <yorksun@freescale.com> |
armv8: fsl-layerscale: Rewrite reserving memory for MC and debug server MC and debug server are not board-specific. Move reserving memory to SoC file, using the new board_reserve_ram_top function. Reduce debug server memory by 2MB to make room for secure memory. In the system with MC and debug server, the top of u-boot memory is not the end of memory. PRAM is not used for this reservation. Signed-off-by: York Sun <yorksun@freescale.com> |
#
c107c0c0 |
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04-Dec-2015 |
York Sun <yorksun@freescale.com> |
armv8: fsl-layerscape: Make DDR non secure in MMU tables DDR has been set as secure in MMU tables. Non-secure master such as SDHC DMA cannot access data correctly. Mixing secure and non- secure MMU entries requirs the MMU tables themselves in secure memory. This patch moves MMU tables into a secure DDR area. Early MMU tables are changed to set DDR as non-secure. A new table is added into final MMU tables so secure memory can have 2MB granuality. gd->secure_ram tracks the location of this secure memory. For ARMv8 SoCs, the RAM base is not zero and RAM is divided into several banks. gd->secure_ram needs to be maintained before using. This maintenance is board-specific, depending on the SoC and memory bank of the secure memory falls into. Signed-off-by: York Sun <yorksun@freescale.com> |
#
b4017364 |
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04-Nov-2015 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
armv8: ls2085a: Add workaround of errata A009635 If the core runs at higher than x3 speed of the platform, there is possiblity about sev instruction to getting missed by other cores. This is because of SoC Run Control block may not able to sample the EVENTI(Sev) signals. Configure Run Control and EPU to periodically send out EVENTI signals to wake up A57 cores. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
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d764129d |
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04-Nov-2015 |
Alison Wang <b18965@freescale.com> |
armv8/layerscape: Update MMU table with execute-never bits For most device addresses excution shouldn't be allowed. Revise the MMU table to enforce execute-never bits. OCRAM, DDR and IFC are allowed for excution. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Alison Wang <alison.wang@freescale.com> Reported-by: Zhichun Hua <zhichun.hua@freescale.com> |
#
44937214 |
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09-Nov-2015 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
armv8: LS2080A: Rename LS2085A to reflect LS2080A LS2080A is a prime personality of Freescale’s LS2085A. It is a non-AIOP personality without support of DP-DDR, L2 switch, 1588, PCIe endpoint etc. So renaming existing LS2085A code base to reflect LS2080A (Prime personality) Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> [York Sun: Dropped #ifdef in cpu.c for cpu_type_list] Reviewed-by: York Sun <yorksun@freescale.com> |
#
e8297341 |
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26-Oct-2015 |
Shaohui Xie <Shaohui.Xie@freescale.com> |
armv8/ls1043a: Add Fman support Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
8281c58f |
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26-Oct-2015 |
Mingkai Hu <Mingkai.Hu@freescale.com> |
armv8/fsl_lsch2: Add fsl_lsch2 SoC Freescale LayerScape with Chassis Generation 2 is a set of SoCs with ARMv8 cores and 2rd generation of Chassis. Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
9f3183d2 |
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26-Oct-2015 |
Mingkai Hu <Mingkai.Hu@freescale.com> |
armv8/fsl_lsch3: Change arch to fsl-layerscape There are two LS series processors are built on ARMv8 Layersacpe architecture currently, LS2085A and LS1043A. They are based on ARMv8 core although use different chassis, so create fsl-layerscape to refactor the common code for the LS series processors which also paves the way for adding LS1043A platform. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
2f8a6db5 |
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14-Dec-2021 |
Tom Rini <trini@konsulko.com> |
Finish conversion of CONFIG_SYS_CLK_FREQ to Kconfig In order to finish moving this symbol to Kconfig for all platforms, we need to do a few more things. First, for all platforms that define this to a function, introduce CONFIG_DYNAMIC_SYS_CLK_FREQ, similar to CONFIG_DYNAMIC_DDR_CLK_FREQ and populate clock_legacy.h. This entails also switching all users from CONFIG_SYS_CLK_FREQ to get_board_sys_clk() and updating a few preprocessor tests. With that done, all platforms that define a value here can be converted to Kconfig, and a fall-back of zero is sufficiently safe to use (and what is used today in cases where code may or may not have this available). Make sure that code which calls this function includes <clock_legacy.h> to get the prototype. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
77b11f76 |
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18-Sep-2021 |
Vladimir Oltean <vladimir.oltean@nxp.com> |
net: replace the "xfi" phy-mode with "10gbase-r" As part of the effort of making U-Boot work with the same device tree as Linux, there is an issue with the "xfi" phy-mode. To be precise, in Linux there was a discussion (for those who have time to read: https://lore.kernel.org/netdev/1576768881-24971-2-git-send-email-madalin.bucur@oss.nxp.com/) which led to a patch: https://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next.git/commit/?id=c114574ebfdf42f826776f717c8056a00fa94881 TL;DR: "xfi" was standardized in Linux as "10gbase-r". This patch changes the relevant occurrences in U-Boot to use "10gbase-r" instead of "xfi" wherever applicable. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> |
#
84c2e044 |
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20-Apr-2021 |
Jiafei Pan <Jiafei.Pan@nxp.com> |
armv8: layerscape: add PSCI support for cpu release For cpu release command, check whether PSCI is supported firstly, if supported, use PSCI to kick off secondary cores, otherwise still use spin table. Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com> [Fixed checkpatch alignment CHECKs] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
35b65dd8 |
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15-Dec-2020 |
Harald Seiler <hws@denx.de> |
reset: Remove addr parameter from reset_cpu() Historically, the reset_cpu() function had an `addr` parameter which was meant to pass in an address of the reset vector location, where the CPU should reset to. This feature is no longer used anywhere in U-Boot as all reset_cpu() implementations now ignore the passed value. Generic code has been added which always calls reset_cpu() with `0` which means this feature can no longer be used easily anyway. Over time, many implementations seem to have "misunderstood" the existence of this parameter as a way to customize/parameterize the reset (e.g. COLD vs WARM resets). As this is not properly supported, the code will almost always not do what it is intended to (because all call-sites just call reset_cpu() with 0). To avoid confusion and to clean up the codebase from unused left-overs of the past, remove the `addr` parameter entirely. Code which intends to support different kinds of resets should be rewritten as a sysreset driver instead. This transformation was done with the following coccinelle patch: @@ expression argvalue; @@ - reset_cpu(argvalue) + reset_cpu() @@ identifier argname; type argtype; @@ - reset_cpu(argtype argname) + reset_cpu(void) { ... } Signed-off-by: Harald Seiler <hws@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
401d1c4f |
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30-Oct-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop asm/global_data.h from common header Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
3a187cff |
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29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
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c760095a |
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23-Oct-2020 |
Razvan Ionut Cirjan <razvanionut.cirjan@nxp.com> |
net: lx2160a.c: Update to set ECx_PMUX precedence As per hardware documentation, ECx_PMUX has precedence over SerDes protocol. For LX2160/LX2162 if DPMACs 17 and 18 are enabled as SGMII through SerDes protocol but ECx_PMUX configured them as RGMII, then the ports will be configured as RGMII and not SGMII. Signed-off-by: Razvan Ionut Cirjan <razvanionut.cirjan@nxp.com> [Rebased] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
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d31f3a1b |
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09-Sep-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2160a: fix reset sequence Make sure that SW_RST_REQ and RST_REQ_MSK are cleared before triggering hardware reset request. Signed-off-by: Thirupathaiah Annapureddy <thiruan@linux.microsoft.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
b75d8dc5 |
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26-Jun-2020 |
Masahiro Yamada <masahiroy@kernel.org> |
treewide: convert bd_t to struct bd_info by coccinelle The Linux coding style guide (Documentation/process/coding-style.rst) clearly says: It's a **mistake** to use typedef for structures and pointers. Besides, using typedef for structures is annoying when you try to make headers self-contained. Let's say you have the following function declaration in a header: void foo(bd_t *bd); This is not self-contained since bd_t is not defined. To tell the compiler what 'bd_t' is, you need to include <asm/u-boot.h> #include <asm/u-boot.h> void foo(bd_t *bd); Then, the include direcective pulls in more bloat needlessly. If you use 'struct bd_info' instead, it is enough to put a forward declaration as follows: struct bd_info; void foo(struct bd_info *bd); Right, typedef'ing bd_t is a mistake. I used coccinelle to generate this commit. The semantic patch that makes this change is as follows: <smpl> @@ typedef bd_t; @@ -bd_t +struct bd_info </smpl> Signed-off-by: Masahiro Yamada <masahiroy@kernel.org> |
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25a5818f |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop asm/ptrace.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
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f7ae49fc |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
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90526e9f |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop net.h from common header Move this header out of the common header. Network support is used in quite a few places but it still does not warrant blanket inclusion. Note that this net.h header itself has quite a lot in it. It could be split into the driver-mode support, functions, structures, checksumming, etc. Signed-off-by: Simon Glass <sjg@chromium.org> |
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714497e3 |
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16-May-2020 |
Michael Walle <michael@walle.cc> |
efi_loader: round the memory area in efi_add_memory_map() Virtually all callers of this function do the rounding on their own. Some do it right, some don't. Instead of doing this in each caller, do the rounding in efi_add_memory_map(). Change the size parameter to bytes instead of pages and remove aligning and size calculation in all callers. There is no more need to make the original efi_add_memory_map() (which takes pages as size) available outside the module. Thus rename it to efi_add_memory_map_pg() and make it static to prevent further misuse outside the module. Signed-off-by: Michael Walle <michael@walle.cc> Add missing comma in sunxi_display.c. Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de> |
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6eb32a03 |
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23-Apr-2020 |
Madalin Bucur <madalin.bucur@oss.nxp.com> |
driver: net: fm: add DM ETH support Probe the FMan MACs based on the device tree while retaining the legacy code/functionality. One notable change introduced here is that, for DM_ETH, the name of the interfaces is corrected to the fmX-macY format, that avoids the referral to the MAC block names which were incorrect for FMan v3 devices (i.e. DTSEC, TGEC) and had weird formatting (i.e. FM1@DTSEC6, FM1@TGEC1). The legacy code is left unchanged in this respect. Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
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6ebd4883 |
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27-Apr-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
fsl-layerscape: Add RESV_RAM check in resv_ram addr The initialization of gd->arch.resv_ram pointer should depend on if the RESV_RAM config is enabled. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Wasim Khan <wasim.khan@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
0d9d557d |
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10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
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db41d65a |
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28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move hang() to the same header as panic() At present panic() is in the vsprintf.h header file. That does not seem like an obvious choice for hang(), even though it relates to panic(). So let's put hang() in its own header. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Migrate a few more files] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
9b4a205f |
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28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move RAM-sizing functions to init.h These functions relate to memory init so move them into the init header. Signed-off-by: Simon Glass <sjg@chromium.org> |
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3499dd03 |
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27-Nov-2019 |
Alex Marginean <alexandru.marginean@nxp.com> |
ls1028a: Configure stream IDs for integrated PCI and fix up Linux DT Hardware comes out of reset with implicit values, but these are outside the accepted range for Layerscape gen 3 chassis spec used on LS1028A. Allocate different IDs and fix up Linux DT to use them. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
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b5981474 |
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14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some CPU functions out of common.h These functions belong in cpu_func.h since they do not use driver model. Move them over. Don't bother adding comments since these functions should be deleted. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
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68a6aa85 |
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14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move mii_init() function out of common.h This function belongs in mii.h so move it over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
2189d5f1 |
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14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
Move strtomhz() to vsprintf.h At present this function sits in its own file but it does not really justify it. There are similar string functions in vsprintf.h, so move it there. Also add the missing function comment. Use the vsprintf.h include file explicitly where needed. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
812ff53c |
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30-Oct-2019 |
Pankaj Bansal <pankaj.bansal@nxp.com> |
fsl-layerscape: fix warning if no hwconfig is defined While getting the 'subarg' of 'hwconfig' env variable in config_core_prefetch(), if no hwconfig variable is defined, below warning is received: WARNING: Calling __hwconfig without a buffer and before environment is ready Fix this by checking 'hwconfig' env variable. If not found return without further processing. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Tested-by: Michael Walle <michael@walle.cc> |
#
28f9393b |
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17-Oct-2019 |
Mathew McBride <matt@traverse.com.au> |
fsl-layerscape: do not use layerscape EFI reset if PSCI used If the secure world reset handlers are used (via CONFIG_PSCI_RESET), then do not use the layerscape-specific implementation. Signed-off-by: Mathew McBride <matt@traverse.com.au> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
6ed69523 |
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18-Sep-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add more personalities support Add LS1027A, LS1018A and LS1017A personalities support to LS1028A SoC family. LS1028A is the prime personality of LS1028A SoC family. LS1027A is a lower funtionality version of QorIQ LS1028A which does not support the multimedia subsystems, such as LCD controller, GPU, and eDP PHY. The QorIQ LS1018A and LS1017A SoCs are single 64-bit Arm A72 core, low power versions of the QorIQ LS1028A and LS1027A SoCs respectively. Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
0490cab5 |
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08-Aug-2019 |
Thomas Schaefer <thomas.schaefer@kontron.com> |
armv8: ls1028a: configure PMU's PCTBENR to enable WDT The SP805-WDT module on LS1028A requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. The watchdog clock needs to be enabled first. Signed-off-by: Thomas Schaefer <thomas.schaefer@kontron.com> Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
f3998fdc |
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02-Aug-2019 |
Simon Glass <sjg@chromium.org> |
env: Rename environment.h to env_internal.h This file contains lots of internal details about the environment. Most code can include env.h instead, calling the functions there as needed. Rename this file and add a comment at the top to indicate its internal nature. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> [trini: Fixup apalis-tk1.c] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
3a7d5571 |
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01-Aug-2019 |
Simon Glass <sjg@chromium.org> |
env: Move env_get_f() to env.h Move this function over to the new header file. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
d9532e80 |
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23-Apr-2019 |
Udit Agarwal <udit.agarwal@nxp.com> |
armv8: fsl-layerscape: Set env_loc to ENVL_NOWHERE with CONFIG_ENV_IS_NOWHERE. ENVL_NOWHERE is dependent on CONFIG_ENV_IS_NOWHERE and not on CONFIG_CHAIN_OF_TRUST so return ENVL_NOWHERE when CONFIG_ENV_IS_NOWHERE is enabled Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
d4ad111d |
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10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
059d9422 |
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08-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: lx2160a: add MMU table entries for PCIe The lx2160a have up to 6 PCIe controllers and have different address and size of PCIe region. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
8348e798 |
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08-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: layerscape: use PCIe address macro for precompile PCIe MMU entry Change to use PCIe address macro to determine if precompile the PCIe MMU table entry. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
10015025 |
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03-May-2019 |
Trevor Woerner <trevor@toganlabs.com> |
CONFIG_SPL_SYS_[DI]CACHE_OFF: add While converting CONFIG_SYS_[DI]CACHE_OFF to Kconfig, there are instances where these configuration items are conditional on SPL. This commit adds SPL variants of these configuration items, uses CONFIG_IS_ENABLED(), and updates the configurations as required. Acked-by: Alexey Brodkin <abrodkin@synopsys.com> Signed-off-by: Trevor Woerner <trevor@toganlabs.com> [trini: Make the default depend on the setting for full U-Boot, update more zynq hardware] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
2e53759d |
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29-Oct-2018 |
Pankaj Bansal <pankaj.bansal@nxp.com> |
armv8: fsl-layerscape: reorder rgmii dpmacs' enablement some dpmacs in armv8a based freescale layerscape SOCs can be configured via both serdes(sgmii, xfi, xlaui etc) bits and via EC*_PMUX(rgmii) bits in RCW. e.g. dpmac 17 and 18 in LX2160A can be configured as SGMII from serdes bits and as RGMII via EC1_PMUX/EC2_PMUX bits Now if a dpmac is enabled by serdes bits then it takes precedence over EC*_PMUX bits. i.e. in LX2160A if we select serdes protocol that configures dpmac17 as SGMII and set the EC1_PMUX as RGMII, then the dpmac is SGMII and not RGMII. Therefore, move the fsl_rgmii_init after fsl_serdes_init. in fsl_rgmii_init function of SOC, we will check if the dpmac is enabled or not? if it is (fsl_serdes_init has already enabled the dpmac), then don't enable it. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
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ec88ff80 |
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19-Dec-2018 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1043a: add SVR definitions for 23x23 package silicon LS1043A/LS1023A 23x23 package silicon has different SVR:VAR_PER. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
d23da2ae |
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26-Dec-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: fixes for TFABOOT framework Fixes for TFABOOT framework - update eMMC bootsrc to SD_MMC - Increase buffer size for mcinitcmd from 256 to 512 - Fix mcinitcmd and bootcmd for Secure Boot Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
4909b89e |
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29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
d6fdec21 |
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29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8:fsl-layerscape: Add support for Chassis 3.2 NXP layerscape architecture Chassis 3.2 builds upon chassis3 architecture with changes like DDR Memory map change, removal of IFC and support of upto 8 I2C controller. Patch add README.lsch3_2 and the above changes under macro CONFIG_NXP_LSCH3_2. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
56db948b |
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05-Nov-2018 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: Update parsing boot source Workaround of erratum A010539 clears the RCW source field in PORSR1 register, causing failure of detecting boot source using this method. Use SMC call if U-Boot runs at EL2. If SMC is not implemented or running at EL3, continue to read PORSR1 and presume QSPI as boot source if erratum workaround A010539 is enabled and RCW source is cleared. Signed-off-by: York Sun <york.sun@nxp.com> |
#
681d489e |
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05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: layerscape: add SMC calls for DDR size and bank info Adds SMC calls for getting DDR size and bank info for TFABOOT. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
2141d250 |
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05-Nov-2018 |
Pankit Garg <pankit.garg@nxp.com> |
armv8: fsl-layerscape: bootcmd identification for TFABOOT Adds bootcmd identificaton on basis on boot source, valid in TFABOOT configuration. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> [YS: remove unnecessary braces] Reviewed-by: York Sun <york.sun@nxp.com> |
#
4c417384 |
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05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com> |
#
535d76a1 |
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05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: layerscape: Add TFABOOT support Adds TFABOOT support config option and add generic code to enable execution from DDR. Signed-off-by: York Sun <york.sun@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> |
#
e3506480 |
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05-Nov-2018 |
Pankit Garg <pankit.garg@nxp.com> |
armv8: fsl-layerscape: change tlb base from OCRAM to DDR in EL < 3 Change tlb base address from OCRAM to DDR when exception level is less than 3. Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
d171c707 |
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05-Nov-2018 |
York Sun <york.sun@nxp.com> |
move data structure out of cpu.h Move static definitions to cpu.c file, as it doesn't allow the cpu.h file to be included in multiple c files. Signed-off-by: York Sun <york.sun@nxp.com> |
#
9b5e6396 |
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30-Aug-2018 |
Stephen Warren <swarren@nvidia.com> |
efi_loader: simplify ifdefs Use CONFIG_IS_ENABLED(EFI_LOADER) to avoid explicitly checking CONFIG_SPL too. This simplifies the conditional. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Alexander Graf <agraf@suse.de> |
#
9cce5663 |
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16-Jul-2018 |
Joe Hershberger <joe.hershberger@ni.com> |
arm: Prevent redefinition error in fsl-layerscape The include/phy.h will start including dm.h, which pulls in linux/compat.h after the attempted redefinition in arch/arm/include/asm/armv8/mmu.h, so move this include to allow redefinition. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> |
#
83d290c5 |
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06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
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482fc90c |
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06-Feb-2018 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
efi_loader: add missing EFI_RESET_PLATFORM_SPECIFIC EFI_RESET_PLATFORM_SPECIFIC is one of the values that can be used for the EFI service ResetSystem. The missing definition is added. The value has to handled in efi_reset_system(). Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Alexander Graf <agraf@suse.de> |
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22c793e6 |
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03-Mar-2018 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
efi_loader: exit status for efi_reset_system_init efi_reset_system_init provides the architecture or board specific initialization of the EFI subsystem. Errors should be caught and signalled by a return code. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Alexander Graf <agraf@suse.de> |
#
958b2ed5 |
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09-Jan-2018 |
Zhang Ying-22455 <ying.zhang22455@nxp.com> |
armv8/ls1088a: configure PMU's PCTBENR to enable WDT The SP805-WDT module on LS1088A requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. The watchdog clock needs to be enabled first. Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
44262327 |
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15-Dec-2017 |
Ahmed Mansour <ahmed.mansour@nxp.com> |
drivers/misc: Share qbman init between archs This patch adds changes necessary to move functionality present in PowerPC folders with ARM architectures that have DPAA1 QBMan hardware - Create new board/freescale/common/fsl_portals.c to house shared device tree fixups for DPAA1 devices with ARM and PowerPC cores - Add new header file to top includes directory to allow files in both architectures to grab the function prototypes - Port inhibit_portals() from PowerPC to ARM. This function is used in setup to disable interrupts on all QMan and BMan portals. It is needed because the interrupts are enabled by default for all portals including unused/uninitialised portals. When the kernel attempts to go to deep sleep the unused portals prevent it from doing so Signed-off-by: Ahmed Mansour <ahmed.mansour@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
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a8f33034 |
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03-Dec-2017 |
Wenbin song <wenbin.song@nxp.com> |
armv8: ls1043a/ls2080a: check SoC by device ID Check LS1043A/LS2080a by device ID without using personality ID to determine revision number. This check applies to all various personalities of the same SoC family. Signed-off-by: Wenbin Song <wenbin.song@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
2db53cfe |
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09-Nov-2017 |
Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
armv8: fsl-layerscape: Add support of disabling core prefetch Instruction prefetch feature is by default enabled during core release. This patch add support of disabling instruction prefetch by setting core mask in PPA. Here each core mask bit represents a core and prefetch is disabled at the time of core release. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
7eb40f0f |
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28-Sep-2017 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: Avoid running dram_init_banksize again gd->ram_size is reduced in this function to reserve secure memory. Avoid running this function again to further reduce memory size. This fixes issue for SPL boot with PPA image loaded in which case secure memory is incorrectly allocated due to repeated calling. Signed-off-by: York Sun <york.sun@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
710d0cd7 |
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03-Oct-2017 |
Sumit Garg <sumit.garg@nxp.com> |
armv8: fsl-layerscape: Allocate Secure memory from first ddr region This change is required due to trusted OS (OP-TEE) not being position independent code, it requires compile time fixed base address. To take care of this it is assumed that all layerscape armv8 platforms has minimum 2G ddr in first region. So we can have fixed address space (66 MB -> (2MB for PPA + 64MB for trusted OS)) allocated from top of first 2G ddr region and compile trusted OS with this fixed base address. But one exception here is ls1012 where we have only 1G (rdb) or 512M (frdm) ddr memory. For those we can have different fixed compile time base addresses for trusted OS. Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
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e9303a41 |
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07-Sep-2017 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: Fix MC reserved memory calculation In case high region memory doesn't have enough space for Management Complex (MC), the return value should indicate a failure so the caller can handle it accordingly. Signed-off-by: York Sun <york.sun@nxp.com> Reported-by: Ebony Zhu <ebony.zhu@nxp.com> |
#
17d066fc |
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31-Aug-2017 |
Ashish Kumar <Ashish.Kumar@nxp.com> |
armv8: fsl-layerscape: Support to add RGMII for ls1088aqds This patch adds support for RGMII protocol NXP's LDPAA2 support RGMII protocol. LS1088A is the first Soc supporting both RGMII and SGMII. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Amrita Kumari <amrita.kumari@nxp.com> Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
63b2316c |
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10-Aug-2017 |
Ashish Kumar <Ashish.Kumar@nxp.com> |
fsl-layerscape: Consolidate registers space defination for CCI-400 bus CoreLink Cache Coherent Interconnect (CCI) provides full cache coherency between two clusters of multi-core CPUs and I/O coherency for devices and I/O masters. This patch add new config option SYS_FSL_HAS_CCI400 and moves existing register space definaton of CCI-400 bus to fsl_immap to be shared. CONFIG_SYS_CCI400_ADDR is replaced with SYS_CCI400_OFFSET in Kconfig. Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> [YS: revised commit message, squashed patches for armv8 and armv7] Reviewed-by: York Sun <york.sun@nxp.com> |
#
6e2941d7 |
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17-May-2017 |
Simon Glass <sjg@chromium.org> |
common: freescale: Move arch-specific declarations The declarations should not be in common.h. Move them to the arch-specific headers. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Fixup thinko defined(FSL_LSCH3) -> defined(CONFIG_FSL_LSCH3)] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
399e2bb6 |
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15-May-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Make U-Boot EL2 safe When U-Boot boots from EL2, skip some lowlevel init code requiring EL3, including CCI-400/CCN-504, trust zone, GIC, etc. These initialization tasks are carried out before U-Boot runs. This applies to the RAM version image used for SPL boot if PPA is loaded first. Signed-off-by: York Sun <york.sun@nxp.com> |
#
1f55a938 |
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05-May-2017 |
Santan Kumar <santan.kumar@nxp.com> |
armv8: ls2080aqds: Add support for SD boot Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
e809e747 |
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27-Apr-2017 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: fsl-layerscape: Add NXP LS2081A, LS2041A SoC support The QorIQ LS2081A SoC has eight 64-bit ARM v8 Cortex A72 cores and is built on layerscape architecture. It is 40-pin derivative of LS2084A (non-AIOP personality of LS2088A). So feature-wise it is same as LS2084A. LS2041A is a 4-core personality of LS2081A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
026f30ec |
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18-Apr-2017 |
Yuantian Tang <andy.tang@nxp.com> |
arm: psci: make psci usable on single core socs PSCI can be used on both multiple and single core socs. Current implementation only allows PSCI to work on multiple core socs. This patch removes this restriction so that PSCI can work on single core socs as well. Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
4a3ab193 |
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27-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: ls2080a: Drop macro CONFIG_LS2080A Use CONFIG_ARCH_LS2080A instead. Signed-off-by: York Sun <york.sun@nxp.com> |
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3eace37e |
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06-Apr-2017 |
Simon Glass <sjg@chromium.org> |
arm: freescale: Rename initdram() to fsl_initdram() This function name shadows a global name but is in fact different. This is very confusing. Rename it to help with the following refactoring. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
76b00aca |
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31-Mar-2017 |
Simon Glass <sjg@chromium.org> |
board_f: Drop setup_dram_config() wrapper By making dram_init_banksize() return an error code we can drop the wrapper. Adjust this and clean up all implementations. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
088454cd |
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31-Mar-2017 |
Simon Glass <sjg@chromium.org> |
board_f: Drop return value from initdram() At present we cannot use this function as an init sequence call without a wrapper, since it returns the RAM size. Adjust it to set the RAM size in global_data instead, and return 0 on success. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> |
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52c41180 |
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31-Mar-2017 |
Simon Glass <sjg@chromium.org> |
board_f: Drop board_type parameter from initdram() It looks like only cm5200 and tqm8xx use this feature, so we don't really need it in generic code. Drop it and have the users access gd->board_type directly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
3d8553f0 |
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02-Mar-2017 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
pci: layerscape: add LS2088A series SoC pcie support The LS2088A series SoCs has different physical memory map address and CCSR registers address against LS2080A series SoCs. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
eea1cb77 |
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13-Feb-2017 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8/fsl-layerscape: Update erratum A009635 implementation Erratum A009635 is valid only for LS2080A SoC and its personality. Add SoC svr check. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
4961eafc |
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06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Update early MMU for DDR after initialization In early MMU table, DDR has to be mapped as device memory to avoid speculative access. After DDR is initialized, it needs to be updated to normal memory to allow code execution. To simplify the code, dram_init() is moved into a common file as a weak function. Signed-off-by: York Sun <york.sun@nxp.com> |
#
a045a0c3 |
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06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Fix the sequence of changing MMU table This patch follows the break-before-make process when making changes to MMU table. MMU is disabled before changing TTBR to avoid any potential race condition. Signed-off-by: York Sun <york.sun@nxp.com> |
#
24f55496 |
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06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Update MMU mapping with actual DDR size Update mapping with actual DDR size. Non-existing memory should not be mapped as "normal" memory to avoid speculative access. Signed-off-by: York Sun <york.sun@nxp.com> |
#
36cc0de0 |
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06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Rewrite memory reservation For ARMv8 Layerscape SoCs, secure memory and MC memorey are reserved at the end of DDR. DDR is spit into two or three banks. This patch reverts commit aabd7ddb and simplifies the calculation of reserved memory, and moves the code into common SoC file. Secure memory is carved out first. DDR bank size is reduced. Reserved memory is then allocated on the top of available memory. U-Boot still has access to reserved memory as data transferring is needed. Device tree is fixed with reduced memory size to hide the reserved memory from OS. The same region is reserved for efi_loader. Signed-off-by: York Sun <york.sun@nxp.com> |
#
daa92644 |
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16-Jan-2017 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
ARMv8/sec_firmware: relocated and renamed the config FSL_PPA_ARMV8_PSCI Moved the config FSL_PPA_ARMV8_PSCI from fsl-layerscape's Kconfig to Kconfig under armv8 and renamed it to SEC_FIRMWARE_ARMV8_PSCI. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
904110c7 |
|
10-Jan-2017 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8/fsl-lsch2: refactor the clock system initialization Up to now, there are 3 kind of SoCs under Layerscape Chassis 2, like LS1043A, LS1046A and LS1012A. But the clocks tree has a lot of differences, for instance, the IP modules have different dividers to derive its clock from Platform PLL. And the core cluster PLL and platform PLL maybe have different reference clocks, such as LS1012A. Another problem is which clock/PLL should be described by sys_info->freq_systembus, it is confused in Layerscape Chissis 2. This patch is to bind the sys_info->freq_systembus to the Platform PLL, and handle the different divider of IP modules separately between different SoCs, and separate reference clocks of core cluster PLL and platform PLL. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
2d16a1a6 |
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07-Dec-2016 |
macro.wave.z@gmail.com <macro.wave.z@gmail.com> |
ARMv8: LS1043A: change macro CONFIG_ARMV8_PSCI definition NXP/Freescale uses macro CONFIG_ARMV8_PSCI to enable their private PSCI implementation in PPA firmware, but this macro naming too generic, so this patch replaces it with a specic one CONFIG_FSL_PPA_ARMV8_PSCI. And this macro CONFIG_ARMV8_PSCI will be used for a generic PSCI for ARMv8 which will be added in following patchs. Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
02fb2761 |
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20-Nov-2016 |
Shengzhou Liu <Shengzhou.Liu@nxp.com> |
fsl/ddr: Add erratum_a009942_check_cpo and clean related erratum - add additional function erratum_a009942_check_cpo to check if the board needs tuning CPO calibration for optimal setting. - move ERRATUM_A009942(with revision to check cpo_sample option) from fsl_ddr_gen4.c to ctrl_regs.c for reuse on all DDR4/DDR3 parts. - move ERRATUM_A008378 from fsl_ddr_gen4.c to ctrl_regs.c - remove obsolete ERRATUM_A004934 which is replaced with ERRATUM_A009942. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> [YS: Replaced CONFIG_QEMU_E500 with CONFIG_ARCH_QEMU_E500] Reviewed-by: York Sun <york.sun@nxp.com> |
#
e87c673c |
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16-Nov-2016 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8/fsl-lsch3: Update code to release secondary cores NXP ARMv8 SoC LS2080A release all secondary cores in one-go. But other new SoCs like LS2088A, LS1088A release secondary cores one by one. Update code to release secondary cores based on SoC SVR Add code to release cores one by one for non LS2080A SoCs Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> [YS: remove "inline" from declaration of initiator_type] Reviewed-by: York Sun <york.sun@nxp.com> |
#
f6b96ff6 |
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16-Nov-2016 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Use SVR based timer base address detection Timer controller base address has been changed from LS2080A SoC (and its personalities) to new SoCs like LS2088A, LS1088A. Use SVR based timer base address detection to avoid compile time #ifdef. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
f6a70b3a |
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16-Nov-2016 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add generic get_svr() in assembly Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
78d57842 |
|
16-Nov-2016 |
Alexander Graf <agraf@csgraf.de> |
armv8: fsl-layerscape: Add support for efi_loader RTS reset When implementing efi loader support, we can expose runtime services for payloads. One such service is CPU reset. This patch implements RTS CPU reset support for layerscape systems. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: York Sun <york.sun@nxp.com> |
#
ef9a5fd8 |
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13-Sep-2016 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: Fix "cpu status" command The core position is not continuous for some SoCs. For example, valid cores may present at position 0, 1, 4, 5, 8, 9, etc. Some registers (including boot release register) only count existing cores. Current implementation of cpu_mask() complies with the continuous numbering. However, command "cpu status" queries the spin table with actual core position. Add functions to calculate core position from core number, to correctly calculate offsets. Tested on LS2080ARDB and LS1043ARDB. Signed-off-by: York Sun <york.sun@nxp.com> |
#
5d1a7a9d |
|
13-Sep-2016 |
Wenbin Song <wenbin.song@nxp.com> |
armv8/fsl-layerscape: print SoC revsion number The exact SoC revsion number can be recognized from U-Boot log. Signed-off-by: Wenbin Song <wenbin.song@nxp.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
cbe7706a |
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26-Sep-2016 |
Tom Rini <trini@konsulko.com> |
Merge git://git.denx.de/u-boot-fsl-qoriq trini: Drop local memset() from examples/standalone/mem_to_mem_idma2intr.c Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
1221ce45 |
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20-Sep-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
treewide: replace #include <asm/errno.h> with <linux/errno.h> Now, arch/${ARCH}/include/asm/errno.h and include/linux/errno.h have the same content. (both just wrap <asm-generic/errno.h>) Replace all include directives for <asm/errno.h> with <linux/errno.h>. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> [trini: Fixup include/clk.] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
b63a9506 |
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03-Aug-2016 |
York Sun <york.sun@nxp.com> |
armv8: ls2080a: Remove debug server support Debug server feature has been dropped from roadmap. Signed-off-by: York Sun <york.sun@nxp.com> |
#
ed7a3943 |
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22-Jul-2016 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: mmu: Fix enabling MMU MMU bit in SCTLR needs to be set explicitly after tables are created. It isn't an issue for EL3 becuase this bit is already set by early MMU setup. But for other exception levels this bit was not set. Signed-off-by: York Sun <york.sun@nxp.com> |
#
79119a4d |
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05-Jul-2016 |
Alison Wang <b18965@freescale.com> |
armv8: fsl-layerscape: Add A72 core detection Add support to detect Cortex-A72 core for printing it out. The Initiator Version of A72 core should be 0x4. Signed-off-by: Alison Wang <alison.wang@nxp.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
032d5bb4 |
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28-Jun-2016 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
ARMv8/Layerscape: switch SMP method accordingly If the PSCI and PPA is ready, skip the fixup for spin-table and waking secondary cores. Otherwise, change SMP method to spin-table, and the device node of PSCI will be removed. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
85cdf38e |
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28-Jun-2016 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: fsl-layerscape: add i/d-cache enable function to enable_caches This function assume that the d-cache and MMU has been enabled earlier, so it just created MMU table in main memory. But the assumption is not always correct, for example, the early setup is done in EL3, while enable_caches() is called when the PE has turned into another EL. Define the function mmu_setup() for fsl-layerscape to cover the weak one. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
5ad5823d |
|
24-Jun-2016 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Convert to use common MMU framework Drop platform code to create static MMU tables. Use common framework to create MMU tables on the run. Tested on LS2080ARDB with secure and non-secure ram scenarios. Signed-off-by: York Sun <york.sun@nxp.com> |
#
e61a7534 |
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24-Jun-2016 |
York Sun <york.sun@nxp.com> |
armv8: Move secure_ram variable out of generic global data Secure_ram variable was put in generic global data. But only ARMv8 uses this variable. Move it to ARM specific data structure. Signed-off-by: York Sun <york.sun@nxp.com> |
#
a10a31ec |
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18-Jun-2016 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of git://git.denx.de/u-boot-usb Signed-off-by: Tom Rini <trini@konsulko.com> Conflicts: arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
|
#
6fb522dc |
|
12-Jun-2016 |
Sriram Dash <sriram.dash@nxp.com> |
arm64: fsl-layerscape: add get_svr and IS_SVR_REV helper Adds get_svr and IS_SVR_REV helpers for ARMv8 platforms, similar to PPC and ARMv7. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> |
#
a758177f |
|
07-Jun-2016 |
Yunhui Cui <yunhui.cui@nxp.com> |
armv8/ls2080a: configure PMU's PCTBENR to enable WDT The SP805-WDT module on LS2080A requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. The watchdog clock needs to be enabled first. Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
acb8f5e9 |
|
21-Apr-2016 |
Alison Wang <b18965@freescale.com> |
armv8: fsl-layerscape: Remove unnecessary flushing dcache As the issue about the stack will get corrupted when switching between the early and final mmu tables is fixed by commit 70e21b064, the workaround to flush dcache is unnecessary and should be removed. Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
3c1d218a |
|
04-Apr-2016 |
York Sun <york.sun@nxp.com> |
armv8: LS2080A: Consolidate LS2080A and LS2085A LS2080A is the primary SoC, and LS2085A is a personality with AIOP and DPAA DDR. The RDB and QDS boards support both personality. By detecting the SVR at runtime, a single image per board can support both SoCs. It gives users flexibility to swtich SoC without the need to reprogram the board. Signed-off-by: York Sun <york.sun@nxp.com> CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
c05016ab |
|
21-Mar-2016 |
Alexander Graf <agraf@csgraf.de> |
arm64: Fix layerscape mmu setup With commit 7985cdf we converted all systems except for the Layerscape SoCs to the generic descriptor table based page table setup. On the Layerscape SoCs however, we just provide an empty table stub and do the setup ourselves. To reserve enough memory for the tables, we need to override the default counting mechanism which would end up with an empty table because we have no maps. Fixes: 7985cdf Reported-by: York Sun <york.sun@nxp.com> CC: Alison Wang <alison.wang@nxp.com> CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Alexander Graf <agraf@suse.de> Tested-by: York Sun <york.sun@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
7985cdf7 |
|
03-Mar-2016 |
Alexander Graf <agraf@csgraf.de> |
arm64: Remove non-full-va map code By now the code to only have a single page table level with 64k page size and 42 bit address space is no longer used by any board in tree, so we can safely remove it. To clean up code, move the layerscape mmu code to the new defines, removing redundant field definitions. Signed-off-by: Alexander Graf <agraf@suse.de> |
#
c0492141 |
|
07-Dec-2015 |
York Sun <yorksun@freescale.com> |
armv8: fsl-layerscale: Rewrite reserving memory for MC and debug server MC and debug server are not board-specific. Move reserving memory to SoC file, using the new board_reserve_ram_top function. Reduce debug server memory by 2MB to make room for secure memory. In the system with MC and debug server, the top of u-boot memory is not the end of memory. PRAM is not used for this reservation. Signed-off-by: York Sun <yorksun@freescale.com> |
#
c107c0c0 |
|
04-Dec-2015 |
York Sun <yorksun@freescale.com> |
armv8: fsl-layerscape: Make DDR non secure in MMU tables DDR has been set as secure in MMU tables. Non-secure master such as SDHC DMA cannot access data correctly. Mixing secure and non- secure MMU entries requirs the MMU tables themselves in secure memory. This patch moves MMU tables into a secure DDR area. Early MMU tables are changed to set DDR as non-secure. A new table is added into final MMU tables so secure memory can have 2MB granuality. gd->secure_ram tracks the location of this secure memory. For ARMv8 SoCs, the RAM base is not zero and RAM is divided into several banks. gd->secure_ram needs to be maintained before using. This maintenance is board-specific, depending on the SoC and memory bank of the secure memory falls into. Signed-off-by: York Sun <yorksun@freescale.com> |
#
b4017364 |
|
04-Nov-2015 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
armv8: ls2085a: Add workaround of errata A009635 If the core runs at higher than x3 speed of the platform, there is possiblity about sev instruction to getting missed by other cores. This is because of SoC Run Control block may not able to sample the EVENTI(Sev) signals. Configure Run Control and EPU to periodically send out EVENTI signals to wake up A57 cores. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
d764129d |
|
04-Nov-2015 |
Alison Wang <b18965@freescale.com> |
armv8/layerscape: Update MMU table with execute-never bits For most device addresses excution shouldn't be allowed. Revise the MMU table to enforce execute-never bits. OCRAM, DDR and IFC are allowed for excution. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Alison Wang <alison.wang@freescale.com> Reported-by: Zhichun Hua <zhichun.hua@freescale.com> |
#
44937214 |
|
09-Nov-2015 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
armv8: LS2080A: Rename LS2085A to reflect LS2080A LS2080A is a prime personality of Freescale’s LS2085A. It is a non-AIOP personality without support of DP-DDR, L2 switch, 1588, PCIe endpoint etc. So renaming existing LS2085A code base to reflect LS2080A (Prime personality) Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> [York Sun: Dropped #ifdef in cpu.c for cpu_type_list] Reviewed-by: York Sun <yorksun@freescale.com> |
#
e8297341 |
|
26-Oct-2015 |
Shaohui Xie <Shaohui.Xie@freescale.com> |
armv8/ls1043a: Add Fman support Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
8281c58f |
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26-Oct-2015 |
Mingkai Hu <Mingkai.Hu@freescale.com> |
armv8/fsl_lsch2: Add fsl_lsch2 SoC Freescale LayerScape with Chassis Generation 2 is a set of SoCs with ARMv8 cores and 2rd generation of Chassis. Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
9f3183d2 |
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26-Oct-2015 |
Mingkai Hu <Mingkai.Hu@freescale.com> |
armv8/fsl_lsch3: Change arch to fsl-layerscape There are two LS series processors are built on ARMv8 Layersacpe architecture currently, LS2085A and LS1043A. They are based on ARMv8 core although use different chassis, so create fsl-layerscape to refactor the common code for the LS series processors which also paves the way for adding LS1043A platform. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
77b11f76 |
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18-Sep-2021 |
Vladimir Oltean <vladimir.oltean@nxp.com> |
net: replace the "xfi" phy-mode with "10gbase-r" As part of the effort of making U-Boot work with the same device tree as Linux, there is an issue with the "xfi" phy-mode. To be precise, in Linux there was a discussion (for those who have time to read: https://lore.kernel.org/netdev/1576768881-24971-2-git-send-email-madalin.bucur@oss.nxp.com/) which led to a patch: https://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next.git/commit/?id=c114574ebfdf42f826776f717c8056a00fa94881 TL;DR: "xfi" was standardized in Linux as "10gbase-r". This patch changes the relevant occurrences in U-Boot to use "10gbase-r" instead of "xfi" wherever applicable. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> |
#
84c2e044 |
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20-Apr-2021 |
Jiafei Pan <Jiafei.Pan@nxp.com> |
armv8: layerscape: add PSCI support for cpu release For cpu release command, check whether PSCI is supported firstly, if supported, use PSCI to kick off secondary cores, otherwise still use spin table. Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com> [Fixed checkpatch alignment CHECKs] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
35b65dd8 |
|
15-Dec-2020 |
Harald Seiler <hws@denx.de> |
reset: Remove addr parameter from reset_cpu() Historically, the reset_cpu() function had an `addr` parameter which was meant to pass in an address of the reset vector location, where the CPU should reset to. This feature is no longer used anywhere in U-Boot as all reset_cpu() implementations now ignore the passed value. Generic code has been added which always calls reset_cpu() with `0` which means this feature can no longer be used easily anyway. Over time, many implementations seem to have "misunderstood" the existence of this parameter as a way to customize/parameterize the reset (e.g. COLD vs WARM resets). As this is not properly supported, the code will almost always not do what it is intended to (because all call-sites just call reset_cpu() with 0). To avoid confusion and to clean up the codebase from unused left-overs of the past, remove the `addr` parameter entirely. Code which intends to support different kinds of resets should be rewritten as a sysreset driver instead. This transformation was done with the following coccinelle patch: @@ expression argvalue; @@ - reset_cpu(argvalue) + reset_cpu() @@ identifier argname; type argtype; @@ - reset_cpu(argtype argname) + reset_cpu(void) { ... } Signed-off-by: Harald Seiler <hws@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
401d1c4f |
|
30-Oct-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop asm/global_data.h from common header Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
3a187cff |
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29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
c760095a |
|
23-Oct-2020 |
Razvan Ionut Cirjan <razvanionut.cirjan@nxp.com> |
net: lx2160a.c: Update to set ECx_PMUX precedence As per hardware documentation, ECx_PMUX has precedence over SerDes protocol. For LX2160/LX2162 if DPMACs 17 and 18 are enabled as SGMII through SerDes protocol but ECx_PMUX configured them as RGMII, then the ports will be configured as RGMII and not SGMII. Signed-off-by: Razvan Ionut Cirjan <razvanionut.cirjan@nxp.com> [Rebased] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
d31f3a1b |
|
09-Sep-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2160a: fix reset sequence Make sure that SW_RST_REQ and RST_REQ_MSK are cleared before triggering hardware reset request. Signed-off-by: Thirupathaiah Annapureddy <thiruan@linux.microsoft.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
b75d8dc5 |
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26-Jun-2020 |
Masahiro Yamada <masahiroy@kernel.org> |
treewide: convert bd_t to struct bd_info by coccinelle The Linux coding style guide (Documentation/process/coding-style.rst) clearly says: It's a **mistake** to use typedef for structures and pointers. Besides, using typedef for structures is annoying when you try to make headers self-contained. Let's say you have the following function declaration in a header: void foo(bd_t *bd); This is not self-contained since bd_t is not defined. To tell the compiler what 'bd_t' is, you need to include <asm/u-boot.h> #include <asm/u-boot.h> void foo(bd_t *bd); Then, the include direcective pulls in more bloat needlessly. If you use 'struct bd_info' instead, it is enough to put a forward declaration as follows: struct bd_info; void foo(struct bd_info *bd); Right, typedef'ing bd_t is a mistake. I used coccinelle to generate this commit. The semantic patch that makes this change is as follows: <smpl> @@ typedef bd_t; @@ -bd_t +struct bd_info </smpl> Signed-off-by: Masahiro Yamada <masahiroy@kernel.org> |
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25a5818f |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop asm/ptrace.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
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f7ae49fc |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
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90526e9f |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop net.h from common header Move this header out of the common header. Network support is used in quite a few places but it still does not warrant blanket inclusion. Note that this net.h header itself has quite a lot in it. It could be split into the driver-mode support, functions, structures, checksumming, etc. Signed-off-by: Simon Glass <sjg@chromium.org> |
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714497e3 |
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16-May-2020 |
Michael Walle <michael@walle.cc> |
efi_loader: round the memory area in efi_add_memory_map() Virtually all callers of this function do the rounding on their own. Some do it right, some don't. Instead of doing this in each caller, do the rounding in efi_add_memory_map(). Change the size parameter to bytes instead of pages and remove aligning and size calculation in all callers. There is no more need to make the original efi_add_memory_map() (which takes pages as size) available outside the module. Thus rename it to efi_add_memory_map_pg() and make it static to prevent further misuse outside the module. Signed-off-by: Michael Walle <michael@walle.cc> Add missing comma in sunxi_display.c. Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de> |
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6eb32a03 |
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23-Apr-2020 |
Madalin Bucur <madalin.bucur@oss.nxp.com> |
driver: net: fm: add DM ETH support Probe the FMan MACs based on the device tree while retaining the legacy code/functionality. One notable change introduced here is that, for DM_ETH, the name of the interfaces is corrected to the fmX-macY format, that avoids the referral to the MAC block names which were incorrect for FMan v3 devices (i.e. DTSEC, TGEC) and had weird formatting (i.e. FM1@DTSEC6, FM1@TGEC1). The legacy code is left unchanged in this respect. Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
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6ebd4883 |
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27-Apr-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
fsl-layerscape: Add RESV_RAM check in resv_ram addr The initialization of gd->arch.resv_ram pointer should depend on if the RESV_RAM config is enabled. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Wasim Khan <wasim.khan@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
0d9d557d |
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10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
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db41d65a |
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28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move hang() to the same header as panic() At present panic() is in the vsprintf.h header file. That does not seem like an obvious choice for hang(), even though it relates to panic(). So let's put hang() in its own header. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Migrate a few more files] Signed-off-by: Tom Rini <trini@konsulko.com> |
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9b4a205f |
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28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move RAM-sizing functions to init.h These functions relate to memory init so move them into the init header. Signed-off-by: Simon Glass <sjg@chromium.org> |
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3499dd03 |
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27-Nov-2019 |
Alex Marginean <alexandru.marginean@nxp.com> |
ls1028a: Configure stream IDs for integrated PCI and fix up Linux DT Hardware comes out of reset with implicit values, but these are outside the accepted range for Layerscape gen 3 chassis spec used on LS1028A. Allocate different IDs and fix up Linux DT to use them. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
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b5981474 |
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14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some CPU functions out of common.h These functions belong in cpu_func.h since they do not use driver model. Move them over. Don't bother adding comments since these functions should be deleted. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
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68a6aa85 |
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14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move mii_init() function out of common.h This function belongs in mii.h so move it over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
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2189d5f1 |
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14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
Move strtomhz() to vsprintf.h At present this function sits in its own file but it does not really justify it. There are similar string functions in vsprintf.h, so move it there. Also add the missing function comment. Use the vsprintf.h include file explicitly where needed. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
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812ff53c |
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30-Oct-2019 |
Pankaj Bansal <pankaj.bansal@nxp.com> |
fsl-layerscape: fix warning if no hwconfig is defined While getting the 'subarg' of 'hwconfig' env variable in config_core_prefetch(), if no hwconfig variable is defined, below warning is received: WARNING: Calling __hwconfig without a buffer and before environment is ready Fix this by checking 'hwconfig' env variable. If not found return without further processing. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Tested-by: Michael Walle <michael@walle.cc> |
#
28f9393b |
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17-Oct-2019 |
Mathew McBride <matt@traverse.com.au> |
fsl-layerscape: do not use layerscape EFI reset if PSCI used If the secure world reset handlers are used (via CONFIG_PSCI_RESET), then do not use the layerscape-specific implementation. Signed-off-by: Mathew McBride <matt@traverse.com.au> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
6ed69523 |
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18-Sep-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add more personalities support Add LS1027A, LS1018A and LS1017A personalities support to LS1028A SoC family. LS1028A is the prime personality of LS1028A SoC family. LS1027A is a lower funtionality version of QorIQ LS1028A which does not support the multimedia subsystems, such as LCD controller, GPU, and eDP PHY. The QorIQ LS1018A and LS1017A SoCs are single 64-bit Arm A72 core, low power versions of the QorIQ LS1028A and LS1027A SoCs respectively. Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
0490cab5 |
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08-Aug-2019 |
Thomas Schaefer <thomas.schaefer@kontron.com> |
armv8: ls1028a: configure PMU's PCTBENR to enable WDT The SP805-WDT module on LS1028A requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. The watchdog clock needs to be enabled first. Signed-off-by: Thomas Schaefer <thomas.schaefer@kontron.com> Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
f3998fdc |
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02-Aug-2019 |
Simon Glass <sjg@chromium.org> |
env: Rename environment.h to env_internal.h This file contains lots of internal details about the environment. Most code can include env.h instead, calling the functions there as needed. Rename this file and add a comment at the top to indicate its internal nature. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> [trini: Fixup apalis-tk1.c] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
3a7d5571 |
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01-Aug-2019 |
Simon Glass <sjg@chromium.org> |
env: Move env_get_f() to env.h Move this function over to the new header file. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
d9532e80 |
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23-Apr-2019 |
Udit Agarwal <udit.agarwal@nxp.com> |
armv8: fsl-layerscape: Set env_loc to ENVL_NOWHERE with CONFIG_ENV_IS_NOWHERE. ENVL_NOWHERE is dependent on CONFIG_ENV_IS_NOWHERE and not on CONFIG_CHAIN_OF_TRUST so return ENVL_NOWHERE when CONFIG_ENV_IS_NOWHERE is enabled Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
d4ad111d |
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10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
059d9422 |
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08-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: lx2160a: add MMU table entries for PCIe The lx2160a have up to 6 PCIe controllers and have different address and size of PCIe region. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
8348e798 |
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08-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: layerscape: use PCIe address macro for precompile PCIe MMU entry Change to use PCIe address macro to determine if precompile the PCIe MMU table entry. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
10015025 |
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03-May-2019 |
Trevor Woerner <trevor@toganlabs.com> |
CONFIG_SPL_SYS_[DI]CACHE_OFF: add While converting CONFIG_SYS_[DI]CACHE_OFF to Kconfig, there are instances where these configuration items are conditional on SPL. This commit adds SPL variants of these configuration items, uses CONFIG_IS_ENABLED(), and updates the configurations as required. Acked-by: Alexey Brodkin <abrodkin@synopsys.com> Signed-off-by: Trevor Woerner <trevor@toganlabs.com> [trini: Make the default depend on the setting for full U-Boot, update more zynq hardware] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
2e53759d |
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29-Oct-2018 |
Pankaj Bansal <pankaj.bansal@nxp.com> |
armv8: fsl-layerscape: reorder rgmii dpmacs' enablement some dpmacs in armv8a based freescale layerscape SOCs can be configured via both serdes(sgmii, xfi, xlaui etc) bits and via EC*_PMUX(rgmii) bits in RCW. e.g. dpmac 17 and 18 in LX2160A can be configured as SGMII from serdes bits and as RGMII via EC1_PMUX/EC2_PMUX bits Now if a dpmac is enabled by serdes bits then it takes precedence over EC*_PMUX bits. i.e. in LX2160A if we select serdes protocol that configures dpmac17 as SGMII and set the EC1_PMUX as RGMII, then the dpmac is SGMII and not RGMII. Therefore, move the fsl_rgmii_init after fsl_serdes_init. in fsl_rgmii_init function of SOC, we will check if the dpmac is enabled or not? if it is (fsl_serdes_init has already enabled the dpmac), then don't enable it. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
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ec88ff80 |
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19-Dec-2018 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1043a: add SVR definitions for 23x23 package silicon LS1043A/LS1023A 23x23 package silicon has different SVR:VAR_PER. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
d23da2ae |
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26-Dec-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: fixes for TFABOOT framework Fixes for TFABOOT framework - update eMMC bootsrc to SD_MMC - Increase buffer size for mcinitcmd from 256 to 512 - Fix mcinitcmd and bootcmd for Secure Boot Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
4909b89e |
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29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
d6fdec21 |
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29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8:fsl-layerscape: Add support for Chassis 3.2 NXP layerscape architecture Chassis 3.2 builds upon chassis3 architecture with changes like DDR Memory map change, removal of IFC and support of upto 8 I2C controller. Patch add README.lsch3_2 and the above changes under macro CONFIG_NXP_LSCH3_2. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
56db948b |
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05-Nov-2018 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: Update parsing boot source Workaround of erratum A010539 clears the RCW source field in PORSR1 register, causing failure of detecting boot source using this method. Use SMC call if U-Boot runs at EL2. If SMC is not implemented or running at EL3, continue to read PORSR1 and presume QSPI as boot source if erratum workaround A010539 is enabled and RCW source is cleared. Signed-off-by: York Sun <york.sun@nxp.com> |
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681d489e |
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05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: layerscape: add SMC calls for DDR size and bank info Adds SMC calls for getting DDR size and bank info for TFABOOT. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
2141d250 |
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05-Nov-2018 |
Pankit Garg <pankit.garg@nxp.com> |
armv8: fsl-layerscape: bootcmd identification for TFABOOT Adds bootcmd identificaton on basis on boot source, valid in TFABOOT configuration. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> [YS: remove unnecessary braces] Reviewed-by: York Sun <york.sun@nxp.com> |
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4c417384 |
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05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com> |
#
535d76a1 |
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05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: layerscape: Add TFABOOT support Adds TFABOOT support config option and add generic code to enable execution from DDR. Signed-off-by: York Sun <york.sun@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> |
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e3506480 |
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05-Nov-2018 |
Pankit Garg <pankit.garg@nxp.com> |
armv8: fsl-layerscape: change tlb base from OCRAM to DDR in EL < 3 Change tlb base address from OCRAM to DDR when exception level is less than 3. Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
d171c707 |
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05-Nov-2018 |
York Sun <york.sun@nxp.com> |
move data structure out of cpu.h Move static definitions to cpu.c file, as it doesn't allow the cpu.h file to be included in multiple c files. Signed-off-by: York Sun <york.sun@nxp.com> |
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9b5e6396 |
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30-Aug-2018 |
Stephen Warren <swarren@nvidia.com> |
efi_loader: simplify ifdefs Use CONFIG_IS_ENABLED(EFI_LOADER) to avoid explicitly checking CONFIG_SPL too. This simplifies the conditional. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Alexander Graf <agraf@suse.de> |
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9cce5663 |
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16-Jul-2018 |
Joe Hershberger <joe.hershberger@ni.com> |
arm: Prevent redefinition error in fsl-layerscape The include/phy.h will start including dm.h, which pulls in linux/compat.h after the attempted redefinition in arch/arm/include/asm/armv8/mmu.h, so move this include to allow redefinition. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> |
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83d290c5 |
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06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
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482fc90c |
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06-Feb-2018 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
efi_loader: add missing EFI_RESET_PLATFORM_SPECIFIC EFI_RESET_PLATFORM_SPECIFIC is one of the values that can be used for the EFI service ResetSystem. The missing definition is added. The value has to handled in efi_reset_system(). Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Alexander Graf <agraf@suse.de> |
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22c793e6 |
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03-Mar-2018 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
efi_loader: exit status for efi_reset_system_init efi_reset_system_init provides the architecture or board specific initialization of the EFI subsystem. Errors should be caught and signalled by a return code. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Alexander Graf <agraf@suse.de> |
#
958b2ed5 |
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09-Jan-2018 |
Zhang Ying-22455 <ying.zhang22455@nxp.com> |
armv8/ls1088a: configure PMU's PCTBENR to enable WDT The SP805-WDT module on LS1088A requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. The watchdog clock needs to be enabled first. Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
44262327 |
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15-Dec-2017 |
Ahmed Mansour <ahmed.mansour@nxp.com> |
drivers/misc: Share qbman init between archs This patch adds changes necessary to move functionality present in PowerPC folders with ARM architectures that have DPAA1 QBMan hardware - Create new board/freescale/common/fsl_portals.c to house shared device tree fixups for DPAA1 devices with ARM and PowerPC cores - Add new header file to top includes directory to allow files in both architectures to grab the function prototypes - Port inhibit_portals() from PowerPC to ARM. This function is used in setup to disable interrupts on all QMan and BMan portals. It is needed because the interrupts are enabled by default for all portals including unused/uninitialised portals. When the kernel attempts to go to deep sleep the unused portals prevent it from doing so Signed-off-by: Ahmed Mansour <ahmed.mansour@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
a8f33034 |
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03-Dec-2017 |
Wenbin song <wenbin.song@nxp.com> |
armv8: ls1043a/ls2080a: check SoC by device ID Check LS1043A/LS2080a by device ID without using personality ID to determine revision number. This check applies to all various personalities of the same SoC family. Signed-off-by: Wenbin Song <wenbin.song@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
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2db53cfe |
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09-Nov-2017 |
Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
armv8: fsl-layerscape: Add support of disabling core prefetch Instruction prefetch feature is by default enabled during core release. This patch add support of disabling instruction prefetch by setting core mask in PPA. Here each core mask bit represents a core and prefetch is disabled at the time of core release. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
7eb40f0f |
|
28-Sep-2017 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: Avoid running dram_init_banksize again gd->ram_size is reduced in this function to reserve secure memory. Avoid running this function again to further reduce memory size. This fixes issue for SPL boot with PPA image loaded in which case secure memory is incorrectly allocated due to repeated calling. Signed-off-by: York Sun <york.sun@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
710d0cd7 |
|
03-Oct-2017 |
Sumit Garg <sumit.garg@nxp.com> |
armv8: fsl-layerscape: Allocate Secure memory from first ddr region This change is required due to trusted OS (OP-TEE) not being position independent code, it requires compile time fixed base address. To take care of this it is assumed that all layerscape armv8 platforms has minimum 2G ddr in first region. So we can have fixed address space (66 MB -> (2MB for PPA + 64MB for trusted OS)) allocated from top of first 2G ddr region and compile trusted OS with this fixed base address. But one exception here is ls1012 where we have only 1G (rdb) or 512M (frdm) ddr memory. For those we can have different fixed compile time base addresses for trusted OS. Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
e9303a41 |
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07-Sep-2017 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: Fix MC reserved memory calculation In case high region memory doesn't have enough space for Management Complex (MC), the return value should indicate a failure so the caller can handle it accordingly. Signed-off-by: York Sun <york.sun@nxp.com> Reported-by: Ebony Zhu <ebony.zhu@nxp.com> |
#
17d066fc |
|
31-Aug-2017 |
Ashish Kumar <Ashish.Kumar@nxp.com> |
armv8: fsl-layerscape: Support to add RGMII for ls1088aqds This patch adds support for RGMII protocol NXP's LDPAA2 support RGMII protocol. LS1088A is the first Soc supporting both RGMII and SGMII. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Amrita Kumari <amrita.kumari@nxp.com> Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
63b2316c |
|
10-Aug-2017 |
Ashish Kumar <Ashish.Kumar@nxp.com> |
fsl-layerscape: Consolidate registers space defination for CCI-400 bus CoreLink Cache Coherent Interconnect (CCI) provides full cache coherency between two clusters of multi-core CPUs and I/O coherency for devices and I/O masters. This patch add new config option SYS_FSL_HAS_CCI400 and moves existing register space definaton of CCI-400 bus to fsl_immap to be shared. CONFIG_SYS_CCI400_ADDR is replaced with SYS_CCI400_OFFSET in Kconfig. Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> [YS: revised commit message, squashed patches for armv8 and armv7] Reviewed-by: York Sun <york.sun@nxp.com> |
#
6e2941d7 |
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17-May-2017 |
Simon Glass <sjg@chromium.org> |
common: freescale: Move arch-specific declarations The declarations should not be in common.h. Move them to the arch-specific headers. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Fixup thinko defined(FSL_LSCH3) -> defined(CONFIG_FSL_LSCH3)] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
399e2bb6 |
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15-May-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Make U-Boot EL2 safe When U-Boot boots from EL2, skip some lowlevel init code requiring EL3, including CCI-400/CCN-504, trust zone, GIC, etc. These initialization tasks are carried out before U-Boot runs. This applies to the RAM version image used for SPL boot if PPA is loaded first. Signed-off-by: York Sun <york.sun@nxp.com> |
#
1f55a938 |
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05-May-2017 |
Santan Kumar <santan.kumar@nxp.com> |
armv8: ls2080aqds: Add support for SD boot Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
e809e747 |
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27-Apr-2017 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: fsl-layerscape: Add NXP LS2081A, LS2041A SoC support The QorIQ LS2081A SoC has eight 64-bit ARM v8 Cortex A72 cores and is built on layerscape architecture. It is 40-pin derivative of LS2084A (non-AIOP personality of LS2088A). So feature-wise it is same as LS2084A. LS2041A is a 4-core personality of LS2081A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
026f30ec |
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18-Apr-2017 |
Yuantian Tang <andy.tang@nxp.com> |
arm: psci: make psci usable on single core socs PSCI can be used on both multiple and single core socs. Current implementation only allows PSCI to work on multiple core socs. This patch removes this restriction so that PSCI can work on single core socs as well. Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
4a3ab193 |
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27-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: ls2080a: Drop macro CONFIG_LS2080A Use CONFIG_ARCH_LS2080A instead. Signed-off-by: York Sun <york.sun@nxp.com> |
#
3eace37e |
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06-Apr-2017 |
Simon Glass <sjg@chromium.org> |
arm: freescale: Rename initdram() to fsl_initdram() This function name shadows a global name but is in fact different. This is very confusing. Rename it to help with the following refactoring. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
76b00aca |
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31-Mar-2017 |
Simon Glass <sjg@chromium.org> |
board_f: Drop setup_dram_config() wrapper By making dram_init_banksize() return an error code we can drop the wrapper. Adjust this and clean up all implementations. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
088454cd |
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31-Mar-2017 |
Simon Glass <sjg@chromium.org> |
board_f: Drop return value from initdram() At present we cannot use this function as an init sequence call without a wrapper, since it returns the RAM size. Adjust it to set the RAM size in global_data instead, and return 0 on success. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
52c41180 |
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31-Mar-2017 |
Simon Glass <sjg@chromium.org> |
board_f: Drop board_type parameter from initdram() It looks like only cm5200 and tqm8xx use this feature, so we don't really need it in generic code. Drop it and have the users access gd->board_type directly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
3d8553f0 |
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02-Mar-2017 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
pci: layerscape: add LS2088A series SoC pcie support The LS2088A series SoCs has different physical memory map address and CCSR registers address against LS2080A series SoCs. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
eea1cb77 |
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13-Feb-2017 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8/fsl-layerscape: Update erratum A009635 implementation Erratum A009635 is valid only for LS2080A SoC and its personality. Add SoC svr check. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
4961eafc |
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06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Update early MMU for DDR after initialization In early MMU table, DDR has to be mapped as device memory to avoid speculative access. After DDR is initialized, it needs to be updated to normal memory to allow code execution. To simplify the code, dram_init() is moved into a common file as a weak function. Signed-off-by: York Sun <york.sun@nxp.com> |
#
a045a0c3 |
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06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Fix the sequence of changing MMU table This patch follows the break-before-make process when making changes to MMU table. MMU is disabled before changing TTBR to avoid any potential race condition. Signed-off-by: York Sun <york.sun@nxp.com> |
#
24f55496 |
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06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Update MMU mapping with actual DDR size Update mapping with actual DDR size. Non-existing memory should not be mapped as "normal" memory to avoid speculative access. Signed-off-by: York Sun <york.sun@nxp.com> |
#
36cc0de0 |
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06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Rewrite memory reservation For ARMv8 Layerscape SoCs, secure memory and MC memorey are reserved at the end of DDR. DDR is spit into two or three banks. This patch reverts commit aabd7ddb and simplifies the calculation of reserved memory, and moves the code into common SoC file. Secure memory is carved out first. DDR bank size is reduced. Reserved memory is then allocated on the top of available memory. U-Boot still has access to reserved memory as data transferring is needed. Device tree is fixed with reduced memory size to hide the reserved memory from OS. The same region is reserved for efi_loader. Signed-off-by: York Sun <york.sun@nxp.com> |
#
daa92644 |
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16-Jan-2017 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
ARMv8/sec_firmware: relocated and renamed the config FSL_PPA_ARMV8_PSCI Moved the config FSL_PPA_ARMV8_PSCI from fsl-layerscape's Kconfig to Kconfig under armv8 and renamed it to SEC_FIRMWARE_ARMV8_PSCI. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
904110c7 |
|
10-Jan-2017 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8/fsl-lsch2: refactor the clock system initialization Up to now, there are 3 kind of SoCs under Layerscape Chassis 2, like LS1043A, LS1046A and LS1012A. But the clocks tree has a lot of differences, for instance, the IP modules have different dividers to derive its clock from Platform PLL. And the core cluster PLL and platform PLL maybe have different reference clocks, such as LS1012A. Another problem is which clock/PLL should be described by sys_info->freq_systembus, it is confused in Layerscape Chissis 2. This patch is to bind the sys_info->freq_systembus to the Platform PLL, and handle the different divider of IP modules separately between different SoCs, and separate reference clocks of core cluster PLL and platform PLL. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
2d16a1a6 |
|
07-Dec-2016 |
macro.wave.z@gmail.com <macro.wave.z@gmail.com> |
ARMv8: LS1043A: change macro CONFIG_ARMV8_PSCI definition NXP/Freescale uses macro CONFIG_ARMV8_PSCI to enable their private PSCI implementation in PPA firmware, but this macro naming too generic, so this patch replaces it with a specic one CONFIG_FSL_PPA_ARMV8_PSCI. And this macro CONFIG_ARMV8_PSCI will be used for a generic PSCI for ARMv8 which will be added in following patchs. Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
02fb2761 |
|
20-Nov-2016 |
Shengzhou Liu <Shengzhou.Liu@nxp.com> |
fsl/ddr: Add erratum_a009942_check_cpo and clean related erratum - add additional function erratum_a009942_check_cpo to check if the board needs tuning CPO calibration for optimal setting. - move ERRATUM_A009942(with revision to check cpo_sample option) from fsl_ddr_gen4.c to ctrl_regs.c for reuse on all DDR4/DDR3 parts. - move ERRATUM_A008378 from fsl_ddr_gen4.c to ctrl_regs.c - remove obsolete ERRATUM_A004934 which is replaced with ERRATUM_A009942. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> [YS: Replaced CONFIG_QEMU_E500 with CONFIG_ARCH_QEMU_E500] Reviewed-by: York Sun <york.sun@nxp.com> |
#
e87c673c |
|
16-Nov-2016 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8/fsl-lsch3: Update code to release secondary cores NXP ARMv8 SoC LS2080A release all secondary cores in one-go. But other new SoCs like LS2088A, LS1088A release secondary cores one by one. Update code to release secondary cores based on SoC SVR Add code to release cores one by one for non LS2080A SoCs Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> [YS: remove "inline" from declaration of initiator_type] Reviewed-by: York Sun <york.sun@nxp.com> |
#
f6b96ff6 |
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16-Nov-2016 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Use SVR based timer base address detection Timer controller base address has been changed from LS2080A SoC (and its personalities) to new SoCs like LS2088A, LS1088A. Use SVR based timer base address detection to avoid compile time #ifdef. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
f6a70b3a |
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16-Nov-2016 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add generic get_svr() in assembly Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
78d57842 |
|
16-Nov-2016 |
Alexander Graf <agraf@csgraf.de> |
armv8: fsl-layerscape: Add support for efi_loader RTS reset When implementing efi loader support, we can expose runtime services for payloads. One such service is CPU reset. This patch implements RTS CPU reset support for layerscape systems. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: York Sun <york.sun@nxp.com> |
#
ef9a5fd8 |
|
13-Sep-2016 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: Fix "cpu status" command The core position is not continuous for some SoCs. For example, valid cores may present at position 0, 1, 4, 5, 8, 9, etc. Some registers (including boot release register) only count existing cores. Current implementation of cpu_mask() complies with the continuous numbering. However, command "cpu status" queries the spin table with actual core position. Add functions to calculate core position from core number, to correctly calculate offsets. Tested on LS2080ARDB and LS1043ARDB. Signed-off-by: York Sun <york.sun@nxp.com> |
#
5d1a7a9d |
|
13-Sep-2016 |
Wenbin Song <wenbin.song@nxp.com> |
armv8/fsl-layerscape: print SoC revsion number The exact SoC revsion number can be recognized from U-Boot log. Signed-off-by: Wenbin Song <wenbin.song@nxp.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
cbe7706a |
|
26-Sep-2016 |
Tom Rini <trini@konsulko.com> |
Merge git://git.denx.de/u-boot-fsl-qoriq trini: Drop local memset() from examples/standalone/mem_to_mem_idma2intr.c Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
1221ce45 |
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20-Sep-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
treewide: replace #include <asm/errno.h> with <linux/errno.h> Now, arch/${ARCH}/include/asm/errno.h and include/linux/errno.h have the same content. (both just wrap <asm-generic/errno.h>) Replace all include directives for <asm/errno.h> with <linux/errno.h>. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> [trini: Fixup include/clk.] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
b63a9506 |
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03-Aug-2016 |
York Sun <york.sun@nxp.com> |
armv8: ls2080a: Remove debug server support Debug server feature has been dropped from roadmap. Signed-off-by: York Sun <york.sun@nxp.com> |
#
ed7a3943 |
|
22-Jul-2016 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: mmu: Fix enabling MMU MMU bit in SCTLR needs to be set explicitly after tables are created. It isn't an issue for EL3 becuase this bit is already set by early MMU setup. But for other exception levels this bit was not set. Signed-off-by: York Sun <york.sun@nxp.com> |
#
79119a4d |
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05-Jul-2016 |
Alison Wang <b18965@freescale.com> |
armv8: fsl-layerscape: Add A72 core detection Add support to detect Cortex-A72 core for printing it out. The Initiator Version of A72 core should be 0x4. Signed-off-by: Alison Wang <alison.wang@nxp.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
032d5bb4 |
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28-Jun-2016 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
ARMv8/Layerscape: switch SMP method accordingly If the PSCI and PPA is ready, skip the fixup for spin-table and waking secondary cores. Otherwise, change SMP method to spin-table, and the device node of PSCI will be removed. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
85cdf38e |
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28-Jun-2016 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: fsl-layerscape: add i/d-cache enable function to enable_caches This function assume that the d-cache and MMU has been enabled earlier, so it just created MMU table in main memory. But the assumption is not always correct, for example, the early setup is done in EL3, while enable_caches() is called when the PE has turned into another EL. Define the function mmu_setup() for fsl-layerscape to cover the weak one. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
5ad5823d |
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24-Jun-2016 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Convert to use common MMU framework Drop platform code to create static MMU tables. Use common framework to create MMU tables on the run. Tested on LS2080ARDB with secure and non-secure ram scenarios. Signed-off-by: York Sun <york.sun@nxp.com> |
#
e61a7534 |
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24-Jun-2016 |
York Sun <york.sun@nxp.com> |
armv8: Move secure_ram variable out of generic global data Secure_ram variable was put in generic global data. But only ARMv8 uses this variable. Move it to ARM specific data structure. Signed-off-by: York Sun <york.sun@nxp.com> |
#
a10a31ec |
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18-Jun-2016 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of git://git.denx.de/u-boot-usb Signed-off-by: Tom Rini <trini@konsulko.com> Conflicts: arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
|
#
6fb522dc |
|
12-Jun-2016 |
Sriram Dash <sriram.dash@nxp.com> |
arm64: fsl-layerscape: add get_svr and IS_SVR_REV helper Adds get_svr and IS_SVR_REV helpers for ARMv8 platforms, similar to PPC and ARMv7. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> |
#
a758177f |
|
07-Jun-2016 |
Yunhui Cui <yunhui.cui@nxp.com> |
armv8/ls2080a: configure PMU's PCTBENR to enable WDT The SP805-WDT module on LS2080A requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. The watchdog clock needs to be enabled first. Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
acb8f5e9 |
|
21-Apr-2016 |
Alison Wang <b18965@freescale.com> |
armv8: fsl-layerscape: Remove unnecessary flushing dcache As the issue about the stack will get corrupted when switching between the early and final mmu tables is fixed by commit 70e21b064, the workaround to flush dcache is unnecessary and should be removed. Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
3c1d218a |
|
04-Apr-2016 |
York Sun <york.sun@nxp.com> |
armv8: LS2080A: Consolidate LS2080A and LS2085A LS2080A is the primary SoC, and LS2085A is a personality with AIOP and DPAA DDR. The RDB and QDS boards support both personality. By detecting the SVR at runtime, a single image per board can support both SoCs. It gives users flexibility to swtich SoC without the need to reprogram the board. Signed-off-by: York Sun <york.sun@nxp.com> CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
c05016ab |
|
21-Mar-2016 |
Alexander Graf <agraf@csgraf.de> |
arm64: Fix layerscape mmu setup With commit 7985cdf we converted all systems except for the Layerscape SoCs to the generic descriptor table based page table setup. On the Layerscape SoCs however, we just provide an empty table stub and do the setup ourselves. To reserve enough memory for the tables, we need to override the default counting mechanism which would end up with an empty table because we have no maps. Fixes: 7985cdf Reported-by: York Sun <york.sun@nxp.com> CC: Alison Wang <alison.wang@nxp.com> CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Alexander Graf <agraf@suse.de> Tested-by: York Sun <york.sun@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
7985cdf7 |
|
03-Mar-2016 |
Alexander Graf <agraf@csgraf.de> |
arm64: Remove non-full-va map code By now the code to only have a single page table level with 64k page size and 42 bit address space is no longer used by any board in tree, so we can safely remove it. To clean up code, move the layerscape mmu code to the new defines, removing redundant field definitions. Signed-off-by: Alexander Graf <agraf@suse.de> |
#
c0492141 |
|
07-Dec-2015 |
York Sun <yorksun@freescale.com> |
armv8: fsl-layerscale: Rewrite reserving memory for MC and debug server MC and debug server are not board-specific. Move reserving memory to SoC file, using the new board_reserve_ram_top function. Reduce debug server memory by 2MB to make room for secure memory. In the system with MC and debug server, the top of u-boot memory is not the end of memory. PRAM is not used for this reservation. Signed-off-by: York Sun <yorksun@freescale.com> |
#
c107c0c0 |
|
04-Dec-2015 |
York Sun <yorksun@freescale.com> |
armv8: fsl-layerscape: Make DDR non secure in MMU tables DDR has been set as secure in MMU tables. Non-secure master such as SDHC DMA cannot access data correctly. Mixing secure and non- secure MMU entries requirs the MMU tables themselves in secure memory. This patch moves MMU tables into a secure DDR area. Early MMU tables are changed to set DDR as non-secure. A new table is added into final MMU tables so secure memory can have 2MB granuality. gd->secure_ram tracks the location of this secure memory. For ARMv8 SoCs, the RAM base is not zero and RAM is divided into several banks. gd->secure_ram needs to be maintained before using. This maintenance is board-specific, depending on the SoC and memory bank of the secure memory falls into. Signed-off-by: York Sun <yorksun@freescale.com> |
#
b4017364 |
|
04-Nov-2015 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
armv8: ls2085a: Add workaround of errata A009635 If the core runs at higher than x3 speed of the platform, there is possiblity about sev instruction to getting missed by other cores. This is because of SoC Run Control block may not able to sample the EVENTI(Sev) signals. Configure Run Control and EPU to periodically send out EVENTI signals to wake up A57 cores. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
d764129d |
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04-Nov-2015 |
Alison Wang <b18965@freescale.com> |
armv8/layerscape: Update MMU table with execute-never bits For most device addresses excution shouldn't be allowed. Revise the MMU table to enforce execute-never bits. OCRAM, DDR and IFC are allowed for excution. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Alison Wang <alison.wang@freescale.com> Reported-by: Zhichun Hua <zhichun.hua@freescale.com> |
#
44937214 |
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09-Nov-2015 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
armv8: LS2080A: Rename LS2085A to reflect LS2080A LS2080A is a prime personality of Freescale’s LS2085A. It is a non-AIOP personality without support of DP-DDR, L2 switch, 1588, PCIe endpoint etc. So renaming existing LS2085A code base to reflect LS2080A (Prime personality) Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> [York Sun: Dropped #ifdef in cpu.c for cpu_type_list] Reviewed-by: York Sun <yorksun@freescale.com> |
#
e8297341 |
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26-Oct-2015 |
Shaohui Xie <Shaohui.Xie@freescale.com> |
armv8/ls1043a: Add Fman support Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
8281c58f |
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26-Oct-2015 |
Mingkai Hu <Mingkai.Hu@freescale.com> |
armv8/fsl_lsch2: Add fsl_lsch2 SoC Freescale LayerScape with Chassis Generation 2 is a set of SoCs with ARMv8 cores and 2rd generation of Chassis. Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
9f3183d2 |
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26-Oct-2015 |
Mingkai Hu <Mingkai.Hu@freescale.com> |
armv8/fsl_lsch3: Change arch to fsl-layerscape There are two LS series processors are built on ARMv8 Layersacpe architecture currently, LS2085A and LS1043A. They are based on ARMv8 core although use different chassis, so create fsl-layerscape to refactor the common code for the LS series processors which also paves the way for adding LS1043A platform. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
84c2e044 |
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20-Apr-2021 |
Jiafei Pan <Jiafei.Pan@nxp.com> |
armv8: layerscape: add PSCI support for cpu release For cpu release command, check whether PSCI is supported firstly, if supported, use PSCI to kick off secondary cores, otherwise still use spin table. Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com> [Fixed checkpatch alignment CHECKs] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
35b65dd8 |
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15-Dec-2020 |
Harald Seiler <hws@denx.de> |
reset: Remove addr parameter from reset_cpu() Historically, the reset_cpu() function had an `addr` parameter which was meant to pass in an address of the reset vector location, where the CPU should reset to. This feature is no longer used anywhere in U-Boot as all reset_cpu() implementations now ignore the passed value. Generic code has been added which always calls reset_cpu() with `0` which means this feature can no longer be used easily anyway. Over time, many implementations seem to have "misunderstood" the existence of this parameter as a way to customize/parameterize the reset (e.g. COLD vs WARM resets). As this is not properly supported, the code will almost always not do what it is intended to (because all call-sites just call reset_cpu() with 0). To avoid confusion and to clean up the codebase from unused left-overs of the past, remove the `addr` parameter entirely. Code which intends to support different kinds of resets should be rewritten as a sysreset driver instead. This transformation was done with the following coccinelle patch: @@ expression argvalue; @@ - reset_cpu(argvalue) + reset_cpu() @@ identifier argname; type argtype; @@ - reset_cpu(argtype argname) + reset_cpu(void) { ... } Signed-off-by: Harald Seiler <hws@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
401d1c4f |
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30-Oct-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop asm/global_data.h from common header Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
3a187cff |
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29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
c760095a |
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23-Oct-2020 |
Razvan Ionut Cirjan <razvanionut.cirjan@nxp.com> |
net: lx2160a.c: Update to set ECx_PMUX precedence As per hardware documentation, ECx_PMUX has precedence over SerDes protocol. For LX2160/LX2162 if DPMACs 17 and 18 are enabled as SGMII through SerDes protocol but ECx_PMUX configured them as RGMII, then the ports will be configured as RGMII and not SGMII. Signed-off-by: Razvan Ionut Cirjan <razvanionut.cirjan@nxp.com> [Rebased] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
d31f3a1b |
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09-Sep-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2160a: fix reset sequence Make sure that SW_RST_REQ and RST_REQ_MSK are cleared before triggering hardware reset request. Signed-off-by: Thirupathaiah Annapureddy <thiruan@linux.microsoft.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
b75d8dc5 |
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26-Jun-2020 |
Masahiro Yamada <masahiroy@kernel.org> |
treewide: convert bd_t to struct bd_info by coccinelle The Linux coding style guide (Documentation/process/coding-style.rst) clearly says: It's a **mistake** to use typedef for structures and pointers. Besides, using typedef for structures is annoying when you try to make headers self-contained. Let's say you have the following function declaration in a header: void foo(bd_t *bd); This is not self-contained since bd_t is not defined. To tell the compiler what 'bd_t' is, you need to include <asm/u-boot.h> #include <asm/u-boot.h> void foo(bd_t *bd); Then, the include direcective pulls in more bloat needlessly. If you use 'struct bd_info' instead, it is enough to put a forward declaration as follows: struct bd_info; void foo(struct bd_info *bd); Right, typedef'ing bd_t is a mistake. I used coccinelle to generate this commit. The semantic patch that makes this change is as follows: <smpl> @@ typedef bd_t; @@ -bd_t +struct bd_info </smpl> Signed-off-by: Masahiro Yamada <masahiroy@kernel.org> |
#
25a5818f |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop asm/ptrace.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
f7ae49fc |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
90526e9f |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop net.h from common header Move this header out of the common header. Network support is used in quite a few places but it still does not warrant blanket inclusion. Note that this net.h header itself has quite a lot in it. It could be split into the driver-mode support, functions, structures, checksumming, etc. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
714497e3 |
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16-May-2020 |
Michael Walle <michael@walle.cc> |
efi_loader: round the memory area in efi_add_memory_map() Virtually all callers of this function do the rounding on their own. Some do it right, some don't. Instead of doing this in each caller, do the rounding in efi_add_memory_map(). Change the size parameter to bytes instead of pages and remove aligning and size calculation in all callers. There is no more need to make the original efi_add_memory_map() (which takes pages as size) available outside the module. Thus rename it to efi_add_memory_map_pg() and make it static to prevent further misuse outside the module. Signed-off-by: Michael Walle <michael@walle.cc> Add missing comma in sunxi_display.c. Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de> |
#
6eb32a03 |
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23-Apr-2020 |
Madalin Bucur <madalin.bucur@oss.nxp.com> |
driver: net: fm: add DM ETH support Probe the FMan MACs based on the device tree while retaining the legacy code/functionality. One notable change introduced here is that, for DM_ETH, the name of the interfaces is corrected to the fmX-macY format, that avoids the referral to the MAC block names which were incorrect for FMan v3 devices (i.e. DTSEC, TGEC) and had weird formatting (i.e. FM1@DTSEC6, FM1@TGEC1). The legacy code is left unchanged in this respect. Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
6ebd4883 |
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27-Apr-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
fsl-layerscape: Add RESV_RAM check in resv_ram addr The initialization of gd->arch.resv_ram pointer should depend on if the RESV_RAM config is enabled. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Wasim Khan <wasim.khan@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
0d9d557d |
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10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
db41d65a |
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28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move hang() to the same header as panic() At present panic() is in the vsprintf.h header file. That does not seem like an obvious choice for hang(), even though it relates to panic(). So let's put hang() in its own header. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Migrate a few more files] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
9b4a205f |
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28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move RAM-sizing functions to init.h These functions relate to memory init so move them into the init header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
3499dd03 |
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27-Nov-2019 |
Alex Marginean <alexandru.marginean@nxp.com> |
ls1028a: Configure stream IDs for integrated PCI and fix up Linux DT Hardware comes out of reset with implicit values, but these are outside the accepted range for Layerscape gen 3 chassis spec used on LS1028A. Allocate different IDs and fix up Linux DT to use them. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
b5981474 |
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14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some CPU functions out of common.h These functions belong in cpu_func.h since they do not use driver model. Move them over. Don't bother adding comments since these functions should be deleted. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
68a6aa85 |
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14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move mii_init() function out of common.h This function belongs in mii.h so move it over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
2189d5f1 |
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14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
Move strtomhz() to vsprintf.h At present this function sits in its own file but it does not really justify it. There are similar string functions in vsprintf.h, so move it there. Also add the missing function comment. Use the vsprintf.h include file explicitly where needed. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
812ff53c |
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30-Oct-2019 |
Pankaj Bansal <pankaj.bansal@nxp.com> |
fsl-layerscape: fix warning if no hwconfig is defined While getting the 'subarg' of 'hwconfig' env variable in config_core_prefetch(), if no hwconfig variable is defined, below warning is received: WARNING: Calling __hwconfig without a buffer and before environment is ready Fix this by checking 'hwconfig' env variable. If not found return without further processing. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Tested-by: Michael Walle <michael@walle.cc> |
#
28f9393b |
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17-Oct-2019 |
Mathew McBride <matt@traverse.com.au> |
fsl-layerscape: do not use layerscape EFI reset if PSCI used If the secure world reset handlers are used (via CONFIG_PSCI_RESET), then do not use the layerscape-specific implementation. Signed-off-by: Mathew McBride <matt@traverse.com.au> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
6ed69523 |
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18-Sep-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add more personalities support Add LS1027A, LS1018A and LS1017A personalities support to LS1028A SoC family. LS1028A is the prime personality of LS1028A SoC family. LS1027A is a lower funtionality version of QorIQ LS1028A which does not support the multimedia subsystems, such as LCD controller, GPU, and eDP PHY. The QorIQ LS1018A and LS1017A SoCs are single 64-bit Arm A72 core, low power versions of the QorIQ LS1028A and LS1027A SoCs respectively. Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
0490cab5 |
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08-Aug-2019 |
Thomas Schaefer <thomas.schaefer@kontron.com> |
armv8: ls1028a: configure PMU's PCTBENR to enable WDT The SP805-WDT module on LS1028A requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. The watchdog clock needs to be enabled first. Signed-off-by: Thomas Schaefer <thomas.schaefer@kontron.com> Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
f3998fdc |
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02-Aug-2019 |
Simon Glass <sjg@chromium.org> |
env: Rename environment.h to env_internal.h This file contains lots of internal details about the environment. Most code can include env.h instead, calling the functions there as needed. Rename this file and add a comment at the top to indicate its internal nature. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> [trini: Fixup apalis-tk1.c] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
3a7d5571 |
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01-Aug-2019 |
Simon Glass <sjg@chromium.org> |
env: Move env_get_f() to env.h Move this function over to the new header file. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
d9532e80 |
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23-Apr-2019 |
Udit Agarwal <udit.agarwal@nxp.com> |
armv8: fsl-layerscape: Set env_loc to ENVL_NOWHERE with CONFIG_ENV_IS_NOWHERE. ENVL_NOWHERE is dependent on CONFIG_ENV_IS_NOWHERE and not on CONFIG_CHAIN_OF_TRUST so return ENVL_NOWHERE when CONFIG_ENV_IS_NOWHERE is enabled Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
d4ad111d |
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10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
059d9422 |
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08-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: lx2160a: add MMU table entries for PCIe The lx2160a have up to 6 PCIe controllers and have different address and size of PCIe region. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
8348e798 |
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08-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: layerscape: use PCIe address macro for precompile PCIe MMU entry Change to use PCIe address macro to determine if precompile the PCIe MMU table entry. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
10015025 |
|
03-May-2019 |
Trevor Woerner <trevor@toganlabs.com> |
CONFIG_SPL_SYS_[DI]CACHE_OFF: add While converting CONFIG_SYS_[DI]CACHE_OFF to Kconfig, there are instances where these configuration items are conditional on SPL. This commit adds SPL variants of these configuration items, uses CONFIG_IS_ENABLED(), and updates the configurations as required. Acked-by: Alexey Brodkin <abrodkin@synopsys.com> Signed-off-by: Trevor Woerner <trevor@toganlabs.com> [trini: Make the default depend on the setting for full U-Boot, update more zynq hardware] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
2e53759d |
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29-Oct-2018 |
Pankaj Bansal <pankaj.bansal@nxp.com> |
armv8: fsl-layerscape: reorder rgmii dpmacs' enablement some dpmacs in armv8a based freescale layerscape SOCs can be configured via both serdes(sgmii, xfi, xlaui etc) bits and via EC*_PMUX(rgmii) bits in RCW. e.g. dpmac 17 and 18 in LX2160A can be configured as SGMII from serdes bits and as RGMII via EC1_PMUX/EC2_PMUX bits Now if a dpmac is enabled by serdes bits then it takes precedence over EC*_PMUX bits. i.e. in LX2160A if we select serdes protocol that configures dpmac17 as SGMII and set the EC1_PMUX as RGMII, then the dpmac is SGMII and not RGMII. Therefore, move the fsl_rgmii_init after fsl_serdes_init. in fsl_rgmii_init function of SOC, we will check if the dpmac is enabled or not? if it is (fsl_serdes_init has already enabled the dpmac), then don't enable it. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
ec88ff80 |
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19-Dec-2018 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1043a: add SVR definitions for 23x23 package silicon LS1043A/LS1023A 23x23 package silicon has different SVR:VAR_PER. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
d23da2ae |
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26-Dec-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: fixes for TFABOOT framework Fixes for TFABOOT framework - update eMMC bootsrc to SD_MMC - Increase buffer size for mcinitcmd from 256 to 512 - Fix mcinitcmd and bootcmd for Secure Boot Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
4909b89e |
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29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
d6fdec21 |
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29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8:fsl-layerscape: Add support for Chassis 3.2 NXP layerscape architecture Chassis 3.2 builds upon chassis3 architecture with changes like DDR Memory map change, removal of IFC and support of upto 8 I2C controller. Patch add README.lsch3_2 and the above changes under macro CONFIG_NXP_LSCH3_2. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
56db948b |
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05-Nov-2018 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: Update parsing boot source Workaround of erratum A010539 clears the RCW source field in PORSR1 register, causing failure of detecting boot source using this method. Use SMC call if U-Boot runs at EL2. If SMC is not implemented or running at EL3, continue to read PORSR1 and presume QSPI as boot source if erratum workaround A010539 is enabled and RCW source is cleared. Signed-off-by: York Sun <york.sun@nxp.com> |
#
681d489e |
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05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: layerscape: add SMC calls for DDR size and bank info Adds SMC calls for getting DDR size and bank info for TFABOOT. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
2141d250 |
|
05-Nov-2018 |
Pankit Garg <pankit.garg@nxp.com> |
armv8: fsl-layerscape: bootcmd identification for TFABOOT Adds bootcmd identificaton on basis on boot source, valid in TFABOOT configuration. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> [YS: remove unnecessary braces] Reviewed-by: York Sun <york.sun@nxp.com> |
#
4c417384 |
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05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com> |
#
535d76a1 |
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05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: layerscape: Add TFABOOT support Adds TFABOOT support config option and add generic code to enable execution from DDR. Signed-off-by: York Sun <york.sun@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> |
#
e3506480 |
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05-Nov-2018 |
Pankit Garg <pankit.garg@nxp.com> |
armv8: fsl-layerscape: change tlb base from OCRAM to DDR in EL < 3 Change tlb base address from OCRAM to DDR when exception level is less than 3. Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
d171c707 |
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05-Nov-2018 |
York Sun <york.sun@nxp.com> |
move data structure out of cpu.h Move static definitions to cpu.c file, as it doesn't allow the cpu.h file to be included in multiple c files. Signed-off-by: York Sun <york.sun@nxp.com> |
#
9b5e6396 |
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30-Aug-2018 |
Stephen Warren <swarren@nvidia.com> |
efi_loader: simplify ifdefs Use CONFIG_IS_ENABLED(EFI_LOADER) to avoid explicitly checking CONFIG_SPL too. This simplifies the conditional. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Alexander Graf <agraf@suse.de> |
#
9cce5663 |
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16-Jul-2018 |
Joe Hershberger <joe.hershberger@ni.com> |
arm: Prevent redefinition error in fsl-layerscape The include/phy.h will start including dm.h, which pulls in linux/compat.h after the attempted redefinition in arch/arm/include/asm/armv8/mmu.h, so move this include to allow redefinition. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> |
#
83d290c5 |
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06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
482fc90c |
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06-Feb-2018 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
efi_loader: add missing EFI_RESET_PLATFORM_SPECIFIC EFI_RESET_PLATFORM_SPECIFIC is one of the values that can be used for the EFI service ResetSystem. The missing definition is added. The value has to handled in efi_reset_system(). Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Alexander Graf <agraf@suse.de> |
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22c793e6 |
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03-Mar-2018 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
efi_loader: exit status for efi_reset_system_init efi_reset_system_init provides the architecture or board specific initialization of the EFI subsystem. Errors should be caught and signalled by a return code. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Alexander Graf <agraf@suse.de> |
#
958b2ed5 |
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09-Jan-2018 |
Zhang Ying-22455 <ying.zhang22455@nxp.com> |
armv8/ls1088a: configure PMU's PCTBENR to enable WDT The SP805-WDT module on LS1088A requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. The watchdog clock needs to be enabled first. Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
44262327 |
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15-Dec-2017 |
Ahmed Mansour <ahmed.mansour@nxp.com> |
drivers/misc: Share qbman init between archs This patch adds changes necessary to move functionality present in PowerPC folders with ARM architectures that have DPAA1 QBMan hardware - Create new board/freescale/common/fsl_portals.c to house shared device tree fixups for DPAA1 devices with ARM and PowerPC cores - Add new header file to top includes directory to allow files in both architectures to grab the function prototypes - Port inhibit_portals() from PowerPC to ARM. This function is used in setup to disable interrupts on all QMan and BMan portals. It is needed because the interrupts are enabled by default for all portals including unused/uninitialised portals. When the kernel attempts to go to deep sleep the unused portals prevent it from doing so Signed-off-by: Ahmed Mansour <ahmed.mansour@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
a8f33034 |
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03-Dec-2017 |
Wenbin song <wenbin.song@nxp.com> |
armv8: ls1043a/ls2080a: check SoC by device ID Check LS1043A/LS2080a by device ID without using personality ID to determine revision number. This check applies to all various personalities of the same SoC family. Signed-off-by: Wenbin Song <wenbin.song@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
2db53cfe |
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09-Nov-2017 |
Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
armv8: fsl-layerscape: Add support of disabling core prefetch Instruction prefetch feature is by default enabled during core release. This patch add support of disabling instruction prefetch by setting core mask in PPA. Here each core mask bit represents a core and prefetch is disabled at the time of core release. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
7eb40f0f |
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28-Sep-2017 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: Avoid running dram_init_banksize again gd->ram_size is reduced in this function to reserve secure memory. Avoid running this function again to further reduce memory size. This fixes issue for SPL boot with PPA image loaded in which case secure memory is incorrectly allocated due to repeated calling. Signed-off-by: York Sun <york.sun@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
710d0cd7 |
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03-Oct-2017 |
Sumit Garg <sumit.garg@nxp.com> |
armv8: fsl-layerscape: Allocate Secure memory from first ddr region This change is required due to trusted OS (OP-TEE) not being position independent code, it requires compile time fixed base address. To take care of this it is assumed that all layerscape armv8 platforms has minimum 2G ddr in first region. So we can have fixed address space (66 MB -> (2MB for PPA + 64MB for trusted OS)) allocated from top of first 2G ddr region and compile trusted OS with this fixed base address. But one exception here is ls1012 where we have only 1G (rdb) or 512M (frdm) ddr memory. For those we can have different fixed compile time base addresses for trusted OS. Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
e9303a41 |
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07-Sep-2017 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: Fix MC reserved memory calculation In case high region memory doesn't have enough space for Management Complex (MC), the return value should indicate a failure so the caller can handle it accordingly. Signed-off-by: York Sun <york.sun@nxp.com> Reported-by: Ebony Zhu <ebony.zhu@nxp.com> |
#
17d066fc |
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31-Aug-2017 |
Ashish Kumar <Ashish.Kumar@nxp.com> |
armv8: fsl-layerscape: Support to add RGMII for ls1088aqds This patch adds support for RGMII protocol NXP's LDPAA2 support RGMII protocol. LS1088A is the first Soc supporting both RGMII and SGMII. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Amrita Kumari <amrita.kumari@nxp.com> Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
63b2316c |
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10-Aug-2017 |
Ashish Kumar <Ashish.Kumar@nxp.com> |
fsl-layerscape: Consolidate registers space defination for CCI-400 bus CoreLink Cache Coherent Interconnect (CCI) provides full cache coherency between two clusters of multi-core CPUs and I/O coherency for devices and I/O masters. This patch add new config option SYS_FSL_HAS_CCI400 and moves existing register space definaton of CCI-400 bus to fsl_immap to be shared. CONFIG_SYS_CCI400_ADDR is replaced with SYS_CCI400_OFFSET in Kconfig. Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> [YS: revised commit message, squashed patches for armv8 and armv7] Reviewed-by: York Sun <york.sun@nxp.com> |
#
6e2941d7 |
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17-May-2017 |
Simon Glass <sjg@chromium.org> |
common: freescale: Move arch-specific declarations The declarations should not be in common.h. Move them to the arch-specific headers. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Fixup thinko defined(FSL_LSCH3) -> defined(CONFIG_FSL_LSCH3)] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
399e2bb6 |
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15-May-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Make U-Boot EL2 safe When U-Boot boots from EL2, skip some lowlevel init code requiring EL3, including CCI-400/CCN-504, trust zone, GIC, etc. These initialization tasks are carried out before U-Boot runs. This applies to the RAM version image used for SPL boot if PPA is loaded first. Signed-off-by: York Sun <york.sun@nxp.com> |
#
1f55a938 |
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05-May-2017 |
Santan Kumar <santan.kumar@nxp.com> |
armv8: ls2080aqds: Add support for SD boot Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
e809e747 |
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27-Apr-2017 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: fsl-layerscape: Add NXP LS2081A, LS2041A SoC support The QorIQ LS2081A SoC has eight 64-bit ARM v8 Cortex A72 cores and is built on layerscape architecture. It is 40-pin derivative of LS2084A (non-AIOP personality of LS2088A). So feature-wise it is same as LS2084A. LS2041A is a 4-core personality of LS2081A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
026f30ec |
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18-Apr-2017 |
Yuantian Tang <andy.tang@nxp.com> |
arm: psci: make psci usable on single core socs PSCI can be used on both multiple and single core socs. Current implementation only allows PSCI to work on multiple core socs. This patch removes this restriction so that PSCI can work on single core socs as well. Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
4a3ab193 |
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27-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: ls2080a: Drop macro CONFIG_LS2080A Use CONFIG_ARCH_LS2080A instead. Signed-off-by: York Sun <york.sun@nxp.com> |
#
3eace37e |
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06-Apr-2017 |
Simon Glass <sjg@chromium.org> |
arm: freescale: Rename initdram() to fsl_initdram() This function name shadows a global name but is in fact different. This is very confusing. Rename it to help with the following refactoring. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
76b00aca |
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31-Mar-2017 |
Simon Glass <sjg@chromium.org> |
board_f: Drop setup_dram_config() wrapper By making dram_init_banksize() return an error code we can drop the wrapper. Adjust this and clean up all implementations. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
088454cd |
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31-Mar-2017 |
Simon Glass <sjg@chromium.org> |
board_f: Drop return value from initdram() At present we cannot use this function as an init sequence call without a wrapper, since it returns the RAM size. Adjust it to set the RAM size in global_data instead, and return 0 on success. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
52c41180 |
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31-Mar-2017 |
Simon Glass <sjg@chromium.org> |
board_f: Drop board_type parameter from initdram() It looks like only cm5200 and tqm8xx use this feature, so we don't really need it in generic code. Drop it and have the users access gd->board_type directly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
3d8553f0 |
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02-Mar-2017 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
pci: layerscape: add LS2088A series SoC pcie support The LS2088A series SoCs has different physical memory map address and CCSR registers address against LS2080A series SoCs. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
eea1cb77 |
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13-Feb-2017 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8/fsl-layerscape: Update erratum A009635 implementation Erratum A009635 is valid only for LS2080A SoC and its personality. Add SoC svr check. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
4961eafc |
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06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Update early MMU for DDR after initialization In early MMU table, DDR has to be mapped as device memory to avoid speculative access. After DDR is initialized, it needs to be updated to normal memory to allow code execution. To simplify the code, dram_init() is moved into a common file as a weak function. Signed-off-by: York Sun <york.sun@nxp.com> |
#
a045a0c3 |
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06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Fix the sequence of changing MMU table This patch follows the break-before-make process when making changes to MMU table. MMU is disabled before changing TTBR to avoid any potential race condition. Signed-off-by: York Sun <york.sun@nxp.com> |
#
24f55496 |
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06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Update MMU mapping with actual DDR size Update mapping with actual DDR size. Non-existing memory should not be mapped as "normal" memory to avoid speculative access. Signed-off-by: York Sun <york.sun@nxp.com> |
#
36cc0de0 |
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06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Rewrite memory reservation For ARMv8 Layerscape SoCs, secure memory and MC memorey are reserved at the end of DDR. DDR is spit into two or three banks. This patch reverts commit aabd7ddb and simplifies the calculation of reserved memory, and moves the code into common SoC file. Secure memory is carved out first. DDR bank size is reduced. Reserved memory is then allocated on the top of available memory. U-Boot still has access to reserved memory as data transferring is needed. Device tree is fixed with reduced memory size to hide the reserved memory from OS. The same region is reserved for efi_loader. Signed-off-by: York Sun <york.sun@nxp.com> |
#
daa92644 |
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16-Jan-2017 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
ARMv8/sec_firmware: relocated and renamed the config FSL_PPA_ARMV8_PSCI Moved the config FSL_PPA_ARMV8_PSCI from fsl-layerscape's Kconfig to Kconfig under armv8 and renamed it to SEC_FIRMWARE_ARMV8_PSCI. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
904110c7 |
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10-Jan-2017 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8/fsl-lsch2: refactor the clock system initialization Up to now, there are 3 kind of SoCs under Layerscape Chassis 2, like LS1043A, LS1046A and LS1012A. But the clocks tree has a lot of differences, for instance, the IP modules have different dividers to derive its clock from Platform PLL. And the core cluster PLL and platform PLL maybe have different reference clocks, such as LS1012A. Another problem is which clock/PLL should be described by sys_info->freq_systembus, it is confused in Layerscape Chissis 2. This patch is to bind the sys_info->freq_systembus to the Platform PLL, and handle the different divider of IP modules separately between different SoCs, and separate reference clocks of core cluster PLL and platform PLL. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
2d16a1a6 |
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07-Dec-2016 |
macro.wave.z@gmail.com <macro.wave.z@gmail.com> |
ARMv8: LS1043A: change macro CONFIG_ARMV8_PSCI definition NXP/Freescale uses macro CONFIG_ARMV8_PSCI to enable their private PSCI implementation in PPA firmware, but this macro naming too generic, so this patch replaces it with a specic one CONFIG_FSL_PPA_ARMV8_PSCI. And this macro CONFIG_ARMV8_PSCI will be used for a generic PSCI for ARMv8 which will be added in following patchs. Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
02fb2761 |
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20-Nov-2016 |
Shengzhou Liu <Shengzhou.Liu@nxp.com> |
fsl/ddr: Add erratum_a009942_check_cpo and clean related erratum - add additional function erratum_a009942_check_cpo to check if the board needs tuning CPO calibration for optimal setting. - move ERRATUM_A009942(with revision to check cpo_sample option) from fsl_ddr_gen4.c to ctrl_regs.c for reuse on all DDR4/DDR3 parts. - move ERRATUM_A008378 from fsl_ddr_gen4.c to ctrl_regs.c - remove obsolete ERRATUM_A004934 which is replaced with ERRATUM_A009942. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> [YS: Replaced CONFIG_QEMU_E500 with CONFIG_ARCH_QEMU_E500] Reviewed-by: York Sun <york.sun@nxp.com> |
#
e87c673c |
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16-Nov-2016 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8/fsl-lsch3: Update code to release secondary cores NXP ARMv8 SoC LS2080A release all secondary cores in one-go. But other new SoCs like LS2088A, LS1088A release secondary cores one by one. Update code to release secondary cores based on SoC SVR Add code to release cores one by one for non LS2080A SoCs Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> [YS: remove "inline" from declaration of initiator_type] Reviewed-by: York Sun <york.sun@nxp.com> |
#
f6b96ff6 |
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16-Nov-2016 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Use SVR based timer base address detection Timer controller base address has been changed from LS2080A SoC (and its personalities) to new SoCs like LS2088A, LS1088A. Use SVR based timer base address detection to avoid compile time #ifdef. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
f6a70b3a |
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16-Nov-2016 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add generic get_svr() in assembly Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
78d57842 |
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16-Nov-2016 |
Alexander Graf <agraf@csgraf.de> |
armv8: fsl-layerscape: Add support for efi_loader RTS reset When implementing efi loader support, we can expose runtime services for payloads. One such service is CPU reset. This patch implements RTS CPU reset support for layerscape systems. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: York Sun <york.sun@nxp.com> |
#
ef9a5fd8 |
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13-Sep-2016 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: Fix "cpu status" command The core position is not continuous for some SoCs. For example, valid cores may present at position 0, 1, 4, 5, 8, 9, etc. Some registers (including boot release register) only count existing cores. Current implementation of cpu_mask() complies with the continuous numbering. However, command "cpu status" queries the spin table with actual core position. Add functions to calculate core position from core number, to correctly calculate offsets. Tested on LS2080ARDB and LS1043ARDB. Signed-off-by: York Sun <york.sun@nxp.com> |
#
5d1a7a9d |
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13-Sep-2016 |
Wenbin Song <wenbin.song@nxp.com> |
armv8/fsl-layerscape: print SoC revsion number The exact SoC revsion number can be recognized from U-Boot log. Signed-off-by: Wenbin Song <wenbin.song@nxp.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
cbe7706a |
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26-Sep-2016 |
Tom Rini <trini@konsulko.com> |
Merge git://git.denx.de/u-boot-fsl-qoriq trini: Drop local memset() from examples/standalone/mem_to_mem_idma2intr.c Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
1221ce45 |
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20-Sep-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
treewide: replace #include <asm/errno.h> with <linux/errno.h> Now, arch/${ARCH}/include/asm/errno.h and include/linux/errno.h have the same content. (both just wrap <asm-generic/errno.h>) Replace all include directives for <asm/errno.h> with <linux/errno.h>. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> [trini: Fixup include/clk.] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
b63a9506 |
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03-Aug-2016 |
York Sun <york.sun@nxp.com> |
armv8: ls2080a: Remove debug server support Debug server feature has been dropped from roadmap. Signed-off-by: York Sun <york.sun@nxp.com> |
#
ed7a3943 |
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22-Jul-2016 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: mmu: Fix enabling MMU MMU bit in SCTLR needs to be set explicitly after tables are created. It isn't an issue for EL3 becuase this bit is already set by early MMU setup. But for other exception levels this bit was not set. Signed-off-by: York Sun <york.sun@nxp.com> |
#
79119a4d |
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05-Jul-2016 |
Alison Wang <b18965@freescale.com> |
armv8: fsl-layerscape: Add A72 core detection Add support to detect Cortex-A72 core for printing it out. The Initiator Version of A72 core should be 0x4. Signed-off-by: Alison Wang <alison.wang@nxp.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
032d5bb4 |
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28-Jun-2016 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
ARMv8/Layerscape: switch SMP method accordingly If the PSCI and PPA is ready, skip the fixup for spin-table and waking secondary cores. Otherwise, change SMP method to spin-table, and the device node of PSCI will be removed. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
85cdf38e |
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28-Jun-2016 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: fsl-layerscape: add i/d-cache enable function to enable_caches This function assume that the d-cache and MMU has been enabled earlier, so it just created MMU table in main memory. But the assumption is not always correct, for example, the early setup is done in EL3, while enable_caches() is called when the PE has turned into another EL. Define the function mmu_setup() for fsl-layerscape to cover the weak one. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
5ad5823d |
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24-Jun-2016 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Convert to use common MMU framework Drop platform code to create static MMU tables. Use common framework to create MMU tables on the run. Tested on LS2080ARDB with secure and non-secure ram scenarios. Signed-off-by: York Sun <york.sun@nxp.com> |
#
e61a7534 |
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24-Jun-2016 |
York Sun <york.sun@nxp.com> |
armv8: Move secure_ram variable out of generic global data Secure_ram variable was put in generic global data. But only ARMv8 uses this variable. Move it to ARM specific data structure. Signed-off-by: York Sun <york.sun@nxp.com> |
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a10a31ec |
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18-Jun-2016 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of git://git.denx.de/u-boot-usb Signed-off-by: Tom Rini <trini@konsulko.com> Conflicts: arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
|
#
6fb522dc |
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12-Jun-2016 |
Sriram Dash <sriram.dash@nxp.com> |
arm64: fsl-layerscape: add get_svr and IS_SVR_REV helper Adds get_svr and IS_SVR_REV helpers for ARMv8 platforms, similar to PPC and ARMv7. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> |
#
a758177f |
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07-Jun-2016 |
Yunhui Cui <yunhui.cui@nxp.com> |
armv8/ls2080a: configure PMU's PCTBENR to enable WDT The SP805-WDT module on LS2080A requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. The watchdog clock needs to be enabled first. Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
acb8f5e9 |
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21-Apr-2016 |
Alison Wang <b18965@freescale.com> |
armv8: fsl-layerscape: Remove unnecessary flushing dcache As the issue about the stack will get corrupted when switching between the early and final mmu tables is fixed by commit 70e21b064, the workaround to flush dcache is unnecessary and should be removed. Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
3c1d218a |
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04-Apr-2016 |
York Sun <york.sun@nxp.com> |
armv8: LS2080A: Consolidate LS2080A and LS2085A LS2080A is the primary SoC, and LS2085A is a personality with AIOP and DPAA DDR. The RDB and QDS boards support both personality. By detecting the SVR at runtime, a single image per board can support both SoCs. It gives users flexibility to swtich SoC without the need to reprogram the board. Signed-off-by: York Sun <york.sun@nxp.com> CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
c05016ab |
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21-Mar-2016 |
Alexander Graf <agraf@csgraf.de> |
arm64: Fix layerscape mmu setup With commit 7985cdf we converted all systems except for the Layerscape SoCs to the generic descriptor table based page table setup. On the Layerscape SoCs however, we just provide an empty table stub and do the setup ourselves. To reserve enough memory for the tables, we need to override the default counting mechanism which would end up with an empty table because we have no maps. Fixes: 7985cdf Reported-by: York Sun <york.sun@nxp.com> CC: Alison Wang <alison.wang@nxp.com> CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Alexander Graf <agraf@suse.de> Tested-by: York Sun <york.sun@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
7985cdf7 |
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03-Mar-2016 |
Alexander Graf <agraf@csgraf.de> |
arm64: Remove non-full-va map code By now the code to only have a single page table level with 64k page size and 42 bit address space is no longer used by any board in tree, so we can safely remove it. To clean up code, move the layerscape mmu code to the new defines, removing redundant field definitions. Signed-off-by: Alexander Graf <agraf@suse.de> |
#
c0492141 |
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07-Dec-2015 |
York Sun <yorksun@freescale.com> |
armv8: fsl-layerscale: Rewrite reserving memory for MC and debug server MC and debug server are not board-specific. Move reserving memory to SoC file, using the new board_reserve_ram_top function. Reduce debug server memory by 2MB to make room for secure memory. In the system with MC and debug server, the top of u-boot memory is not the end of memory. PRAM is not used for this reservation. Signed-off-by: York Sun <yorksun@freescale.com> |
#
c107c0c0 |
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04-Dec-2015 |
York Sun <yorksun@freescale.com> |
armv8: fsl-layerscape: Make DDR non secure in MMU tables DDR has been set as secure in MMU tables. Non-secure master such as SDHC DMA cannot access data correctly. Mixing secure and non- secure MMU entries requirs the MMU tables themselves in secure memory. This patch moves MMU tables into a secure DDR area. Early MMU tables are changed to set DDR as non-secure. A new table is added into final MMU tables so secure memory can have 2MB granuality. gd->secure_ram tracks the location of this secure memory. For ARMv8 SoCs, the RAM base is not zero and RAM is divided into several banks. gd->secure_ram needs to be maintained before using. This maintenance is board-specific, depending on the SoC and memory bank of the secure memory falls into. Signed-off-by: York Sun <yorksun@freescale.com> |
#
b4017364 |
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04-Nov-2015 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
armv8: ls2085a: Add workaround of errata A009635 If the core runs at higher than x3 speed of the platform, there is possiblity about sev instruction to getting missed by other cores. This is because of SoC Run Control block may not able to sample the EVENTI(Sev) signals. Configure Run Control and EPU to periodically send out EVENTI signals to wake up A57 cores. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
d764129d |
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04-Nov-2015 |
Alison Wang <b18965@freescale.com> |
armv8/layerscape: Update MMU table with execute-never bits For most device addresses excution shouldn't be allowed. Revise the MMU table to enforce execute-never bits. OCRAM, DDR and IFC are allowed for excution. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Alison Wang <alison.wang@freescale.com> Reported-by: Zhichun Hua <zhichun.hua@freescale.com> |
#
44937214 |
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09-Nov-2015 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
armv8: LS2080A: Rename LS2085A to reflect LS2080A LS2080A is a prime personality of Freescale’s LS2085A. It is a non-AIOP personality without support of DP-DDR, L2 switch, 1588, PCIe endpoint etc. So renaming existing LS2085A code base to reflect LS2080A (Prime personality) Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> [York Sun: Dropped #ifdef in cpu.c for cpu_type_list] Reviewed-by: York Sun <yorksun@freescale.com> |
#
e8297341 |
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26-Oct-2015 |
Shaohui Xie <Shaohui.Xie@freescale.com> |
armv8/ls1043a: Add Fman support Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
8281c58f |
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26-Oct-2015 |
Mingkai Hu <Mingkai.Hu@freescale.com> |
armv8/fsl_lsch2: Add fsl_lsch2 SoC Freescale LayerScape with Chassis Generation 2 is a set of SoCs with ARMv8 cores and 2rd generation of Chassis. Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
9f3183d2 |
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26-Oct-2015 |
Mingkai Hu <Mingkai.Hu@freescale.com> |
armv8/fsl_lsch3: Change arch to fsl-layerscape There are two LS series processors are built on ARMv8 Layersacpe architecture currently, LS2085A and LS1043A. They are based on ARMv8 core although use different chassis, so create fsl-layerscape to refactor the common code for the LS series processors which also paves the way for adding LS1043A platform. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
35b65dd8 |
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15-Dec-2020 |
Harald Seiler <hws@denx.de> |
reset: Remove addr parameter from reset_cpu() Historically, the reset_cpu() function had an `addr` parameter which was meant to pass in an address of the reset vector location, where the CPU should reset to. This feature is no longer used anywhere in U-Boot as all reset_cpu() implementations now ignore the passed value. Generic code has been added which always calls reset_cpu() with `0` which means this feature can no longer be used easily anyway. Over time, many implementations seem to have "misunderstood" the existence of this parameter as a way to customize/parameterize the reset (e.g. COLD vs WARM resets). As this is not properly supported, the code will almost always not do what it is intended to (because all call-sites just call reset_cpu() with 0). To avoid confusion and to clean up the codebase from unused left-overs of the past, remove the `addr` parameter entirely. Code which intends to support different kinds of resets should be rewritten as a sysreset driver instead. This transformation was done with the following coccinelle patch: @@ expression argvalue; @@ - reset_cpu(argvalue) + reset_cpu() @@ identifier argname; type argtype; @@ - reset_cpu(argtype argname) + reset_cpu(void) { ... } Signed-off-by: Harald Seiler <hws@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
401d1c4f |
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30-Oct-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop asm/global_data.h from common header Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
3a187cff |
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29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
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c760095a |
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23-Oct-2020 |
Razvan Ionut Cirjan <razvanionut.cirjan@nxp.com> |
net: lx2160a.c: Update to set ECx_PMUX precedence As per hardware documentation, ECx_PMUX has precedence over SerDes protocol. For LX2160/LX2162 if DPMACs 17 and 18 are enabled as SGMII through SerDes protocol but ECx_PMUX configured them as RGMII, then the ports will be configured as RGMII and not SGMII. Signed-off-by: Razvan Ionut Cirjan <razvanionut.cirjan@nxp.com> [Rebased] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
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d31f3a1b |
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09-Sep-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2160a: fix reset sequence Make sure that SW_RST_REQ and RST_REQ_MSK are cleared before triggering hardware reset request. Signed-off-by: Thirupathaiah Annapureddy <thiruan@linux.microsoft.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
b75d8dc5 |
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26-Jun-2020 |
Masahiro Yamada <masahiroy@kernel.org> |
treewide: convert bd_t to struct bd_info by coccinelle The Linux coding style guide (Documentation/process/coding-style.rst) clearly says: It's a **mistake** to use typedef for structures and pointers. Besides, using typedef for structures is annoying when you try to make headers self-contained. Let's say you have the following function declaration in a header: void foo(bd_t *bd); This is not self-contained since bd_t is not defined. To tell the compiler what 'bd_t' is, you need to include <asm/u-boot.h> #include <asm/u-boot.h> void foo(bd_t *bd); Then, the include direcective pulls in more bloat needlessly. If you use 'struct bd_info' instead, it is enough to put a forward declaration as follows: struct bd_info; void foo(struct bd_info *bd); Right, typedef'ing bd_t is a mistake. I used coccinelle to generate this commit. The semantic patch that makes this change is as follows: <smpl> @@ typedef bd_t; @@ -bd_t +struct bd_info </smpl> Signed-off-by: Masahiro Yamada <masahiroy@kernel.org> |
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25a5818f |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop asm/ptrace.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
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f7ae49fc |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
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90526e9f |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop net.h from common header Move this header out of the common header. Network support is used in quite a few places but it still does not warrant blanket inclusion. Note that this net.h header itself has quite a lot in it. It could be split into the driver-mode support, functions, structures, checksumming, etc. Signed-off-by: Simon Glass <sjg@chromium.org> |
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714497e3 |
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16-May-2020 |
Michael Walle <michael@walle.cc> |
efi_loader: round the memory area in efi_add_memory_map() Virtually all callers of this function do the rounding on their own. Some do it right, some don't. Instead of doing this in each caller, do the rounding in efi_add_memory_map(). Change the size parameter to bytes instead of pages and remove aligning and size calculation in all callers. There is no more need to make the original efi_add_memory_map() (which takes pages as size) available outside the module. Thus rename it to efi_add_memory_map_pg() and make it static to prevent further misuse outside the module. Signed-off-by: Michael Walle <michael@walle.cc> Add missing comma in sunxi_display.c. Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de> |
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6eb32a03 |
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23-Apr-2020 |
Madalin Bucur <madalin.bucur@oss.nxp.com> |
driver: net: fm: add DM ETH support Probe the FMan MACs based on the device tree while retaining the legacy code/functionality. One notable change introduced here is that, for DM_ETH, the name of the interfaces is corrected to the fmX-macY format, that avoids the referral to the MAC block names which were incorrect for FMan v3 devices (i.e. DTSEC, TGEC) and had weird formatting (i.e. FM1@DTSEC6, FM1@TGEC1). The legacy code is left unchanged in this respect. Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
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6ebd4883 |
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27-Apr-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
fsl-layerscape: Add RESV_RAM check in resv_ram addr The initialization of gd->arch.resv_ram pointer should depend on if the RESV_RAM config is enabled. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Wasim Khan <wasim.khan@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
0d9d557d |
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10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
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db41d65a |
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28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move hang() to the same header as panic() At present panic() is in the vsprintf.h header file. That does not seem like an obvious choice for hang(), even though it relates to panic(). So let's put hang() in its own header. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Migrate a few more files] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
9b4a205f |
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28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move RAM-sizing functions to init.h These functions relate to memory init so move them into the init header. Signed-off-by: Simon Glass <sjg@chromium.org> |
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3499dd03 |
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27-Nov-2019 |
Alex Marginean <alexandru.marginean@nxp.com> |
ls1028a: Configure stream IDs for integrated PCI and fix up Linux DT Hardware comes out of reset with implicit values, but these are outside the accepted range for Layerscape gen 3 chassis spec used on LS1028A. Allocate different IDs and fix up Linux DT to use them. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
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b5981474 |
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14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some CPU functions out of common.h These functions belong in cpu_func.h since they do not use driver model. Move them over. Don't bother adding comments since these functions should be deleted. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
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68a6aa85 |
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14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move mii_init() function out of common.h This function belongs in mii.h so move it over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
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2189d5f1 |
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14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
Move strtomhz() to vsprintf.h At present this function sits in its own file but it does not really justify it. There are similar string functions in vsprintf.h, so move it there. Also add the missing function comment. Use the vsprintf.h include file explicitly where needed. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
812ff53c |
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30-Oct-2019 |
Pankaj Bansal <pankaj.bansal@nxp.com> |
fsl-layerscape: fix warning if no hwconfig is defined While getting the 'subarg' of 'hwconfig' env variable in config_core_prefetch(), if no hwconfig variable is defined, below warning is received: WARNING: Calling __hwconfig without a buffer and before environment is ready Fix this by checking 'hwconfig' env variable. If not found return without further processing. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Tested-by: Michael Walle <michael@walle.cc> |
#
28f9393b |
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17-Oct-2019 |
Mathew McBride <matt@traverse.com.au> |
fsl-layerscape: do not use layerscape EFI reset if PSCI used If the secure world reset handlers are used (via CONFIG_PSCI_RESET), then do not use the layerscape-specific implementation. Signed-off-by: Mathew McBride <matt@traverse.com.au> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
6ed69523 |
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18-Sep-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add more personalities support Add LS1027A, LS1018A and LS1017A personalities support to LS1028A SoC family. LS1028A is the prime personality of LS1028A SoC family. LS1027A is a lower funtionality version of QorIQ LS1028A which does not support the multimedia subsystems, such as LCD controller, GPU, and eDP PHY. The QorIQ LS1018A and LS1017A SoCs are single 64-bit Arm A72 core, low power versions of the QorIQ LS1028A and LS1027A SoCs respectively. Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
0490cab5 |
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08-Aug-2019 |
Thomas Schaefer <thomas.schaefer@kontron.com> |
armv8: ls1028a: configure PMU's PCTBENR to enable WDT The SP805-WDT module on LS1028A requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. The watchdog clock needs to be enabled first. Signed-off-by: Thomas Schaefer <thomas.schaefer@kontron.com> Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
f3998fdc |
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02-Aug-2019 |
Simon Glass <sjg@chromium.org> |
env: Rename environment.h to env_internal.h This file contains lots of internal details about the environment. Most code can include env.h instead, calling the functions there as needed. Rename this file and add a comment at the top to indicate its internal nature. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> [trini: Fixup apalis-tk1.c] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
3a7d5571 |
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01-Aug-2019 |
Simon Glass <sjg@chromium.org> |
env: Move env_get_f() to env.h Move this function over to the new header file. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
d9532e80 |
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23-Apr-2019 |
Udit Agarwal <udit.agarwal@nxp.com> |
armv8: fsl-layerscape: Set env_loc to ENVL_NOWHERE with CONFIG_ENV_IS_NOWHERE. ENVL_NOWHERE is dependent on CONFIG_ENV_IS_NOWHERE and not on CONFIG_CHAIN_OF_TRUST so return ENVL_NOWHERE when CONFIG_ENV_IS_NOWHERE is enabled Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
059d9422 |
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08-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: lx2160a: add MMU table entries for PCIe The lx2160a have up to 6 PCIe controllers and have different address and size of PCIe region. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
8348e798 |
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08-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: layerscape: use PCIe address macro for precompile PCIe MMU entry Change to use PCIe address macro to determine if precompile the PCIe MMU table entry. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
10015025 |
|
03-May-2019 |
Trevor Woerner <trevor@toganlabs.com> |
CONFIG_SPL_SYS_[DI]CACHE_OFF: add While converting CONFIG_SYS_[DI]CACHE_OFF to Kconfig, there are instances where these configuration items are conditional on SPL. This commit adds SPL variants of these configuration items, uses CONFIG_IS_ENABLED(), and updates the configurations as required. Acked-by: Alexey Brodkin <abrodkin@synopsys.com> Signed-off-by: Trevor Woerner <trevor@toganlabs.com> [trini: Make the default depend on the setting for full U-Boot, update more zynq hardware] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
2e53759d |
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29-Oct-2018 |
Pankaj Bansal <pankaj.bansal@nxp.com> |
armv8: fsl-layerscape: reorder rgmii dpmacs' enablement some dpmacs in armv8a based freescale layerscape SOCs can be configured via both serdes(sgmii, xfi, xlaui etc) bits and via EC*_PMUX(rgmii) bits in RCW. e.g. dpmac 17 and 18 in LX2160A can be configured as SGMII from serdes bits and as RGMII via EC1_PMUX/EC2_PMUX bits Now if a dpmac is enabled by serdes bits then it takes precedence over EC*_PMUX bits. i.e. in LX2160A if we select serdes protocol that configures dpmac17 as SGMII and set the EC1_PMUX as RGMII, then the dpmac is SGMII and not RGMII. Therefore, move the fsl_rgmii_init after fsl_serdes_init. in fsl_rgmii_init function of SOC, we will check if the dpmac is enabled or not? if it is (fsl_serdes_init has already enabled the dpmac), then don't enable it. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
ec88ff80 |
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19-Dec-2018 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1043a: add SVR definitions for 23x23 package silicon LS1043A/LS1023A 23x23 package silicon has different SVR:VAR_PER. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
d23da2ae |
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26-Dec-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: fixes for TFABOOT framework Fixes for TFABOOT framework - update eMMC bootsrc to SD_MMC - Increase buffer size for mcinitcmd from 256 to 512 - Fix mcinitcmd and bootcmd for Secure Boot Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
4909b89e |
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29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
d6fdec21 |
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29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8:fsl-layerscape: Add support for Chassis 3.2 NXP layerscape architecture Chassis 3.2 builds upon chassis3 architecture with changes like DDR Memory map change, removal of IFC and support of upto 8 I2C controller. Patch add README.lsch3_2 and the above changes under macro CONFIG_NXP_LSCH3_2. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
56db948b |
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05-Nov-2018 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: Update parsing boot source Workaround of erratum A010539 clears the RCW source field in PORSR1 register, causing failure of detecting boot source using this method. Use SMC call if U-Boot runs at EL2. If SMC is not implemented or running at EL3, continue to read PORSR1 and presume QSPI as boot source if erratum workaround A010539 is enabled and RCW source is cleared. Signed-off-by: York Sun <york.sun@nxp.com> |
#
681d489e |
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05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: layerscape: add SMC calls for DDR size and bank info Adds SMC calls for getting DDR size and bank info for TFABOOT. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
2141d250 |
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05-Nov-2018 |
Pankit Garg <pankit.garg@nxp.com> |
armv8: fsl-layerscape: bootcmd identification for TFABOOT Adds bootcmd identificaton on basis on boot source, valid in TFABOOT configuration. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> [YS: remove unnecessary braces] Reviewed-by: York Sun <york.sun@nxp.com> |
#
4c417384 |
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05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com> |
#
535d76a1 |
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05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: layerscape: Add TFABOOT support Adds TFABOOT support config option and add generic code to enable execution from DDR. Signed-off-by: York Sun <york.sun@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> |
#
e3506480 |
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05-Nov-2018 |
Pankit Garg <pankit.garg@nxp.com> |
armv8: fsl-layerscape: change tlb base from OCRAM to DDR in EL < 3 Change tlb base address from OCRAM to DDR when exception level is less than 3. Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
d171c707 |
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05-Nov-2018 |
York Sun <york.sun@nxp.com> |
move data structure out of cpu.h Move static definitions to cpu.c file, as it doesn't allow the cpu.h file to be included in multiple c files. Signed-off-by: York Sun <york.sun@nxp.com> |
#
9b5e6396 |
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30-Aug-2018 |
Stephen Warren <swarren@nvidia.com> |
efi_loader: simplify ifdefs Use CONFIG_IS_ENABLED(EFI_LOADER) to avoid explicitly checking CONFIG_SPL too. This simplifies the conditional. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Alexander Graf <agraf@suse.de> |
#
9cce5663 |
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16-Jul-2018 |
Joe Hershberger <joe.hershberger@ni.com> |
arm: Prevent redefinition error in fsl-layerscape The include/phy.h will start including dm.h, which pulls in linux/compat.h after the attempted redefinition in arch/arm/include/asm/armv8/mmu.h, so move this include to allow redefinition. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> |
#
83d290c5 |
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06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
482fc90c |
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06-Feb-2018 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
efi_loader: add missing EFI_RESET_PLATFORM_SPECIFIC EFI_RESET_PLATFORM_SPECIFIC is one of the values that can be used for the EFI service ResetSystem. The missing definition is added. The value has to handled in efi_reset_system(). Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Alexander Graf <agraf@suse.de> |
#
22c793e6 |
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03-Mar-2018 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
efi_loader: exit status for efi_reset_system_init efi_reset_system_init provides the architecture or board specific initialization of the EFI subsystem. Errors should be caught and signalled by a return code. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Alexander Graf <agraf@suse.de> |
#
958b2ed5 |
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09-Jan-2018 |
Zhang Ying-22455 <ying.zhang22455@nxp.com> |
armv8/ls1088a: configure PMU's PCTBENR to enable WDT The SP805-WDT module on LS1088A requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. The watchdog clock needs to be enabled first. Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
44262327 |
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15-Dec-2017 |
Ahmed Mansour <ahmed.mansour@nxp.com> |
drivers/misc: Share qbman init between archs This patch adds changes necessary to move functionality present in PowerPC folders with ARM architectures that have DPAA1 QBMan hardware - Create new board/freescale/common/fsl_portals.c to house shared device tree fixups for DPAA1 devices with ARM and PowerPC cores - Add new header file to top includes directory to allow files in both architectures to grab the function prototypes - Port inhibit_portals() from PowerPC to ARM. This function is used in setup to disable interrupts on all QMan and BMan portals. It is needed because the interrupts are enabled by default for all portals including unused/uninitialised portals. When the kernel attempts to go to deep sleep the unused portals prevent it from doing so Signed-off-by: Ahmed Mansour <ahmed.mansour@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
a8f33034 |
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03-Dec-2017 |
Wenbin song <wenbin.song@nxp.com> |
armv8: ls1043a/ls2080a: check SoC by device ID Check LS1043A/LS2080a by device ID without using personality ID to determine revision number. This check applies to all various personalities of the same SoC family. Signed-off-by: Wenbin Song <wenbin.song@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
2db53cfe |
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09-Nov-2017 |
Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
armv8: fsl-layerscape: Add support of disabling core prefetch Instruction prefetch feature is by default enabled during core release. This patch add support of disabling instruction prefetch by setting core mask in PPA. Here each core mask bit represents a core and prefetch is disabled at the time of core release. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
7eb40f0f |
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28-Sep-2017 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: Avoid running dram_init_banksize again gd->ram_size is reduced in this function to reserve secure memory. Avoid running this function again to further reduce memory size. This fixes issue for SPL boot with PPA image loaded in which case secure memory is incorrectly allocated due to repeated calling. Signed-off-by: York Sun <york.sun@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
710d0cd7 |
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03-Oct-2017 |
Sumit Garg <sumit.garg@nxp.com> |
armv8: fsl-layerscape: Allocate Secure memory from first ddr region This change is required due to trusted OS (OP-TEE) not being position independent code, it requires compile time fixed base address. To take care of this it is assumed that all layerscape armv8 platforms has minimum 2G ddr in first region. So we can have fixed address space (66 MB -> (2MB for PPA + 64MB for trusted OS)) allocated from top of first 2G ddr region and compile trusted OS with this fixed base address. But one exception here is ls1012 where we have only 1G (rdb) or 512M (frdm) ddr memory. For those we can have different fixed compile time base addresses for trusted OS. Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
e9303a41 |
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07-Sep-2017 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: Fix MC reserved memory calculation In case high region memory doesn't have enough space for Management Complex (MC), the return value should indicate a failure so the caller can handle it accordingly. Signed-off-by: York Sun <york.sun@nxp.com> Reported-by: Ebony Zhu <ebony.zhu@nxp.com> |
#
17d066fc |
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31-Aug-2017 |
Ashish Kumar <Ashish.Kumar@nxp.com> |
armv8: fsl-layerscape: Support to add RGMII for ls1088aqds This patch adds support for RGMII protocol NXP's LDPAA2 support RGMII protocol. LS1088A is the first Soc supporting both RGMII and SGMII. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Amrita Kumari <amrita.kumari@nxp.com> Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
63b2316c |
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10-Aug-2017 |
Ashish Kumar <Ashish.Kumar@nxp.com> |
fsl-layerscape: Consolidate registers space defination for CCI-400 bus CoreLink Cache Coherent Interconnect (CCI) provides full cache coherency between two clusters of multi-core CPUs and I/O coherency for devices and I/O masters. This patch add new config option SYS_FSL_HAS_CCI400 and moves existing register space definaton of CCI-400 bus to fsl_immap to be shared. CONFIG_SYS_CCI400_ADDR is replaced with SYS_CCI400_OFFSET in Kconfig. Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> [YS: revised commit message, squashed patches for armv8 and armv7] Reviewed-by: York Sun <york.sun@nxp.com> |
#
6e2941d7 |
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17-May-2017 |
Simon Glass <sjg@chromium.org> |
common: freescale: Move arch-specific declarations The declarations should not be in common.h. Move them to the arch-specific headers. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Fixup thinko defined(FSL_LSCH3) -> defined(CONFIG_FSL_LSCH3)] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
399e2bb6 |
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15-May-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Make U-Boot EL2 safe When U-Boot boots from EL2, skip some lowlevel init code requiring EL3, including CCI-400/CCN-504, trust zone, GIC, etc. These initialization tasks are carried out before U-Boot runs. This applies to the RAM version image used for SPL boot if PPA is loaded first. Signed-off-by: York Sun <york.sun@nxp.com> |
#
1f55a938 |
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05-May-2017 |
Santan Kumar <santan.kumar@nxp.com> |
armv8: ls2080aqds: Add support for SD boot Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
e809e747 |
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27-Apr-2017 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: fsl-layerscape: Add NXP LS2081A, LS2041A SoC support The QorIQ LS2081A SoC has eight 64-bit ARM v8 Cortex A72 cores and is built on layerscape architecture. It is 40-pin derivative of LS2084A (non-AIOP personality of LS2088A). So feature-wise it is same as LS2084A. LS2041A is a 4-core personality of LS2081A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
026f30ec |
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18-Apr-2017 |
Yuantian Tang <andy.tang@nxp.com> |
arm: psci: make psci usable on single core socs PSCI can be used on both multiple and single core socs. Current implementation only allows PSCI to work on multiple core socs. This patch removes this restriction so that PSCI can work on single core socs as well. Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
4a3ab193 |
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27-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: ls2080a: Drop macro CONFIG_LS2080A Use CONFIG_ARCH_LS2080A instead. Signed-off-by: York Sun <york.sun@nxp.com> |
#
3eace37e |
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06-Apr-2017 |
Simon Glass <sjg@chromium.org> |
arm: freescale: Rename initdram() to fsl_initdram() This function name shadows a global name but is in fact different. This is very confusing. Rename it to help with the following refactoring. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
76b00aca |
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31-Mar-2017 |
Simon Glass <sjg@chromium.org> |
board_f: Drop setup_dram_config() wrapper By making dram_init_banksize() return an error code we can drop the wrapper. Adjust this and clean up all implementations. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
088454cd |
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31-Mar-2017 |
Simon Glass <sjg@chromium.org> |
board_f: Drop return value from initdram() At present we cannot use this function as an init sequence call without a wrapper, since it returns the RAM size. Adjust it to set the RAM size in global_data instead, and return 0 on success. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
52c41180 |
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31-Mar-2017 |
Simon Glass <sjg@chromium.org> |
board_f: Drop board_type parameter from initdram() It looks like only cm5200 and tqm8xx use this feature, so we don't really need it in generic code. Drop it and have the users access gd->board_type directly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
3d8553f0 |
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02-Mar-2017 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
pci: layerscape: add LS2088A series SoC pcie support The LS2088A series SoCs has different physical memory map address and CCSR registers address against LS2080A series SoCs. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
eea1cb77 |
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13-Feb-2017 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8/fsl-layerscape: Update erratum A009635 implementation Erratum A009635 is valid only for LS2080A SoC and its personality. Add SoC svr check. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
4961eafc |
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06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Update early MMU for DDR after initialization In early MMU table, DDR has to be mapped as device memory to avoid speculative access. After DDR is initialized, it needs to be updated to normal memory to allow code execution. To simplify the code, dram_init() is moved into a common file as a weak function. Signed-off-by: York Sun <york.sun@nxp.com> |
#
a045a0c3 |
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06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Fix the sequence of changing MMU table This patch follows the break-before-make process when making changes to MMU table. MMU is disabled before changing TTBR to avoid any potential race condition. Signed-off-by: York Sun <york.sun@nxp.com> |
#
24f55496 |
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06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Update MMU mapping with actual DDR size Update mapping with actual DDR size. Non-existing memory should not be mapped as "normal" memory to avoid speculative access. Signed-off-by: York Sun <york.sun@nxp.com> |
#
36cc0de0 |
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06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Rewrite memory reservation For ARMv8 Layerscape SoCs, secure memory and MC memorey are reserved at the end of DDR. DDR is spit into two or three banks. This patch reverts commit aabd7ddb and simplifies the calculation of reserved memory, and moves the code into common SoC file. Secure memory is carved out first. DDR bank size is reduced. Reserved memory is then allocated on the top of available memory. U-Boot still has access to reserved memory as data transferring is needed. Device tree is fixed with reduced memory size to hide the reserved memory from OS. The same region is reserved for efi_loader. Signed-off-by: York Sun <york.sun@nxp.com> |
#
daa92644 |
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16-Jan-2017 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
ARMv8/sec_firmware: relocated and renamed the config FSL_PPA_ARMV8_PSCI Moved the config FSL_PPA_ARMV8_PSCI from fsl-layerscape's Kconfig to Kconfig under armv8 and renamed it to SEC_FIRMWARE_ARMV8_PSCI. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
904110c7 |
|
10-Jan-2017 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8/fsl-lsch2: refactor the clock system initialization Up to now, there are 3 kind of SoCs under Layerscape Chassis 2, like LS1043A, LS1046A and LS1012A. But the clocks tree has a lot of differences, for instance, the IP modules have different dividers to derive its clock from Platform PLL. And the core cluster PLL and platform PLL maybe have different reference clocks, such as LS1012A. Another problem is which clock/PLL should be described by sys_info->freq_systembus, it is confused in Layerscape Chissis 2. This patch is to bind the sys_info->freq_systembus to the Platform PLL, and handle the different divider of IP modules separately between different SoCs, and separate reference clocks of core cluster PLL and platform PLL. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
2d16a1a6 |
|
07-Dec-2016 |
macro.wave.z@gmail.com <macro.wave.z@gmail.com> |
ARMv8: LS1043A: change macro CONFIG_ARMV8_PSCI definition NXP/Freescale uses macro CONFIG_ARMV8_PSCI to enable their private PSCI implementation in PPA firmware, but this macro naming too generic, so this patch replaces it with a specic one CONFIG_FSL_PPA_ARMV8_PSCI. And this macro CONFIG_ARMV8_PSCI will be used for a generic PSCI for ARMv8 which will be added in following patchs. Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
02fb2761 |
|
20-Nov-2016 |
Shengzhou Liu <Shengzhou.Liu@nxp.com> |
fsl/ddr: Add erratum_a009942_check_cpo and clean related erratum - add additional function erratum_a009942_check_cpo to check if the board needs tuning CPO calibration for optimal setting. - move ERRATUM_A009942(with revision to check cpo_sample option) from fsl_ddr_gen4.c to ctrl_regs.c for reuse on all DDR4/DDR3 parts. - move ERRATUM_A008378 from fsl_ddr_gen4.c to ctrl_regs.c - remove obsolete ERRATUM_A004934 which is replaced with ERRATUM_A009942. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> [YS: Replaced CONFIG_QEMU_E500 with CONFIG_ARCH_QEMU_E500] Reviewed-by: York Sun <york.sun@nxp.com> |
#
e87c673c |
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16-Nov-2016 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8/fsl-lsch3: Update code to release secondary cores NXP ARMv8 SoC LS2080A release all secondary cores in one-go. But other new SoCs like LS2088A, LS1088A release secondary cores one by one. Update code to release secondary cores based on SoC SVR Add code to release cores one by one for non LS2080A SoCs Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> [YS: remove "inline" from declaration of initiator_type] Reviewed-by: York Sun <york.sun@nxp.com> |
#
f6b96ff6 |
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16-Nov-2016 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Use SVR based timer base address detection Timer controller base address has been changed from LS2080A SoC (and its personalities) to new SoCs like LS2088A, LS1088A. Use SVR based timer base address detection to avoid compile time #ifdef. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
f6a70b3a |
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16-Nov-2016 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add generic get_svr() in assembly Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
78d57842 |
|
16-Nov-2016 |
Alexander Graf <agraf@csgraf.de> |
armv8: fsl-layerscape: Add support for efi_loader RTS reset When implementing efi loader support, we can expose runtime services for payloads. One such service is CPU reset. This patch implements RTS CPU reset support for layerscape systems. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: York Sun <york.sun@nxp.com> |
#
ef9a5fd8 |
|
13-Sep-2016 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: Fix "cpu status" command The core position is not continuous for some SoCs. For example, valid cores may present at position 0, 1, 4, 5, 8, 9, etc. Some registers (including boot release register) only count existing cores. Current implementation of cpu_mask() complies with the continuous numbering. However, command "cpu status" queries the spin table with actual core position. Add functions to calculate core position from core number, to correctly calculate offsets. Tested on LS2080ARDB and LS1043ARDB. Signed-off-by: York Sun <york.sun@nxp.com> |
#
5d1a7a9d |
|
13-Sep-2016 |
Wenbin Song <wenbin.song@nxp.com> |
armv8/fsl-layerscape: print SoC revsion number The exact SoC revsion number can be recognized from U-Boot log. Signed-off-by: Wenbin Song <wenbin.song@nxp.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
cbe7706a |
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26-Sep-2016 |
Tom Rini <trini@konsulko.com> |
Merge git://git.denx.de/u-boot-fsl-qoriq trini: Drop local memset() from examples/standalone/mem_to_mem_idma2intr.c Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
1221ce45 |
|
20-Sep-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
treewide: replace #include <asm/errno.h> with <linux/errno.h> Now, arch/${ARCH}/include/asm/errno.h and include/linux/errno.h have the same content. (both just wrap <asm-generic/errno.h>) Replace all include directives for <asm/errno.h> with <linux/errno.h>. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> [trini: Fixup include/clk.] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
b63a9506 |
|
03-Aug-2016 |
York Sun <york.sun@nxp.com> |
armv8: ls2080a: Remove debug server support Debug server feature has been dropped from roadmap. Signed-off-by: York Sun <york.sun@nxp.com> |
#
ed7a3943 |
|
22-Jul-2016 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: mmu: Fix enabling MMU MMU bit in SCTLR needs to be set explicitly after tables are created. It isn't an issue for EL3 becuase this bit is already set by early MMU setup. But for other exception levels this bit was not set. Signed-off-by: York Sun <york.sun@nxp.com> |
#
79119a4d |
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05-Jul-2016 |
Alison Wang <b18965@freescale.com> |
armv8: fsl-layerscape: Add A72 core detection Add support to detect Cortex-A72 core for printing it out. The Initiator Version of A72 core should be 0x4. Signed-off-by: Alison Wang <alison.wang@nxp.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
032d5bb4 |
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28-Jun-2016 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
ARMv8/Layerscape: switch SMP method accordingly If the PSCI and PPA is ready, skip the fixup for spin-table and waking secondary cores. Otherwise, change SMP method to spin-table, and the device node of PSCI will be removed. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
85cdf38e |
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28-Jun-2016 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: fsl-layerscape: add i/d-cache enable function to enable_caches This function assume that the d-cache and MMU has been enabled earlier, so it just created MMU table in main memory. But the assumption is not always correct, for example, the early setup is done in EL3, while enable_caches() is called when the PE has turned into another EL. Define the function mmu_setup() for fsl-layerscape to cover the weak one. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
5ad5823d |
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24-Jun-2016 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Convert to use common MMU framework Drop platform code to create static MMU tables. Use common framework to create MMU tables on the run. Tested on LS2080ARDB with secure and non-secure ram scenarios. Signed-off-by: York Sun <york.sun@nxp.com> |
#
e61a7534 |
|
24-Jun-2016 |
York Sun <york.sun@nxp.com> |
armv8: Move secure_ram variable out of generic global data Secure_ram variable was put in generic global data. But only ARMv8 uses this variable. Move it to ARM specific data structure. Signed-off-by: York Sun <york.sun@nxp.com> |
#
a10a31ec |
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18-Jun-2016 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of git://git.denx.de/u-boot-usb Signed-off-by: Tom Rini <trini@konsulko.com> Conflicts: arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
|
#
6fb522dc |
|
12-Jun-2016 |
Sriram Dash <sriram.dash@nxp.com> |
arm64: fsl-layerscape: add get_svr and IS_SVR_REV helper Adds get_svr and IS_SVR_REV helpers for ARMv8 platforms, similar to PPC and ARMv7. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> |
#
a758177f |
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07-Jun-2016 |
Yunhui Cui <yunhui.cui@nxp.com> |
armv8/ls2080a: configure PMU's PCTBENR to enable WDT The SP805-WDT module on LS2080A requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. The watchdog clock needs to be enabled first. Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
acb8f5e9 |
|
21-Apr-2016 |
Alison Wang <b18965@freescale.com> |
armv8: fsl-layerscape: Remove unnecessary flushing dcache As the issue about the stack will get corrupted when switching between the early and final mmu tables is fixed by commit 70e21b064, the workaround to flush dcache is unnecessary and should be removed. Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
3c1d218a |
|
04-Apr-2016 |
York Sun <york.sun@nxp.com> |
armv8: LS2080A: Consolidate LS2080A and LS2085A LS2080A is the primary SoC, and LS2085A is a personality with AIOP and DPAA DDR. The RDB and QDS boards support both personality. By detecting the SVR at runtime, a single image per board can support both SoCs. It gives users flexibility to swtich SoC without the need to reprogram the board. Signed-off-by: York Sun <york.sun@nxp.com> CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
c05016ab |
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21-Mar-2016 |
Alexander Graf <agraf@csgraf.de> |
arm64: Fix layerscape mmu setup With commit 7985cdf we converted all systems except for the Layerscape SoCs to the generic descriptor table based page table setup. On the Layerscape SoCs however, we just provide an empty table stub and do the setup ourselves. To reserve enough memory for the tables, we need to override the default counting mechanism which would end up with an empty table because we have no maps. Fixes: 7985cdf Reported-by: York Sun <york.sun@nxp.com> CC: Alison Wang <alison.wang@nxp.com> CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Alexander Graf <agraf@suse.de> Tested-by: York Sun <york.sun@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
7985cdf7 |
|
03-Mar-2016 |
Alexander Graf <agraf@csgraf.de> |
arm64: Remove non-full-va map code By now the code to only have a single page table level with 64k page size and 42 bit address space is no longer used by any board in tree, so we can safely remove it. To clean up code, move the layerscape mmu code to the new defines, removing redundant field definitions. Signed-off-by: Alexander Graf <agraf@suse.de> |
#
c0492141 |
|
07-Dec-2015 |
York Sun <yorksun@freescale.com> |
armv8: fsl-layerscale: Rewrite reserving memory for MC and debug server MC and debug server are not board-specific. Move reserving memory to SoC file, using the new board_reserve_ram_top function. Reduce debug server memory by 2MB to make room for secure memory. In the system with MC and debug server, the top of u-boot memory is not the end of memory. PRAM is not used for this reservation. Signed-off-by: York Sun <yorksun@freescale.com> |
#
c107c0c0 |
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04-Dec-2015 |
York Sun <yorksun@freescale.com> |
armv8: fsl-layerscape: Make DDR non secure in MMU tables DDR has been set as secure in MMU tables. Non-secure master such as SDHC DMA cannot access data correctly. Mixing secure and non- secure MMU entries requirs the MMU tables themselves in secure memory. This patch moves MMU tables into a secure DDR area. Early MMU tables are changed to set DDR as non-secure. A new table is added into final MMU tables so secure memory can have 2MB granuality. gd->secure_ram tracks the location of this secure memory. For ARMv8 SoCs, the RAM base is not zero and RAM is divided into several banks. gd->secure_ram needs to be maintained before using. This maintenance is board-specific, depending on the SoC and memory bank of the secure memory falls into. Signed-off-by: York Sun <yorksun@freescale.com> |
#
b4017364 |
|
04-Nov-2015 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
armv8: ls2085a: Add workaround of errata A009635 If the core runs at higher than x3 speed of the platform, there is possiblity about sev instruction to getting missed by other cores. This is because of SoC Run Control block may not able to sample the EVENTI(Sev) signals. Configure Run Control and EPU to periodically send out EVENTI signals to wake up A57 cores. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
d764129d |
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04-Nov-2015 |
Alison Wang <b18965@freescale.com> |
armv8/layerscape: Update MMU table with execute-never bits For most device addresses excution shouldn't be allowed. Revise the MMU table to enforce execute-never bits. OCRAM, DDR and IFC are allowed for excution. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Alison Wang <alison.wang@freescale.com> Reported-by: Zhichun Hua <zhichun.hua@freescale.com> |
#
44937214 |
|
09-Nov-2015 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
armv8: LS2080A: Rename LS2085A to reflect LS2080A LS2080A is a prime personality of Freescale’s LS2085A. It is a non-AIOP personality without support of DP-DDR, L2 switch, 1588, PCIe endpoint etc. So renaming existing LS2085A code base to reflect LS2080A (Prime personality) Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> [York Sun: Dropped #ifdef in cpu.c for cpu_type_list] Reviewed-by: York Sun <yorksun@freescale.com> |
#
e8297341 |
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26-Oct-2015 |
Shaohui Xie <Shaohui.Xie@freescale.com> |
armv8/ls1043a: Add Fman support Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
8281c58f |
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26-Oct-2015 |
Mingkai Hu <Mingkai.Hu@freescale.com> |
armv8/fsl_lsch2: Add fsl_lsch2 SoC Freescale LayerScape with Chassis Generation 2 is a set of SoCs with ARMv8 cores and 2rd generation of Chassis. Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
9f3183d2 |
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26-Oct-2015 |
Mingkai Hu <Mingkai.Hu@freescale.com> |
armv8/fsl_lsch3: Change arch to fsl-layerscape There are two LS series processors are built on ARMv8 Layersacpe architecture currently, LS2085A and LS1043A. They are based on ARMv8 core although use different chassis, so create fsl-layerscape to refactor the common code for the LS series processors which also paves the way for adding LS1043A platform. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
401d1c4f |
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30-Oct-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop asm/global_data.h from common header Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
3a187cff |
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29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
c760095a |
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23-Oct-2020 |
Razvan Ionut Cirjan <razvanionut.cirjan@nxp.com> |
net: lx2160a.c: Update to set ECx_PMUX precedence As per hardware documentation, ECx_PMUX has precedence over SerDes protocol. For LX2160/LX2162 if DPMACs 17 and 18 are enabled as SGMII through SerDes protocol but ECx_PMUX configured them as RGMII, then the ports will be configured as RGMII and not SGMII. Signed-off-by: Razvan Ionut Cirjan <razvanionut.cirjan@nxp.com> [Rebased] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
d31f3a1b |
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09-Sep-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2160a: fix reset sequence Make sure that SW_RST_REQ and RST_REQ_MSK are cleared before triggering hardware reset request. Signed-off-by: Thirupathaiah Annapureddy <thiruan@linux.microsoft.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
b75d8dc5 |
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26-Jun-2020 |
Masahiro Yamada <masahiroy@kernel.org> |
treewide: convert bd_t to struct bd_info by coccinelle The Linux coding style guide (Documentation/process/coding-style.rst) clearly says: It's a **mistake** to use typedef for structures and pointers. Besides, using typedef for structures is annoying when you try to make headers self-contained. Let's say you have the following function declaration in a header: void foo(bd_t *bd); This is not self-contained since bd_t is not defined. To tell the compiler what 'bd_t' is, you need to include <asm/u-boot.h> #include <asm/u-boot.h> void foo(bd_t *bd); Then, the include direcective pulls in more bloat needlessly. If you use 'struct bd_info' instead, it is enough to put a forward declaration as follows: struct bd_info; void foo(struct bd_info *bd); Right, typedef'ing bd_t is a mistake. I used coccinelle to generate this commit. The semantic patch that makes this change is as follows: <smpl> @@ typedef bd_t; @@ -bd_t +struct bd_info </smpl> Signed-off-by: Masahiro Yamada <masahiroy@kernel.org> |
#
25a5818f |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop asm/ptrace.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
f7ae49fc |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
90526e9f |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop net.h from common header Move this header out of the common header. Network support is used in quite a few places but it still does not warrant blanket inclusion. Note that this net.h header itself has quite a lot in it. It could be split into the driver-mode support, functions, structures, checksumming, etc. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
714497e3 |
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16-May-2020 |
Michael Walle <michael@walle.cc> |
efi_loader: round the memory area in efi_add_memory_map() Virtually all callers of this function do the rounding on their own. Some do it right, some don't. Instead of doing this in each caller, do the rounding in efi_add_memory_map(). Change the size parameter to bytes instead of pages and remove aligning and size calculation in all callers. There is no more need to make the original efi_add_memory_map() (which takes pages as size) available outside the module. Thus rename it to efi_add_memory_map_pg() and make it static to prevent further misuse outside the module. Signed-off-by: Michael Walle <michael@walle.cc> Add missing comma in sunxi_display.c. Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de> |
#
6eb32a03 |
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23-Apr-2020 |
Madalin Bucur <madalin.bucur@oss.nxp.com> |
driver: net: fm: add DM ETH support Probe the FMan MACs based on the device tree while retaining the legacy code/functionality. One notable change introduced here is that, for DM_ETH, the name of the interfaces is corrected to the fmX-macY format, that avoids the referral to the MAC block names which were incorrect for FMan v3 devices (i.e. DTSEC, TGEC) and had weird formatting (i.e. FM1@DTSEC6, FM1@TGEC1). The legacy code is left unchanged in this respect. Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
6ebd4883 |
|
27-Apr-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
fsl-layerscape: Add RESV_RAM check in resv_ram addr The initialization of gd->arch.resv_ram pointer should depend on if the RESV_RAM config is enabled. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Wasim Khan <wasim.khan@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
db41d65a |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move hang() to the same header as panic() At present panic() is in the vsprintf.h header file. That does not seem like an obvious choice for hang(), even though it relates to panic(). So let's put hang() in its own header. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Migrate a few more files] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
9b4a205f |
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28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move RAM-sizing functions to init.h These functions relate to memory init so move them into the init header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
3499dd03 |
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27-Nov-2019 |
Alex Marginean <alexandru.marginean@nxp.com> |
ls1028a: Configure stream IDs for integrated PCI and fix up Linux DT Hardware comes out of reset with implicit values, but these are outside the accepted range for Layerscape gen 3 chassis spec used on LS1028A. Allocate different IDs and fix up Linux DT to use them. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
b5981474 |
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14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some CPU functions out of common.h These functions belong in cpu_func.h since they do not use driver model. Move them over. Don't bother adding comments since these functions should be deleted. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
68a6aa85 |
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14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move mii_init() function out of common.h This function belongs in mii.h so move it over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
2189d5f1 |
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14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
Move strtomhz() to vsprintf.h At present this function sits in its own file but it does not really justify it. There are similar string functions in vsprintf.h, so move it there. Also add the missing function comment. Use the vsprintf.h include file explicitly where needed. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
812ff53c |
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30-Oct-2019 |
Pankaj Bansal <pankaj.bansal@nxp.com> |
fsl-layerscape: fix warning if no hwconfig is defined While getting the 'subarg' of 'hwconfig' env variable in config_core_prefetch(), if no hwconfig variable is defined, below warning is received: WARNING: Calling __hwconfig without a buffer and before environment is ready Fix this by checking 'hwconfig' env variable. If not found return without further processing. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Tested-by: Michael Walle <michael@walle.cc> |
#
28f9393b |
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17-Oct-2019 |
Mathew McBride <matt@traverse.com.au> |
fsl-layerscape: do not use layerscape EFI reset if PSCI used If the secure world reset handlers are used (via CONFIG_PSCI_RESET), then do not use the layerscape-specific implementation. Signed-off-by: Mathew McBride <matt@traverse.com.au> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
6ed69523 |
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18-Sep-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add more personalities support Add LS1027A, LS1018A and LS1017A personalities support to LS1028A SoC family. LS1028A is the prime personality of LS1028A SoC family. LS1027A is a lower funtionality version of QorIQ LS1028A which does not support the multimedia subsystems, such as LCD controller, GPU, and eDP PHY. The QorIQ LS1018A and LS1017A SoCs are single 64-bit Arm A72 core, low power versions of the QorIQ LS1028A and LS1027A SoCs respectively. Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
0490cab5 |
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08-Aug-2019 |
Thomas Schaefer <thomas.schaefer@kontron.com> |
armv8: ls1028a: configure PMU's PCTBENR to enable WDT The SP805-WDT module on LS1028A requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. The watchdog clock needs to be enabled first. Signed-off-by: Thomas Schaefer <thomas.schaefer@kontron.com> Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
f3998fdc |
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02-Aug-2019 |
Simon Glass <sjg@chromium.org> |
env: Rename environment.h to env_internal.h This file contains lots of internal details about the environment. Most code can include env.h instead, calling the functions there as needed. Rename this file and add a comment at the top to indicate its internal nature. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> [trini: Fixup apalis-tk1.c] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
3a7d5571 |
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01-Aug-2019 |
Simon Glass <sjg@chromium.org> |
env: Move env_get_f() to env.h Move this function over to the new header file. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
d9532e80 |
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23-Apr-2019 |
Udit Agarwal <udit.agarwal@nxp.com> |
armv8: fsl-layerscape: Set env_loc to ENVL_NOWHERE with CONFIG_ENV_IS_NOWHERE. ENVL_NOWHERE is dependent on CONFIG_ENV_IS_NOWHERE and not on CONFIG_CHAIN_OF_TRUST so return ENVL_NOWHERE when CONFIG_ENV_IS_NOWHERE is enabled Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
d4ad111d |
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10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
059d9422 |
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08-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: lx2160a: add MMU table entries for PCIe The lx2160a have up to 6 PCIe controllers and have different address and size of PCIe region. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
8348e798 |
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08-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: layerscape: use PCIe address macro for precompile PCIe MMU entry Change to use PCIe address macro to determine if precompile the PCIe MMU table entry. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
10015025 |
|
03-May-2019 |
Trevor Woerner <trevor@toganlabs.com> |
CONFIG_SPL_SYS_[DI]CACHE_OFF: add While converting CONFIG_SYS_[DI]CACHE_OFF to Kconfig, there are instances where these configuration items are conditional on SPL. This commit adds SPL variants of these configuration items, uses CONFIG_IS_ENABLED(), and updates the configurations as required. Acked-by: Alexey Brodkin <abrodkin@synopsys.com> Signed-off-by: Trevor Woerner <trevor@toganlabs.com> [trini: Make the default depend on the setting for full U-Boot, update more zynq hardware] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
2e53759d |
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29-Oct-2018 |
Pankaj Bansal <pankaj.bansal@nxp.com> |
armv8: fsl-layerscape: reorder rgmii dpmacs' enablement some dpmacs in armv8a based freescale layerscape SOCs can be configured via both serdes(sgmii, xfi, xlaui etc) bits and via EC*_PMUX(rgmii) bits in RCW. e.g. dpmac 17 and 18 in LX2160A can be configured as SGMII from serdes bits and as RGMII via EC1_PMUX/EC2_PMUX bits Now if a dpmac is enabled by serdes bits then it takes precedence over EC*_PMUX bits. i.e. in LX2160A if we select serdes protocol that configures dpmac17 as SGMII and set the EC1_PMUX as RGMII, then the dpmac is SGMII and not RGMII. Therefore, move the fsl_rgmii_init after fsl_serdes_init. in fsl_rgmii_init function of SOC, we will check if the dpmac is enabled or not? if it is (fsl_serdes_init has already enabled the dpmac), then don't enable it. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
ec88ff80 |
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19-Dec-2018 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1043a: add SVR definitions for 23x23 package silicon LS1043A/LS1023A 23x23 package silicon has different SVR:VAR_PER. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
d23da2ae |
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26-Dec-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: fixes for TFABOOT framework Fixes for TFABOOT framework - update eMMC bootsrc to SD_MMC - Increase buffer size for mcinitcmd from 256 to 512 - Fix mcinitcmd and bootcmd for Secure Boot Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
4909b89e |
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29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
d6fdec21 |
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29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8:fsl-layerscape: Add support for Chassis 3.2 NXP layerscape architecture Chassis 3.2 builds upon chassis3 architecture with changes like DDR Memory map change, removal of IFC and support of upto 8 I2C controller. Patch add README.lsch3_2 and the above changes under macro CONFIG_NXP_LSCH3_2. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
56db948b |
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05-Nov-2018 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: Update parsing boot source Workaround of erratum A010539 clears the RCW source field in PORSR1 register, causing failure of detecting boot source using this method. Use SMC call if U-Boot runs at EL2. If SMC is not implemented or running at EL3, continue to read PORSR1 and presume QSPI as boot source if erratum workaround A010539 is enabled and RCW source is cleared. Signed-off-by: York Sun <york.sun@nxp.com> |
#
681d489e |
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05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: layerscape: add SMC calls for DDR size and bank info Adds SMC calls for getting DDR size and bank info for TFABOOT. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
2141d250 |
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05-Nov-2018 |
Pankit Garg <pankit.garg@nxp.com> |
armv8: fsl-layerscape: bootcmd identification for TFABOOT Adds bootcmd identificaton on basis on boot source, valid in TFABOOT configuration. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> [YS: remove unnecessary braces] Reviewed-by: York Sun <york.sun@nxp.com> |
#
4c417384 |
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05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com> |
#
535d76a1 |
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05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: layerscape: Add TFABOOT support Adds TFABOOT support config option and add generic code to enable execution from DDR. Signed-off-by: York Sun <york.sun@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> |
#
e3506480 |
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05-Nov-2018 |
Pankit Garg <pankit.garg@nxp.com> |
armv8: fsl-layerscape: change tlb base from OCRAM to DDR in EL < 3 Change tlb base address from OCRAM to DDR when exception level is less than 3. Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
d171c707 |
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05-Nov-2018 |
York Sun <york.sun@nxp.com> |
move data structure out of cpu.h Move static definitions to cpu.c file, as it doesn't allow the cpu.h file to be included in multiple c files. Signed-off-by: York Sun <york.sun@nxp.com> |
#
9b5e6396 |
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30-Aug-2018 |
Stephen Warren <swarren@nvidia.com> |
efi_loader: simplify ifdefs Use CONFIG_IS_ENABLED(EFI_LOADER) to avoid explicitly checking CONFIG_SPL too. This simplifies the conditional. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Alexander Graf <agraf@suse.de> |
#
9cce5663 |
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16-Jul-2018 |
Joe Hershberger <joe.hershberger@ni.com> |
arm: Prevent redefinition error in fsl-layerscape The include/phy.h will start including dm.h, which pulls in linux/compat.h after the attempted redefinition in arch/arm/include/asm/armv8/mmu.h, so move this include to allow redefinition. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> |
#
83d290c5 |
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06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
482fc90c |
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06-Feb-2018 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
efi_loader: add missing EFI_RESET_PLATFORM_SPECIFIC EFI_RESET_PLATFORM_SPECIFIC is one of the values that can be used for the EFI service ResetSystem. The missing definition is added. The value has to handled in efi_reset_system(). Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Alexander Graf <agraf@suse.de> |
#
22c793e6 |
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03-Mar-2018 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
efi_loader: exit status for efi_reset_system_init efi_reset_system_init provides the architecture or board specific initialization of the EFI subsystem. Errors should be caught and signalled by a return code. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Alexander Graf <agraf@suse.de> |
#
958b2ed5 |
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09-Jan-2018 |
Zhang Ying-22455 <ying.zhang22455@nxp.com> |
armv8/ls1088a: configure PMU's PCTBENR to enable WDT The SP805-WDT module on LS1088A requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. The watchdog clock needs to be enabled first. Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
44262327 |
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15-Dec-2017 |
Ahmed Mansour <ahmed.mansour@nxp.com> |
drivers/misc: Share qbman init between archs This patch adds changes necessary to move functionality present in PowerPC folders with ARM architectures that have DPAA1 QBMan hardware - Create new board/freescale/common/fsl_portals.c to house shared device tree fixups for DPAA1 devices with ARM and PowerPC cores - Add new header file to top includes directory to allow files in both architectures to grab the function prototypes - Port inhibit_portals() from PowerPC to ARM. This function is used in setup to disable interrupts on all QMan and BMan portals. It is needed because the interrupts are enabled by default for all portals including unused/uninitialised portals. When the kernel attempts to go to deep sleep the unused portals prevent it from doing so Signed-off-by: Ahmed Mansour <ahmed.mansour@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
a8f33034 |
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03-Dec-2017 |
Wenbin song <wenbin.song@nxp.com> |
armv8: ls1043a/ls2080a: check SoC by device ID Check LS1043A/LS2080a by device ID without using personality ID to determine revision number. This check applies to all various personalities of the same SoC family. Signed-off-by: Wenbin Song <wenbin.song@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
2db53cfe |
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09-Nov-2017 |
Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
armv8: fsl-layerscape: Add support of disabling core prefetch Instruction prefetch feature is by default enabled during core release. This patch add support of disabling instruction prefetch by setting core mask in PPA. Here each core mask bit represents a core and prefetch is disabled at the time of core release. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
7eb40f0f |
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28-Sep-2017 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: Avoid running dram_init_banksize again gd->ram_size is reduced in this function to reserve secure memory. Avoid running this function again to further reduce memory size. This fixes issue for SPL boot with PPA image loaded in which case secure memory is incorrectly allocated due to repeated calling. Signed-off-by: York Sun <york.sun@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
710d0cd7 |
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03-Oct-2017 |
Sumit Garg <sumit.garg@nxp.com> |
armv8: fsl-layerscape: Allocate Secure memory from first ddr region This change is required due to trusted OS (OP-TEE) not being position independent code, it requires compile time fixed base address. To take care of this it is assumed that all layerscape armv8 platforms has minimum 2G ddr in first region. So we can have fixed address space (66 MB -> (2MB for PPA + 64MB for trusted OS)) allocated from top of first 2G ddr region and compile trusted OS with this fixed base address. But one exception here is ls1012 where we have only 1G (rdb) or 512M (frdm) ddr memory. For those we can have different fixed compile time base addresses for trusted OS. Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
e9303a41 |
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07-Sep-2017 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: Fix MC reserved memory calculation In case high region memory doesn't have enough space for Management Complex (MC), the return value should indicate a failure so the caller can handle it accordingly. Signed-off-by: York Sun <york.sun@nxp.com> Reported-by: Ebony Zhu <ebony.zhu@nxp.com> |
#
17d066fc |
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31-Aug-2017 |
Ashish Kumar <Ashish.Kumar@nxp.com> |
armv8: fsl-layerscape: Support to add RGMII for ls1088aqds This patch adds support for RGMII protocol NXP's LDPAA2 support RGMII protocol. LS1088A is the first Soc supporting both RGMII and SGMII. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Amrita Kumari <amrita.kumari@nxp.com> Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
63b2316c |
|
10-Aug-2017 |
Ashish Kumar <Ashish.Kumar@nxp.com> |
fsl-layerscape: Consolidate registers space defination for CCI-400 bus CoreLink Cache Coherent Interconnect (CCI) provides full cache coherency between two clusters of multi-core CPUs and I/O coherency for devices and I/O masters. This patch add new config option SYS_FSL_HAS_CCI400 and moves existing register space definaton of CCI-400 bus to fsl_immap to be shared. CONFIG_SYS_CCI400_ADDR is replaced with SYS_CCI400_OFFSET in Kconfig. Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> [YS: revised commit message, squashed patches for armv8 and armv7] Reviewed-by: York Sun <york.sun@nxp.com> |
#
6e2941d7 |
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17-May-2017 |
Simon Glass <sjg@chromium.org> |
common: freescale: Move arch-specific declarations The declarations should not be in common.h. Move them to the arch-specific headers. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Fixup thinko defined(FSL_LSCH3) -> defined(CONFIG_FSL_LSCH3)] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
399e2bb6 |
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15-May-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Make U-Boot EL2 safe When U-Boot boots from EL2, skip some lowlevel init code requiring EL3, including CCI-400/CCN-504, trust zone, GIC, etc. These initialization tasks are carried out before U-Boot runs. This applies to the RAM version image used for SPL boot if PPA is loaded first. Signed-off-by: York Sun <york.sun@nxp.com> |
#
1f55a938 |
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05-May-2017 |
Santan Kumar <santan.kumar@nxp.com> |
armv8: ls2080aqds: Add support for SD boot Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
e809e747 |
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27-Apr-2017 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: fsl-layerscape: Add NXP LS2081A, LS2041A SoC support The QorIQ LS2081A SoC has eight 64-bit ARM v8 Cortex A72 cores and is built on layerscape architecture. It is 40-pin derivative of LS2084A (non-AIOP personality of LS2088A). So feature-wise it is same as LS2084A. LS2041A is a 4-core personality of LS2081A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
026f30ec |
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18-Apr-2017 |
Yuantian Tang <andy.tang@nxp.com> |
arm: psci: make psci usable on single core socs PSCI can be used on both multiple and single core socs. Current implementation only allows PSCI to work on multiple core socs. This patch removes this restriction so that PSCI can work on single core socs as well. Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
4a3ab193 |
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27-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: ls2080a: Drop macro CONFIG_LS2080A Use CONFIG_ARCH_LS2080A instead. Signed-off-by: York Sun <york.sun@nxp.com> |
#
3eace37e |
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06-Apr-2017 |
Simon Glass <sjg@chromium.org> |
arm: freescale: Rename initdram() to fsl_initdram() This function name shadows a global name but is in fact different. This is very confusing. Rename it to help with the following refactoring. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
76b00aca |
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31-Mar-2017 |
Simon Glass <sjg@chromium.org> |
board_f: Drop setup_dram_config() wrapper By making dram_init_banksize() return an error code we can drop the wrapper. Adjust this and clean up all implementations. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
088454cd |
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31-Mar-2017 |
Simon Glass <sjg@chromium.org> |
board_f: Drop return value from initdram() At present we cannot use this function as an init sequence call without a wrapper, since it returns the RAM size. Adjust it to set the RAM size in global_data instead, and return 0 on success. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
52c41180 |
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31-Mar-2017 |
Simon Glass <sjg@chromium.org> |
board_f: Drop board_type parameter from initdram() It looks like only cm5200 and tqm8xx use this feature, so we don't really need it in generic code. Drop it and have the users access gd->board_type directly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
3d8553f0 |
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02-Mar-2017 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
pci: layerscape: add LS2088A series SoC pcie support The LS2088A series SoCs has different physical memory map address and CCSR registers address against LS2080A series SoCs. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
eea1cb77 |
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13-Feb-2017 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8/fsl-layerscape: Update erratum A009635 implementation Erratum A009635 is valid only for LS2080A SoC and its personality. Add SoC svr check. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
4961eafc |
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06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Update early MMU for DDR after initialization In early MMU table, DDR has to be mapped as device memory to avoid speculative access. After DDR is initialized, it needs to be updated to normal memory to allow code execution. To simplify the code, dram_init() is moved into a common file as a weak function. Signed-off-by: York Sun <york.sun@nxp.com> |
#
a045a0c3 |
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06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Fix the sequence of changing MMU table This patch follows the break-before-make process when making changes to MMU table. MMU is disabled before changing TTBR to avoid any potential race condition. Signed-off-by: York Sun <york.sun@nxp.com> |
#
24f55496 |
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06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Update MMU mapping with actual DDR size Update mapping with actual DDR size. Non-existing memory should not be mapped as "normal" memory to avoid speculative access. Signed-off-by: York Sun <york.sun@nxp.com> |
#
36cc0de0 |
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06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Rewrite memory reservation For ARMv8 Layerscape SoCs, secure memory and MC memorey are reserved at the end of DDR. DDR is spit into two or three banks. This patch reverts commit aabd7ddb and simplifies the calculation of reserved memory, and moves the code into common SoC file. Secure memory is carved out first. DDR bank size is reduced. Reserved memory is then allocated on the top of available memory. U-Boot still has access to reserved memory as data transferring is needed. Device tree is fixed with reduced memory size to hide the reserved memory from OS. The same region is reserved for efi_loader. Signed-off-by: York Sun <york.sun@nxp.com> |
#
daa92644 |
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16-Jan-2017 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
ARMv8/sec_firmware: relocated and renamed the config FSL_PPA_ARMV8_PSCI Moved the config FSL_PPA_ARMV8_PSCI from fsl-layerscape's Kconfig to Kconfig under armv8 and renamed it to SEC_FIRMWARE_ARMV8_PSCI. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
904110c7 |
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10-Jan-2017 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8/fsl-lsch2: refactor the clock system initialization Up to now, there are 3 kind of SoCs under Layerscape Chassis 2, like LS1043A, LS1046A and LS1012A. But the clocks tree has a lot of differences, for instance, the IP modules have different dividers to derive its clock from Platform PLL. And the core cluster PLL and platform PLL maybe have different reference clocks, such as LS1012A. Another problem is which clock/PLL should be described by sys_info->freq_systembus, it is confused in Layerscape Chissis 2. This patch is to bind the sys_info->freq_systembus to the Platform PLL, and handle the different divider of IP modules separately between different SoCs, and separate reference clocks of core cluster PLL and platform PLL. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
2d16a1a6 |
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07-Dec-2016 |
macro.wave.z@gmail.com <macro.wave.z@gmail.com> |
ARMv8: LS1043A: change macro CONFIG_ARMV8_PSCI definition NXP/Freescale uses macro CONFIG_ARMV8_PSCI to enable their private PSCI implementation in PPA firmware, but this macro naming too generic, so this patch replaces it with a specic one CONFIG_FSL_PPA_ARMV8_PSCI. And this macro CONFIG_ARMV8_PSCI will be used for a generic PSCI for ARMv8 which will be added in following patchs. Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
02fb2761 |
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20-Nov-2016 |
Shengzhou Liu <Shengzhou.Liu@nxp.com> |
fsl/ddr: Add erratum_a009942_check_cpo and clean related erratum - add additional function erratum_a009942_check_cpo to check if the board needs tuning CPO calibration for optimal setting. - move ERRATUM_A009942(with revision to check cpo_sample option) from fsl_ddr_gen4.c to ctrl_regs.c for reuse on all DDR4/DDR3 parts. - move ERRATUM_A008378 from fsl_ddr_gen4.c to ctrl_regs.c - remove obsolete ERRATUM_A004934 which is replaced with ERRATUM_A009942. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> [YS: Replaced CONFIG_QEMU_E500 with CONFIG_ARCH_QEMU_E500] Reviewed-by: York Sun <york.sun@nxp.com> |
#
e87c673c |
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16-Nov-2016 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8/fsl-lsch3: Update code to release secondary cores NXP ARMv8 SoC LS2080A release all secondary cores in one-go. But other new SoCs like LS2088A, LS1088A release secondary cores one by one. Update code to release secondary cores based on SoC SVR Add code to release cores one by one for non LS2080A SoCs Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> [YS: remove "inline" from declaration of initiator_type] Reviewed-by: York Sun <york.sun@nxp.com> |
#
f6b96ff6 |
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16-Nov-2016 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Use SVR based timer base address detection Timer controller base address has been changed from LS2080A SoC (and its personalities) to new SoCs like LS2088A, LS1088A. Use SVR based timer base address detection to avoid compile time #ifdef. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
f6a70b3a |
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16-Nov-2016 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add generic get_svr() in assembly Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
78d57842 |
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16-Nov-2016 |
Alexander Graf <agraf@csgraf.de> |
armv8: fsl-layerscape: Add support for efi_loader RTS reset When implementing efi loader support, we can expose runtime services for payloads. One such service is CPU reset. This patch implements RTS CPU reset support for layerscape systems. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: York Sun <york.sun@nxp.com> |
#
ef9a5fd8 |
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13-Sep-2016 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: Fix "cpu status" command The core position is not continuous for some SoCs. For example, valid cores may present at position 0, 1, 4, 5, 8, 9, etc. Some registers (including boot release register) only count existing cores. Current implementation of cpu_mask() complies with the continuous numbering. However, command "cpu status" queries the spin table with actual core position. Add functions to calculate core position from core number, to correctly calculate offsets. Tested on LS2080ARDB and LS1043ARDB. Signed-off-by: York Sun <york.sun@nxp.com> |
#
5d1a7a9d |
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13-Sep-2016 |
Wenbin Song <wenbin.song@nxp.com> |
armv8/fsl-layerscape: print SoC revsion number The exact SoC revsion number can be recognized from U-Boot log. Signed-off-by: Wenbin Song <wenbin.song@nxp.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
cbe7706a |
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26-Sep-2016 |
Tom Rini <trini@konsulko.com> |
Merge git://git.denx.de/u-boot-fsl-qoriq trini: Drop local memset() from examples/standalone/mem_to_mem_idma2intr.c Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
1221ce45 |
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20-Sep-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
treewide: replace #include <asm/errno.h> with <linux/errno.h> Now, arch/${ARCH}/include/asm/errno.h and include/linux/errno.h have the same content. (both just wrap <asm-generic/errno.h>) Replace all include directives for <asm/errno.h> with <linux/errno.h>. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> [trini: Fixup include/clk.] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
b63a9506 |
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03-Aug-2016 |
York Sun <york.sun@nxp.com> |
armv8: ls2080a: Remove debug server support Debug server feature has been dropped from roadmap. Signed-off-by: York Sun <york.sun@nxp.com> |
#
ed7a3943 |
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22-Jul-2016 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: mmu: Fix enabling MMU MMU bit in SCTLR needs to be set explicitly after tables are created. It isn't an issue for EL3 becuase this bit is already set by early MMU setup. But for other exception levels this bit was not set. Signed-off-by: York Sun <york.sun@nxp.com> |
#
79119a4d |
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05-Jul-2016 |
Alison Wang <b18965@freescale.com> |
armv8: fsl-layerscape: Add A72 core detection Add support to detect Cortex-A72 core for printing it out. The Initiator Version of A72 core should be 0x4. Signed-off-by: Alison Wang <alison.wang@nxp.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
032d5bb4 |
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28-Jun-2016 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
ARMv8/Layerscape: switch SMP method accordingly If the PSCI and PPA is ready, skip the fixup for spin-table and waking secondary cores. Otherwise, change SMP method to spin-table, and the device node of PSCI will be removed. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
85cdf38e |
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28-Jun-2016 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: fsl-layerscape: add i/d-cache enable function to enable_caches This function assume that the d-cache and MMU has been enabled earlier, so it just created MMU table in main memory. But the assumption is not always correct, for example, the early setup is done in EL3, while enable_caches() is called when the PE has turned into another EL. Define the function mmu_setup() for fsl-layerscape to cover the weak one. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
5ad5823d |
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24-Jun-2016 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Convert to use common MMU framework Drop platform code to create static MMU tables. Use common framework to create MMU tables on the run. Tested on LS2080ARDB with secure and non-secure ram scenarios. Signed-off-by: York Sun <york.sun@nxp.com> |
#
e61a7534 |
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24-Jun-2016 |
York Sun <york.sun@nxp.com> |
armv8: Move secure_ram variable out of generic global data Secure_ram variable was put in generic global data. But only ARMv8 uses this variable. Move it to ARM specific data structure. Signed-off-by: York Sun <york.sun@nxp.com> |
#
a10a31ec |
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18-Jun-2016 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of git://git.denx.de/u-boot-usb Signed-off-by: Tom Rini <trini@konsulko.com> Conflicts: arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
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#
6fb522dc |
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12-Jun-2016 |
Sriram Dash <sriram.dash@nxp.com> |
arm64: fsl-layerscape: add get_svr and IS_SVR_REV helper Adds get_svr and IS_SVR_REV helpers for ARMv8 platforms, similar to PPC and ARMv7. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> |
#
a758177f |
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07-Jun-2016 |
Yunhui Cui <yunhui.cui@nxp.com> |
armv8/ls2080a: configure PMU's PCTBENR to enable WDT The SP805-WDT module on LS2080A requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. The watchdog clock needs to be enabled first. Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
acb8f5e9 |
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21-Apr-2016 |
Alison Wang <b18965@freescale.com> |
armv8: fsl-layerscape: Remove unnecessary flushing dcache As the issue about the stack will get corrupted when switching between the early and final mmu tables is fixed by commit 70e21b064, the workaround to flush dcache is unnecessary and should be removed. Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
3c1d218a |
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04-Apr-2016 |
York Sun <york.sun@nxp.com> |
armv8: LS2080A: Consolidate LS2080A and LS2085A LS2080A is the primary SoC, and LS2085A is a personality with AIOP and DPAA DDR. The RDB and QDS boards support both personality. By detecting the SVR at runtime, a single image per board can support both SoCs. It gives users flexibility to swtich SoC without the need to reprogram the board. Signed-off-by: York Sun <york.sun@nxp.com> CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
c05016ab |
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21-Mar-2016 |
Alexander Graf <agraf@csgraf.de> |
arm64: Fix layerscape mmu setup With commit 7985cdf we converted all systems except for the Layerscape SoCs to the generic descriptor table based page table setup. On the Layerscape SoCs however, we just provide an empty table stub and do the setup ourselves. To reserve enough memory for the tables, we need to override the default counting mechanism which would end up with an empty table because we have no maps. Fixes: 7985cdf Reported-by: York Sun <york.sun@nxp.com> CC: Alison Wang <alison.wang@nxp.com> CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Alexander Graf <agraf@suse.de> Tested-by: York Sun <york.sun@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
7985cdf7 |
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03-Mar-2016 |
Alexander Graf <agraf@csgraf.de> |
arm64: Remove non-full-va map code By now the code to only have a single page table level with 64k page size and 42 bit address space is no longer used by any board in tree, so we can safely remove it. To clean up code, move the layerscape mmu code to the new defines, removing redundant field definitions. Signed-off-by: Alexander Graf <agraf@suse.de> |
#
c0492141 |
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07-Dec-2015 |
York Sun <yorksun@freescale.com> |
armv8: fsl-layerscale: Rewrite reserving memory for MC and debug server MC and debug server are not board-specific. Move reserving memory to SoC file, using the new board_reserve_ram_top function. Reduce debug server memory by 2MB to make room for secure memory. In the system with MC and debug server, the top of u-boot memory is not the end of memory. PRAM is not used for this reservation. Signed-off-by: York Sun <yorksun@freescale.com> |
#
c107c0c0 |
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04-Dec-2015 |
York Sun <yorksun@freescale.com> |
armv8: fsl-layerscape: Make DDR non secure in MMU tables DDR has been set as secure in MMU tables. Non-secure master such as SDHC DMA cannot access data correctly. Mixing secure and non- secure MMU entries requirs the MMU tables themselves in secure memory. This patch moves MMU tables into a secure DDR area. Early MMU tables are changed to set DDR as non-secure. A new table is added into final MMU tables so secure memory can have 2MB granuality. gd->secure_ram tracks the location of this secure memory. For ARMv8 SoCs, the RAM base is not zero and RAM is divided into several banks. gd->secure_ram needs to be maintained before using. This maintenance is board-specific, depending on the SoC and memory bank of the secure memory falls into. Signed-off-by: York Sun <yorksun@freescale.com> |
#
b4017364 |
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04-Nov-2015 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
armv8: ls2085a: Add workaround of errata A009635 If the core runs at higher than x3 speed of the platform, there is possiblity about sev instruction to getting missed by other cores. This is because of SoC Run Control block may not able to sample the EVENTI(Sev) signals. Configure Run Control and EPU to periodically send out EVENTI signals to wake up A57 cores. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
d764129d |
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04-Nov-2015 |
Alison Wang <b18965@freescale.com> |
armv8/layerscape: Update MMU table with execute-never bits For most device addresses excution shouldn't be allowed. Revise the MMU table to enforce execute-never bits. OCRAM, DDR and IFC are allowed for excution. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Alison Wang <alison.wang@freescale.com> Reported-by: Zhichun Hua <zhichun.hua@freescale.com> |
#
44937214 |
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09-Nov-2015 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
armv8: LS2080A: Rename LS2085A to reflect LS2080A LS2080A is a prime personality of Freescale’s LS2085A. It is a non-AIOP personality without support of DP-DDR, L2 switch, 1588, PCIe endpoint etc. So renaming existing LS2085A code base to reflect LS2080A (Prime personality) Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> [York Sun: Dropped #ifdef in cpu.c for cpu_type_list] Reviewed-by: York Sun <yorksun@freescale.com> |
#
e8297341 |
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26-Oct-2015 |
Shaohui Xie <Shaohui.Xie@freescale.com> |
armv8/ls1043a: Add Fman support Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
8281c58f |
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26-Oct-2015 |
Mingkai Hu <Mingkai.Hu@freescale.com> |
armv8/fsl_lsch2: Add fsl_lsch2 SoC Freescale LayerScape with Chassis Generation 2 is a set of SoCs with ARMv8 cores and 2rd generation of Chassis. Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
9f3183d2 |
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26-Oct-2015 |
Mingkai Hu <Mingkai.Hu@freescale.com> |
armv8/fsl_lsch3: Change arch to fsl-layerscape There are two LS series processors are built on ARMv8 Layersacpe architecture currently, LS2085A and LS1043A. They are based on ARMv8 core although use different chassis, so create fsl-layerscape to refactor the common code for the LS series processors which also paves the way for adding LS1043A platform. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
3a187cff |
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29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
c760095a |
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23-Oct-2020 |
Razvan Ionut Cirjan <razvanionut.cirjan@nxp.com> |
net: lx2160a.c: Update to set ECx_PMUX precedence As per hardware documentation, ECx_PMUX has precedence over SerDes protocol. For LX2160/LX2162 if DPMACs 17 and 18 are enabled as SGMII through SerDes protocol but ECx_PMUX configured them as RGMII, then the ports will be configured as RGMII and not SGMII. Signed-off-by: Razvan Ionut Cirjan <razvanionut.cirjan@nxp.com> [Rebased] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
d31f3a1b |
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09-Sep-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2160a: fix reset sequence Make sure that SW_RST_REQ and RST_REQ_MSK are cleared before triggering hardware reset request. Signed-off-by: Thirupathaiah Annapureddy <thiruan@linux.microsoft.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
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b75d8dc5 |
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26-Jun-2020 |
Masahiro Yamada <masahiroy@kernel.org> |
treewide: convert bd_t to struct bd_info by coccinelle The Linux coding style guide (Documentation/process/coding-style.rst) clearly says: It's a **mistake** to use typedef for structures and pointers. Besides, using typedef for structures is annoying when you try to make headers self-contained. Let's say you have the following function declaration in a header: void foo(bd_t *bd); This is not self-contained since bd_t is not defined. To tell the compiler what 'bd_t' is, you need to include <asm/u-boot.h> #include <asm/u-boot.h> void foo(bd_t *bd); Then, the include direcective pulls in more bloat needlessly. If you use 'struct bd_info' instead, it is enough to put a forward declaration as follows: struct bd_info; void foo(struct bd_info *bd); Right, typedef'ing bd_t is a mistake. I used coccinelle to generate this commit. The semantic patch that makes this change is as follows: <smpl> @@ typedef bd_t; @@ -bd_t +struct bd_info </smpl> Signed-off-by: Masahiro Yamada <masahiroy@kernel.org> |
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25a5818f |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop asm/ptrace.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
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f7ae49fc |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
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90526e9f |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop net.h from common header Move this header out of the common header. Network support is used in quite a few places but it still does not warrant blanket inclusion. Note that this net.h header itself has quite a lot in it. It could be split into the driver-mode support, functions, structures, checksumming, etc. Signed-off-by: Simon Glass <sjg@chromium.org> |
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714497e3 |
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16-May-2020 |
Michael Walle <michael@walle.cc> |
efi_loader: round the memory area in efi_add_memory_map() Virtually all callers of this function do the rounding on their own. Some do it right, some don't. Instead of doing this in each caller, do the rounding in efi_add_memory_map(). Change the size parameter to bytes instead of pages and remove aligning and size calculation in all callers. There is no more need to make the original efi_add_memory_map() (which takes pages as size) available outside the module. Thus rename it to efi_add_memory_map_pg() and make it static to prevent further misuse outside the module. Signed-off-by: Michael Walle <michael@walle.cc> Add missing comma in sunxi_display.c. Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de> |
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6eb32a03 |
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23-Apr-2020 |
Madalin Bucur <madalin.bucur@oss.nxp.com> |
driver: net: fm: add DM ETH support Probe the FMan MACs based on the device tree while retaining the legacy code/functionality. One notable change introduced here is that, for DM_ETH, the name of the interfaces is corrected to the fmX-macY format, that avoids the referral to the MAC block names which were incorrect for FMan v3 devices (i.e. DTSEC, TGEC) and had weird formatting (i.e. FM1@DTSEC6, FM1@TGEC1). The legacy code is left unchanged in this respect. Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
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6ebd4883 |
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27-Apr-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
fsl-layerscape: Add RESV_RAM check in resv_ram addr The initialization of gd->arch.resv_ram pointer should depend on if the RESV_RAM config is enabled. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Wasim Khan <wasim.khan@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
0d9d557d |
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10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
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db41d65a |
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28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move hang() to the same header as panic() At present panic() is in the vsprintf.h header file. That does not seem like an obvious choice for hang(), even though it relates to panic(). So let's put hang() in its own header. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Migrate a few more files] Signed-off-by: Tom Rini <trini@konsulko.com> |
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9b4a205f |
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28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move RAM-sizing functions to init.h These functions relate to memory init so move them into the init header. Signed-off-by: Simon Glass <sjg@chromium.org> |
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3499dd03 |
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27-Nov-2019 |
Alex Marginean <alexandru.marginean@nxp.com> |
ls1028a: Configure stream IDs for integrated PCI and fix up Linux DT Hardware comes out of reset with implicit values, but these are outside the accepted range for Layerscape gen 3 chassis spec used on LS1028A. Allocate different IDs and fix up Linux DT to use them. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
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b5981474 |
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14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some CPU functions out of common.h These functions belong in cpu_func.h since they do not use driver model. Move them over. Don't bother adding comments since these functions should be deleted. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
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68a6aa85 |
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14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move mii_init() function out of common.h This function belongs in mii.h so move it over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
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2189d5f1 |
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14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
Move strtomhz() to vsprintf.h At present this function sits in its own file but it does not really justify it. There are similar string functions in vsprintf.h, so move it there. Also add the missing function comment. Use the vsprintf.h include file explicitly where needed. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
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812ff53c |
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30-Oct-2019 |
Pankaj Bansal <pankaj.bansal@nxp.com> |
fsl-layerscape: fix warning if no hwconfig is defined While getting the 'subarg' of 'hwconfig' env variable in config_core_prefetch(), if no hwconfig variable is defined, below warning is received: WARNING: Calling __hwconfig without a buffer and before environment is ready Fix this by checking 'hwconfig' env variable. If not found return without further processing. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Tested-by: Michael Walle <michael@walle.cc> |
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28f9393b |
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17-Oct-2019 |
Mathew McBride <matt@traverse.com.au> |
fsl-layerscape: do not use layerscape EFI reset if PSCI used If the secure world reset handlers are used (via CONFIG_PSCI_RESET), then do not use the layerscape-specific implementation. Signed-off-by: Mathew McBride <matt@traverse.com.au> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
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6ed69523 |
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18-Sep-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add more personalities support Add LS1027A, LS1018A and LS1017A personalities support to LS1028A SoC family. LS1028A is the prime personality of LS1028A SoC family. LS1027A is a lower funtionality version of QorIQ LS1028A which does not support the multimedia subsystems, such as LCD controller, GPU, and eDP PHY. The QorIQ LS1018A and LS1017A SoCs are single 64-bit Arm A72 core, low power versions of the QorIQ LS1028A and LS1027A SoCs respectively. Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
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0490cab5 |
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08-Aug-2019 |
Thomas Schaefer <thomas.schaefer@kontron.com> |
armv8: ls1028a: configure PMU's PCTBENR to enable WDT The SP805-WDT module on LS1028A requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. The watchdog clock needs to be enabled first. Signed-off-by: Thomas Schaefer <thomas.schaefer@kontron.com> Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
f3998fdc |
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02-Aug-2019 |
Simon Glass <sjg@chromium.org> |
env: Rename environment.h to env_internal.h This file contains lots of internal details about the environment. Most code can include env.h instead, calling the functions there as needed. Rename this file and add a comment at the top to indicate its internal nature. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> [trini: Fixup apalis-tk1.c] Signed-off-by: Tom Rini <trini@konsulko.com> |
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3a7d5571 |
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01-Aug-2019 |
Simon Glass <sjg@chromium.org> |
env: Move env_get_f() to env.h Move this function over to the new header file. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
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d9532e80 |
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23-Apr-2019 |
Udit Agarwal <udit.agarwal@nxp.com> |
armv8: fsl-layerscape: Set env_loc to ENVL_NOWHERE with CONFIG_ENV_IS_NOWHERE. ENVL_NOWHERE is dependent on CONFIG_ENV_IS_NOWHERE and not on CONFIG_CHAIN_OF_TRUST so return ENVL_NOWHERE when CONFIG_ENV_IS_NOWHERE is enabled Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
d4ad111d |
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10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
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059d9422 |
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08-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: lx2160a: add MMU table entries for PCIe The lx2160a have up to 6 PCIe controllers and have different address and size of PCIe region. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
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8348e798 |
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08-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: layerscape: use PCIe address macro for precompile PCIe MMU entry Change to use PCIe address macro to determine if precompile the PCIe MMU table entry. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
10015025 |
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03-May-2019 |
Trevor Woerner <trevor@toganlabs.com> |
CONFIG_SPL_SYS_[DI]CACHE_OFF: add While converting CONFIG_SYS_[DI]CACHE_OFF to Kconfig, there are instances where these configuration items are conditional on SPL. This commit adds SPL variants of these configuration items, uses CONFIG_IS_ENABLED(), and updates the configurations as required. Acked-by: Alexey Brodkin <abrodkin@synopsys.com> Signed-off-by: Trevor Woerner <trevor@toganlabs.com> [trini: Make the default depend on the setting for full U-Boot, update more zynq hardware] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
2e53759d |
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29-Oct-2018 |
Pankaj Bansal <pankaj.bansal@nxp.com> |
armv8: fsl-layerscape: reorder rgmii dpmacs' enablement some dpmacs in armv8a based freescale layerscape SOCs can be configured via both serdes(sgmii, xfi, xlaui etc) bits and via EC*_PMUX(rgmii) bits in RCW. e.g. dpmac 17 and 18 in LX2160A can be configured as SGMII from serdes bits and as RGMII via EC1_PMUX/EC2_PMUX bits Now if a dpmac is enabled by serdes bits then it takes precedence over EC*_PMUX bits. i.e. in LX2160A if we select serdes protocol that configures dpmac17 as SGMII and set the EC1_PMUX as RGMII, then the dpmac is SGMII and not RGMII. Therefore, move the fsl_rgmii_init after fsl_serdes_init. in fsl_rgmii_init function of SOC, we will check if the dpmac is enabled or not? if it is (fsl_serdes_init has already enabled the dpmac), then don't enable it. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
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ec88ff80 |
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19-Dec-2018 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1043a: add SVR definitions for 23x23 package silicon LS1043A/LS1023A 23x23 package silicon has different SVR:VAR_PER. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
d23da2ae |
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26-Dec-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: fixes for TFABOOT framework Fixes for TFABOOT framework - update eMMC bootsrc to SD_MMC - Increase buffer size for mcinitcmd from 256 to 512 - Fix mcinitcmd and bootcmd for Secure Boot Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
4909b89e |
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29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
d6fdec21 |
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29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8:fsl-layerscape: Add support for Chassis 3.2 NXP layerscape architecture Chassis 3.2 builds upon chassis3 architecture with changes like DDR Memory map change, removal of IFC and support of upto 8 I2C controller. Patch add README.lsch3_2 and the above changes under macro CONFIG_NXP_LSCH3_2. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
56db948b |
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05-Nov-2018 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: Update parsing boot source Workaround of erratum A010539 clears the RCW source field in PORSR1 register, causing failure of detecting boot source using this method. Use SMC call if U-Boot runs at EL2. If SMC is not implemented or running at EL3, continue to read PORSR1 and presume QSPI as boot source if erratum workaround A010539 is enabled and RCW source is cleared. Signed-off-by: York Sun <york.sun@nxp.com> |
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681d489e |
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05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: layerscape: add SMC calls for DDR size and bank info Adds SMC calls for getting DDR size and bank info for TFABOOT. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
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2141d250 |
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05-Nov-2018 |
Pankit Garg <pankit.garg@nxp.com> |
armv8: fsl-layerscape: bootcmd identification for TFABOOT Adds bootcmd identificaton on basis on boot source, valid in TFABOOT configuration. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> [YS: remove unnecessary braces] Reviewed-by: York Sun <york.sun@nxp.com> |
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4c417384 |
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05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com> |
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535d76a1 |
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05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: layerscape: Add TFABOOT support Adds TFABOOT support config option and add generic code to enable execution from DDR. Signed-off-by: York Sun <york.sun@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> |
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e3506480 |
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05-Nov-2018 |
Pankit Garg <pankit.garg@nxp.com> |
armv8: fsl-layerscape: change tlb base from OCRAM to DDR in EL < 3 Change tlb base address from OCRAM to DDR when exception level is less than 3. Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
d171c707 |
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05-Nov-2018 |
York Sun <york.sun@nxp.com> |
move data structure out of cpu.h Move static definitions to cpu.c file, as it doesn't allow the cpu.h file to be included in multiple c files. Signed-off-by: York Sun <york.sun@nxp.com> |
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9b5e6396 |
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30-Aug-2018 |
Stephen Warren <swarren@nvidia.com> |
efi_loader: simplify ifdefs Use CONFIG_IS_ENABLED(EFI_LOADER) to avoid explicitly checking CONFIG_SPL too. This simplifies the conditional. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Alexander Graf <agraf@suse.de> |
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9cce5663 |
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16-Jul-2018 |
Joe Hershberger <joe.hershberger@ni.com> |
arm: Prevent redefinition error in fsl-layerscape The include/phy.h will start including dm.h, which pulls in linux/compat.h after the attempted redefinition in arch/arm/include/asm/armv8/mmu.h, so move this include to allow redefinition. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> |
#
83d290c5 |
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06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
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482fc90c |
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06-Feb-2018 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
efi_loader: add missing EFI_RESET_PLATFORM_SPECIFIC EFI_RESET_PLATFORM_SPECIFIC is one of the values that can be used for the EFI service ResetSystem. The missing definition is added. The value has to handled in efi_reset_system(). Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Alexander Graf <agraf@suse.de> |
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22c793e6 |
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03-Mar-2018 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
efi_loader: exit status for efi_reset_system_init efi_reset_system_init provides the architecture or board specific initialization of the EFI subsystem. Errors should be caught and signalled by a return code. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Alexander Graf <agraf@suse.de> |
#
958b2ed5 |
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09-Jan-2018 |
Zhang Ying-22455 <ying.zhang22455@nxp.com> |
armv8/ls1088a: configure PMU's PCTBENR to enable WDT The SP805-WDT module on LS1088A requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. The watchdog clock needs to be enabled first. Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
44262327 |
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15-Dec-2017 |
Ahmed Mansour <ahmed.mansour@nxp.com> |
drivers/misc: Share qbman init between archs This patch adds changes necessary to move functionality present in PowerPC folders with ARM architectures that have DPAA1 QBMan hardware - Create new board/freescale/common/fsl_portals.c to house shared device tree fixups for DPAA1 devices with ARM and PowerPC cores - Add new header file to top includes directory to allow files in both architectures to grab the function prototypes - Port inhibit_portals() from PowerPC to ARM. This function is used in setup to disable interrupts on all QMan and BMan portals. It is needed because the interrupts are enabled by default for all portals including unused/uninitialised portals. When the kernel attempts to go to deep sleep the unused portals prevent it from doing so Signed-off-by: Ahmed Mansour <ahmed.mansour@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
a8f33034 |
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03-Dec-2017 |
Wenbin song <wenbin.song@nxp.com> |
armv8: ls1043a/ls2080a: check SoC by device ID Check LS1043A/LS2080a by device ID without using personality ID to determine revision number. This check applies to all various personalities of the same SoC family. Signed-off-by: Wenbin Song <wenbin.song@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
2db53cfe |
|
09-Nov-2017 |
Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
armv8: fsl-layerscape: Add support of disabling core prefetch Instruction prefetch feature is by default enabled during core release. This patch add support of disabling instruction prefetch by setting core mask in PPA. Here each core mask bit represents a core and prefetch is disabled at the time of core release. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
7eb40f0f |
|
28-Sep-2017 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: Avoid running dram_init_banksize again gd->ram_size is reduced in this function to reserve secure memory. Avoid running this function again to further reduce memory size. This fixes issue for SPL boot with PPA image loaded in which case secure memory is incorrectly allocated due to repeated calling. Signed-off-by: York Sun <york.sun@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
710d0cd7 |
|
03-Oct-2017 |
Sumit Garg <sumit.garg@nxp.com> |
armv8: fsl-layerscape: Allocate Secure memory from first ddr region This change is required due to trusted OS (OP-TEE) not being position independent code, it requires compile time fixed base address. To take care of this it is assumed that all layerscape armv8 platforms has minimum 2G ddr in first region. So we can have fixed address space (66 MB -> (2MB for PPA + 64MB for trusted OS)) allocated from top of first 2G ddr region and compile trusted OS with this fixed base address. But one exception here is ls1012 where we have only 1G (rdb) or 512M (frdm) ddr memory. For those we can have different fixed compile time base addresses for trusted OS. Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
e9303a41 |
|
07-Sep-2017 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: Fix MC reserved memory calculation In case high region memory doesn't have enough space for Management Complex (MC), the return value should indicate a failure so the caller can handle it accordingly. Signed-off-by: York Sun <york.sun@nxp.com> Reported-by: Ebony Zhu <ebony.zhu@nxp.com> |
#
17d066fc |
|
31-Aug-2017 |
Ashish Kumar <Ashish.Kumar@nxp.com> |
armv8: fsl-layerscape: Support to add RGMII for ls1088aqds This patch adds support for RGMII protocol NXP's LDPAA2 support RGMII protocol. LS1088A is the first Soc supporting both RGMII and SGMII. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Amrita Kumari <amrita.kumari@nxp.com> Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
63b2316c |
|
10-Aug-2017 |
Ashish Kumar <Ashish.Kumar@nxp.com> |
fsl-layerscape: Consolidate registers space defination for CCI-400 bus CoreLink Cache Coherent Interconnect (CCI) provides full cache coherency between two clusters of multi-core CPUs and I/O coherency for devices and I/O masters. This patch add new config option SYS_FSL_HAS_CCI400 and moves existing register space definaton of CCI-400 bus to fsl_immap to be shared. CONFIG_SYS_CCI400_ADDR is replaced with SYS_CCI400_OFFSET in Kconfig. Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> [YS: revised commit message, squashed patches for armv8 and armv7] Reviewed-by: York Sun <york.sun@nxp.com> |
#
6e2941d7 |
|
17-May-2017 |
Simon Glass <sjg@chromium.org> |
common: freescale: Move arch-specific declarations The declarations should not be in common.h. Move them to the arch-specific headers. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Fixup thinko defined(FSL_LSCH3) -> defined(CONFIG_FSL_LSCH3)] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
399e2bb6 |
|
15-May-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Make U-Boot EL2 safe When U-Boot boots from EL2, skip some lowlevel init code requiring EL3, including CCI-400/CCN-504, trust zone, GIC, etc. These initialization tasks are carried out before U-Boot runs. This applies to the RAM version image used for SPL boot if PPA is loaded first. Signed-off-by: York Sun <york.sun@nxp.com> |
#
1f55a938 |
|
05-May-2017 |
Santan Kumar <santan.kumar@nxp.com> |
armv8: ls2080aqds: Add support for SD boot Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
e809e747 |
|
27-Apr-2017 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: fsl-layerscape: Add NXP LS2081A, LS2041A SoC support The QorIQ LS2081A SoC has eight 64-bit ARM v8 Cortex A72 cores and is built on layerscape architecture. It is 40-pin derivative of LS2084A (non-AIOP personality of LS2088A). So feature-wise it is same as LS2084A. LS2041A is a 4-core personality of LS2081A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
026f30ec |
|
18-Apr-2017 |
Yuantian Tang <andy.tang@nxp.com> |
arm: psci: make psci usable on single core socs PSCI can be used on both multiple and single core socs. Current implementation only allows PSCI to work on multiple core socs. This patch removes this restriction so that PSCI can work on single core socs as well. Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
4a3ab193 |
|
27-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: ls2080a: Drop macro CONFIG_LS2080A Use CONFIG_ARCH_LS2080A instead. Signed-off-by: York Sun <york.sun@nxp.com> |
#
3eace37e |
|
06-Apr-2017 |
Simon Glass <sjg@chromium.org> |
arm: freescale: Rename initdram() to fsl_initdram() This function name shadows a global name but is in fact different. This is very confusing. Rename it to help with the following refactoring. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
76b00aca |
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31-Mar-2017 |
Simon Glass <sjg@chromium.org> |
board_f: Drop setup_dram_config() wrapper By making dram_init_banksize() return an error code we can drop the wrapper. Adjust this and clean up all implementations. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
088454cd |
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31-Mar-2017 |
Simon Glass <sjg@chromium.org> |
board_f: Drop return value from initdram() At present we cannot use this function as an init sequence call without a wrapper, since it returns the RAM size. Adjust it to set the RAM size in global_data instead, and return 0 on success. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
52c41180 |
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31-Mar-2017 |
Simon Glass <sjg@chromium.org> |
board_f: Drop board_type parameter from initdram() It looks like only cm5200 and tqm8xx use this feature, so we don't really need it in generic code. Drop it and have the users access gd->board_type directly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
3d8553f0 |
|
02-Mar-2017 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
pci: layerscape: add LS2088A series SoC pcie support The LS2088A series SoCs has different physical memory map address and CCSR registers address against LS2080A series SoCs. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
eea1cb77 |
|
13-Feb-2017 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8/fsl-layerscape: Update erratum A009635 implementation Erratum A009635 is valid only for LS2080A SoC and its personality. Add SoC svr check. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
4961eafc |
|
06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Update early MMU for DDR after initialization In early MMU table, DDR has to be mapped as device memory to avoid speculative access. After DDR is initialized, it needs to be updated to normal memory to allow code execution. To simplify the code, dram_init() is moved into a common file as a weak function. Signed-off-by: York Sun <york.sun@nxp.com> |
#
a045a0c3 |
|
06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Fix the sequence of changing MMU table This patch follows the break-before-make process when making changes to MMU table. MMU is disabled before changing TTBR to avoid any potential race condition. Signed-off-by: York Sun <york.sun@nxp.com> |
#
24f55496 |
|
06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Update MMU mapping with actual DDR size Update mapping with actual DDR size. Non-existing memory should not be mapped as "normal" memory to avoid speculative access. Signed-off-by: York Sun <york.sun@nxp.com> |
#
36cc0de0 |
|
06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Rewrite memory reservation For ARMv8 Layerscape SoCs, secure memory and MC memorey are reserved at the end of DDR. DDR is spit into two or three banks. This patch reverts commit aabd7ddb and simplifies the calculation of reserved memory, and moves the code into common SoC file. Secure memory is carved out first. DDR bank size is reduced. Reserved memory is then allocated on the top of available memory. U-Boot still has access to reserved memory as data transferring is needed. Device tree is fixed with reduced memory size to hide the reserved memory from OS. The same region is reserved for efi_loader. Signed-off-by: York Sun <york.sun@nxp.com> |
#
daa92644 |
|
16-Jan-2017 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
ARMv8/sec_firmware: relocated and renamed the config FSL_PPA_ARMV8_PSCI Moved the config FSL_PPA_ARMV8_PSCI from fsl-layerscape's Kconfig to Kconfig under armv8 and renamed it to SEC_FIRMWARE_ARMV8_PSCI. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
904110c7 |
|
10-Jan-2017 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8/fsl-lsch2: refactor the clock system initialization Up to now, there are 3 kind of SoCs under Layerscape Chassis 2, like LS1043A, LS1046A and LS1012A. But the clocks tree has a lot of differences, for instance, the IP modules have different dividers to derive its clock from Platform PLL. And the core cluster PLL and platform PLL maybe have different reference clocks, such as LS1012A. Another problem is which clock/PLL should be described by sys_info->freq_systembus, it is confused in Layerscape Chissis 2. This patch is to bind the sys_info->freq_systembus to the Platform PLL, and handle the different divider of IP modules separately between different SoCs, and separate reference clocks of core cluster PLL and platform PLL. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
2d16a1a6 |
|
07-Dec-2016 |
macro.wave.z@gmail.com <macro.wave.z@gmail.com> |
ARMv8: LS1043A: change macro CONFIG_ARMV8_PSCI definition NXP/Freescale uses macro CONFIG_ARMV8_PSCI to enable their private PSCI implementation in PPA firmware, but this macro naming too generic, so this patch replaces it with a specic one CONFIG_FSL_PPA_ARMV8_PSCI. And this macro CONFIG_ARMV8_PSCI will be used for a generic PSCI for ARMv8 which will be added in following patchs. Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
02fb2761 |
|
20-Nov-2016 |
Shengzhou Liu <Shengzhou.Liu@nxp.com> |
fsl/ddr: Add erratum_a009942_check_cpo and clean related erratum - add additional function erratum_a009942_check_cpo to check if the board needs tuning CPO calibration for optimal setting. - move ERRATUM_A009942(with revision to check cpo_sample option) from fsl_ddr_gen4.c to ctrl_regs.c for reuse on all DDR4/DDR3 parts. - move ERRATUM_A008378 from fsl_ddr_gen4.c to ctrl_regs.c - remove obsolete ERRATUM_A004934 which is replaced with ERRATUM_A009942. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> [YS: Replaced CONFIG_QEMU_E500 with CONFIG_ARCH_QEMU_E500] Reviewed-by: York Sun <york.sun@nxp.com> |
#
e87c673c |
|
16-Nov-2016 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8/fsl-lsch3: Update code to release secondary cores NXP ARMv8 SoC LS2080A release all secondary cores in one-go. But other new SoCs like LS2088A, LS1088A release secondary cores one by one. Update code to release secondary cores based on SoC SVR Add code to release cores one by one for non LS2080A SoCs Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> [YS: remove "inline" from declaration of initiator_type] Reviewed-by: York Sun <york.sun@nxp.com> |
#
f6b96ff6 |
|
16-Nov-2016 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Use SVR based timer base address detection Timer controller base address has been changed from LS2080A SoC (and its personalities) to new SoCs like LS2088A, LS1088A. Use SVR based timer base address detection to avoid compile time #ifdef. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
f6a70b3a |
|
16-Nov-2016 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add generic get_svr() in assembly Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
78d57842 |
|
16-Nov-2016 |
Alexander Graf <agraf@csgraf.de> |
armv8: fsl-layerscape: Add support for efi_loader RTS reset When implementing efi loader support, we can expose runtime services for payloads. One such service is CPU reset. This patch implements RTS CPU reset support for layerscape systems. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: York Sun <york.sun@nxp.com> |
#
ef9a5fd8 |
|
13-Sep-2016 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: Fix "cpu status" command The core position is not continuous for some SoCs. For example, valid cores may present at position 0, 1, 4, 5, 8, 9, etc. Some registers (including boot release register) only count existing cores. Current implementation of cpu_mask() complies with the continuous numbering. However, command "cpu status" queries the spin table with actual core position. Add functions to calculate core position from core number, to correctly calculate offsets. Tested on LS2080ARDB and LS1043ARDB. Signed-off-by: York Sun <york.sun@nxp.com> |
#
5d1a7a9d |
|
13-Sep-2016 |
Wenbin Song <wenbin.song@nxp.com> |
armv8/fsl-layerscape: print SoC revsion number The exact SoC revsion number can be recognized from U-Boot log. Signed-off-by: Wenbin Song <wenbin.song@nxp.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
cbe7706a |
|
26-Sep-2016 |
Tom Rini <trini@konsulko.com> |
Merge git://git.denx.de/u-boot-fsl-qoriq trini: Drop local memset() from examples/standalone/mem_to_mem_idma2intr.c Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
1221ce45 |
|
20-Sep-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
treewide: replace #include <asm/errno.h> with <linux/errno.h> Now, arch/${ARCH}/include/asm/errno.h and include/linux/errno.h have the same content. (both just wrap <asm-generic/errno.h>) Replace all include directives for <asm/errno.h> with <linux/errno.h>. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> [trini: Fixup include/clk.] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
b63a9506 |
|
03-Aug-2016 |
York Sun <york.sun@nxp.com> |
armv8: ls2080a: Remove debug server support Debug server feature has been dropped from roadmap. Signed-off-by: York Sun <york.sun@nxp.com> |
#
ed7a3943 |
|
22-Jul-2016 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: mmu: Fix enabling MMU MMU bit in SCTLR needs to be set explicitly after tables are created. It isn't an issue for EL3 becuase this bit is already set by early MMU setup. But for other exception levels this bit was not set. Signed-off-by: York Sun <york.sun@nxp.com> |
#
79119a4d |
|
05-Jul-2016 |
Alison Wang <b18965@freescale.com> |
armv8: fsl-layerscape: Add A72 core detection Add support to detect Cortex-A72 core for printing it out. The Initiator Version of A72 core should be 0x4. Signed-off-by: Alison Wang <alison.wang@nxp.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
032d5bb4 |
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28-Jun-2016 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
ARMv8/Layerscape: switch SMP method accordingly If the PSCI and PPA is ready, skip the fixup for spin-table and waking secondary cores. Otherwise, change SMP method to spin-table, and the device node of PSCI will be removed. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
85cdf38e |
|
28-Jun-2016 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: fsl-layerscape: add i/d-cache enable function to enable_caches This function assume that the d-cache and MMU has been enabled earlier, so it just created MMU table in main memory. But the assumption is not always correct, for example, the early setup is done in EL3, while enable_caches() is called when the PE has turned into another EL. Define the function mmu_setup() for fsl-layerscape to cover the weak one. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
5ad5823d |
|
24-Jun-2016 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Convert to use common MMU framework Drop platform code to create static MMU tables. Use common framework to create MMU tables on the run. Tested on LS2080ARDB with secure and non-secure ram scenarios. Signed-off-by: York Sun <york.sun@nxp.com> |
#
e61a7534 |
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24-Jun-2016 |
York Sun <york.sun@nxp.com> |
armv8: Move secure_ram variable out of generic global data Secure_ram variable was put in generic global data. But only ARMv8 uses this variable. Move it to ARM specific data structure. Signed-off-by: York Sun <york.sun@nxp.com> |
#
a10a31ec |
|
18-Jun-2016 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of git://git.denx.de/u-boot-usb Signed-off-by: Tom Rini <trini@konsulko.com> Conflicts: arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
|
#
6fb522dc |
|
12-Jun-2016 |
Sriram Dash <sriram.dash@nxp.com> |
arm64: fsl-layerscape: add get_svr and IS_SVR_REV helper Adds get_svr and IS_SVR_REV helpers for ARMv8 platforms, similar to PPC and ARMv7. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> |
#
a758177f |
|
07-Jun-2016 |
Yunhui Cui <yunhui.cui@nxp.com> |
armv8/ls2080a: configure PMU's PCTBENR to enable WDT The SP805-WDT module on LS2080A requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. The watchdog clock needs to be enabled first. Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
acb8f5e9 |
|
21-Apr-2016 |
Alison Wang <b18965@freescale.com> |
armv8: fsl-layerscape: Remove unnecessary flushing dcache As the issue about the stack will get corrupted when switching between the early and final mmu tables is fixed by commit 70e21b064, the workaround to flush dcache is unnecessary and should be removed. Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
3c1d218a |
|
04-Apr-2016 |
York Sun <york.sun@nxp.com> |
armv8: LS2080A: Consolidate LS2080A and LS2085A LS2080A is the primary SoC, and LS2085A is a personality with AIOP and DPAA DDR. The RDB and QDS boards support both personality. By detecting the SVR at runtime, a single image per board can support both SoCs. It gives users flexibility to swtich SoC without the need to reprogram the board. Signed-off-by: York Sun <york.sun@nxp.com> CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
c05016ab |
|
21-Mar-2016 |
Alexander Graf <agraf@csgraf.de> |
arm64: Fix layerscape mmu setup With commit 7985cdf we converted all systems except for the Layerscape SoCs to the generic descriptor table based page table setup. On the Layerscape SoCs however, we just provide an empty table stub and do the setup ourselves. To reserve enough memory for the tables, we need to override the default counting mechanism which would end up with an empty table because we have no maps. Fixes: 7985cdf Reported-by: York Sun <york.sun@nxp.com> CC: Alison Wang <alison.wang@nxp.com> CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Alexander Graf <agraf@suse.de> Tested-by: York Sun <york.sun@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
7985cdf7 |
|
03-Mar-2016 |
Alexander Graf <agraf@csgraf.de> |
arm64: Remove non-full-va map code By now the code to only have a single page table level with 64k page size and 42 bit address space is no longer used by any board in tree, so we can safely remove it. To clean up code, move the layerscape mmu code to the new defines, removing redundant field definitions. Signed-off-by: Alexander Graf <agraf@suse.de> |
#
c0492141 |
|
07-Dec-2015 |
York Sun <yorksun@freescale.com> |
armv8: fsl-layerscale: Rewrite reserving memory for MC and debug server MC and debug server are not board-specific. Move reserving memory to SoC file, using the new board_reserve_ram_top function. Reduce debug server memory by 2MB to make room for secure memory. In the system with MC and debug server, the top of u-boot memory is not the end of memory. PRAM is not used for this reservation. Signed-off-by: York Sun <yorksun@freescale.com> |
#
c107c0c0 |
|
04-Dec-2015 |
York Sun <yorksun@freescale.com> |
armv8: fsl-layerscape: Make DDR non secure in MMU tables DDR has been set as secure in MMU tables. Non-secure master such as SDHC DMA cannot access data correctly. Mixing secure and non- secure MMU entries requirs the MMU tables themselves in secure memory. This patch moves MMU tables into a secure DDR area. Early MMU tables are changed to set DDR as non-secure. A new table is added into final MMU tables so secure memory can have 2MB granuality. gd->secure_ram tracks the location of this secure memory. For ARMv8 SoCs, the RAM base is not zero and RAM is divided into several banks. gd->secure_ram needs to be maintained before using. This maintenance is board-specific, depending on the SoC and memory bank of the secure memory falls into. Signed-off-by: York Sun <yorksun@freescale.com> |
#
b4017364 |
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04-Nov-2015 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
armv8: ls2085a: Add workaround of errata A009635 If the core runs at higher than x3 speed of the platform, there is possiblity about sev instruction to getting missed by other cores. This is because of SoC Run Control block may not able to sample the EVENTI(Sev) signals. Configure Run Control and EPU to periodically send out EVENTI signals to wake up A57 cores. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
d764129d |
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04-Nov-2015 |
Alison Wang <b18965@freescale.com> |
armv8/layerscape: Update MMU table with execute-never bits For most device addresses excution shouldn't be allowed. Revise the MMU table to enforce execute-never bits. OCRAM, DDR and IFC are allowed for excution. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Alison Wang <alison.wang@freescale.com> Reported-by: Zhichun Hua <zhichun.hua@freescale.com> |
#
44937214 |
|
09-Nov-2015 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
armv8: LS2080A: Rename LS2085A to reflect LS2080A LS2080A is a prime personality of Freescale’s LS2085A. It is a non-AIOP personality without support of DP-DDR, L2 switch, 1588, PCIe endpoint etc. So renaming existing LS2085A code base to reflect LS2080A (Prime personality) Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> [York Sun: Dropped #ifdef in cpu.c for cpu_type_list] Reviewed-by: York Sun <yorksun@freescale.com> |
#
e8297341 |
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26-Oct-2015 |
Shaohui Xie <Shaohui.Xie@freescale.com> |
armv8/ls1043a: Add Fman support Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
8281c58f |
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26-Oct-2015 |
Mingkai Hu <Mingkai.Hu@freescale.com> |
armv8/fsl_lsch2: Add fsl_lsch2 SoC Freescale LayerScape with Chassis Generation 2 is a set of SoCs with ARMv8 cores and 2rd generation of Chassis. Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
9f3183d2 |
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26-Oct-2015 |
Mingkai Hu <Mingkai.Hu@freescale.com> |
armv8/fsl_lsch3: Change arch to fsl-layerscape There are two LS series processors are built on ARMv8 Layersacpe architecture currently, LS2085A and LS1043A. They are based on ARMv8 core although use different chassis, so create fsl-layerscape to refactor the common code for the LS series processors which also paves the way for adding LS1043A platform. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
c760095a |
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23-Oct-2020 |
Razvan Ionut Cirjan <razvanionut.cirjan@nxp.com> |
net: lx2160a.c: Update to set ECx_PMUX precedence As per hardware documentation, ECx_PMUX has precedence over SerDes protocol. For LX2160/LX2162 if DPMACs 17 and 18 are enabled as SGMII through SerDes protocol but ECx_PMUX configured them as RGMII, then the ports will be configured as RGMII and not SGMII. Signed-off-by: Razvan Ionut Cirjan <razvanionut.cirjan@nxp.com> [Rebased] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
d31f3a1b |
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09-Sep-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2160a: fix reset sequence Make sure that SW_RST_REQ and RST_REQ_MSK are cleared before triggering hardware reset request. Signed-off-by: Thirupathaiah Annapureddy <thiruan@linux.microsoft.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
b75d8dc5 |
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26-Jun-2020 |
Masahiro Yamada <masahiroy@kernel.org> |
treewide: convert bd_t to struct bd_info by coccinelle The Linux coding style guide (Documentation/process/coding-style.rst) clearly says: It's a **mistake** to use typedef for structures and pointers. Besides, using typedef for structures is annoying when you try to make headers self-contained. Let's say you have the following function declaration in a header: void foo(bd_t *bd); This is not self-contained since bd_t is not defined. To tell the compiler what 'bd_t' is, you need to include <asm/u-boot.h> #include <asm/u-boot.h> void foo(bd_t *bd); Then, the include direcective pulls in more bloat needlessly. If you use 'struct bd_info' instead, it is enough to put a forward declaration as follows: struct bd_info; void foo(struct bd_info *bd); Right, typedef'ing bd_t is a mistake. I used coccinelle to generate this commit. The semantic patch that makes this change is as follows: <smpl> @@ typedef bd_t; @@ -bd_t +struct bd_info </smpl> Signed-off-by: Masahiro Yamada <masahiroy@kernel.org> |
#
25a5818f |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop asm/ptrace.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
f7ae49fc |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
90526e9f |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop net.h from common header Move this header out of the common header. Network support is used in quite a few places but it still does not warrant blanket inclusion. Note that this net.h header itself has quite a lot in it. It could be split into the driver-mode support, functions, structures, checksumming, etc. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
714497e3 |
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16-May-2020 |
Michael Walle <michael@walle.cc> |
efi_loader: round the memory area in efi_add_memory_map() Virtually all callers of this function do the rounding on their own. Some do it right, some don't. Instead of doing this in each caller, do the rounding in efi_add_memory_map(). Change the size parameter to bytes instead of pages and remove aligning and size calculation in all callers. There is no more need to make the original efi_add_memory_map() (which takes pages as size) available outside the module. Thus rename it to efi_add_memory_map_pg() and make it static to prevent further misuse outside the module. Signed-off-by: Michael Walle <michael@walle.cc> Add missing comma in sunxi_display.c. Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de> |
#
6eb32a03 |
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23-Apr-2020 |
Madalin Bucur <madalin.bucur@oss.nxp.com> |
driver: net: fm: add DM ETH support Probe the FMan MACs based on the device tree while retaining the legacy code/functionality. One notable change introduced here is that, for DM_ETH, the name of the interfaces is corrected to the fmX-macY format, that avoids the referral to the MAC block names which were incorrect for FMan v3 devices (i.e. DTSEC, TGEC) and had weird formatting (i.e. FM1@DTSEC6, FM1@TGEC1). The legacy code is left unchanged in this respect. Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
6ebd4883 |
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27-Apr-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
fsl-layerscape: Add RESV_RAM check in resv_ram addr The initialization of gd->arch.resv_ram pointer should depend on if the RESV_RAM config is enabled. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Wasim Khan <wasim.khan@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
0d9d557d |
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10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
db41d65a |
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28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move hang() to the same header as panic() At present panic() is in the vsprintf.h header file. That does not seem like an obvious choice for hang(), even though it relates to panic(). So let's put hang() in its own header. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Migrate a few more files] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
9b4a205f |
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28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move RAM-sizing functions to init.h These functions relate to memory init so move them into the init header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
3499dd03 |
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27-Nov-2019 |
Alex Marginean <alexandru.marginean@nxp.com> |
ls1028a: Configure stream IDs for integrated PCI and fix up Linux DT Hardware comes out of reset with implicit values, but these are outside the accepted range for Layerscape gen 3 chassis spec used on LS1028A. Allocate different IDs and fix up Linux DT to use them. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
b5981474 |
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14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some CPU functions out of common.h These functions belong in cpu_func.h since they do not use driver model. Move them over. Don't bother adding comments since these functions should be deleted. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
68a6aa85 |
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14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move mii_init() function out of common.h This function belongs in mii.h so move it over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
2189d5f1 |
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14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
Move strtomhz() to vsprintf.h At present this function sits in its own file but it does not really justify it. There are similar string functions in vsprintf.h, so move it there. Also add the missing function comment. Use the vsprintf.h include file explicitly where needed. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
812ff53c |
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30-Oct-2019 |
Pankaj Bansal <pankaj.bansal@nxp.com> |
fsl-layerscape: fix warning if no hwconfig is defined While getting the 'subarg' of 'hwconfig' env variable in config_core_prefetch(), if no hwconfig variable is defined, below warning is received: WARNING: Calling __hwconfig without a buffer and before environment is ready Fix this by checking 'hwconfig' env variable. If not found return without further processing. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Tested-by: Michael Walle <michael@walle.cc> |
#
28f9393b |
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17-Oct-2019 |
Mathew McBride <matt@traverse.com.au> |
fsl-layerscape: do not use layerscape EFI reset if PSCI used If the secure world reset handlers are used (via CONFIG_PSCI_RESET), then do not use the layerscape-specific implementation. Signed-off-by: Mathew McBride <matt@traverse.com.au> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
6ed69523 |
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18-Sep-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add more personalities support Add LS1027A, LS1018A and LS1017A personalities support to LS1028A SoC family. LS1028A is the prime personality of LS1028A SoC family. LS1027A is a lower funtionality version of QorIQ LS1028A which does not support the multimedia subsystems, such as LCD controller, GPU, and eDP PHY. The QorIQ LS1018A and LS1017A SoCs are single 64-bit Arm A72 core, low power versions of the QorIQ LS1028A and LS1027A SoCs respectively. Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
0490cab5 |
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08-Aug-2019 |
Thomas Schaefer <thomas.schaefer@kontron.com> |
armv8: ls1028a: configure PMU's PCTBENR to enable WDT The SP805-WDT module on LS1028A requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. The watchdog clock needs to be enabled first. Signed-off-by: Thomas Schaefer <thomas.schaefer@kontron.com> Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
f3998fdc |
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02-Aug-2019 |
Simon Glass <sjg@chromium.org> |
env: Rename environment.h to env_internal.h This file contains lots of internal details about the environment. Most code can include env.h instead, calling the functions there as needed. Rename this file and add a comment at the top to indicate its internal nature. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> [trini: Fixup apalis-tk1.c] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
3a7d5571 |
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01-Aug-2019 |
Simon Glass <sjg@chromium.org> |
env: Move env_get_f() to env.h Move this function over to the new header file. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
d9532e80 |
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23-Apr-2019 |
Udit Agarwal <udit.agarwal@nxp.com> |
armv8: fsl-layerscape: Set env_loc to ENVL_NOWHERE with CONFIG_ENV_IS_NOWHERE. ENVL_NOWHERE is dependent on CONFIG_ENV_IS_NOWHERE and not on CONFIG_CHAIN_OF_TRUST so return ENVL_NOWHERE when CONFIG_ENV_IS_NOWHERE is enabled Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
d4ad111d |
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10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
059d9422 |
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08-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: lx2160a: add MMU table entries for PCIe The lx2160a have up to 6 PCIe controllers and have different address and size of PCIe region. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
8348e798 |
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08-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: layerscape: use PCIe address macro for precompile PCIe MMU entry Change to use PCIe address macro to determine if precompile the PCIe MMU table entry. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
10015025 |
|
03-May-2019 |
Trevor Woerner <trevor@toganlabs.com> |
CONFIG_SPL_SYS_[DI]CACHE_OFF: add While converting CONFIG_SYS_[DI]CACHE_OFF to Kconfig, there are instances where these configuration items are conditional on SPL. This commit adds SPL variants of these configuration items, uses CONFIG_IS_ENABLED(), and updates the configurations as required. Acked-by: Alexey Brodkin <abrodkin@synopsys.com> Signed-off-by: Trevor Woerner <trevor@toganlabs.com> [trini: Make the default depend on the setting for full U-Boot, update more zynq hardware] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
2e53759d |
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29-Oct-2018 |
Pankaj Bansal <pankaj.bansal@nxp.com> |
armv8: fsl-layerscape: reorder rgmii dpmacs' enablement some dpmacs in armv8a based freescale layerscape SOCs can be configured via both serdes(sgmii, xfi, xlaui etc) bits and via EC*_PMUX(rgmii) bits in RCW. e.g. dpmac 17 and 18 in LX2160A can be configured as SGMII from serdes bits and as RGMII via EC1_PMUX/EC2_PMUX bits Now if a dpmac is enabled by serdes bits then it takes precedence over EC*_PMUX bits. i.e. in LX2160A if we select serdes protocol that configures dpmac17 as SGMII and set the EC1_PMUX as RGMII, then the dpmac is SGMII and not RGMII. Therefore, move the fsl_rgmii_init after fsl_serdes_init. in fsl_rgmii_init function of SOC, we will check if the dpmac is enabled or not? if it is (fsl_serdes_init has already enabled the dpmac), then don't enable it. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
ec88ff80 |
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19-Dec-2018 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1043a: add SVR definitions for 23x23 package silicon LS1043A/LS1023A 23x23 package silicon has different SVR:VAR_PER. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
d23da2ae |
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26-Dec-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: fixes for TFABOOT framework Fixes for TFABOOT framework - update eMMC bootsrc to SD_MMC - Increase buffer size for mcinitcmd from 256 to 512 - Fix mcinitcmd and bootcmd for Secure Boot Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
4909b89e |
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29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
d6fdec21 |
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29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8:fsl-layerscape: Add support for Chassis 3.2 NXP layerscape architecture Chassis 3.2 builds upon chassis3 architecture with changes like DDR Memory map change, removal of IFC and support of upto 8 I2C controller. Patch add README.lsch3_2 and the above changes under macro CONFIG_NXP_LSCH3_2. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
56db948b |
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05-Nov-2018 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: Update parsing boot source Workaround of erratum A010539 clears the RCW source field in PORSR1 register, causing failure of detecting boot source using this method. Use SMC call if U-Boot runs at EL2. If SMC is not implemented or running at EL3, continue to read PORSR1 and presume QSPI as boot source if erratum workaround A010539 is enabled and RCW source is cleared. Signed-off-by: York Sun <york.sun@nxp.com> |
#
681d489e |
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05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: layerscape: add SMC calls for DDR size and bank info Adds SMC calls for getting DDR size and bank info for TFABOOT. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
2141d250 |
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05-Nov-2018 |
Pankit Garg <pankit.garg@nxp.com> |
armv8: fsl-layerscape: bootcmd identification for TFABOOT Adds bootcmd identificaton on basis on boot source, valid in TFABOOT configuration. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> [YS: remove unnecessary braces] Reviewed-by: York Sun <york.sun@nxp.com> |
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com> |
#
535d76a1 |
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05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: layerscape: Add TFABOOT support Adds TFABOOT support config option and add generic code to enable execution from DDR. Signed-off-by: York Sun <york.sun@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> |
#
e3506480 |
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05-Nov-2018 |
Pankit Garg <pankit.garg@nxp.com> |
armv8: fsl-layerscape: change tlb base from OCRAM to DDR in EL < 3 Change tlb base address from OCRAM to DDR when exception level is less than 3. Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
d171c707 |
|
05-Nov-2018 |
York Sun <york.sun@nxp.com> |
move data structure out of cpu.h Move static definitions to cpu.c file, as it doesn't allow the cpu.h file to be included in multiple c files. Signed-off-by: York Sun <york.sun@nxp.com> |
#
9b5e6396 |
|
30-Aug-2018 |
Stephen Warren <swarren@nvidia.com> |
efi_loader: simplify ifdefs Use CONFIG_IS_ENABLED(EFI_LOADER) to avoid explicitly checking CONFIG_SPL too. This simplifies the conditional. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Alexander Graf <agraf@suse.de> |
#
9cce5663 |
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16-Jul-2018 |
Joe Hershberger <joe.hershberger@ni.com> |
arm: Prevent redefinition error in fsl-layerscape The include/phy.h will start including dm.h, which pulls in linux/compat.h after the attempted redefinition in arch/arm/include/asm/armv8/mmu.h, so move this include to allow redefinition. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> |
#
83d290c5 |
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06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
482fc90c |
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06-Feb-2018 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
efi_loader: add missing EFI_RESET_PLATFORM_SPECIFIC EFI_RESET_PLATFORM_SPECIFIC is one of the values that can be used for the EFI service ResetSystem. The missing definition is added. The value has to handled in efi_reset_system(). Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Alexander Graf <agraf@suse.de> |
#
22c793e6 |
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03-Mar-2018 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
efi_loader: exit status for efi_reset_system_init efi_reset_system_init provides the architecture or board specific initialization of the EFI subsystem. Errors should be caught and signalled by a return code. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Alexander Graf <agraf@suse.de> |
#
958b2ed5 |
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09-Jan-2018 |
Zhang Ying-22455 <ying.zhang22455@nxp.com> |
armv8/ls1088a: configure PMU's PCTBENR to enable WDT The SP805-WDT module on LS1088A requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. The watchdog clock needs to be enabled first. Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
44262327 |
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15-Dec-2017 |
Ahmed Mansour <ahmed.mansour@nxp.com> |
drivers/misc: Share qbman init between archs This patch adds changes necessary to move functionality present in PowerPC folders with ARM architectures that have DPAA1 QBMan hardware - Create new board/freescale/common/fsl_portals.c to house shared device tree fixups for DPAA1 devices with ARM and PowerPC cores - Add new header file to top includes directory to allow files in both architectures to grab the function prototypes - Port inhibit_portals() from PowerPC to ARM. This function is used in setup to disable interrupts on all QMan and BMan portals. It is needed because the interrupts are enabled by default for all portals including unused/uninitialised portals. When the kernel attempts to go to deep sleep the unused portals prevent it from doing so Signed-off-by: Ahmed Mansour <ahmed.mansour@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
a8f33034 |
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03-Dec-2017 |
Wenbin song <wenbin.song@nxp.com> |
armv8: ls1043a/ls2080a: check SoC by device ID Check LS1043A/LS2080a by device ID without using personality ID to determine revision number. This check applies to all various personalities of the same SoC family. Signed-off-by: Wenbin Song <wenbin.song@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
2db53cfe |
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09-Nov-2017 |
Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
armv8: fsl-layerscape: Add support of disabling core prefetch Instruction prefetch feature is by default enabled during core release. This patch add support of disabling instruction prefetch by setting core mask in PPA. Here each core mask bit represents a core and prefetch is disabled at the time of core release. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
7eb40f0f |
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28-Sep-2017 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: Avoid running dram_init_banksize again gd->ram_size is reduced in this function to reserve secure memory. Avoid running this function again to further reduce memory size. This fixes issue for SPL boot with PPA image loaded in which case secure memory is incorrectly allocated due to repeated calling. Signed-off-by: York Sun <york.sun@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
710d0cd7 |
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03-Oct-2017 |
Sumit Garg <sumit.garg@nxp.com> |
armv8: fsl-layerscape: Allocate Secure memory from first ddr region This change is required due to trusted OS (OP-TEE) not being position independent code, it requires compile time fixed base address. To take care of this it is assumed that all layerscape armv8 platforms has minimum 2G ddr in first region. So we can have fixed address space (66 MB -> (2MB for PPA + 64MB for trusted OS)) allocated from top of first 2G ddr region and compile trusted OS with this fixed base address. But one exception here is ls1012 where we have only 1G (rdb) or 512M (frdm) ddr memory. For those we can have different fixed compile time base addresses for trusted OS. Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
e9303a41 |
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07-Sep-2017 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: Fix MC reserved memory calculation In case high region memory doesn't have enough space for Management Complex (MC), the return value should indicate a failure so the caller can handle it accordingly. Signed-off-by: York Sun <york.sun@nxp.com> Reported-by: Ebony Zhu <ebony.zhu@nxp.com> |
#
17d066fc |
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31-Aug-2017 |
Ashish Kumar <Ashish.Kumar@nxp.com> |
armv8: fsl-layerscape: Support to add RGMII for ls1088aqds This patch adds support for RGMII protocol NXP's LDPAA2 support RGMII protocol. LS1088A is the first Soc supporting both RGMII and SGMII. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Amrita Kumari <amrita.kumari@nxp.com> Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
63b2316c |
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10-Aug-2017 |
Ashish Kumar <Ashish.Kumar@nxp.com> |
fsl-layerscape: Consolidate registers space defination for CCI-400 bus CoreLink Cache Coherent Interconnect (CCI) provides full cache coherency between two clusters of multi-core CPUs and I/O coherency for devices and I/O masters. This patch add new config option SYS_FSL_HAS_CCI400 and moves existing register space definaton of CCI-400 bus to fsl_immap to be shared. CONFIG_SYS_CCI400_ADDR is replaced with SYS_CCI400_OFFSET in Kconfig. Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> [YS: revised commit message, squashed patches for armv8 and armv7] Reviewed-by: York Sun <york.sun@nxp.com> |
#
6e2941d7 |
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17-May-2017 |
Simon Glass <sjg@chromium.org> |
common: freescale: Move arch-specific declarations The declarations should not be in common.h. Move them to the arch-specific headers. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Fixup thinko defined(FSL_LSCH3) -> defined(CONFIG_FSL_LSCH3)] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
399e2bb6 |
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15-May-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Make U-Boot EL2 safe When U-Boot boots from EL2, skip some lowlevel init code requiring EL3, including CCI-400/CCN-504, trust zone, GIC, etc. These initialization tasks are carried out before U-Boot runs. This applies to the RAM version image used for SPL boot if PPA is loaded first. Signed-off-by: York Sun <york.sun@nxp.com> |
#
1f55a938 |
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05-May-2017 |
Santan Kumar <santan.kumar@nxp.com> |
armv8: ls2080aqds: Add support for SD boot Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
e809e747 |
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27-Apr-2017 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: fsl-layerscape: Add NXP LS2081A, LS2041A SoC support The QorIQ LS2081A SoC has eight 64-bit ARM v8 Cortex A72 cores and is built on layerscape architecture. It is 40-pin derivative of LS2084A (non-AIOP personality of LS2088A). So feature-wise it is same as LS2084A. LS2041A is a 4-core personality of LS2081A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
026f30ec |
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18-Apr-2017 |
Yuantian Tang <andy.tang@nxp.com> |
arm: psci: make psci usable on single core socs PSCI can be used on both multiple and single core socs. Current implementation only allows PSCI to work on multiple core socs. This patch removes this restriction so that PSCI can work on single core socs as well. Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
4a3ab193 |
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27-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: ls2080a: Drop macro CONFIG_LS2080A Use CONFIG_ARCH_LS2080A instead. Signed-off-by: York Sun <york.sun@nxp.com> |
#
3eace37e |
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06-Apr-2017 |
Simon Glass <sjg@chromium.org> |
arm: freescale: Rename initdram() to fsl_initdram() This function name shadows a global name but is in fact different. This is very confusing. Rename it to help with the following refactoring. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
76b00aca |
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31-Mar-2017 |
Simon Glass <sjg@chromium.org> |
board_f: Drop setup_dram_config() wrapper By making dram_init_banksize() return an error code we can drop the wrapper. Adjust this and clean up all implementations. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
088454cd |
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31-Mar-2017 |
Simon Glass <sjg@chromium.org> |
board_f: Drop return value from initdram() At present we cannot use this function as an init sequence call without a wrapper, since it returns the RAM size. Adjust it to set the RAM size in global_data instead, and return 0 on success. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
52c41180 |
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31-Mar-2017 |
Simon Glass <sjg@chromium.org> |
board_f: Drop board_type parameter from initdram() It looks like only cm5200 and tqm8xx use this feature, so we don't really need it in generic code. Drop it and have the users access gd->board_type directly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
3d8553f0 |
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02-Mar-2017 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
pci: layerscape: add LS2088A series SoC pcie support The LS2088A series SoCs has different physical memory map address and CCSR registers address against LS2080A series SoCs. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
eea1cb77 |
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13-Feb-2017 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8/fsl-layerscape: Update erratum A009635 implementation Erratum A009635 is valid only for LS2080A SoC and its personality. Add SoC svr check. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
4961eafc |
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06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Update early MMU for DDR after initialization In early MMU table, DDR has to be mapped as device memory to avoid speculative access. After DDR is initialized, it needs to be updated to normal memory to allow code execution. To simplify the code, dram_init() is moved into a common file as a weak function. Signed-off-by: York Sun <york.sun@nxp.com> |
#
a045a0c3 |
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06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Fix the sequence of changing MMU table This patch follows the break-before-make process when making changes to MMU table. MMU is disabled before changing TTBR to avoid any potential race condition. Signed-off-by: York Sun <york.sun@nxp.com> |
#
24f55496 |
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06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Update MMU mapping with actual DDR size Update mapping with actual DDR size. Non-existing memory should not be mapped as "normal" memory to avoid speculative access. Signed-off-by: York Sun <york.sun@nxp.com> |
#
36cc0de0 |
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06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Rewrite memory reservation For ARMv8 Layerscape SoCs, secure memory and MC memorey are reserved at the end of DDR. DDR is spit into two or three banks. This patch reverts commit aabd7ddb and simplifies the calculation of reserved memory, and moves the code into common SoC file. Secure memory is carved out first. DDR bank size is reduced. Reserved memory is then allocated on the top of available memory. U-Boot still has access to reserved memory as data transferring is needed. Device tree is fixed with reduced memory size to hide the reserved memory from OS. The same region is reserved for efi_loader. Signed-off-by: York Sun <york.sun@nxp.com> |
#
daa92644 |
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16-Jan-2017 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
ARMv8/sec_firmware: relocated and renamed the config FSL_PPA_ARMV8_PSCI Moved the config FSL_PPA_ARMV8_PSCI from fsl-layerscape's Kconfig to Kconfig under armv8 and renamed it to SEC_FIRMWARE_ARMV8_PSCI. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
904110c7 |
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10-Jan-2017 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8/fsl-lsch2: refactor the clock system initialization Up to now, there are 3 kind of SoCs under Layerscape Chassis 2, like LS1043A, LS1046A and LS1012A. But the clocks tree has a lot of differences, for instance, the IP modules have different dividers to derive its clock from Platform PLL. And the core cluster PLL and platform PLL maybe have different reference clocks, such as LS1012A. Another problem is which clock/PLL should be described by sys_info->freq_systembus, it is confused in Layerscape Chissis 2. This patch is to bind the sys_info->freq_systembus to the Platform PLL, and handle the different divider of IP modules separately between different SoCs, and separate reference clocks of core cluster PLL and platform PLL. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
2d16a1a6 |
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07-Dec-2016 |
macro.wave.z@gmail.com <macro.wave.z@gmail.com> |
ARMv8: LS1043A: change macro CONFIG_ARMV8_PSCI definition NXP/Freescale uses macro CONFIG_ARMV8_PSCI to enable their private PSCI implementation in PPA firmware, but this macro naming too generic, so this patch replaces it with a specic one CONFIG_FSL_PPA_ARMV8_PSCI. And this macro CONFIG_ARMV8_PSCI will be used for a generic PSCI for ARMv8 which will be added in following patchs. Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
02fb2761 |
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20-Nov-2016 |
Shengzhou Liu <Shengzhou.Liu@nxp.com> |
fsl/ddr: Add erratum_a009942_check_cpo and clean related erratum - add additional function erratum_a009942_check_cpo to check if the board needs tuning CPO calibration for optimal setting. - move ERRATUM_A009942(with revision to check cpo_sample option) from fsl_ddr_gen4.c to ctrl_regs.c for reuse on all DDR4/DDR3 parts. - move ERRATUM_A008378 from fsl_ddr_gen4.c to ctrl_regs.c - remove obsolete ERRATUM_A004934 which is replaced with ERRATUM_A009942. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> [YS: Replaced CONFIG_QEMU_E500 with CONFIG_ARCH_QEMU_E500] Reviewed-by: York Sun <york.sun@nxp.com> |
#
e87c673c |
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16-Nov-2016 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8/fsl-lsch3: Update code to release secondary cores NXP ARMv8 SoC LS2080A release all secondary cores in one-go. But other new SoCs like LS2088A, LS1088A release secondary cores one by one. Update code to release secondary cores based on SoC SVR Add code to release cores one by one for non LS2080A SoCs Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> [YS: remove "inline" from declaration of initiator_type] Reviewed-by: York Sun <york.sun@nxp.com> |
#
f6b96ff6 |
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16-Nov-2016 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Use SVR based timer base address detection Timer controller base address has been changed from LS2080A SoC (and its personalities) to new SoCs like LS2088A, LS1088A. Use SVR based timer base address detection to avoid compile time #ifdef. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
f6a70b3a |
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16-Nov-2016 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add generic get_svr() in assembly Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
78d57842 |
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16-Nov-2016 |
Alexander Graf <agraf@csgraf.de> |
armv8: fsl-layerscape: Add support for efi_loader RTS reset When implementing efi loader support, we can expose runtime services for payloads. One such service is CPU reset. This patch implements RTS CPU reset support for layerscape systems. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: York Sun <york.sun@nxp.com> |
#
ef9a5fd8 |
|
13-Sep-2016 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: Fix "cpu status" command The core position is not continuous for some SoCs. For example, valid cores may present at position 0, 1, 4, 5, 8, 9, etc. Some registers (including boot release register) only count existing cores. Current implementation of cpu_mask() complies with the continuous numbering. However, command "cpu status" queries the spin table with actual core position. Add functions to calculate core position from core number, to correctly calculate offsets. Tested on LS2080ARDB and LS1043ARDB. Signed-off-by: York Sun <york.sun@nxp.com> |
#
5d1a7a9d |
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13-Sep-2016 |
Wenbin Song <wenbin.song@nxp.com> |
armv8/fsl-layerscape: print SoC revsion number The exact SoC revsion number can be recognized from U-Boot log. Signed-off-by: Wenbin Song <wenbin.song@nxp.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
cbe7706a |
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26-Sep-2016 |
Tom Rini <trini@konsulko.com> |
Merge git://git.denx.de/u-boot-fsl-qoriq trini: Drop local memset() from examples/standalone/mem_to_mem_idma2intr.c Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
1221ce45 |
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20-Sep-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
treewide: replace #include <asm/errno.h> with <linux/errno.h> Now, arch/${ARCH}/include/asm/errno.h and include/linux/errno.h have the same content. (both just wrap <asm-generic/errno.h>) Replace all include directives for <asm/errno.h> with <linux/errno.h>. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> [trini: Fixup include/clk.] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
b63a9506 |
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03-Aug-2016 |
York Sun <york.sun@nxp.com> |
armv8: ls2080a: Remove debug server support Debug server feature has been dropped from roadmap. Signed-off-by: York Sun <york.sun@nxp.com> |
#
ed7a3943 |
|
22-Jul-2016 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: mmu: Fix enabling MMU MMU bit in SCTLR needs to be set explicitly after tables are created. It isn't an issue for EL3 becuase this bit is already set by early MMU setup. But for other exception levels this bit was not set. Signed-off-by: York Sun <york.sun@nxp.com> |
#
79119a4d |
|
05-Jul-2016 |
Alison Wang <b18965@freescale.com> |
armv8: fsl-layerscape: Add A72 core detection Add support to detect Cortex-A72 core for printing it out. The Initiator Version of A72 core should be 0x4. Signed-off-by: Alison Wang <alison.wang@nxp.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
032d5bb4 |
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28-Jun-2016 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
ARMv8/Layerscape: switch SMP method accordingly If the PSCI and PPA is ready, skip the fixup for spin-table and waking secondary cores. Otherwise, change SMP method to spin-table, and the device node of PSCI will be removed. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
85cdf38e |
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28-Jun-2016 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: fsl-layerscape: add i/d-cache enable function to enable_caches This function assume that the d-cache and MMU has been enabled earlier, so it just created MMU table in main memory. But the assumption is not always correct, for example, the early setup is done in EL3, while enable_caches() is called when the PE has turned into another EL. Define the function mmu_setup() for fsl-layerscape to cover the weak one. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
5ad5823d |
|
24-Jun-2016 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Convert to use common MMU framework Drop platform code to create static MMU tables. Use common framework to create MMU tables on the run. Tested on LS2080ARDB with secure and non-secure ram scenarios. Signed-off-by: York Sun <york.sun@nxp.com> |
#
e61a7534 |
|
24-Jun-2016 |
York Sun <york.sun@nxp.com> |
armv8: Move secure_ram variable out of generic global data Secure_ram variable was put in generic global data. But only ARMv8 uses this variable. Move it to ARM specific data structure. Signed-off-by: York Sun <york.sun@nxp.com> |
#
a10a31ec |
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18-Jun-2016 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of git://git.denx.de/u-boot-usb Signed-off-by: Tom Rini <trini@konsulko.com> Conflicts: arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
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#
6fb522dc |
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12-Jun-2016 |
Sriram Dash <sriram.dash@nxp.com> |
arm64: fsl-layerscape: add get_svr and IS_SVR_REV helper Adds get_svr and IS_SVR_REV helpers for ARMv8 platforms, similar to PPC and ARMv7. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> |
#
a758177f |
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07-Jun-2016 |
Yunhui Cui <yunhui.cui@nxp.com> |
armv8/ls2080a: configure PMU's PCTBENR to enable WDT The SP805-WDT module on LS2080A requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. The watchdog clock needs to be enabled first. Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
acb8f5e9 |
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21-Apr-2016 |
Alison Wang <b18965@freescale.com> |
armv8: fsl-layerscape: Remove unnecessary flushing dcache As the issue about the stack will get corrupted when switching between the early and final mmu tables is fixed by commit 70e21b064, the workaround to flush dcache is unnecessary and should be removed. Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
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3c1d218a |
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04-Apr-2016 |
York Sun <york.sun@nxp.com> |
armv8: LS2080A: Consolidate LS2080A and LS2085A LS2080A is the primary SoC, and LS2085A is a personality with AIOP and DPAA DDR. The RDB and QDS boards support both personality. By detecting the SVR at runtime, a single image per board can support both SoCs. It gives users flexibility to swtich SoC without the need to reprogram the board. Signed-off-by: York Sun <york.sun@nxp.com> CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
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c05016ab |
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21-Mar-2016 |
Alexander Graf <agraf@csgraf.de> |
arm64: Fix layerscape mmu setup With commit 7985cdf we converted all systems except for the Layerscape SoCs to the generic descriptor table based page table setup. On the Layerscape SoCs however, we just provide an empty table stub and do the setup ourselves. To reserve enough memory for the tables, we need to override the default counting mechanism which would end up with an empty table because we have no maps. Fixes: 7985cdf Reported-by: York Sun <york.sun@nxp.com> CC: Alison Wang <alison.wang@nxp.com> CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Alexander Graf <agraf@suse.de> Tested-by: York Sun <york.sun@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
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7985cdf7 |
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03-Mar-2016 |
Alexander Graf <agraf@csgraf.de> |
arm64: Remove non-full-va map code By now the code to only have a single page table level with 64k page size and 42 bit address space is no longer used by any board in tree, so we can safely remove it. To clean up code, move the layerscape mmu code to the new defines, removing redundant field definitions. Signed-off-by: Alexander Graf <agraf@suse.de> |
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c0492141 |
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07-Dec-2015 |
York Sun <yorksun@freescale.com> |
armv8: fsl-layerscale: Rewrite reserving memory for MC and debug server MC and debug server are not board-specific. Move reserving memory to SoC file, using the new board_reserve_ram_top function. Reduce debug server memory by 2MB to make room for secure memory. In the system with MC and debug server, the top of u-boot memory is not the end of memory. PRAM is not used for this reservation. Signed-off-by: York Sun <yorksun@freescale.com> |
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c107c0c0 |
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04-Dec-2015 |
York Sun <yorksun@freescale.com> |
armv8: fsl-layerscape: Make DDR non secure in MMU tables DDR has been set as secure in MMU tables. Non-secure master such as SDHC DMA cannot access data correctly. Mixing secure and non- secure MMU entries requirs the MMU tables themselves in secure memory. This patch moves MMU tables into a secure DDR area. Early MMU tables are changed to set DDR as non-secure. A new table is added into final MMU tables so secure memory can have 2MB granuality. gd->secure_ram tracks the location of this secure memory. For ARMv8 SoCs, the RAM base is not zero and RAM is divided into several banks. gd->secure_ram needs to be maintained before using. This maintenance is board-specific, depending on the SoC and memory bank of the secure memory falls into. Signed-off-by: York Sun <yorksun@freescale.com> |
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b4017364 |
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04-Nov-2015 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
armv8: ls2085a: Add workaround of errata A009635 If the core runs at higher than x3 speed of the platform, there is possiblity about sev instruction to getting missed by other cores. This is because of SoC Run Control block may not able to sample the EVENTI(Sev) signals. Configure Run Control and EPU to periodically send out EVENTI signals to wake up A57 cores. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
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d764129d |
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04-Nov-2015 |
Alison Wang <b18965@freescale.com> |
armv8/layerscape: Update MMU table with execute-never bits For most device addresses excution shouldn't be allowed. Revise the MMU table to enforce execute-never bits. OCRAM, DDR and IFC are allowed for excution. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Alison Wang <alison.wang@freescale.com> Reported-by: Zhichun Hua <zhichun.hua@freescale.com> |
#
44937214 |
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09-Nov-2015 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
armv8: LS2080A: Rename LS2085A to reflect LS2080A LS2080A is a prime personality of Freescale’s LS2085A. It is a non-AIOP personality without support of DP-DDR, L2 switch, 1588, PCIe endpoint etc. So renaming existing LS2085A code base to reflect LS2080A (Prime personality) Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> [York Sun: Dropped #ifdef in cpu.c for cpu_type_list] Reviewed-by: York Sun <yorksun@freescale.com> |
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e8297341 |
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26-Oct-2015 |
Shaohui Xie <Shaohui.Xie@freescale.com> |
armv8/ls1043a: Add Fman support Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
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8281c58f |
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26-Oct-2015 |
Mingkai Hu <Mingkai.Hu@freescale.com> |
armv8/fsl_lsch2: Add fsl_lsch2 SoC Freescale LayerScape with Chassis Generation 2 is a set of SoCs with ARMv8 cores and 2rd generation of Chassis. Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
9f3183d2 |
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26-Oct-2015 |
Mingkai Hu <Mingkai.Hu@freescale.com> |
armv8/fsl_lsch3: Change arch to fsl-layerscape There are two LS series processors are built on ARMv8 Layersacpe architecture currently, LS2085A and LS1043A. They are based on ARMv8 core although use different chassis, so create fsl-layerscape to refactor the common code for the LS series processors which also paves the way for adding LS1043A platform. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
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b75d8dc5 |
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26-Jun-2020 |
Masahiro Yamada <masahiroy@kernel.org> |
treewide: convert bd_t to struct bd_info by coccinelle The Linux coding style guide (Documentation/process/coding-style.rst) clearly says: It's a **mistake** to use typedef for structures and pointers. Besides, using typedef for structures is annoying when you try to make headers self-contained. Let's say you have the following function declaration in a header: void foo(bd_t *bd); This is not self-contained since bd_t is not defined. To tell the compiler what 'bd_t' is, you need to include <asm/u-boot.h> #include <asm/u-boot.h> void foo(bd_t *bd); Then, the include direcective pulls in more bloat needlessly. If you use 'struct bd_info' instead, it is enough to put a forward declaration as follows: struct bd_info; void foo(struct bd_info *bd); Right, typedef'ing bd_t is a mistake. I used coccinelle to generate this commit. The semantic patch that makes this change is as follows: <smpl> @@ typedef bd_t; @@ -bd_t +struct bd_info </smpl> Signed-off-by: Masahiro Yamada <masahiroy@kernel.org> |
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25a5818f |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop asm/ptrace.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
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f7ae49fc |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
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90526e9f |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop net.h from common header Move this header out of the common header. Network support is used in quite a few places but it still does not warrant blanket inclusion. Note that this net.h header itself has quite a lot in it. It could be split into the driver-mode support, functions, structures, checksumming, etc. Signed-off-by: Simon Glass <sjg@chromium.org> |
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714497e3 |
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16-May-2020 |
Michael Walle <michael@walle.cc> |
efi_loader: round the memory area in efi_add_memory_map() Virtually all callers of this function do the rounding on their own. Some do it right, some don't. Instead of doing this in each caller, do the rounding in efi_add_memory_map(). Change the size parameter to bytes instead of pages and remove aligning and size calculation in all callers. There is no more need to make the original efi_add_memory_map() (which takes pages as size) available outside the module. Thus rename it to efi_add_memory_map_pg() and make it static to prevent further misuse outside the module. Signed-off-by: Michael Walle <michael@walle.cc> Add missing comma in sunxi_display.c. Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de> |
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6eb32a03 |
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23-Apr-2020 |
Madalin Bucur <madalin.bucur@oss.nxp.com> |
driver: net: fm: add DM ETH support Probe the FMan MACs based on the device tree while retaining the legacy code/functionality. One notable change introduced here is that, for DM_ETH, the name of the interfaces is corrected to the fmX-macY format, that avoids the referral to the MAC block names which were incorrect for FMan v3 devices (i.e. DTSEC, TGEC) and had weird formatting (i.e. FM1@DTSEC6, FM1@TGEC1). The legacy code is left unchanged in this respect. Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
6ebd4883 |
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27-Apr-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
fsl-layerscape: Add RESV_RAM check in resv_ram addr The initialization of gd->arch.resv_ram pointer should depend on if the RESV_RAM config is enabled. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Wasim Khan <wasim.khan@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
0d9d557d |
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10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
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db41d65a |
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28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move hang() to the same header as panic() At present panic() is in the vsprintf.h header file. That does not seem like an obvious choice for hang(), even though it relates to panic(). So let's put hang() in its own header. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Migrate a few more files] Signed-off-by: Tom Rini <trini@konsulko.com> |
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9b4a205f |
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28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move RAM-sizing functions to init.h These functions relate to memory init so move them into the init header. Signed-off-by: Simon Glass <sjg@chromium.org> |
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3499dd03 |
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27-Nov-2019 |
Alex Marginean <alexandru.marginean@nxp.com> |
ls1028a: Configure stream IDs for integrated PCI and fix up Linux DT Hardware comes out of reset with implicit values, but these are outside the accepted range for Layerscape gen 3 chassis spec used on LS1028A. Allocate different IDs and fix up Linux DT to use them. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
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b5981474 |
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14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some CPU functions out of common.h These functions belong in cpu_func.h since they do not use driver model. Move them over. Don't bother adding comments since these functions should be deleted. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
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68a6aa85 |
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14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move mii_init() function out of common.h This function belongs in mii.h so move it over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
2189d5f1 |
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14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
Move strtomhz() to vsprintf.h At present this function sits in its own file but it does not really justify it. There are similar string functions in vsprintf.h, so move it there. Also add the missing function comment. Use the vsprintf.h include file explicitly where needed. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
812ff53c |
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30-Oct-2019 |
Pankaj Bansal <pankaj.bansal@nxp.com> |
fsl-layerscape: fix warning if no hwconfig is defined While getting the 'subarg' of 'hwconfig' env variable in config_core_prefetch(), if no hwconfig variable is defined, below warning is received: WARNING: Calling __hwconfig without a buffer and before environment is ready Fix this by checking 'hwconfig' env variable. If not found return without further processing. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Tested-by: Michael Walle <michael@walle.cc> |
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28f9393b |
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17-Oct-2019 |
Mathew McBride <matt@traverse.com.au> |
fsl-layerscape: do not use layerscape EFI reset if PSCI used If the secure world reset handlers are used (via CONFIG_PSCI_RESET), then do not use the layerscape-specific implementation. Signed-off-by: Mathew McBride <matt@traverse.com.au> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
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6ed69523 |
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18-Sep-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add more personalities support Add LS1027A, LS1018A and LS1017A personalities support to LS1028A SoC family. LS1028A is the prime personality of LS1028A SoC family. LS1027A is a lower funtionality version of QorIQ LS1028A which does not support the multimedia subsystems, such as LCD controller, GPU, and eDP PHY. The QorIQ LS1018A and LS1017A SoCs are single 64-bit Arm A72 core, low power versions of the QorIQ LS1028A and LS1027A SoCs respectively. Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
0490cab5 |
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08-Aug-2019 |
Thomas Schaefer <thomas.schaefer@kontron.com> |
armv8: ls1028a: configure PMU's PCTBENR to enable WDT The SP805-WDT module on LS1028A requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. The watchdog clock needs to be enabled first. Signed-off-by: Thomas Schaefer <thomas.schaefer@kontron.com> Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
f3998fdc |
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02-Aug-2019 |
Simon Glass <sjg@chromium.org> |
env: Rename environment.h to env_internal.h This file contains lots of internal details about the environment. Most code can include env.h instead, calling the functions there as needed. Rename this file and add a comment at the top to indicate its internal nature. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> [trini: Fixup apalis-tk1.c] Signed-off-by: Tom Rini <trini@konsulko.com> |
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3a7d5571 |
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01-Aug-2019 |
Simon Glass <sjg@chromium.org> |
env: Move env_get_f() to env.h Move this function over to the new header file. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
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d9532e80 |
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23-Apr-2019 |
Udit Agarwal <udit.agarwal@nxp.com> |
armv8: fsl-layerscape: Set env_loc to ENVL_NOWHERE with CONFIG_ENV_IS_NOWHERE. ENVL_NOWHERE is dependent on CONFIG_ENV_IS_NOWHERE and not on CONFIG_CHAIN_OF_TRUST so return ENVL_NOWHERE when CONFIG_ENV_IS_NOWHERE is enabled Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
d4ad111d |
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10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
059d9422 |
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08-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: lx2160a: add MMU table entries for PCIe The lx2160a have up to 6 PCIe controllers and have different address and size of PCIe region. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
8348e798 |
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08-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: layerscape: use PCIe address macro for precompile PCIe MMU entry Change to use PCIe address macro to determine if precompile the PCIe MMU table entry. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
10015025 |
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03-May-2019 |
Trevor Woerner <trevor@toganlabs.com> |
CONFIG_SPL_SYS_[DI]CACHE_OFF: add While converting CONFIG_SYS_[DI]CACHE_OFF to Kconfig, there are instances where these configuration items are conditional on SPL. This commit adds SPL variants of these configuration items, uses CONFIG_IS_ENABLED(), and updates the configurations as required. Acked-by: Alexey Brodkin <abrodkin@synopsys.com> Signed-off-by: Trevor Woerner <trevor@toganlabs.com> [trini: Make the default depend on the setting for full U-Boot, update more zynq hardware] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
2e53759d |
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29-Oct-2018 |
Pankaj Bansal <pankaj.bansal@nxp.com> |
armv8: fsl-layerscape: reorder rgmii dpmacs' enablement some dpmacs in armv8a based freescale layerscape SOCs can be configured via both serdes(sgmii, xfi, xlaui etc) bits and via EC*_PMUX(rgmii) bits in RCW. e.g. dpmac 17 and 18 in LX2160A can be configured as SGMII from serdes bits and as RGMII via EC1_PMUX/EC2_PMUX bits Now if a dpmac is enabled by serdes bits then it takes precedence over EC*_PMUX bits. i.e. in LX2160A if we select serdes protocol that configures dpmac17 as SGMII and set the EC1_PMUX as RGMII, then the dpmac is SGMII and not RGMII. Therefore, move the fsl_rgmii_init after fsl_serdes_init. in fsl_rgmii_init function of SOC, we will check if the dpmac is enabled or not? if it is (fsl_serdes_init has already enabled the dpmac), then don't enable it. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
ec88ff80 |
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19-Dec-2018 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1043a: add SVR definitions for 23x23 package silicon LS1043A/LS1023A 23x23 package silicon has different SVR:VAR_PER. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
d23da2ae |
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26-Dec-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: fixes for TFABOOT framework Fixes for TFABOOT framework - update eMMC bootsrc to SD_MMC - Increase buffer size for mcinitcmd from 256 to 512 - Fix mcinitcmd and bootcmd for Secure Boot Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
4909b89e |
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29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
d6fdec21 |
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29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8:fsl-layerscape: Add support for Chassis 3.2 NXP layerscape architecture Chassis 3.2 builds upon chassis3 architecture with changes like DDR Memory map change, removal of IFC and support of upto 8 I2C controller. Patch add README.lsch3_2 and the above changes under macro CONFIG_NXP_LSCH3_2. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
56db948b |
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05-Nov-2018 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: Update parsing boot source Workaround of erratum A010539 clears the RCW source field in PORSR1 register, causing failure of detecting boot source using this method. Use SMC call if U-Boot runs at EL2. If SMC is not implemented or running at EL3, continue to read PORSR1 and presume QSPI as boot source if erratum workaround A010539 is enabled and RCW source is cleared. Signed-off-by: York Sun <york.sun@nxp.com> |
#
681d489e |
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05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: layerscape: add SMC calls for DDR size and bank info Adds SMC calls for getting DDR size and bank info for TFABOOT. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
2141d250 |
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05-Nov-2018 |
Pankit Garg <pankit.garg@nxp.com> |
armv8: fsl-layerscape: bootcmd identification for TFABOOT Adds bootcmd identificaton on basis on boot source, valid in TFABOOT configuration. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> [YS: remove unnecessary braces] Reviewed-by: York Sun <york.sun@nxp.com> |
#
4c417384 |
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05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com> |
#
535d76a1 |
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05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: layerscape: Add TFABOOT support Adds TFABOOT support config option and add generic code to enable execution from DDR. Signed-off-by: York Sun <york.sun@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> |
#
e3506480 |
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05-Nov-2018 |
Pankit Garg <pankit.garg@nxp.com> |
armv8: fsl-layerscape: change tlb base from OCRAM to DDR in EL < 3 Change tlb base address from OCRAM to DDR when exception level is less than 3. Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
d171c707 |
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05-Nov-2018 |
York Sun <york.sun@nxp.com> |
move data structure out of cpu.h Move static definitions to cpu.c file, as it doesn't allow the cpu.h file to be included in multiple c files. Signed-off-by: York Sun <york.sun@nxp.com> |
#
9b5e6396 |
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30-Aug-2018 |
Stephen Warren <swarren@nvidia.com> |
efi_loader: simplify ifdefs Use CONFIG_IS_ENABLED(EFI_LOADER) to avoid explicitly checking CONFIG_SPL too. This simplifies the conditional. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Alexander Graf <agraf@suse.de> |
#
9cce5663 |
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16-Jul-2018 |
Joe Hershberger <joe.hershberger@ni.com> |
arm: Prevent redefinition error in fsl-layerscape The include/phy.h will start including dm.h, which pulls in linux/compat.h after the attempted redefinition in arch/arm/include/asm/armv8/mmu.h, so move this include to allow redefinition. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> |
#
83d290c5 |
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06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
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482fc90c |
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06-Feb-2018 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
efi_loader: add missing EFI_RESET_PLATFORM_SPECIFIC EFI_RESET_PLATFORM_SPECIFIC is one of the values that can be used for the EFI service ResetSystem. The missing definition is added. The value has to handled in efi_reset_system(). Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Alexander Graf <agraf@suse.de> |
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22c793e6 |
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03-Mar-2018 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
efi_loader: exit status for efi_reset_system_init efi_reset_system_init provides the architecture or board specific initialization of the EFI subsystem. Errors should be caught and signalled by a return code. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Alexander Graf <agraf@suse.de> |
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958b2ed5 |
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09-Jan-2018 |
Zhang Ying-22455 <ying.zhang22455@nxp.com> |
armv8/ls1088a: configure PMU's PCTBENR to enable WDT The SP805-WDT module on LS1088A requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. The watchdog clock needs to be enabled first. Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
44262327 |
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15-Dec-2017 |
Ahmed Mansour <ahmed.mansour@nxp.com> |
drivers/misc: Share qbman init between archs This patch adds changes necessary to move functionality present in PowerPC folders with ARM architectures that have DPAA1 QBMan hardware - Create new board/freescale/common/fsl_portals.c to house shared device tree fixups for DPAA1 devices with ARM and PowerPC cores - Add new header file to top includes directory to allow files in both architectures to grab the function prototypes - Port inhibit_portals() from PowerPC to ARM. This function is used in setup to disable interrupts on all QMan and BMan portals. It is needed because the interrupts are enabled by default for all portals including unused/uninitialised portals. When the kernel attempts to go to deep sleep the unused portals prevent it from doing so Signed-off-by: Ahmed Mansour <ahmed.mansour@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
a8f33034 |
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03-Dec-2017 |
Wenbin song <wenbin.song@nxp.com> |
armv8: ls1043a/ls2080a: check SoC by device ID Check LS1043A/LS2080a by device ID without using personality ID to determine revision number. This check applies to all various personalities of the same SoC family. Signed-off-by: Wenbin Song <wenbin.song@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
2db53cfe |
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09-Nov-2017 |
Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
armv8: fsl-layerscape: Add support of disabling core prefetch Instruction prefetch feature is by default enabled during core release. This patch add support of disabling instruction prefetch by setting core mask in PPA. Here each core mask bit represents a core and prefetch is disabled at the time of core release. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
7eb40f0f |
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28-Sep-2017 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: Avoid running dram_init_banksize again gd->ram_size is reduced in this function to reserve secure memory. Avoid running this function again to further reduce memory size. This fixes issue for SPL boot with PPA image loaded in which case secure memory is incorrectly allocated due to repeated calling. Signed-off-by: York Sun <york.sun@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
710d0cd7 |
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03-Oct-2017 |
Sumit Garg <sumit.garg@nxp.com> |
armv8: fsl-layerscape: Allocate Secure memory from first ddr region This change is required due to trusted OS (OP-TEE) not being position independent code, it requires compile time fixed base address. To take care of this it is assumed that all layerscape armv8 platforms has minimum 2G ddr in first region. So we can have fixed address space (66 MB -> (2MB for PPA + 64MB for trusted OS)) allocated from top of first 2G ddr region and compile trusted OS with this fixed base address. But one exception here is ls1012 where we have only 1G (rdb) or 512M (frdm) ddr memory. For those we can have different fixed compile time base addresses for trusted OS. Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
e9303a41 |
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07-Sep-2017 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: Fix MC reserved memory calculation In case high region memory doesn't have enough space for Management Complex (MC), the return value should indicate a failure so the caller can handle it accordingly. Signed-off-by: York Sun <york.sun@nxp.com> Reported-by: Ebony Zhu <ebony.zhu@nxp.com> |
#
17d066fc |
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31-Aug-2017 |
Ashish Kumar <Ashish.Kumar@nxp.com> |
armv8: fsl-layerscape: Support to add RGMII for ls1088aqds This patch adds support for RGMII protocol NXP's LDPAA2 support RGMII protocol. LS1088A is the first Soc supporting both RGMII and SGMII. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Amrita Kumari <amrita.kumari@nxp.com> Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
63b2316c |
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10-Aug-2017 |
Ashish Kumar <Ashish.Kumar@nxp.com> |
fsl-layerscape: Consolidate registers space defination for CCI-400 bus CoreLink Cache Coherent Interconnect (CCI) provides full cache coherency between two clusters of multi-core CPUs and I/O coherency for devices and I/O masters. This patch add new config option SYS_FSL_HAS_CCI400 and moves existing register space definaton of CCI-400 bus to fsl_immap to be shared. CONFIG_SYS_CCI400_ADDR is replaced with SYS_CCI400_OFFSET in Kconfig. Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> [YS: revised commit message, squashed patches for armv8 and armv7] Reviewed-by: York Sun <york.sun@nxp.com> |
#
6e2941d7 |
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17-May-2017 |
Simon Glass <sjg@chromium.org> |
common: freescale: Move arch-specific declarations The declarations should not be in common.h. Move them to the arch-specific headers. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Fixup thinko defined(FSL_LSCH3) -> defined(CONFIG_FSL_LSCH3)] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
399e2bb6 |
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15-May-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Make U-Boot EL2 safe When U-Boot boots from EL2, skip some lowlevel init code requiring EL3, including CCI-400/CCN-504, trust zone, GIC, etc. These initialization tasks are carried out before U-Boot runs. This applies to the RAM version image used for SPL boot if PPA is loaded first. Signed-off-by: York Sun <york.sun@nxp.com> |
#
1f55a938 |
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05-May-2017 |
Santan Kumar <santan.kumar@nxp.com> |
armv8: ls2080aqds: Add support for SD boot Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
e809e747 |
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27-Apr-2017 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: fsl-layerscape: Add NXP LS2081A, LS2041A SoC support The QorIQ LS2081A SoC has eight 64-bit ARM v8 Cortex A72 cores and is built on layerscape architecture. It is 40-pin derivative of LS2084A (non-AIOP personality of LS2088A). So feature-wise it is same as LS2084A. LS2041A is a 4-core personality of LS2081A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
026f30ec |
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18-Apr-2017 |
Yuantian Tang <andy.tang@nxp.com> |
arm: psci: make psci usable on single core socs PSCI can be used on both multiple and single core socs. Current implementation only allows PSCI to work on multiple core socs. This patch removes this restriction so that PSCI can work on single core socs as well. Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
4a3ab193 |
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27-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: ls2080a: Drop macro CONFIG_LS2080A Use CONFIG_ARCH_LS2080A instead. Signed-off-by: York Sun <york.sun@nxp.com> |
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3eace37e |
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06-Apr-2017 |
Simon Glass <sjg@chromium.org> |
arm: freescale: Rename initdram() to fsl_initdram() This function name shadows a global name but is in fact different. This is very confusing. Rename it to help with the following refactoring. Signed-off-by: Simon Glass <sjg@chromium.org> |
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76b00aca |
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31-Mar-2017 |
Simon Glass <sjg@chromium.org> |
board_f: Drop setup_dram_config() wrapper By making dram_init_banksize() return an error code we can drop the wrapper. Adjust this and clean up all implementations. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> |
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088454cd |
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31-Mar-2017 |
Simon Glass <sjg@chromium.org> |
board_f: Drop return value from initdram() At present we cannot use this function as an init sequence call without a wrapper, since it returns the RAM size. Adjust it to set the RAM size in global_data instead, and return 0 on success. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> |
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52c41180 |
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31-Mar-2017 |
Simon Glass <sjg@chromium.org> |
board_f: Drop board_type parameter from initdram() It looks like only cm5200 and tqm8xx use this feature, so we don't really need it in generic code. Drop it and have the users access gd->board_type directly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
3d8553f0 |
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02-Mar-2017 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
pci: layerscape: add LS2088A series SoC pcie support The LS2088A series SoCs has different physical memory map address and CCSR registers address against LS2080A series SoCs. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
eea1cb77 |
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13-Feb-2017 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8/fsl-layerscape: Update erratum A009635 implementation Erratum A009635 is valid only for LS2080A SoC and its personality. Add SoC svr check. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
4961eafc |
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06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Update early MMU for DDR after initialization In early MMU table, DDR has to be mapped as device memory to avoid speculative access. After DDR is initialized, it needs to be updated to normal memory to allow code execution. To simplify the code, dram_init() is moved into a common file as a weak function. Signed-off-by: York Sun <york.sun@nxp.com> |
#
a045a0c3 |
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06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Fix the sequence of changing MMU table This patch follows the break-before-make process when making changes to MMU table. MMU is disabled before changing TTBR to avoid any potential race condition. Signed-off-by: York Sun <york.sun@nxp.com> |
#
24f55496 |
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06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Update MMU mapping with actual DDR size Update mapping with actual DDR size. Non-existing memory should not be mapped as "normal" memory to avoid speculative access. Signed-off-by: York Sun <york.sun@nxp.com> |
#
36cc0de0 |
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06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Rewrite memory reservation For ARMv8 Layerscape SoCs, secure memory and MC memorey are reserved at the end of DDR. DDR is spit into two or three banks. This patch reverts commit aabd7ddb and simplifies the calculation of reserved memory, and moves the code into common SoC file. Secure memory is carved out first. DDR bank size is reduced. Reserved memory is then allocated on the top of available memory. U-Boot still has access to reserved memory as data transferring is needed. Device tree is fixed with reduced memory size to hide the reserved memory from OS. The same region is reserved for efi_loader. Signed-off-by: York Sun <york.sun@nxp.com> |
#
daa92644 |
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16-Jan-2017 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
ARMv8/sec_firmware: relocated and renamed the config FSL_PPA_ARMV8_PSCI Moved the config FSL_PPA_ARMV8_PSCI from fsl-layerscape's Kconfig to Kconfig under armv8 and renamed it to SEC_FIRMWARE_ARMV8_PSCI. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
904110c7 |
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10-Jan-2017 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8/fsl-lsch2: refactor the clock system initialization Up to now, there are 3 kind of SoCs under Layerscape Chassis 2, like LS1043A, LS1046A and LS1012A. But the clocks tree has a lot of differences, for instance, the IP modules have different dividers to derive its clock from Platform PLL. And the core cluster PLL and platform PLL maybe have different reference clocks, such as LS1012A. Another problem is which clock/PLL should be described by sys_info->freq_systembus, it is confused in Layerscape Chissis 2. This patch is to bind the sys_info->freq_systembus to the Platform PLL, and handle the different divider of IP modules separately between different SoCs, and separate reference clocks of core cluster PLL and platform PLL. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
2d16a1a6 |
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07-Dec-2016 |
macro.wave.z@gmail.com <macro.wave.z@gmail.com> |
ARMv8: LS1043A: change macro CONFIG_ARMV8_PSCI definition NXP/Freescale uses macro CONFIG_ARMV8_PSCI to enable their private PSCI implementation in PPA firmware, but this macro naming too generic, so this patch replaces it with a specic one CONFIG_FSL_PPA_ARMV8_PSCI. And this macro CONFIG_ARMV8_PSCI will be used for a generic PSCI for ARMv8 which will be added in following patchs. Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
02fb2761 |
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20-Nov-2016 |
Shengzhou Liu <Shengzhou.Liu@nxp.com> |
fsl/ddr: Add erratum_a009942_check_cpo and clean related erratum - add additional function erratum_a009942_check_cpo to check if the board needs tuning CPO calibration for optimal setting. - move ERRATUM_A009942(with revision to check cpo_sample option) from fsl_ddr_gen4.c to ctrl_regs.c for reuse on all DDR4/DDR3 parts. - move ERRATUM_A008378 from fsl_ddr_gen4.c to ctrl_regs.c - remove obsolete ERRATUM_A004934 which is replaced with ERRATUM_A009942. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> [YS: Replaced CONFIG_QEMU_E500 with CONFIG_ARCH_QEMU_E500] Reviewed-by: York Sun <york.sun@nxp.com> |
#
e87c673c |
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16-Nov-2016 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8/fsl-lsch3: Update code to release secondary cores NXP ARMv8 SoC LS2080A release all secondary cores in one-go. But other new SoCs like LS2088A, LS1088A release secondary cores one by one. Update code to release secondary cores based on SoC SVR Add code to release cores one by one for non LS2080A SoCs Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> [YS: remove "inline" from declaration of initiator_type] Reviewed-by: York Sun <york.sun@nxp.com> |
#
f6b96ff6 |
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16-Nov-2016 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Use SVR based timer base address detection Timer controller base address has been changed from LS2080A SoC (and its personalities) to new SoCs like LS2088A, LS1088A. Use SVR based timer base address detection to avoid compile time #ifdef. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
f6a70b3a |
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16-Nov-2016 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add generic get_svr() in assembly Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
78d57842 |
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16-Nov-2016 |
Alexander Graf <agraf@csgraf.de> |
armv8: fsl-layerscape: Add support for efi_loader RTS reset When implementing efi loader support, we can expose runtime services for payloads. One such service is CPU reset. This patch implements RTS CPU reset support for layerscape systems. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: York Sun <york.sun@nxp.com> |
#
ef9a5fd8 |
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13-Sep-2016 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: Fix "cpu status" command The core position is not continuous for some SoCs. For example, valid cores may present at position 0, 1, 4, 5, 8, 9, etc. Some registers (including boot release register) only count existing cores. Current implementation of cpu_mask() complies with the continuous numbering. However, command "cpu status" queries the spin table with actual core position. Add functions to calculate core position from core number, to correctly calculate offsets. Tested on LS2080ARDB and LS1043ARDB. Signed-off-by: York Sun <york.sun@nxp.com> |
#
5d1a7a9d |
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13-Sep-2016 |
Wenbin Song <wenbin.song@nxp.com> |
armv8/fsl-layerscape: print SoC revsion number The exact SoC revsion number can be recognized from U-Boot log. Signed-off-by: Wenbin Song <wenbin.song@nxp.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
cbe7706a |
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26-Sep-2016 |
Tom Rini <trini@konsulko.com> |
Merge git://git.denx.de/u-boot-fsl-qoriq trini: Drop local memset() from examples/standalone/mem_to_mem_idma2intr.c Signed-off-by: Tom Rini <trini@konsulko.com>
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#
1221ce45 |
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20-Sep-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
treewide: replace #include <asm/errno.h> with <linux/errno.h> Now, arch/${ARCH}/include/asm/errno.h and include/linux/errno.h have the same content. (both just wrap <asm-generic/errno.h>) Replace all include directives for <asm/errno.h> with <linux/errno.h>. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> [trini: Fixup include/clk.] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
b63a9506 |
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03-Aug-2016 |
York Sun <york.sun@nxp.com> |
armv8: ls2080a: Remove debug server support Debug server feature has been dropped from roadmap. Signed-off-by: York Sun <york.sun@nxp.com> |
#
ed7a3943 |
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22-Jul-2016 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: mmu: Fix enabling MMU MMU bit in SCTLR needs to be set explicitly after tables are created. It isn't an issue for EL3 becuase this bit is already set by early MMU setup. But for other exception levels this bit was not set. Signed-off-by: York Sun <york.sun@nxp.com> |
#
79119a4d |
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05-Jul-2016 |
Alison Wang <b18965@freescale.com> |
armv8: fsl-layerscape: Add A72 core detection Add support to detect Cortex-A72 core for printing it out. The Initiator Version of A72 core should be 0x4. Signed-off-by: Alison Wang <alison.wang@nxp.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
032d5bb4 |
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28-Jun-2016 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
ARMv8/Layerscape: switch SMP method accordingly If the PSCI and PPA is ready, skip the fixup for spin-table and waking secondary cores. Otherwise, change SMP method to spin-table, and the device node of PSCI will be removed. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
85cdf38e |
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28-Jun-2016 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: fsl-layerscape: add i/d-cache enable function to enable_caches This function assume that the d-cache and MMU has been enabled earlier, so it just created MMU table in main memory. But the assumption is not always correct, for example, the early setup is done in EL3, while enable_caches() is called when the PE has turned into another EL. Define the function mmu_setup() for fsl-layerscape to cover the weak one. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
5ad5823d |
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24-Jun-2016 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Convert to use common MMU framework Drop platform code to create static MMU tables. Use common framework to create MMU tables on the run. Tested on LS2080ARDB with secure and non-secure ram scenarios. Signed-off-by: York Sun <york.sun@nxp.com> |
#
e61a7534 |
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24-Jun-2016 |
York Sun <york.sun@nxp.com> |
armv8: Move secure_ram variable out of generic global data Secure_ram variable was put in generic global data. But only ARMv8 uses this variable. Move it to ARM specific data structure. Signed-off-by: York Sun <york.sun@nxp.com> |
#
a10a31ec |
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18-Jun-2016 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of git://git.denx.de/u-boot-usb Signed-off-by: Tom Rini <trini@konsulko.com> Conflicts: arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
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#
6fb522dc |
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12-Jun-2016 |
Sriram Dash <sriram.dash@nxp.com> |
arm64: fsl-layerscape: add get_svr and IS_SVR_REV helper Adds get_svr and IS_SVR_REV helpers for ARMv8 platforms, similar to PPC and ARMv7. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> |
#
a758177f |
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07-Jun-2016 |
Yunhui Cui <yunhui.cui@nxp.com> |
armv8/ls2080a: configure PMU's PCTBENR to enable WDT The SP805-WDT module on LS2080A requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. The watchdog clock needs to be enabled first. Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
acb8f5e9 |
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21-Apr-2016 |
Alison Wang <b18965@freescale.com> |
armv8: fsl-layerscape: Remove unnecessary flushing dcache As the issue about the stack will get corrupted when switching between the early and final mmu tables is fixed by commit 70e21b064, the workaround to flush dcache is unnecessary and should be removed. Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
3c1d218a |
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04-Apr-2016 |
York Sun <york.sun@nxp.com> |
armv8: LS2080A: Consolidate LS2080A and LS2085A LS2080A is the primary SoC, and LS2085A is a personality with AIOP and DPAA DDR. The RDB and QDS boards support both personality. By detecting the SVR at runtime, a single image per board can support both SoCs. It gives users flexibility to swtich SoC without the need to reprogram the board. Signed-off-by: York Sun <york.sun@nxp.com> CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
c05016ab |
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21-Mar-2016 |
Alexander Graf <agraf@csgraf.de> |
arm64: Fix layerscape mmu setup With commit 7985cdf we converted all systems except for the Layerscape SoCs to the generic descriptor table based page table setup. On the Layerscape SoCs however, we just provide an empty table stub and do the setup ourselves. To reserve enough memory for the tables, we need to override the default counting mechanism which would end up with an empty table because we have no maps. Fixes: 7985cdf Reported-by: York Sun <york.sun@nxp.com> CC: Alison Wang <alison.wang@nxp.com> CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Alexander Graf <agraf@suse.de> Tested-by: York Sun <york.sun@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
7985cdf7 |
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03-Mar-2016 |
Alexander Graf <agraf@csgraf.de> |
arm64: Remove non-full-va map code By now the code to only have a single page table level with 64k page size and 42 bit address space is no longer used by any board in tree, so we can safely remove it. To clean up code, move the layerscape mmu code to the new defines, removing redundant field definitions. Signed-off-by: Alexander Graf <agraf@suse.de> |
#
c0492141 |
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07-Dec-2015 |
York Sun <yorksun@freescale.com> |
armv8: fsl-layerscale: Rewrite reserving memory for MC and debug server MC and debug server are not board-specific. Move reserving memory to SoC file, using the new board_reserve_ram_top function. Reduce debug server memory by 2MB to make room for secure memory. In the system with MC and debug server, the top of u-boot memory is not the end of memory. PRAM is not used for this reservation. Signed-off-by: York Sun <yorksun@freescale.com> |
#
c107c0c0 |
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04-Dec-2015 |
York Sun <yorksun@freescale.com> |
armv8: fsl-layerscape: Make DDR non secure in MMU tables DDR has been set as secure in MMU tables. Non-secure master such as SDHC DMA cannot access data correctly. Mixing secure and non- secure MMU entries requirs the MMU tables themselves in secure memory. This patch moves MMU tables into a secure DDR area. Early MMU tables are changed to set DDR as non-secure. A new table is added into final MMU tables so secure memory can have 2MB granuality. gd->secure_ram tracks the location of this secure memory. For ARMv8 SoCs, the RAM base is not zero and RAM is divided into several banks. gd->secure_ram needs to be maintained before using. This maintenance is board-specific, depending on the SoC and memory bank of the secure memory falls into. Signed-off-by: York Sun <yorksun@freescale.com> |
#
b4017364 |
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04-Nov-2015 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
armv8: ls2085a: Add workaround of errata A009635 If the core runs at higher than x3 speed of the platform, there is possiblity about sev instruction to getting missed by other cores. This is because of SoC Run Control block may not able to sample the EVENTI(Sev) signals. Configure Run Control and EPU to periodically send out EVENTI signals to wake up A57 cores. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
d764129d |
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04-Nov-2015 |
Alison Wang <b18965@freescale.com> |
armv8/layerscape: Update MMU table with execute-never bits For most device addresses excution shouldn't be allowed. Revise the MMU table to enforce execute-never bits. OCRAM, DDR and IFC are allowed for excution. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Alison Wang <alison.wang@freescale.com> Reported-by: Zhichun Hua <zhichun.hua@freescale.com> |
#
44937214 |
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09-Nov-2015 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
armv8: LS2080A: Rename LS2085A to reflect LS2080A LS2080A is a prime personality of Freescale’s LS2085A. It is a non-AIOP personality without support of DP-DDR, L2 switch, 1588, PCIe endpoint etc. So renaming existing LS2085A code base to reflect LS2080A (Prime personality) Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> [York Sun: Dropped #ifdef in cpu.c for cpu_type_list] Reviewed-by: York Sun <yorksun@freescale.com> |
#
e8297341 |
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26-Oct-2015 |
Shaohui Xie <Shaohui.Xie@freescale.com> |
armv8/ls1043a: Add Fman support Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
8281c58f |
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26-Oct-2015 |
Mingkai Hu <Mingkai.Hu@freescale.com> |
armv8/fsl_lsch2: Add fsl_lsch2 SoC Freescale LayerScape with Chassis Generation 2 is a set of SoCs with ARMv8 cores and 2rd generation of Chassis. Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
9f3183d2 |
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26-Oct-2015 |
Mingkai Hu <Mingkai.Hu@freescale.com> |
armv8/fsl_lsch3: Change arch to fsl-layerscape There are two LS series processors are built on ARMv8 Layersacpe architecture currently, LS2085A and LS1043A. They are based on ARMv8 core although use different chassis, so create fsl-layerscape to refactor the common code for the LS series processors which also paves the way for adding LS1043A platform. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
25a5818f |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop asm/ptrace.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
f7ae49fc |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
90526e9f |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop net.h from common header Move this header out of the common header. Network support is used in quite a few places but it still does not warrant blanket inclusion. Note that this net.h header itself has quite a lot in it. It could be split into the driver-mode support, functions, structures, checksumming, etc. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
714497e3 |
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16-May-2020 |
Michael Walle <michael@walle.cc> |
efi_loader: round the memory area in efi_add_memory_map() Virtually all callers of this function do the rounding on their own. Some do it right, some don't. Instead of doing this in each caller, do the rounding in efi_add_memory_map(). Change the size parameter to bytes instead of pages and remove aligning and size calculation in all callers. There is no more need to make the original efi_add_memory_map() (which takes pages as size) available outside the module. Thus rename it to efi_add_memory_map_pg() and make it static to prevent further misuse outside the module. Signed-off-by: Michael Walle <michael@walle.cc> Add missing comma in sunxi_display.c. Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de> |
#
6eb32a03 |
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23-Apr-2020 |
Madalin Bucur <madalin.bucur@oss.nxp.com> |
driver: net: fm: add DM ETH support Probe the FMan MACs based on the device tree while retaining the legacy code/functionality. One notable change introduced here is that, for DM_ETH, the name of the interfaces is corrected to the fmX-macY format, that avoids the referral to the MAC block names which were incorrect for FMan v3 devices (i.e. DTSEC, TGEC) and had weird formatting (i.e. FM1@DTSEC6, FM1@TGEC1). The legacy code is left unchanged in this respect. Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
6ebd4883 |
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27-Apr-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
fsl-layerscape: Add RESV_RAM check in resv_ram addr The initialization of gd->arch.resv_ram pointer should depend on if the RESV_RAM config is enabled. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Wasim Khan <wasim.khan@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
0d9d557d |
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10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
db41d65a |
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28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move hang() to the same header as panic() At present panic() is in the vsprintf.h header file. That does not seem like an obvious choice for hang(), even though it relates to panic(). So let's put hang() in its own header. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Migrate a few more files] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
9b4a205f |
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28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move RAM-sizing functions to init.h These functions relate to memory init so move them into the init header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
3499dd03 |
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27-Nov-2019 |
Alex Marginean <alexandru.marginean@nxp.com> |
ls1028a: Configure stream IDs for integrated PCI and fix up Linux DT Hardware comes out of reset with implicit values, but these are outside the accepted range for Layerscape gen 3 chassis spec used on LS1028A. Allocate different IDs and fix up Linux DT to use them. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
b5981474 |
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14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some CPU functions out of common.h These functions belong in cpu_func.h since they do not use driver model. Move them over. Don't bother adding comments since these functions should be deleted. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
68a6aa85 |
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14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move mii_init() function out of common.h This function belongs in mii.h so move it over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
2189d5f1 |
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14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
Move strtomhz() to vsprintf.h At present this function sits in its own file but it does not really justify it. There are similar string functions in vsprintf.h, so move it there. Also add the missing function comment. Use the vsprintf.h include file explicitly where needed. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
812ff53c |
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30-Oct-2019 |
Pankaj Bansal <pankaj.bansal@nxp.com> |
fsl-layerscape: fix warning if no hwconfig is defined While getting the 'subarg' of 'hwconfig' env variable in config_core_prefetch(), if no hwconfig variable is defined, below warning is received: WARNING: Calling __hwconfig without a buffer and before environment is ready Fix this by checking 'hwconfig' env variable. If not found return without further processing. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Tested-by: Michael Walle <michael@walle.cc> |
#
28f9393b |
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17-Oct-2019 |
Mathew McBride <matt@traverse.com.au> |
fsl-layerscape: do not use layerscape EFI reset if PSCI used If the secure world reset handlers are used (via CONFIG_PSCI_RESET), then do not use the layerscape-specific implementation. Signed-off-by: Mathew McBride <matt@traverse.com.au> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
6ed69523 |
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18-Sep-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add more personalities support Add LS1027A, LS1018A and LS1017A personalities support to LS1028A SoC family. LS1028A is the prime personality of LS1028A SoC family. LS1027A is a lower funtionality version of QorIQ LS1028A which does not support the multimedia subsystems, such as LCD controller, GPU, and eDP PHY. The QorIQ LS1018A and LS1017A SoCs are single 64-bit Arm A72 core, low power versions of the QorIQ LS1028A and LS1027A SoCs respectively. Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
0490cab5 |
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08-Aug-2019 |
Thomas Schaefer <thomas.schaefer@kontron.com> |
armv8: ls1028a: configure PMU's PCTBENR to enable WDT The SP805-WDT module on LS1028A requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. The watchdog clock needs to be enabled first. Signed-off-by: Thomas Schaefer <thomas.schaefer@kontron.com> Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
f3998fdc |
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02-Aug-2019 |
Simon Glass <sjg@chromium.org> |
env: Rename environment.h to env_internal.h This file contains lots of internal details about the environment. Most code can include env.h instead, calling the functions there as needed. Rename this file and add a comment at the top to indicate its internal nature. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> [trini: Fixup apalis-tk1.c] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
3a7d5571 |
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01-Aug-2019 |
Simon Glass <sjg@chromium.org> |
env: Move env_get_f() to env.h Move this function over to the new header file. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
d9532e80 |
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23-Apr-2019 |
Udit Agarwal <udit.agarwal@nxp.com> |
armv8: fsl-layerscape: Set env_loc to ENVL_NOWHERE with CONFIG_ENV_IS_NOWHERE. ENVL_NOWHERE is dependent on CONFIG_ENV_IS_NOWHERE and not on CONFIG_CHAIN_OF_TRUST so return ENVL_NOWHERE when CONFIG_ENV_IS_NOWHERE is enabled Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
d4ad111d |
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10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
059d9422 |
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08-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: lx2160a: add MMU table entries for PCIe The lx2160a have up to 6 PCIe controllers and have different address and size of PCIe region. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
8348e798 |
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08-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: layerscape: use PCIe address macro for precompile PCIe MMU entry Change to use PCIe address macro to determine if precompile the PCIe MMU table entry. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
10015025 |
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03-May-2019 |
Trevor Woerner <trevor@toganlabs.com> |
CONFIG_SPL_SYS_[DI]CACHE_OFF: add While converting CONFIG_SYS_[DI]CACHE_OFF to Kconfig, there are instances where these configuration items are conditional on SPL. This commit adds SPL variants of these configuration items, uses CONFIG_IS_ENABLED(), and updates the configurations as required. Acked-by: Alexey Brodkin <abrodkin@synopsys.com> Signed-off-by: Trevor Woerner <trevor@toganlabs.com> [trini: Make the default depend on the setting for full U-Boot, update more zynq hardware] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
2e53759d |
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29-Oct-2018 |
Pankaj Bansal <pankaj.bansal@nxp.com> |
armv8: fsl-layerscape: reorder rgmii dpmacs' enablement some dpmacs in armv8a based freescale layerscape SOCs can be configured via both serdes(sgmii, xfi, xlaui etc) bits and via EC*_PMUX(rgmii) bits in RCW. e.g. dpmac 17 and 18 in LX2160A can be configured as SGMII from serdes bits and as RGMII via EC1_PMUX/EC2_PMUX bits Now if a dpmac is enabled by serdes bits then it takes precedence over EC*_PMUX bits. i.e. in LX2160A if we select serdes protocol that configures dpmac17 as SGMII and set the EC1_PMUX as RGMII, then the dpmac is SGMII and not RGMII. Therefore, move the fsl_rgmii_init after fsl_serdes_init. in fsl_rgmii_init function of SOC, we will check if the dpmac is enabled or not? if it is (fsl_serdes_init has already enabled the dpmac), then don't enable it. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
ec88ff80 |
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19-Dec-2018 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1043a: add SVR definitions for 23x23 package silicon LS1043A/LS1023A 23x23 package silicon has different SVR:VAR_PER. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
d23da2ae |
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26-Dec-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: fixes for TFABOOT framework Fixes for TFABOOT framework - update eMMC bootsrc to SD_MMC - Increase buffer size for mcinitcmd from 256 to 512 - Fix mcinitcmd and bootcmd for Secure Boot Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
4909b89e |
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29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
d6fdec21 |
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29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8:fsl-layerscape: Add support for Chassis 3.2 NXP layerscape architecture Chassis 3.2 builds upon chassis3 architecture with changes like DDR Memory map change, removal of IFC and support of upto 8 I2C controller. Patch add README.lsch3_2 and the above changes under macro CONFIG_NXP_LSCH3_2. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
56db948b |
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05-Nov-2018 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: Update parsing boot source Workaround of erratum A010539 clears the RCW source field in PORSR1 register, causing failure of detecting boot source using this method. Use SMC call if U-Boot runs at EL2. If SMC is not implemented or running at EL3, continue to read PORSR1 and presume QSPI as boot source if erratum workaround A010539 is enabled and RCW source is cleared. Signed-off-by: York Sun <york.sun@nxp.com> |
#
681d489e |
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05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: layerscape: add SMC calls for DDR size and bank info Adds SMC calls for getting DDR size and bank info for TFABOOT. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
2141d250 |
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05-Nov-2018 |
Pankit Garg <pankit.garg@nxp.com> |
armv8: fsl-layerscape: bootcmd identification for TFABOOT Adds bootcmd identificaton on basis on boot source, valid in TFABOOT configuration. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> [YS: remove unnecessary braces] Reviewed-by: York Sun <york.sun@nxp.com> |
#
4c417384 |
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05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com> |
#
535d76a1 |
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05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: layerscape: Add TFABOOT support Adds TFABOOT support config option and add generic code to enable execution from DDR. Signed-off-by: York Sun <york.sun@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> |
#
e3506480 |
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05-Nov-2018 |
Pankit Garg <pankit.garg@nxp.com> |
armv8: fsl-layerscape: change tlb base from OCRAM to DDR in EL < 3 Change tlb base address from OCRAM to DDR when exception level is less than 3. Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
d171c707 |
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05-Nov-2018 |
York Sun <york.sun@nxp.com> |
move data structure out of cpu.h Move static definitions to cpu.c file, as it doesn't allow the cpu.h file to be included in multiple c files. Signed-off-by: York Sun <york.sun@nxp.com> |
#
9b5e6396 |
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30-Aug-2018 |
Stephen Warren <swarren@nvidia.com> |
efi_loader: simplify ifdefs Use CONFIG_IS_ENABLED(EFI_LOADER) to avoid explicitly checking CONFIG_SPL too. This simplifies the conditional. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Alexander Graf <agraf@suse.de> |
#
9cce5663 |
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16-Jul-2018 |
Joe Hershberger <joe.hershberger@ni.com> |
arm: Prevent redefinition error in fsl-layerscape The include/phy.h will start including dm.h, which pulls in linux/compat.h after the attempted redefinition in arch/arm/include/asm/armv8/mmu.h, so move this include to allow redefinition. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> |
#
83d290c5 |
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06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
482fc90c |
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06-Feb-2018 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
efi_loader: add missing EFI_RESET_PLATFORM_SPECIFIC EFI_RESET_PLATFORM_SPECIFIC is one of the values that can be used for the EFI service ResetSystem. The missing definition is added. The value has to handled in efi_reset_system(). Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Alexander Graf <agraf@suse.de> |
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22c793e6 |
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03-Mar-2018 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
efi_loader: exit status for efi_reset_system_init efi_reset_system_init provides the architecture or board specific initialization of the EFI subsystem. Errors should be caught and signalled by a return code. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Alexander Graf <agraf@suse.de> |
#
958b2ed5 |
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09-Jan-2018 |
Zhang Ying-22455 <ying.zhang22455@nxp.com> |
armv8/ls1088a: configure PMU's PCTBENR to enable WDT The SP805-WDT module on LS1088A requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. The watchdog clock needs to be enabled first. Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
44262327 |
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15-Dec-2017 |
Ahmed Mansour <ahmed.mansour@nxp.com> |
drivers/misc: Share qbman init between archs This patch adds changes necessary to move functionality present in PowerPC folders with ARM architectures that have DPAA1 QBMan hardware - Create new board/freescale/common/fsl_portals.c to house shared device tree fixups for DPAA1 devices with ARM and PowerPC cores - Add new header file to top includes directory to allow files in both architectures to grab the function prototypes - Port inhibit_portals() from PowerPC to ARM. This function is used in setup to disable interrupts on all QMan and BMan portals. It is needed because the interrupts are enabled by default for all portals including unused/uninitialised portals. When the kernel attempts to go to deep sleep the unused portals prevent it from doing so Signed-off-by: Ahmed Mansour <ahmed.mansour@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
a8f33034 |
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03-Dec-2017 |
Wenbin song <wenbin.song@nxp.com> |
armv8: ls1043a/ls2080a: check SoC by device ID Check LS1043A/LS2080a by device ID without using personality ID to determine revision number. This check applies to all various personalities of the same SoC family. Signed-off-by: Wenbin Song <wenbin.song@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
2db53cfe |
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09-Nov-2017 |
Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
armv8: fsl-layerscape: Add support of disabling core prefetch Instruction prefetch feature is by default enabled during core release. This patch add support of disabling instruction prefetch by setting core mask in PPA. Here each core mask bit represents a core and prefetch is disabled at the time of core release. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
7eb40f0f |
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28-Sep-2017 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: Avoid running dram_init_banksize again gd->ram_size is reduced in this function to reserve secure memory. Avoid running this function again to further reduce memory size. This fixes issue for SPL boot with PPA image loaded in which case secure memory is incorrectly allocated due to repeated calling. Signed-off-by: York Sun <york.sun@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
710d0cd7 |
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03-Oct-2017 |
Sumit Garg <sumit.garg@nxp.com> |
armv8: fsl-layerscape: Allocate Secure memory from first ddr region This change is required due to trusted OS (OP-TEE) not being position independent code, it requires compile time fixed base address. To take care of this it is assumed that all layerscape armv8 platforms has minimum 2G ddr in first region. So we can have fixed address space (66 MB -> (2MB for PPA + 64MB for trusted OS)) allocated from top of first 2G ddr region and compile trusted OS with this fixed base address. But one exception here is ls1012 where we have only 1G (rdb) or 512M (frdm) ddr memory. For those we can have different fixed compile time base addresses for trusted OS. Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
e9303a41 |
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07-Sep-2017 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: Fix MC reserved memory calculation In case high region memory doesn't have enough space for Management Complex (MC), the return value should indicate a failure so the caller can handle it accordingly. Signed-off-by: York Sun <york.sun@nxp.com> Reported-by: Ebony Zhu <ebony.zhu@nxp.com> |
#
17d066fc |
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31-Aug-2017 |
Ashish Kumar <Ashish.Kumar@nxp.com> |
armv8: fsl-layerscape: Support to add RGMII for ls1088aqds This patch adds support for RGMII protocol NXP's LDPAA2 support RGMII protocol. LS1088A is the first Soc supporting both RGMII and SGMII. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Amrita Kumari <amrita.kumari@nxp.com> Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
63b2316c |
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10-Aug-2017 |
Ashish Kumar <Ashish.Kumar@nxp.com> |
fsl-layerscape: Consolidate registers space defination for CCI-400 bus CoreLink Cache Coherent Interconnect (CCI) provides full cache coherency between two clusters of multi-core CPUs and I/O coherency for devices and I/O masters. This patch add new config option SYS_FSL_HAS_CCI400 and moves existing register space definaton of CCI-400 bus to fsl_immap to be shared. CONFIG_SYS_CCI400_ADDR is replaced with SYS_CCI400_OFFSET in Kconfig. Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> [YS: revised commit message, squashed patches for armv8 and armv7] Reviewed-by: York Sun <york.sun@nxp.com> |
#
6e2941d7 |
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17-May-2017 |
Simon Glass <sjg@chromium.org> |
common: freescale: Move arch-specific declarations The declarations should not be in common.h. Move them to the arch-specific headers. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Fixup thinko defined(FSL_LSCH3) -> defined(CONFIG_FSL_LSCH3)] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
399e2bb6 |
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15-May-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Make U-Boot EL2 safe When U-Boot boots from EL2, skip some lowlevel init code requiring EL3, including CCI-400/CCN-504, trust zone, GIC, etc. These initialization tasks are carried out before U-Boot runs. This applies to the RAM version image used for SPL boot if PPA is loaded first. Signed-off-by: York Sun <york.sun@nxp.com> |
#
1f55a938 |
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05-May-2017 |
Santan Kumar <santan.kumar@nxp.com> |
armv8: ls2080aqds: Add support for SD boot Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
e809e747 |
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27-Apr-2017 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: fsl-layerscape: Add NXP LS2081A, LS2041A SoC support The QorIQ LS2081A SoC has eight 64-bit ARM v8 Cortex A72 cores and is built on layerscape architecture. It is 40-pin derivative of LS2084A (non-AIOP personality of LS2088A). So feature-wise it is same as LS2084A. LS2041A is a 4-core personality of LS2081A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
026f30ec |
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18-Apr-2017 |
Yuantian Tang <andy.tang@nxp.com> |
arm: psci: make psci usable on single core socs PSCI can be used on both multiple and single core socs. Current implementation only allows PSCI to work on multiple core socs. This patch removes this restriction so that PSCI can work on single core socs as well. Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
4a3ab193 |
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27-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: ls2080a: Drop macro CONFIG_LS2080A Use CONFIG_ARCH_LS2080A instead. Signed-off-by: York Sun <york.sun@nxp.com> |
#
3eace37e |
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06-Apr-2017 |
Simon Glass <sjg@chromium.org> |
arm: freescale: Rename initdram() to fsl_initdram() This function name shadows a global name but is in fact different. This is very confusing. Rename it to help with the following refactoring. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
76b00aca |
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31-Mar-2017 |
Simon Glass <sjg@chromium.org> |
board_f: Drop setup_dram_config() wrapper By making dram_init_banksize() return an error code we can drop the wrapper. Adjust this and clean up all implementations. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
088454cd |
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31-Mar-2017 |
Simon Glass <sjg@chromium.org> |
board_f: Drop return value from initdram() At present we cannot use this function as an init sequence call without a wrapper, since it returns the RAM size. Adjust it to set the RAM size in global_data instead, and return 0 on success. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
52c41180 |
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31-Mar-2017 |
Simon Glass <sjg@chromium.org> |
board_f: Drop board_type parameter from initdram() It looks like only cm5200 and tqm8xx use this feature, so we don't really need it in generic code. Drop it and have the users access gd->board_type directly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
3d8553f0 |
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02-Mar-2017 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
pci: layerscape: add LS2088A series SoC pcie support The LS2088A series SoCs has different physical memory map address and CCSR registers address against LS2080A series SoCs. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
eea1cb77 |
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13-Feb-2017 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8/fsl-layerscape: Update erratum A009635 implementation Erratum A009635 is valid only for LS2080A SoC and its personality. Add SoC svr check. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
4961eafc |
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06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Update early MMU for DDR after initialization In early MMU table, DDR has to be mapped as device memory to avoid speculative access. After DDR is initialized, it needs to be updated to normal memory to allow code execution. To simplify the code, dram_init() is moved into a common file as a weak function. Signed-off-by: York Sun <york.sun@nxp.com> |
#
a045a0c3 |
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06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Fix the sequence of changing MMU table This patch follows the break-before-make process when making changes to MMU table. MMU is disabled before changing TTBR to avoid any potential race condition. Signed-off-by: York Sun <york.sun@nxp.com> |
#
24f55496 |
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06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Update MMU mapping with actual DDR size Update mapping with actual DDR size. Non-existing memory should not be mapped as "normal" memory to avoid speculative access. Signed-off-by: York Sun <york.sun@nxp.com> |
#
36cc0de0 |
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06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Rewrite memory reservation For ARMv8 Layerscape SoCs, secure memory and MC memorey are reserved at the end of DDR. DDR is spit into two or three banks. This patch reverts commit aabd7ddb and simplifies the calculation of reserved memory, and moves the code into common SoC file. Secure memory is carved out first. DDR bank size is reduced. Reserved memory is then allocated on the top of available memory. U-Boot still has access to reserved memory as data transferring is needed. Device tree is fixed with reduced memory size to hide the reserved memory from OS. The same region is reserved for efi_loader. Signed-off-by: York Sun <york.sun@nxp.com> |
#
daa92644 |
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16-Jan-2017 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
ARMv8/sec_firmware: relocated and renamed the config FSL_PPA_ARMV8_PSCI Moved the config FSL_PPA_ARMV8_PSCI from fsl-layerscape's Kconfig to Kconfig under armv8 and renamed it to SEC_FIRMWARE_ARMV8_PSCI. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
904110c7 |
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10-Jan-2017 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8/fsl-lsch2: refactor the clock system initialization Up to now, there are 3 kind of SoCs under Layerscape Chassis 2, like LS1043A, LS1046A and LS1012A. But the clocks tree has a lot of differences, for instance, the IP modules have different dividers to derive its clock from Platform PLL. And the core cluster PLL and platform PLL maybe have different reference clocks, such as LS1012A. Another problem is which clock/PLL should be described by sys_info->freq_systembus, it is confused in Layerscape Chissis 2. This patch is to bind the sys_info->freq_systembus to the Platform PLL, and handle the different divider of IP modules separately between different SoCs, and separate reference clocks of core cluster PLL and platform PLL. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
2d16a1a6 |
|
07-Dec-2016 |
macro.wave.z@gmail.com <macro.wave.z@gmail.com> |
ARMv8: LS1043A: change macro CONFIG_ARMV8_PSCI definition NXP/Freescale uses macro CONFIG_ARMV8_PSCI to enable their private PSCI implementation in PPA firmware, but this macro naming too generic, so this patch replaces it with a specic one CONFIG_FSL_PPA_ARMV8_PSCI. And this macro CONFIG_ARMV8_PSCI will be used for a generic PSCI for ARMv8 which will be added in following patchs. Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
02fb2761 |
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20-Nov-2016 |
Shengzhou Liu <Shengzhou.Liu@nxp.com> |
fsl/ddr: Add erratum_a009942_check_cpo and clean related erratum - add additional function erratum_a009942_check_cpo to check if the board needs tuning CPO calibration for optimal setting. - move ERRATUM_A009942(with revision to check cpo_sample option) from fsl_ddr_gen4.c to ctrl_regs.c for reuse on all DDR4/DDR3 parts. - move ERRATUM_A008378 from fsl_ddr_gen4.c to ctrl_regs.c - remove obsolete ERRATUM_A004934 which is replaced with ERRATUM_A009942. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> [YS: Replaced CONFIG_QEMU_E500 with CONFIG_ARCH_QEMU_E500] Reviewed-by: York Sun <york.sun@nxp.com> |
#
e87c673c |
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16-Nov-2016 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8/fsl-lsch3: Update code to release secondary cores NXP ARMv8 SoC LS2080A release all secondary cores in one-go. But other new SoCs like LS2088A, LS1088A release secondary cores one by one. Update code to release secondary cores based on SoC SVR Add code to release cores one by one for non LS2080A SoCs Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> [YS: remove "inline" from declaration of initiator_type] Reviewed-by: York Sun <york.sun@nxp.com> |
#
f6b96ff6 |
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16-Nov-2016 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Use SVR based timer base address detection Timer controller base address has been changed from LS2080A SoC (and its personalities) to new SoCs like LS2088A, LS1088A. Use SVR based timer base address detection to avoid compile time #ifdef. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
f6a70b3a |
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16-Nov-2016 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add generic get_svr() in assembly Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
78d57842 |
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16-Nov-2016 |
Alexander Graf <agraf@csgraf.de> |
armv8: fsl-layerscape: Add support for efi_loader RTS reset When implementing efi loader support, we can expose runtime services for payloads. One such service is CPU reset. This patch implements RTS CPU reset support for layerscape systems. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: York Sun <york.sun@nxp.com> |
#
ef9a5fd8 |
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13-Sep-2016 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: Fix "cpu status" command The core position is not continuous for some SoCs. For example, valid cores may present at position 0, 1, 4, 5, 8, 9, etc. Some registers (including boot release register) only count existing cores. Current implementation of cpu_mask() complies with the continuous numbering. However, command "cpu status" queries the spin table with actual core position. Add functions to calculate core position from core number, to correctly calculate offsets. Tested on LS2080ARDB and LS1043ARDB. Signed-off-by: York Sun <york.sun@nxp.com> |
#
5d1a7a9d |
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13-Sep-2016 |
Wenbin Song <wenbin.song@nxp.com> |
armv8/fsl-layerscape: print SoC revsion number The exact SoC revsion number can be recognized from U-Boot log. Signed-off-by: Wenbin Song <wenbin.song@nxp.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
cbe7706a |
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26-Sep-2016 |
Tom Rini <trini@konsulko.com> |
Merge git://git.denx.de/u-boot-fsl-qoriq trini: Drop local memset() from examples/standalone/mem_to_mem_idma2intr.c Signed-off-by: Tom Rini <trini@konsulko.com>
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#
1221ce45 |
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20-Sep-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
treewide: replace #include <asm/errno.h> with <linux/errno.h> Now, arch/${ARCH}/include/asm/errno.h and include/linux/errno.h have the same content. (both just wrap <asm-generic/errno.h>) Replace all include directives for <asm/errno.h> with <linux/errno.h>. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> [trini: Fixup include/clk.] Signed-off-by: Tom Rini <trini@konsulko.com> |
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b63a9506 |
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03-Aug-2016 |
York Sun <york.sun@nxp.com> |
armv8: ls2080a: Remove debug server support Debug server feature has been dropped from roadmap. Signed-off-by: York Sun <york.sun@nxp.com> |
#
ed7a3943 |
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22-Jul-2016 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: mmu: Fix enabling MMU MMU bit in SCTLR needs to be set explicitly after tables are created. It isn't an issue for EL3 becuase this bit is already set by early MMU setup. But for other exception levels this bit was not set. Signed-off-by: York Sun <york.sun@nxp.com> |
#
79119a4d |
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05-Jul-2016 |
Alison Wang <b18965@freescale.com> |
armv8: fsl-layerscape: Add A72 core detection Add support to detect Cortex-A72 core for printing it out. The Initiator Version of A72 core should be 0x4. Signed-off-by: Alison Wang <alison.wang@nxp.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
032d5bb4 |
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28-Jun-2016 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
ARMv8/Layerscape: switch SMP method accordingly If the PSCI and PPA is ready, skip the fixup for spin-table and waking secondary cores. Otherwise, change SMP method to spin-table, and the device node of PSCI will be removed. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
85cdf38e |
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28-Jun-2016 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: fsl-layerscape: add i/d-cache enable function to enable_caches This function assume that the d-cache and MMU has been enabled earlier, so it just created MMU table in main memory. But the assumption is not always correct, for example, the early setup is done in EL3, while enable_caches() is called when the PE has turned into another EL. Define the function mmu_setup() for fsl-layerscape to cover the weak one. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
5ad5823d |
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24-Jun-2016 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Convert to use common MMU framework Drop platform code to create static MMU tables. Use common framework to create MMU tables on the run. Tested on LS2080ARDB with secure and non-secure ram scenarios. Signed-off-by: York Sun <york.sun@nxp.com> |
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e61a7534 |
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24-Jun-2016 |
York Sun <york.sun@nxp.com> |
armv8: Move secure_ram variable out of generic global data Secure_ram variable was put in generic global data. But only ARMv8 uses this variable. Move it to ARM specific data structure. Signed-off-by: York Sun <york.sun@nxp.com> |
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a10a31ec |
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18-Jun-2016 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of git://git.denx.de/u-boot-usb Signed-off-by: Tom Rini <trini@konsulko.com> Conflicts: arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
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#
6fb522dc |
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12-Jun-2016 |
Sriram Dash <sriram.dash@nxp.com> |
arm64: fsl-layerscape: add get_svr and IS_SVR_REV helper Adds get_svr and IS_SVR_REV helpers for ARMv8 platforms, similar to PPC and ARMv7. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> |
#
a758177f |
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07-Jun-2016 |
Yunhui Cui <yunhui.cui@nxp.com> |
armv8/ls2080a: configure PMU's PCTBENR to enable WDT The SP805-WDT module on LS2080A requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. The watchdog clock needs to be enabled first. Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
acb8f5e9 |
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21-Apr-2016 |
Alison Wang <b18965@freescale.com> |
armv8: fsl-layerscape: Remove unnecessary flushing dcache As the issue about the stack will get corrupted when switching between the early and final mmu tables is fixed by commit 70e21b064, the workaround to flush dcache is unnecessary and should be removed. Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
3c1d218a |
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04-Apr-2016 |
York Sun <york.sun@nxp.com> |
armv8: LS2080A: Consolidate LS2080A and LS2085A LS2080A is the primary SoC, and LS2085A is a personality with AIOP and DPAA DDR. The RDB and QDS boards support both personality. By detecting the SVR at runtime, a single image per board can support both SoCs. It gives users flexibility to swtich SoC without the need to reprogram the board. Signed-off-by: York Sun <york.sun@nxp.com> CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
c05016ab |
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21-Mar-2016 |
Alexander Graf <agraf@csgraf.de> |
arm64: Fix layerscape mmu setup With commit 7985cdf we converted all systems except for the Layerscape SoCs to the generic descriptor table based page table setup. On the Layerscape SoCs however, we just provide an empty table stub and do the setup ourselves. To reserve enough memory for the tables, we need to override the default counting mechanism which would end up with an empty table because we have no maps. Fixes: 7985cdf Reported-by: York Sun <york.sun@nxp.com> CC: Alison Wang <alison.wang@nxp.com> CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Alexander Graf <agraf@suse.de> Tested-by: York Sun <york.sun@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
7985cdf7 |
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03-Mar-2016 |
Alexander Graf <agraf@csgraf.de> |
arm64: Remove non-full-va map code By now the code to only have a single page table level with 64k page size and 42 bit address space is no longer used by any board in tree, so we can safely remove it. To clean up code, move the layerscape mmu code to the new defines, removing redundant field definitions. Signed-off-by: Alexander Graf <agraf@suse.de> |
#
c0492141 |
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07-Dec-2015 |
York Sun <yorksun@freescale.com> |
armv8: fsl-layerscale: Rewrite reserving memory for MC and debug server MC and debug server are not board-specific. Move reserving memory to SoC file, using the new board_reserve_ram_top function. Reduce debug server memory by 2MB to make room for secure memory. In the system with MC and debug server, the top of u-boot memory is not the end of memory. PRAM is not used for this reservation. Signed-off-by: York Sun <yorksun@freescale.com> |
#
c107c0c0 |
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04-Dec-2015 |
York Sun <yorksun@freescale.com> |
armv8: fsl-layerscape: Make DDR non secure in MMU tables DDR has been set as secure in MMU tables. Non-secure master such as SDHC DMA cannot access data correctly. Mixing secure and non- secure MMU entries requirs the MMU tables themselves in secure memory. This patch moves MMU tables into a secure DDR area. Early MMU tables are changed to set DDR as non-secure. A new table is added into final MMU tables so secure memory can have 2MB granuality. gd->secure_ram tracks the location of this secure memory. For ARMv8 SoCs, the RAM base is not zero and RAM is divided into several banks. gd->secure_ram needs to be maintained before using. This maintenance is board-specific, depending on the SoC and memory bank of the secure memory falls into. Signed-off-by: York Sun <yorksun@freescale.com> |
#
b4017364 |
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04-Nov-2015 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
armv8: ls2085a: Add workaround of errata A009635 If the core runs at higher than x3 speed of the platform, there is possiblity about sev instruction to getting missed by other cores. This is because of SoC Run Control block may not able to sample the EVENTI(Sev) signals. Configure Run Control and EPU to periodically send out EVENTI signals to wake up A57 cores. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
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d764129d |
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04-Nov-2015 |
Alison Wang <b18965@freescale.com> |
armv8/layerscape: Update MMU table with execute-never bits For most device addresses excution shouldn't be allowed. Revise the MMU table to enforce execute-never bits. OCRAM, DDR and IFC are allowed for excution. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Alison Wang <alison.wang@freescale.com> Reported-by: Zhichun Hua <zhichun.hua@freescale.com> |
#
44937214 |
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09-Nov-2015 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
armv8: LS2080A: Rename LS2085A to reflect LS2080A LS2080A is a prime personality of Freescale’s LS2085A. It is a non-AIOP personality without support of DP-DDR, L2 switch, 1588, PCIe endpoint etc. So renaming existing LS2085A code base to reflect LS2080A (Prime personality) Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> [York Sun: Dropped #ifdef in cpu.c for cpu_type_list] Reviewed-by: York Sun <yorksun@freescale.com> |
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e8297341 |
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26-Oct-2015 |
Shaohui Xie <Shaohui.Xie@freescale.com> |
armv8/ls1043a: Add Fman support Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
8281c58f |
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26-Oct-2015 |
Mingkai Hu <Mingkai.Hu@freescale.com> |
armv8/fsl_lsch2: Add fsl_lsch2 SoC Freescale LayerScape with Chassis Generation 2 is a set of SoCs with ARMv8 cores and 2rd generation of Chassis. Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
9f3183d2 |
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26-Oct-2015 |
Mingkai Hu <Mingkai.Hu@freescale.com> |
armv8/fsl_lsch3: Change arch to fsl-layerscape There are two LS series processors are built on ARMv8 Layersacpe architecture currently, LS2085A and LS1043A. They are based on ARMv8 core although use different chassis, so create fsl-layerscape to refactor the common code for the LS series processors which also paves the way for adding LS1043A platform. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
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714497e3 |
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16-May-2020 |
Michael Walle <michael@walle.cc> |
efi_loader: round the memory area in efi_add_memory_map() Virtually all callers of this function do the rounding on their own. Some do it right, some don't. Instead of doing this in each caller, do the rounding in efi_add_memory_map(). Change the size parameter to bytes instead of pages and remove aligning and size calculation in all callers. There is no more need to make the original efi_add_memory_map() (which takes pages as size) available outside the module. Thus rename it to efi_add_memory_map_pg() and make it static to prevent further misuse outside the module. Signed-off-by: Michael Walle <michael@walle.cc> Add missing comma in sunxi_display.c. Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de> |
#
6eb32a03 |
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23-Apr-2020 |
Madalin Bucur <madalin.bucur@oss.nxp.com> |
driver: net: fm: add DM ETH support Probe the FMan MACs based on the device tree while retaining the legacy code/functionality. One notable change introduced here is that, for DM_ETH, the name of the interfaces is corrected to the fmX-macY format, that avoids the referral to the MAC block names which were incorrect for FMan v3 devices (i.e. DTSEC, TGEC) and had weird formatting (i.e. FM1@DTSEC6, FM1@TGEC1). The legacy code is left unchanged in this respect. Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
6ebd4883 |
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27-Apr-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
fsl-layerscape: Add RESV_RAM check in resv_ram addr The initialization of gd->arch.resv_ram pointer should depend on if the RESV_RAM config is enabled. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Wasim Khan <wasim.khan@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
0d9d557d |
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10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
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db41d65a |
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28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move hang() to the same header as panic() At present panic() is in the vsprintf.h header file. That does not seem like an obvious choice for hang(), even though it relates to panic(). So let's put hang() in its own header. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Migrate a few more files] Signed-off-by: Tom Rini <trini@konsulko.com> |
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9b4a205f |
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28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move RAM-sizing functions to init.h These functions relate to memory init so move them into the init header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
3499dd03 |
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27-Nov-2019 |
Alex Marginean <alexandru.marginean@nxp.com> |
ls1028a: Configure stream IDs for integrated PCI and fix up Linux DT Hardware comes out of reset with implicit values, but these are outside the accepted range for Layerscape gen 3 chassis spec used on LS1028A. Allocate different IDs and fix up Linux DT to use them. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
b5981474 |
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14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some CPU functions out of common.h These functions belong in cpu_func.h since they do not use driver model. Move them over. Don't bother adding comments since these functions should be deleted. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
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68a6aa85 |
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14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move mii_init() function out of common.h This function belongs in mii.h so move it over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
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2189d5f1 |
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14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
Move strtomhz() to vsprintf.h At present this function sits in its own file but it does not really justify it. There are similar string functions in vsprintf.h, so move it there. Also add the missing function comment. Use the vsprintf.h include file explicitly where needed. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
812ff53c |
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30-Oct-2019 |
Pankaj Bansal <pankaj.bansal@nxp.com> |
fsl-layerscape: fix warning if no hwconfig is defined While getting the 'subarg' of 'hwconfig' env variable in config_core_prefetch(), if no hwconfig variable is defined, below warning is received: WARNING: Calling __hwconfig without a buffer and before environment is ready Fix this by checking 'hwconfig' env variable. If not found return without further processing. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Tested-by: Michael Walle <michael@walle.cc> |
#
28f9393b |
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17-Oct-2019 |
Mathew McBride <matt@traverse.com.au> |
fsl-layerscape: do not use layerscape EFI reset if PSCI used If the secure world reset handlers are used (via CONFIG_PSCI_RESET), then do not use the layerscape-specific implementation. Signed-off-by: Mathew McBride <matt@traverse.com.au> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
6ed69523 |
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18-Sep-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add more personalities support Add LS1027A, LS1018A and LS1017A personalities support to LS1028A SoC family. LS1028A is the prime personality of LS1028A SoC family. LS1027A is a lower funtionality version of QorIQ LS1028A which does not support the multimedia subsystems, such as LCD controller, GPU, and eDP PHY. The QorIQ LS1018A and LS1017A SoCs are single 64-bit Arm A72 core, low power versions of the QorIQ LS1028A and LS1027A SoCs respectively. Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
0490cab5 |
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08-Aug-2019 |
Thomas Schaefer <thomas.schaefer@kontron.com> |
armv8: ls1028a: configure PMU's PCTBENR to enable WDT The SP805-WDT module on LS1028A requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. The watchdog clock needs to be enabled first. Signed-off-by: Thomas Schaefer <thomas.schaefer@kontron.com> Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
f3998fdc |
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02-Aug-2019 |
Simon Glass <sjg@chromium.org> |
env: Rename environment.h to env_internal.h This file contains lots of internal details about the environment. Most code can include env.h instead, calling the functions there as needed. Rename this file and add a comment at the top to indicate its internal nature. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> [trini: Fixup apalis-tk1.c] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
3a7d5571 |
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01-Aug-2019 |
Simon Glass <sjg@chromium.org> |
env: Move env_get_f() to env.h Move this function over to the new header file. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
d9532e80 |
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23-Apr-2019 |
Udit Agarwal <udit.agarwal@nxp.com> |
armv8: fsl-layerscape: Set env_loc to ENVL_NOWHERE with CONFIG_ENV_IS_NOWHERE. ENVL_NOWHERE is dependent on CONFIG_ENV_IS_NOWHERE and not on CONFIG_CHAIN_OF_TRUST so return ENVL_NOWHERE when CONFIG_ENV_IS_NOWHERE is enabled Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
d4ad111d |
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10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
059d9422 |
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08-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: lx2160a: add MMU table entries for PCIe The lx2160a have up to 6 PCIe controllers and have different address and size of PCIe region. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
8348e798 |
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08-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: layerscape: use PCIe address macro for precompile PCIe MMU entry Change to use PCIe address macro to determine if precompile the PCIe MMU table entry. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
10015025 |
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03-May-2019 |
Trevor Woerner <trevor@toganlabs.com> |
CONFIG_SPL_SYS_[DI]CACHE_OFF: add While converting CONFIG_SYS_[DI]CACHE_OFF to Kconfig, there are instances where these configuration items are conditional on SPL. This commit adds SPL variants of these configuration items, uses CONFIG_IS_ENABLED(), and updates the configurations as required. Acked-by: Alexey Brodkin <abrodkin@synopsys.com> Signed-off-by: Trevor Woerner <trevor@toganlabs.com> [trini: Make the default depend on the setting for full U-Boot, update more zynq hardware] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
2e53759d |
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29-Oct-2018 |
Pankaj Bansal <pankaj.bansal@nxp.com> |
armv8: fsl-layerscape: reorder rgmii dpmacs' enablement some dpmacs in armv8a based freescale layerscape SOCs can be configured via both serdes(sgmii, xfi, xlaui etc) bits and via EC*_PMUX(rgmii) bits in RCW. e.g. dpmac 17 and 18 in LX2160A can be configured as SGMII from serdes bits and as RGMII via EC1_PMUX/EC2_PMUX bits Now if a dpmac is enabled by serdes bits then it takes precedence over EC*_PMUX bits. i.e. in LX2160A if we select serdes protocol that configures dpmac17 as SGMII and set the EC1_PMUX as RGMII, then the dpmac is SGMII and not RGMII. Therefore, move the fsl_rgmii_init after fsl_serdes_init. in fsl_rgmii_init function of SOC, we will check if the dpmac is enabled or not? if it is (fsl_serdes_init has already enabled the dpmac), then don't enable it. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
ec88ff80 |
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19-Dec-2018 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1043a: add SVR definitions for 23x23 package silicon LS1043A/LS1023A 23x23 package silicon has different SVR:VAR_PER. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
d23da2ae |
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26-Dec-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: fixes for TFABOOT framework Fixes for TFABOOT framework - update eMMC bootsrc to SD_MMC - Increase buffer size for mcinitcmd from 256 to 512 - Fix mcinitcmd and bootcmd for Secure Boot Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
4909b89e |
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29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
d6fdec21 |
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29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8:fsl-layerscape: Add support for Chassis 3.2 NXP layerscape architecture Chassis 3.2 builds upon chassis3 architecture with changes like DDR Memory map change, removal of IFC and support of upto 8 I2C controller. Patch add README.lsch3_2 and the above changes under macro CONFIG_NXP_LSCH3_2. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
56db948b |
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05-Nov-2018 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: Update parsing boot source Workaround of erratum A010539 clears the RCW source field in PORSR1 register, causing failure of detecting boot source using this method. Use SMC call if U-Boot runs at EL2. If SMC is not implemented or running at EL3, continue to read PORSR1 and presume QSPI as boot source if erratum workaround A010539 is enabled and RCW source is cleared. Signed-off-by: York Sun <york.sun@nxp.com> |
#
681d489e |
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05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: layerscape: add SMC calls for DDR size and bank info Adds SMC calls for getting DDR size and bank info for TFABOOT. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
2141d250 |
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05-Nov-2018 |
Pankit Garg <pankit.garg@nxp.com> |
armv8: fsl-layerscape: bootcmd identification for TFABOOT Adds bootcmd identificaton on basis on boot source, valid in TFABOOT configuration. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> [YS: remove unnecessary braces] Reviewed-by: York Sun <york.sun@nxp.com> |
#
4c417384 |
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05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com> |
#
535d76a1 |
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05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: layerscape: Add TFABOOT support Adds TFABOOT support config option and add generic code to enable execution from DDR. Signed-off-by: York Sun <york.sun@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> |
#
e3506480 |
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05-Nov-2018 |
Pankit Garg <pankit.garg@nxp.com> |
armv8: fsl-layerscape: change tlb base from OCRAM to DDR in EL < 3 Change tlb base address from OCRAM to DDR when exception level is less than 3. Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
d171c707 |
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05-Nov-2018 |
York Sun <york.sun@nxp.com> |
move data structure out of cpu.h Move static definitions to cpu.c file, as it doesn't allow the cpu.h file to be included in multiple c files. Signed-off-by: York Sun <york.sun@nxp.com> |
#
9b5e6396 |
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30-Aug-2018 |
Stephen Warren <swarren@nvidia.com> |
efi_loader: simplify ifdefs Use CONFIG_IS_ENABLED(EFI_LOADER) to avoid explicitly checking CONFIG_SPL too. This simplifies the conditional. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Alexander Graf <agraf@suse.de> |
#
9cce5663 |
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16-Jul-2018 |
Joe Hershberger <joe.hershberger@ni.com> |
arm: Prevent redefinition error in fsl-layerscape The include/phy.h will start including dm.h, which pulls in linux/compat.h after the attempted redefinition in arch/arm/include/asm/armv8/mmu.h, so move this include to allow redefinition. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> |
#
83d290c5 |
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06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
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482fc90c |
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06-Feb-2018 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
efi_loader: add missing EFI_RESET_PLATFORM_SPECIFIC EFI_RESET_PLATFORM_SPECIFIC is one of the values that can be used for the EFI service ResetSystem. The missing definition is added. The value has to handled in efi_reset_system(). Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Alexander Graf <agraf@suse.de> |
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22c793e6 |
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03-Mar-2018 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
efi_loader: exit status for efi_reset_system_init efi_reset_system_init provides the architecture or board specific initialization of the EFI subsystem. Errors should be caught and signalled by a return code. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Alexander Graf <agraf@suse.de> |
#
958b2ed5 |
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09-Jan-2018 |
Zhang Ying-22455 <ying.zhang22455@nxp.com> |
armv8/ls1088a: configure PMU's PCTBENR to enable WDT The SP805-WDT module on LS1088A requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. The watchdog clock needs to be enabled first. Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
44262327 |
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15-Dec-2017 |
Ahmed Mansour <ahmed.mansour@nxp.com> |
drivers/misc: Share qbman init between archs This patch adds changes necessary to move functionality present in PowerPC folders with ARM architectures that have DPAA1 QBMan hardware - Create new board/freescale/common/fsl_portals.c to house shared device tree fixups for DPAA1 devices with ARM and PowerPC cores - Add new header file to top includes directory to allow files in both architectures to grab the function prototypes - Port inhibit_portals() from PowerPC to ARM. This function is used in setup to disable interrupts on all QMan and BMan portals. It is needed because the interrupts are enabled by default for all portals including unused/uninitialised portals. When the kernel attempts to go to deep sleep the unused portals prevent it from doing so Signed-off-by: Ahmed Mansour <ahmed.mansour@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
a8f33034 |
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03-Dec-2017 |
Wenbin song <wenbin.song@nxp.com> |
armv8: ls1043a/ls2080a: check SoC by device ID Check LS1043A/LS2080a by device ID without using personality ID to determine revision number. This check applies to all various personalities of the same SoC family. Signed-off-by: Wenbin Song <wenbin.song@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
2db53cfe |
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09-Nov-2017 |
Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
armv8: fsl-layerscape: Add support of disabling core prefetch Instruction prefetch feature is by default enabled during core release. This patch add support of disabling instruction prefetch by setting core mask in PPA. Here each core mask bit represents a core and prefetch is disabled at the time of core release. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
7eb40f0f |
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28-Sep-2017 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: Avoid running dram_init_banksize again gd->ram_size is reduced in this function to reserve secure memory. Avoid running this function again to further reduce memory size. This fixes issue for SPL boot with PPA image loaded in which case secure memory is incorrectly allocated due to repeated calling. Signed-off-by: York Sun <york.sun@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
710d0cd7 |
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03-Oct-2017 |
Sumit Garg <sumit.garg@nxp.com> |
armv8: fsl-layerscape: Allocate Secure memory from first ddr region This change is required due to trusted OS (OP-TEE) not being position independent code, it requires compile time fixed base address. To take care of this it is assumed that all layerscape armv8 platforms has minimum 2G ddr in first region. So we can have fixed address space (66 MB -> (2MB for PPA + 64MB for trusted OS)) allocated from top of first 2G ddr region and compile trusted OS with this fixed base address. But one exception here is ls1012 where we have only 1G (rdb) or 512M (frdm) ddr memory. For those we can have different fixed compile time base addresses for trusted OS. Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
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e9303a41 |
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07-Sep-2017 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: Fix MC reserved memory calculation In case high region memory doesn't have enough space for Management Complex (MC), the return value should indicate a failure so the caller can handle it accordingly. Signed-off-by: York Sun <york.sun@nxp.com> Reported-by: Ebony Zhu <ebony.zhu@nxp.com> |
#
17d066fc |
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31-Aug-2017 |
Ashish Kumar <Ashish.Kumar@nxp.com> |
armv8: fsl-layerscape: Support to add RGMII for ls1088aqds This patch adds support for RGMII protocol NXP's LDPAA2 support RGMII protocol. LS1088A is the first Soc supporting both RGMII and SGMII. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Amrita Kumari <amrita.kumari@nxp.com> Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
63b2316c |
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10-Aug-2017 |
Ashish Kumar <Ashish.Kumar@nxp.com> |
fsl-layerscape: Consolidate registers space defination for CCI-400 bus CoreLink Cache Coherent Interconnect (CCI) provides full cache coherency between two clusters of multi-core CPUs and I/O coherency for devices and I/O masters. This patch add new config option SYS_FSL_HAS_CCI400 and moves existing register space definaton of CCI-400 bus to fsl_immap to be shared. CONFIG_SYS_CCI400_ADDR is replaced with SYS_CCI400_OFFSET in Kconfig. Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> [YS: revised commit message, squashed patches for armv8 and armv7] Reviewed-by: York Sun <york.sun@nxp.com> |
#
6e2941d7 |
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17-May-2017 |
Simon Glass <sjg@chromium.org> |
common: freescale: Move arch-specific declarations The declarations should not be in common.h. Move them to the arch-specific headers. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Fixup thinko defined(FSL_LSCH3) -> defined(CONFIG_FSL_LSCH3)] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
399e2bb6 |
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15-May-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Make U-Boot EL2 safe When U-Boot boots from EL2, skip some lowlevel init code requiring EL3, including CCI-400/CCN-504, trust zone, GIC, etc. These initialization tasks are carried out before U-Boot runs. This applies to the RAM version image used for SPL boot if PPA is loaded first. Signed-off-by: York Sun <york.sun@nxp.com> |
#
1f55a938 |
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05-May-2017 |
Santan Kumar <santan.kumar@nxp.com> |
armv8: ls2080aqds: Add support for SD boot Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
e809e747 |
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27-Apr-2017 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: fsl-layerscape: Add NXP LS2081A, LS2041A SoC support The QorIQ LS2081A SoC has eight 64-bit ARM v8 Cortex A72 cores and is built on layerscape architecture. It is 40-pin derivative of LS2084A (non-AIOP personality of LS2088A). So feature-wise it is same as LS2084A. LS2041A is a 4-core personality of LS2081A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
026f30ec |
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18-Apr-2017 |
Yuantian Tang <andy.tang@nxp.com> |
arm: psci: make psci usable on single core socs PSCI can be used on both multiple and single core socs. Current implementation only allows PSCI to work on multiple core socs. This patch removes this restriction so that PSCI can work on single core socs as well. Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
4a3ab193 |
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27-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: ls2080a: Drop macro CONFIG_LS2080A Use CONFIG_ARCH_LS2080A instead. Signed-off-by: York Sun <york.sun@nxp.com> |
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3eace37e |
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06-Apr-2017 |
Simon Glass <sjg@chromium.org> |
arm: freescale: Rename initdram() to fsl_initdram() This function name shadows a global name but is in fact different. This is very confusing. Rename it to help with the following refactoring. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
76b00aca |
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31-Mar-2017 |
Simon Glass <sjg@chromium.org> |
board_f: Drop setup_dram_config() wrapper By making dram_init_banksize() return an error code we can drop the wrapper. Adjust this and clean up all implementations. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
088454cd |
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31-Mar-2017 |
Simon Glass <sjg@chromium.org> |
board_f: Drop return value from initdram() At present we cannot use this function as an init sequence call without a wrapper, since it returns the RAM size. Adjust it to set the RAM size in global_data instead, and return 0 on success. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> |
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52c41180 |
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31-Mar-2017 |
Simon Glass <sjg@chromium.org> |
board_f: Drop board_type parameter from initdram() It looks like only cm5200 and tqm8xx use this feature, so we don't really need it in generic code. Drop it and have the users access gd->board_type directly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
3d8553f0 |
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02-Mar-2017 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
pci: layerscape: add LS2088A series SoC pcie support The LS2088A series SoCs has different physical memory map address and CCSR registers address against LS2080A series SoCs. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
eea1cb77 |
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13-Feb-2017 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8/fsl-layerscape: Update erratum A009635 implementation Erratum A009635 is valid only for LS2080A SoC and its personality. Add SoC svr check. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
4961eafc |
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06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Update early MMU for DDR after initialization In early MMU table, DDR has to be mapped as device memory to avoid speculative access. After DDR is initialized, it needs to be updated to normal memory to allow code execution. To simplify the code, dram_init() is moved into a common file as a weak function. Signed-off-by: York Sun <york.sun@nxp.com> |
#
a045a0c3 |
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06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Fix the sequence of changing MMU table This patch follows the break-before-make process when making changes to MMU table. MMU is disabled before changing TTBR to avoid any potential race condition. Signed-off-by: York Sun <york.sun@nxp.com> |
#
24f55496 |
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06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Update MMU mapping with actual DDR size Update mapping with actual DDR size. Non-existing memory should not be mapped as "normal" memory to avoid speculative access. Signed-off-by: York Sun <york.sun@nxp.com> |
#
36cc0de0 |
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06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Rewrite memory reservation For ARMv8 Layerscape SoCs, secure memory and MC memorey are reserved at the end of DDR. DDR is spit into two or three banks. This patch reverts commit aabd7ddb and simplifies the calculation of reserved memory, and moves the code into common SoC file. Secure memory is carved out first. DDR bank size is reduced. Reserved memory is then allocated on the top of available memory. U-Boot still has access to reserved memory as data transferring is needed. Device tree is fixed with reduced memory size to hide the reserved memory from OS. The same region is reserved for efi_loader. Signed-off-by: York Sun <york.sun@nxp.com> |
#
daa92644 |
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16-Jan-2017 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
ARMv8/sec_firmware: relocated and renamed the config FSL_PPA_ARMV8_PSCI Moved the config FSL_PPA_ARMV8_PSCI from fsl-layerscape's Kconfig to Kconfig under armv8 and renamed it to SEC_FIRMWARE_ARMV8_PSCI. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
904110c7 |
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10-Jan-2017 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8/fsl-lsch2: refactor the clock system initialization Up to now, there are 3 kind of SoCs under Layerscape Chassis 2, like LS1043A, LS1046A and LS1012A. But the clocks tree has a lot of differences, for instance, the IP modules have different dividers to derive its clock from Platform PLL. And the core cluster PLL and platform PLL maybe have different reference clocks, such as LS1012A. Another problem is which clock/PLL should be described by sys_info->freq_systembus, it is confused in Layerscape Chissis 2. This patch is to bind the sys_info->freq_systembus to the Platform PLL, and handle the different divider of IP modules separately between different SoCs, and separate reference clocks of core cluster PLL and platform PLL. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
2d16a1a6 |
|
07-Dec-2016 |
macro.wave.z@gmail.com <macro.wave.z@gmail.com> |
ARMv8: LS1043A: change macro CONFIG_ARMV8_PSCI definition NXP/Freescale uses macro CONFIG_ARMV8_PSCI to enable their private PSCI implementation in PPA firmware, but this macro naming too generic, so this patch replaces it with a specic one CONFIG_FSL_PPA_ARMV8_PSCI. And this macro CONFIG_ARMV8_PSCI will be used for a generic PSCI for ARMv8 which will be added in following patchs. Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
02fb2761 |
|
20-Nov-2016 |
Shengzhou Liu <Shengzhou.Liu@nxp.com> |
fsl/ddr: Add erratum_a009942_check_cpo and clean related erratum - add additional function erratum_a009942_check_cpo to check if the board needs tuning CPO calibration for optimal setting. - move ERRATUM_A009942(with revision to check cpo_sample option) from fsl_ddr_gen4.c to ctrl_regs.c for reuse on all DDR4/DDR3 parts. - move ERRATUM_A008378 from fsl_ddr_gen4.c to ctrl_regs.c - remove obsolete ERRATUM_A004934 which is replaced with ERRATUM_A009942. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> [YS: Replaced CONFIG_QEMU_E500 with CONFIG_ARCH_QEMU_E500] Reviewed-by: York Sun <york.sun@nxp.com> |
#
e87c673c |
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16-Nov-2016 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8/fsl-lsch3: Update code to release secondary cores NXP ARMv8 SoC LS2080A release all secondary cores in one-go. But other new SoCs like LS2088A, LS1088A release secondary cores one by one. Update code to release secondary cores based on SoC SVR Add code to release cores one by one for non LS2080A SoCs Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> [YS: remove "inline" from declaration of initiator_type] Reviewed-by: York Sun <york.sun@nxp.com> |
#
f6b96ff6 |
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16-Nov-2016 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Use SVR based timer base address detection Timer controller base address has been changed from LS2080A SoC (and its personalities) to new SoCs like LS2088A, LS1088A. Use SVR based timer base address detection to avoid compile time #ifdef. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
f6a70b3a |
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16-Nov-2016 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add generic get_svr() in assembly Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
78d57842 |
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16-Nov-2016 |
Alexander Graf <agraf@csgraf.de> |
armv8: fsl-layerscape: Add support for efi_loader RTS reset When implementing efi loader support, we can expose runtime services for payloads. One such service is CPU reset. This patch implements RTS CPU reset support for layerscape systems. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: York Sun <york.sun@nxp.com> |
#
ef9a5fd8 |
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13-Sep-2016 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: Fix "cpu status" command The core position is not continuous for some SoCs. For example, valid cores may present at position 0, 1, 4, 5, 8, 9, etc. Some registers (including boot release register) only count existing cores. Current implementation of cpu_mask() complies with the continuous numbering. However, command "cpu status" queries the spin table with actual core position. Add functions to calculate core position from core number, to correctly calculate offsets. Tested on LS2080ARDB and LS1043ARDB. Signed-off-by: York Sun <york.sun@nxp.com> |
#
5d1a7a9d |
|
13-Sep-2016 |
Wenbin Song <wenbin.song@nxp.com> |
armv8/fsl-layerscape: print SoC revsion number The exact SoC revsion number can be recognized from U-Boot log. Signed-off-by: Wenbin Song <wenbin.song@nxp.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
cbe7706a |
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26-Sep-2016 |
Tom Rini <trini@konsulko.com> |
Merge git://git.denx.de/u-boot-fsl-qoriq trini: Drop local memset() from examples/standalone/mem_to_mem_idma2intr.c Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
1221ce45 |
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20-Sep-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
treewide: replace #include <asm/errno.h> with <linux/errno.h> Now, arch/${ARCH}/include/asm/errno.h and include/linux/errno.h have the same content. (both just wrap <asm-generic/errno.h>) Replace all include directives for <asm/errno.h> with <linux/errno.h>. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> [trini: Fixup include/clk.] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
b63a9506 |
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03-Aug-2016 |
York Sun <york.sun@nxp.com> |
armv8: ls2080a: Remove debug server support Debug server feature has been dropped from roadmap. Signed-off-by: York Sun <york.sun@nxp.com> |
#
ed7a3943 |
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22-Jul-2016 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: mmu: Fix enabling MMU MMU bit in SCTLR needs to be set explicitly after tables are created. It isn't an issue for EL3 becuase this bit is already set by early MMU setup. But for other exception levels this bit was not set. Signed-off-by: York Sun <york.sun@nxp.com> |
#
79119a4d |
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05-Jul-2016 |
Alison Wang <b18965@freescale.com> |
armv8: fsl-layerscape: Add A72 core detection Add support to detect Cortex-A72 core for printing it out. The Initiator Version of A72 core should be 0x4. Signed-off-by: Alison Wang <alison.wang@nxp.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
032d5bb4 |
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28-Jun-2016 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
ARMv8/Layerscape: switch SMP method accordingly If the PSCI and PPA is ready, skip the fixup for spin-table and waking secondary cores. Otherwise, change SMP method to spin-table, and the device node of PSCI will be removed. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
85cdf38e |
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28-Jun-2016 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: fsl-layerscape: add i/d-cache enable function to enable_caches This function assume that the d-cache and MMU has been enabled earlier, so it just created MMU table in main memory. But the assumption is not always correct, for example, the early setup is done in EL3, while enable_caches() is called when the PE has turned into another EL. Define the function mmu_setup() for fsl-layerscape to cover the weak one. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
5ad5823d |
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24-Jun-2016 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Convert to use common MMU framework Drop platform code to create static MMU tables. Use common framework to create MMU tables on the run. Tested on LS2080ARDB with secure and non-secure ram scenarios. Signed-off-by: York Sun <york.sun@nxp.com> |
#
e61a7534 |
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24-Jun-2016 |
York Sun <york.sun@nxp.com> |
armv8: Move secure_ram variable out of generic global data Secure_ram variable was put in generic global data. But only ARMv8 uses this variable. Move it to ARM specific data structure. Signed-off-by: York Sun <york.sun@nxp.com> |
#
a10a31ec |
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18-Jun-2016 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of git://git.denx.de/u-boot-usb Signed-off-by: Tom Rini <trini@konsulko.com> Conflicts: arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
|
#
6fb522dc |
|
12-Jun-2016 |
Sriram Dash <sriram.dash@nxp.com> |
arm64: fsl-layerscape: add get_svr and IS_SVR_REV helper Adds get_svr and IS_SVR_REV helpers for ARMv8 platforms, similar to PPC and ARMv7. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> |
#
a758177f |
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07-Jun-2016 |
Yunhui Cui <yunhui.cui@nxp.com> |
armv8/ls2080a: configure PMU's PCTBENR to enable WDT The SP805-WDT module on LS2080A requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. The watchdog clock needs to be enabled first. Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
acb8f5e9 |
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21-Apr-2016 |
Alison Wang <b18965@freescale.com> |
armv8: fsl-layerscape: Remove unnecessary flushing dcache As the issue about the stack will get corrupted when switching between the early and final mmu tables is fixed by commit 70e21b064, the workaround to flush dcache is unnecessary and should be removed. Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
3c1d218a |
|
04-Apr-2016 |
York Sun <york.sun@nxp.com> |
armv8: LS2080A: Consolidate LS2080A and LS2085A LS2080A is the primary SoC, and LS2085A is a personality with AIOP and DPAA DDR. The RDB and QDS boards support both personality. By detecting the SVR at runtime, a single image per board can support both SoCs. It gives users flexibility to swtich SoC without the need to reprogram the board. Signed-off-by: York Sun <york.sun@nxp.com> CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
c05016ab |
|
21-Mar-2016 |
Alexander Graf <agraf@csgraf.de> |
arm64: Fix layerscape mmu setup With commit 7985cdf we converted all systems except for the Layerscape SoCs to the generic descriptor table based page table setup. On the Layerscape SoCs however, we just provide an empty table stub and do the setup ourselves. To reserve enough memory for the tables, we need to override the default counting mechanism which would end up with an empty table because we have no maps. Fixes: 7985cdf Reported-by: York Sun <york.sun@nxp.com> CC: Alison Wang <alison.wang@nxp.com> CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Alexander Graf <agraf@suse.de> Tested-by: York Sun <york.sun@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
7985cdf7 |
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03-Mar-2016 |
Alexander Graf <agraf@csgraf.de> |
arm64: Remove non-full-va map code By now the code to only have a single page table level with 64k page size and 42 bit address space is no longer used by any board in tree, so we can safely remove it. To clean up code, move the layerscape mmu code to the new defines, removing redundant field definitions. Signed-off-by: Alexander Graf <agraf@suse.de> |
#
c0492141 |
|
07-Dec-2015 |
York Sun <yorksun@freescale.com> |
armv8: fsl-layerscale: Rewrite reserving memory for MC and debug server MC and debug server are not board-specific. Move reserving memory to SoC file, using the new board_reserve_ram_top function. Reduce debug server memory by 2MB to make room for secure memory. In the system with MC and debug server, the top of u-boot memory is not the end of memory. PRAM is not used for this reservation. Signed-off-by: York Sun <yorksun@freescale.com> |
#
c107c0c0 |
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04-Dec-2015 |
York Sun <yorksun@freescale.com> |
armv8: fsl-layerscape: Make DDR non secure in MMU tables DDR has been set as secure in MMU tables. Non-secure master such as SDHC DMA cannot access data correctly. Mixing secure and non- secure MMU entries requirs the MMU tables themselves in secure memory. This patch moves MMU tables into a secure DDR area. Early MMU tables are changed to set DDR as non-secure. A new table is added into final MMU tables so secure memory can have 2MB granuality. gd->secure_ram tracks the location of this secure memory. For ARMv8 SoCs, the RAM base is not zero and RAM is divided into several banks. gd->secure_ram needs to be maintained before using. This maintenance is board-specific, depending on the SoC and memory bank of the secure memory falls into. Signed-off-by: York Sun <yorksun@freescale.com> |
#
b4017364 |
|
04-Nov-2015 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
armv8: ls2085a: Add workaround of errata A009635 If the core runs at higher than x3 speed of the platform, there is possiblity about sev instruction to getting missed by other cores. This is because of SoC Run Control block may not able to sample the EVENTI(Sev) signals. Configure Run Control and EPU to periodically send out EVENTI signals to wake up A57 cores. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
d764129d |
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04-Nov-2015 |
Alison Wang <b18965@freescale.com> |
armv8/layerscape: Update MMU table with execute-never bits For most device addresses excution shouldn't be allowed. Revise the MMU table to enforce execute-never bits. OCRAM, DDR and IFC are allowed for excution. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Alison Wang <alison.wang@freescale.com> Reported-by: Zhichun Hua <zhichun.hua@freescale.com> |
#
44937214 |
|
09-Nov-2015 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
armv8: LS2080A: Rename LS2085A to reflect LS2080A LS2080A is a prime personality of Freescale’s LS2085A. It is a non-AIOP personality without support of DP-DDR, L2 switch, 1588, PCIe endpoint etc. So renaming existing LS2085A code base to reflect LS2080A (Prime personality) Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> [York Sun: Dropped #ifdef in cpu.c for cpu_type_list] Reviewed-by: York Sun <yorksun@freescale.com> |
#
e8297341 |
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26-Oct-2015 |
Shaohui Xie <Shaohui.Xie@freescale.com> |
armv8/ls1043a: Add Fman support Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
8281c58f |
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26-Oct-2015 |
Mingkai Hu <Mingkai.Hu@freescale.com> |
armv8/fsl_lsch2: Add fsl_lsch2 SoC Freescale LayerScape with Chassis Generation 2 is a set of SoCs with ARMv8 cores and 2rd generation of Chassis. Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
9f3183d2 |
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26-Oct-2015 |
Mingkai Hu <Mingkai.Hu@freescale.com> |
armv8/fsl_lsch3: Change arch to fsl-layerscape There are two LS series processors are built on ARMv8 Layersacpe architecture currently, LS2085A and LS1043A. They are based on ARMv8 core although use different chassis, so create fsl-layerscape to refactor the common code for the LS series processors which also paves the way for adding LS1043A platform. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
6eb32a03 |
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23-Apr-2020 |
Madalin Bucur <madalin.bucur@oss.nxp.com> |
driver: net: fm: add DM ETH support Probe the FMan MACs based on the device tree while retaining the legacy code/functionality. One notable change introduced here is that, for DM_ETH, the name of the interfaces is corrected to the fmX-macY format, that avoids the referral to the MAC block names which were incorrect for FMan v3 devices (i.e. DTSEC, TGEC) and had weird formatting (i.e. FM1@DTSEC6, FM1@TGEC1). The legacy code is left unchanged in this respect. Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
6ebd4883 |
|
27-Apr-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
fsl-layerscape: Add RESV_RAM check in resv_ram addr The initialization of gd->arch.resv_ram pointer should depend on if the RESV_RAM config is enabled. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Wasim Khan <wasim.khan@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
0d9d557d |
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10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
db41d65a |
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28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move hang() to the same header as panic() At present panic() is in the vsprintf.h header file. That does not seem like an obvious choice for hang(), even though it relates to panic(). So let's put hang() in its own header. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Migrate a few more files] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
9b4a205f |
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28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move RAM-sizing functions to init.h These functions relate to memory init so move them into the init header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
3499dd03 |
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27-Nov-2019 |
Alex Marginean <alexandru.marginean@nxp.com> |
ls1028a: Configure stream IDs for integrated PCI and fix up Linux DT Hardware comes out of reset with implicit values, but these are outside the accepted range for Layerscape gen 3 chassis spec used on LS1028A. Allocate different IDs and fix up Linux DT to use them. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
b5981474 |
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14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some CPU functions out of common.h These functions belong in cpu_func.h since they do not use driver model. Move them over. Don't bother adding comments since these functions should be deleted. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
68a6aa85 |
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14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move mii_init() function out of common.h This function belongs in mii.h so move it over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
2189d5f1 |
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14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
Move strtomhz() to vsprintf.h At present this function sits in its own file but it does not really justify it. There are similar string functions in vsprintf.h, so move it there. Also add the missing function comment. Use the vsprintf.h include file explicitly where needed. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
812ff53c |
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30-Oct-2019 |
Pankaj Bansal <pankaj.bansal@nxp.com> |
fsl-layerscape: fix warning if no hwconfig is defined While getting the 'subarg' of 'hwconfig' env variable in config_core_prefetch(), if no hwconfig variable is defined, below warning is received: WARNING: Calling __hwconfig without a buffer and before environment is ready Fix this by checking 'hwconfig' env variable. If not found return without further processing. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Tested-by: Michael Walle <michael@walle.cc> |
#
28f9393b |
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17-Oct-2019 |
Mathew McBride <matt@traverse.com.au> |
fsl-layerscape: do not use layerscape EFI reset if PSCI used If the secure world reset handlers are used (via CONFIG_PSCI_RESET), then do not use the layerscape-specific implementation. Signed-off-by: Mathew McBride <matt@traverse.com.au> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
6ed69523 |
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18-Sep-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add more personalities support Add LS1027A, LS1018A and LS1017A personalities support to LS1028A SoC family. LS1028A is the prime personality of LS1028A SoC family. LS1027A is a lower funtionality version of QorIQ LS1028A which does not support the multimedia subsystems, such as LCD controller, GPU, and eDP PHY. The QorIQ LS1018A and LS1017A SoCs are single 64-bit Arm A72 core, low power versions of the QorIQ LS1028A and LS1027A SoCs respectively. Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
0490cab5 |
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08-Aug-2019 |
Thomas Schaefer <thomas.schaefer@kontron.com> |
armv8: ls1028a: configure PMU's PCTBENR to enable WDT The SP805-WDT module on LS1028A requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. The watchdog clock needs to be enabled first. Signed-off-by: Thomas Schaefer <thomas.schaefer@kontron.com> Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
f3998fdc |
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02-Aug-2019 |
Simon Glass <sjg@chromium.org> |
env: Rename environment.h to env_internal.h This file contains lots of internal details about the environment. Most code can include env.h instead, calling the functions there as needed. Rename this file and add a comment at the top to indicate its internal nature. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> [trini: Fixup apalis-tk1.c] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
3a7d5571 |
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01-Aug-2019 |
Simon Glass <sjg@chromium.org> |
env: Move env_get_f() to env.h Move this function over to the new header file. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
d9532e80 |
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23-Apr-2019 |
Udit Agarwal <udit.agarwal@nxp.com> |
armv8: fsl-layerscape: Set env_loc to ENVL_NOWHERE with CONFIG_ENV_IS_NOWHERE. ENVL_NOWHERE is dependent on CONFIG_ENV_IS_NOWHERE and not on CONFIG_CHAIN_OF_TRUST so return ENVL_NOWHERE when CONFIG_ENV_IS_NOWHERE is enabled Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
d4ad111d |
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10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
059d9422 |
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08-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: lx2160a: add MMU table entries for PCIe The lx2160a have up to 6 PCIe controllers and have different address and size of PCIe region. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
8348e798 |
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08-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: layerscape: use PCIe address macro for precompile PCIe MMU entry Change to use PCIe address macro to determine if precompile the PCIe MMU table entry. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
10015025 |
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03-May-2019 |
Trevor Woerner <trevor@toganlabs.com> |
CONFIG_SPL_SYS_[DI]CACHE_OFF: add While converting CONFIG_SYS_[DI]CACHE_OFF to Kconfig, there are instances where these configuration items are conditional on SPL. This commit adds SPL variants of these configuration items, uses CONFIG_IS_ENABLED(), and updates the configurations as required. Acked-by: Alexey Brodkin <abrodkin@synopsys.com> Signed-off-by: Trevor Woerner <trevor@toganlabs.com> [trini: Make the default depend on the setting for full U-Boot, update more zynq hardware] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
2e53759d |
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29-Oct-2018 |
Pankaj Bansal <pankaj.bansal@nxp.com> |
armv8: fsl-layerscape: reorder rgmii dpmacs' enablement some dpmacs in armv8a based freescale layerscape SOCs can be configured via both serdes(sgmii, xfi, xlaui etc) bits and via EC*_PMUX(rgmii) bits in RCW. e.g. dpmac 17 and 18 in LX2160A can be configured as SGMII from serdes bits and as RGMII via EC1_PMUX/EC2_PMUX bits Now if a dpmac is enabled by serdes bits then it takes precedence over EC*_PMUX bits. i.e. in LX2160A if we select serdes protocol that configures dpmac17 as SGMII and set the EC1_PMUX as RGMII, then the dpmac is SGMII and not RGMII. Therefore, move the fsl_rgmii_init after fsl_serdes_init. in fsl_rgmii_init function of SOC, we will check if the dpmac is enabled or not? if it is (fsl_serdes_init has already enabled the dpmac), then don't enable it. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
ec88ff80 |
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19-Dec-2018 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1043a: add SVR definitions for 23x23 package silicon LS1043A/LS1023A 23x23 package silicon has different SVR:VAR_PER. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
d23da2ae |
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26-Dec-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: fixes for TFABOOT framework Fixes for TFABOOT framework - update eMMC bootsrc to SD_MMC - Increase buffer size for mcinitcmd from 256 to 512 - Fix mcinitcmd and bootcmd for Secure Boot Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
4909b89e |
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29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
d6fdec21 |
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29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8:fsl-layerscape: Add support for Chassis 3.2 NXP layerscape architecture Chassis 3.2 builds upon chassis3 architecture with changes like DDR Memory map change, removal of IFC and support of upto 8 I2C controller. Patch add README.lsch3_2 and the above changes under macro CONFIG_NXP_LSCH3_2. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
56db948b |
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05-Nov-2018 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: Update parsing boot source Workaround of erratum A010539 clears the RCW source field in PORSR1 register, causing failure of detecting boot source using this method. Use SMC call if U-Boot runs at EL2. If SMC is not implemented or running at EL3, continue to read PORSR1 and presume QSPI as boot source if erratum workaround A010539 is enabled and RCW source is cleared. Signed-off-by: York Sun <york.sun@nxp.com> |
#
681d489e |
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05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: layerscape: add SMC calls for DDR size and bank info Adds SMC calls for getting DDR size and bank info for TFABOOT. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
2141d250 |
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05-Nov-2018 |
Pankit Garg <pankit.garg@nxp.com> |
armv8: fsl-layerscape: bootcmd identification for TFABOOT Adds bootcmd identificaton on basis on boot source, valid in TFABOOT configuration. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> [YS: remove unnecessary braces] Reviewed-by: York Sun <york.sun@nxp.com> |
#
4c417384 |
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05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com> |
#
535d76a1 |
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05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: layerscape: Add TFABOOT support Adds TFABOOT support config option and add generic code to enable execution from DDR. Signed-off-by: York Sun <york.sun@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> |
#
e3506480 |
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05-Nov-2018 |
Pankit Garg <pankit.garg@nxp.com> |
armv8: fsl-layerscape: change tlb base from OCRAM to DDR in EL < 3 Change tlb base address from OCRAM to DDR when exception level is less than 3. Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
d171c707 |
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05-Nov-2018 |
York Sun <york.sun@nxp.com> |
move data structure out of cpu.h Move static definitions to cpu.c file, as it doesn't allow the cpu.h file to be included in multiple c files. Signed-off-by: York Sun <york.sun@nxp.com> |
#
9b5e6396 |
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30-Aug-2018 |
Stephen Warren <swarren@nvidia.com> |
efi_loader: simplify ifdefs Use CONFIG_IS_ENABLED(EFI_LOADER) to avoid explicitly checking CONFIG_SPL too. This simplifies the conditional. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Alexander Graf <agraf@suse.de> |
#
9cce5663 |
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16-Jul-2018 |
Joe Hershberger <joe.hershberger@ni.com> |
arm: Prevent redefinition error in fsl-layerscape The include/phy.h will start including dm.h, which pulls in linux/compat.h after the attempted redefinition in arch/arm/include/asm/armv8/mmu.h, so move this include to allow redefinition. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> |
#
83d290c5 |
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06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
482fc90c |
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06-Feb-2018 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
efi_loader: add missing EFI_RESET_PLATFORM_SPECIFIC EFI_RESET_PLATFORM_SPECIFIC is one of the values that can be used for the EFI service ResetSystem. The missing definition is added. The value has to handled in efi_reset_system(). Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Alexander Graf <agraf@suse.de> |
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22c793e6 |
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03-Mar-2018 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
efi_loader: exit status for efi_reset_system_init efi_reset_system_init provides the architecture or board specific initialization of the EFI subsystem. Errors should be caught and signalled by a return code. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Alexander Graf <agraf@suse.de> |
#
958b2ed5 |
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09-Jan-2018 |
Zhang Ying-22455 <ying.zhang22455@nxp.com> |
armv8/ls1088a: configure PMU's PCTBENR to enable WDT The SP805-WDT module on LS1088A requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. The watchdog clock needs to be enabled first. Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
44262327 |
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15-Dec-2017 |
Ahmed Mansour <ahmed.mansour@nxp.com> |
drivers/misc: Share qbman init between archs This patch adds changes necessary to move functionality present in PowerPC folders with ARM architectures that have DPAA1 QBMan hardware - Create new board/freescale/common/fsl_portals.c to house shared device tree fixups for DPAA1 devices with ARM and PowerPC cores - Add new header file to top includes directory to allow files in both architectures to grab the function prototypes - Port inhibit_portals() from PowerPC to ARM. This function is used in setup to disable interrupts on all QMan and BMan portals. It is needed because the interrupts are enabled by default for all portals including unused/uninitialised portals. When the kernel attempts to go to deep sleep the unused portals prevent it from doing so Signed-off-by: Ahmed Mansour <ahmed.mansour@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
a8f33034 |
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03-Dec-2017 |
Wenbin song <wenbin.song@nxp.com> |
armv8: ls1043a/ls2080a: check SoC by device ID Check LS1043A/LS2080a by device ID without using personality ID to determine revision number. This check applies to all various personalities of the same SoC family. Signed-off-by: Wenbin Song <wenbin.song@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
2db53cfe |
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09-Nov-2017 |
Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
armv8: fsl-layerscape: Add support of disabling core prefetch Instruction prefetch feature is by default enabled during core release. This patch add support of disabling instruction prefetch by setting core mask in PPA. Here each core mask bit represents a core and prefetch is disabled at the time of core release. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
7eb40f0f |
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28-Sep-2017 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: Avoid running dram_init_banksize again gd->ram_size is reduced in this function to reserve secure memory. Avoid running this function again to further reduce memory size. This fixes issue for SPL boot with PPA image loaded in which case secure memory is incorrectly allocated due to repeated calling. Signed-off-by: York Sun <york.sun@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
710d0cd7 |
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03-Oct-2017 |
Sumit Garg <sumit.garg@nxp.com> |
armv8: fsl-layerscape: Allocate Secure memory from first ddr region This change is required due to trusted OS (OP-TEE) not being position independent code, it requires compile time fixed base address. To take care of this it is assumed that all layerscape armv8 platforms has minimum 2G ddr in first region. So we can have fixed address space (66 MB -> (2MB for PPA + 64MB for trusted OS)) allocated from top of first 2G ddr region and compile trusted OS with this fixed base address. But one exception here is ls1012 where we have only 1G (rdb) or 512M (frdm) ddr memory. For those we can have different fixed compile time base addresses for trusted OS. Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
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e9303a41 |
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07-Sep-2017 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: Fix MC reserved memory calculation In case high region memory doesn't have enough space for Management Complex (MC), the return value should indicate a failure so the caller can handle it accordingly. Signed-off-by: York Sun <york.sun@nxp.com> Reported-by: Ebony Zhu <ebony.zhu@nxp.com> |
#
17d066fc |
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31-Aug-2017 |
Ashish Kumar <Ashish.Kumar@nxp.com> |
armv8: fsl-layerscape: Support to add RGMII for ls1088aqds This patch adds support for RGMII protocol NXP's LDPAA2 support RGMII protocol. LS1088A is the first Soc supporting both RGMII and SGMII. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Amrita Kumari <amrita.kumari@nxp.com> Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
63b2316c |
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10-Aug-2017 |
Ashish Kumar <Ashish.Kumar@nxp.com> |
fsl-layerscape: Consolidate registers space defination for CCI-400 bus CoreLink Cache Coherent Interconnect (CCI) provides full cache coherency between two clusters of multi-core CPUs and I/O coherency for devices and I/O masters. This patch add new config option SYS_FSL_HAS_CCI400 and moves existing register space definaton of CCI-400 bus to fsl_immap to be shared. CONFIG_SYS_CCI400_ADDR is replaced with SYS_CCI400_OFFSET in Kconfig. Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> [YS: revised commit message, squashed patches for armv8 and armv7] Reviewed-by: York Sun <york.sun@nxp.com> |
#
6e2941d7 |
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17-May-2017 |
Simon Glass <sjg@chromium.org> |
common: freescale: Move arch-specific declarations The declarations should not be in common.h. Move them to the arch-specific headers. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Fixup thinko defined(FSL_LSCH3) -> defined(CONFIG_FSL_LSCH3)] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
399e2bb6 |
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15-May-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Make U-Boot EL2 safe When U-Boot boots from EL2, skip some lowlevel init code requiring EL3, including CCI-400/CCN-504, trust zone, GIC, etc. These initialization tasks are carried out before U-Boot runs. This applies to the RAM version image used for SPL boot if PPA is loaded first. Signed-off-by: York Sun <york.sun@nxp.com> |
#
1f55a938 |
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05-May-2017 |
Santan Kumar <santan.kumar@nxp.com> |
armv8: ls2080aqds: Add support for SD boot Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
e809e747 |
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27-Apr-2017 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: fsl-layerscape: Add NXP LS2081A, LS2041A SoC support The QorIQ LS2081A SoC has eight 64-bit ARM v8 Cortex A72 cores and is built on layerscape architecture. It is 40-pin derivative of LS2084A (non-AIOP personality of LS2088A). So feature-wise it is same as LS2084A. LS2041A is a 4-core personality of LS2081A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
026f30ec |
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18-Apr-2017 |
Yuantian Tang <andy.tang@nxp.com> |
arm: psci: make psci usable on single core socs PSCI can be used on both multiple and single core socs. Current implementation only allows PSCI to work on multiple core socs. This patch removes this restriction so that PSCI can work on single core socs as well. Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
4a3ab193 |
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27-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: ls2080a: Drop macro CONFIG_LS2080A Use CONFIG_ARCH_LS2080A instead. Signed-off-by: York Sun <york.sun@nxp.com> |
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3eace37e |
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06-Apr-2017 |
Simon Glass <sjg@chromium.org> |
arm: freescale: Rename initdram() to fsl_initdram() This function name shadows a global name but is in fact different. This is very confusing. Rename it to help with the following refactoring. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
76b00aca |
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31-Mar-2017 |
Simon Glass <sjg@chromium.org> |
board_f: Drop setup_dram_config() wrapper By making dram_init_banksize() return an error code we can drop the wrapper. Adjust this and clean up all implementations. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
088454cd |
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31-Mar-2017 |
Simon Glass <sjg@chromium.org> |
board_f: Drop return value from initdram() At present we cannot use this function as an init sequence call without a wrapper, since it returns the RAM size. Adjust it to set the RAM size in global_data instead, and return 0 on success. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> |
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52c41180 |
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31-Mar-2017 |
Simon Glass <sjg@chromium.org> |
board_f: Drop board_type parameter from initdram() It looks like only cm5200 and tqm8xx use this feature, so we don't really need it in generic code. Drop it and have the users access gd->board_type directly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
3d8553f0 |
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02-Mar-2017 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
pci: layerscape: add LS2088A series SoC pcie support The LS2088A series SoCs has different physical memory map address and CCSR registers address against LS2080A series SoCs. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
eea1cb77 |
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13-Feb-2017 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8/fsl-layerscape: Update erratum A009635 implementation Erratum A009635 is valid only for LS2080A SoC and its personality. Add SoC svr check. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
4961eafc |
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06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Update early MMU for DDR after initialization In early MMU table, DDR has to be mapped as device memory to avoid speculative access. After DDR is initialized, it needs to be updated to normal memory to allow code execution. To simplify the code, dram_init() is moved into a common file as a weak function. Signed-off-by: York Sun <york.sun@nxp.com> |
#
a045a0c3 |
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06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Fix the sequence of changing MMU table This patch follows the break-before-make process when making changes to MMU table. MMU is disabled before changing TTBR to avoid any potential race condition. Signed-off-by: York Sun <york.sun@nxp.com> |
#
24f55496 |
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06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Update MMU mapping with actual DDR size Update mapping with actual DDR size. Non-existing memory should not be mapped as "normal" memory to avoid speculative access. Signed-off-by: York Sun <york.sun@nxp.com> |
#
36cc0de0 |
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06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Rewrite memory reservation For ARMv8 Layerscape SoCs, secure memory and MC memorey are reserved at the end of DDR. DDR is spit into two or three banks. This patch reverts commit aabd7ddb and simplifies the calculation of reserved memory, and moves the code into common SoC file. Secure memory is carved out first. DDR bank size is reduced. Reserved memory is then allocated on the top of available memory. U-Boot still has access to reserved memory as data transferring is needed. Device tree is fixed with reduced memory size to hide the reserved memory from OS. The same region is reserved for efi_loader. Signed-off-by: York Sun <york.sun@nxp.com> |
#
daa92644 |
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16-Jan-2017 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
ARMv8/sec_firmware: relocated and renamed the config FSL_PPA_ARMV8_PSCI Moved the config FSL_PPA_ARMV8_PSCI from fsl-layerscape's Kconfig to Kconfig under armv8 and renamed it to SEC_FIRMWARE_ARMV8_PSCI. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
904110c7 |
|
10-Jan-2017 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8/fsl-lsch2: refactor the clock system initialization Up to now, there are 3 kind of SoCs under Layerscape Chassis 2, like LS1043A, LS1046A and LS1012A. But the clocks tree has a lot of differences, for instance, the IP modules have different dividers to derive its clock from Platform PLL. And the core cluster PLL and platform PLL maybe have different reference clocks, such as LS1012A. Another problem is which clock/PLL should be described by sys_info->freq_systembus, it is confused in Layerscape Chissis 2. This patch is to bind the sys_info->freq_systembus to the Platform PLL, and handle the different divider of IP modules separately between different SoCs, and separate reference clocks of core cluster PLL and platform PLL. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
2d16a1a6 |
|
07-Dec-2016 |
macro.wave.z@gmail.com <macro.wave.z@gmail.com> |
ARMv8: LS1043A: change macro CONFIG_ARMV8_PSCI definition NXP/Freescale uses macro CONFIG_ARMV8_PSCI to enable their private PSCI implementation in PPA firmware, but this macro naming too generic, so this patch replaces it with a specic one CONFIG_FSL_PPA_ARMV8_PSCI. And this macro CONFIG_ARMV8_PSCI will be used for a generic PSCI for ARMv8 which will be added in following patchs. Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
02fb2761 |
|
20-Nov-2016 |
Shengzhou Liu <Shengzhou.Liu@nxp.com> |
fsl/ddr: Add erratum_a009942_check_cpo and clean related erratum - add additional function erratum_a009942_check_cpo to check if the board needs tuning CPO calibration for optimal setting. - move ERRATUM_A009942(with revision to check cpo_sample option) from fsl_ddr_gen4.c to ctrl_regs.c for reuse on all DDR4/DDR3 parts. - move ERRATUM_A008378 from fsl_ddr_gen4.c to ctrl_regs.c - remove obsolete ERRATUM_A004934 which is replaced with ERRATUM_A009942. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> [YS: Replaced CONFIG_QEMU_E500 with CONFIG_ARCH_QEMU_E500] Reviewed-by: York Sun <york.sun@nxp.com> |
#
e87c673c |
|
16-Nov-2016 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8/fsl-lsch3: Update code to release secondary cores NXP ARMv8 SoC LS2080A release all secondary cores in one-go. But other new SoCs like LS2088A, LS1088A release secondary cores one by one. Update code to release secondary cores based on SoC SVR Add code to release cores one by one for non LS2080A SoCs Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> [YS: remove "inline" from declaration of initiator_type] Reviewed-by: York Sun <york.sun@nxp.com> |
#
f6b96ff6 |
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16-Nov-2016 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Use SVR based timer base address detection Timer controller base address has been changed from LS2080A SoC (and its personalities) to new SoCs like LS2088A, LS1088A. Use SVR based timer base address detection to avoid compile time #ifdef. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
f6a70b3a |
|
16-Nov-2016 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add generic get_svr() in assembly Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
78d57842 |
|
16-Nov-2016 |
Alexander Graf <agraf@csgraf.de> |
armv8: fsl-layerscape: Add support for efi_loader RTS reset When implementing efi loader support, we can expose runtime services for payloads. One such service is CPU reset. This patch implements RTS CPU reset support for layerscape systems. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: York Sun <york.sun@nxp.com> |
#
ef9a5fd8 |
|
13-Sep-2016 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: Fix "cpu status" command The core position is not continuous for some SoCs. For example, valid cores may present at position 0, 1, 4, 5, 8, 9, etc. Some registers (including boot release register) only count existing cores. Current implementation of cpu_mask() complies with the continuous numbering. However, command "cpu status" queries the spin table with actual core position. Add functions to calculate core position from core number, to correctly calculate offsets. Tested on LS2080ARDB and LS1043ARDB. Signed-off-by: York Sun <york.sun@nxp.com> |
#
5d1a7a9d |
|
13-Sep-2016 |
Wenbin Song <wenbin.song@nxp.com> |
armv8/fsl-layerscape: print SoC revsion number The exact SoC revsion number can be recognized from U-Boot log. Signed-off-by: Wenbin Song <wenbin.song@nxp.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
cbe7706a |
|
26-Sep-2016 |
Tom Rini <trini@konsulko.com> |
Merge git://git.denx.de/u-boot-fsl-qoriq trini: Drop local memset() from examples/standalone/mem_to_mem_idma2intr.c Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
1221ce45 |
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20-Sep-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
treewide: replace #include <asm/errno.h> with <linux/errno.h> Now, arch/${ARCH}/include/asm/errno.h and include/linux/errno.h have the same content. (both just wrap <asm-generic/errno.h>) Replace all include directives for <asm/errno.h> with <linux/errno.h>. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> [trini: Fixup include/clk.] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
b63a9506 |
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03-Aug-2016 |
York Sun <york.sun@nxp.com> |
armv8: ls2080a: Remove debug server support Debug server feature has been dropped from roadmap. Signed-off-by: York Sun <york.sun@nxp.com> |
#
ed7a3943 |
|
22-Jul-2016 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: mmu: Fix enabling MMU MMU bit in SCTLR needs to be set explicitly after tables are created. It isn't an issue for EL3 becuase this bit is already set by early MMU setup. But for other exception levels this bit was not set. Signed-off-by: York Sun <york.sun@nxp.com> |
#
79119a4d |
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05-Jul-2016 |
Alison Wang <b18965@freescale.com> |
armv8: fsl-layerscape: Add A72 core detection Add support to detect Cortex-A72 core for printing it out. The Initiator Version of A72 core should be 0x4. Signed-off-by: Alison Wang <alison.wang@nxp.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
032d5bb4 |
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28-Jun-2016 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
ARMv8/Layerscape: switch SMP method accordingly If the PSCI and PPA is ready, skip the fixup for spin-table and waking secondary cores. Otherwise, change SMP method to spin-table, and the device node of PSCI will be removed. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
85cdf38e |
|
28-Jun-2016 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: fsl-layerscape: add i/d-cache enable function to enable_caches This function assume that the d-cache and MMU has been enabled earlier, so it just created MMU table in main memory. But the assumption is not always correct, for example, the early setup is done in EL3, while enable_caches() is called when the PE has turned into another EL. Define the function mmu_setup() for fsl-layerscape to cover the weak one. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
5ad5823d |
|
24-Jun-2016 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Convert to use common MMU framework Drop platform code to create static MMU tables. Use common framework to create MMU tables on the run. Tested on LS2080ARDB with secure and non-secure ram scenarios. Signed-off-by: York Sun <york.sun@nxp.com> |
#
e61a7534 |
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24-Jun-2016 |
York Sun <york.sun@nxp.com> |
armv8: Move secure_ram variable out of generic global data Secure_ram variable was put in generic global data. But only ARMv8 uses this variable. Move it to ARM specific data structure. Signed-off-by: York Sun <york.sun@nxp.com> |
#
a10a31ec |
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18-Jun-2016 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of git://git.denx.de/u-boot-usb Signed-off-by: Tom Rini <trini@konsulko.com> Conflicts: arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
|
#
6fb522dc |
|
12-Jun-2016 |
Sriram Dash <sriram.dash@nxp.com> |
arm64: fsl-layerscape: add get_svr and IS_SVR_REV helper Adds get_svr and IS_SVR_REV helpers for ARMv8 platforms, similar to PPC and ARMv7. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> |
#
a758177f |
|
07-Jun-2016 |
Yunhui Cui <yunhui.cui@nxp.com> |
armv8/ls2080a: configure PMU's PCTBENR to enable WDT The SP805-WDT module on LS2080A requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. The watchdog clock needs to be enabled first. Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
acb8f5e9 |
|
21-Apr-2016 |
Alison Wang <b18965@freescale.com> |
armv8: fsl-layerscape: Remove unnecessary flushing dcache As the issue about the stack will get corrupted when switching between the early and final mmu tables is fixed by commit 70e21b064, the workaround to flush dcache is unnecessary and should be removed. Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
3c1d218a |
|
04-Apr-2016 |
York Sun <york.sun@nxp.com> |
armv8: LS2080A: Consolidate LS2080A and LS2085A LS2080A is the primary SoC, and LS2085A is a personality with AIOP and DPAA DDR. The RDB and QDS boards support both personality. By detecting the SVR at runtime, a single image per board can support both SoCs. It gives users flexibility to swtich SoC without the need to reprogram the board. Signed-off-by: York Sun <york.sun@nxp.com> CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
c05016ab |
|
21-Mar-2016 |
Alexander Graf <agraf@csgraf.de> |
arm64: Fix layerscape mmu setup With commit 7985cdf we converted all systems except for the Layerscape SoCs to the generic descriptor table based page table setup. On the Layerscape SoCs however, we just provide an empty table stub and do the setup ourselves. To reserve enough memory for the tables, we need to override the default counting mechanism which would end up with an empty table because we have no maps. Fixes: 7985cdf Reported-by: York Sun <york.sun@nxp.com> CC: Alison Wang <alison.wang@nxp.com> CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Alexander Graf <agraf@suse.de> Tested-by: York Sun <york.sun@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
7985cdf7 |
|
03-Mar-2016 |
Alexander Graf <agraf@csgraf.de> |
arm64: Remove non-full-va map code By now the code to only have a single page table level with 64k page size and 42 bit address space is no longer used by any board in tree, so we can safely remove it. To clean up code, move the layerscape mmu code to the new defines, removing redundant field definitions. Signed-off-by: Alexander Graf <agraf@suse.de> |
#
c0492141 |
|
07-Dec-2015 |
York Sun <yorksun@freescale.com> |
armv8: fsl-layerscale: Rewrite reserving memory for MC and debug server MC and debug server are not board-specific. Move reserving memory to SoC file, using the new board_reserve_ram_top function. Reduce debug server memory by 2MB to make room for secure memory. In the system with MC and debug server, the top of u-boot memory is not the end of memory. PRAM is not used for this reservation. Signed-off-by: York Sun <yorksun@freescale.com> |
#
c107c0c0 |
|
04-Dec-2015 |
York Sun <yorksun@freescale.com> |
armv8: fsl-layerscape: Make DDR non secure in MMU tables DDR has been set as secure in MMU tables. Non-secure master such as SDHC DMA cannot access data correctly. Mixing secure and non- secure MMU entries requirs the MMU tables themselves in secure memory. This patch moves MMU tables into a secure DDR area. Early MMU tables are changed to set DDR as non-secure. A new table is added into final MMU tables so secure memory can have 2MB granuality. gd->secure_ram tracks the location of this secure memory. For ARMv8 SoCs, the RAM base is not zero and RAM is divided into several banks. gd->secure_ram needs to be maintained before using. This maintenance is board-specific, depending on the SoC and memory bank of the secure memory falls into. Signed-off-by: York Sun <yorksun@freescale.com> |
#
b4017364 |
|
04-Nov-2015 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
armv8: ls2085a: Add workaround of errata A009635 If the core runs at higher than x3 speed of the platform, there is possiblity about sev instruction to getting missed by other cores. This is because of SoC Run Control block may not able to sample the EVENTI(Sev) signals. Configure Run Control and EPU to periodically send out EVENTI signals to wake up A57 cores. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
d764129d |
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04-Nov-2015 |
Alison Wang <b18965@freescale.com> |
armv8/layerscape: Update MMU table with execute-never bits For most device addresses excution shouldn't be allowed. Revise the MMU table to enforce execute-never bits. OCRAM, DDR and IFC are allowed for excution. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Alison Wang <alison.wang@freescale.com> Reported-by: Zhichun Hua <zhichun.hua@freescale.com> |
#
44937214 |
|
09-Nov-2015 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
armv8: LS2080A: Rename LS2085A to reflect LS2080A LS2080A is a prime personality of Freescale’s LS2085A. It is a non-AIOP personality without support of DP-DDR, L2 switch, 1588, PCIe endpoint etc. So renaming existing LS2085A code base to reflect LS2080A (Prime personality) Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> [York Sun: Dropped #ifdef in cpu.c for cpu_type_list] Reviewed-by: York Sun <yorksun@freescale.com> |
#
e8297341 |
|
26-Oct-2015 |
Shaohui Xie <Shaohui.Xie@freescale.com> |
armv8/ls1043a: Add Fman support Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
8281c58f |
|
26-Oct-2015 |
Mingkai Hu <Mingkai.Hu@freescale.com> |
armv8/fsl_lsch2: Add fsl_lsch2 SoC Freescale LayerScape with Chassis Generation 2 is a set of SoCs with ARMv8 cores and 2rd generation of Chassis. Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
9f3183d2 |
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26-Oct-2015 |
Mingkai Hu <Mingkai.Hu@freescale.com> |
armv8/fsl_lsch3: Change arch to fsl-layerscape There are two LS series processors are built on ARMv8 Layersacpe architecture currently, LS2085A and LS1043A. They are based on ARMv8 core although use different chassis, so create fsl-layerscape to refactor the common code for the LS series processors which also paves the way for adding LS1043A platform. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
db41d65a |
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28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move hang() to the same header as panic() At present panic() is in the vsprintf.h header file. That does not seem like an obvious choice for hang(), even though it relates to panic(). So let's put hang() in its own header. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Migrate a few more files] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
9b4a205f |
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28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move RAM-sizing functions to init.h These functions relate to memory init so move them into the init header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
3499dd03 |
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27-Nov-2019 |
Alex Marginean <alexandru.marginean@nxp.com> |
ls1028a: Configure stream IDs for integrated PCI and fix up Linux DT Hardware comes out of reset with implicit values, but these are outside the accepted range for Layerscape gen 3 chassis spec used on LS1028A. Allocate different IDs and fix up Linux DT to use them. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
b5981474 |
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14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some CPU functions out of common.h These functions belong in cpu_func.h since they do not use driver model. Move them over. Don't bother adding comments since these functions should be deleted. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
68a6aa85 |
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14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move mii_init() function out of common.h This function belongs in mii.h so move it over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
2189d5f1 |
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14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
Move strtomhz() to vsprintf.h At present this function sits in its own file but it does not really justify it. There are similar string functions in vsprintf.h, so move it there. Also add the missing function comment. Use the vsprintf.h include file explicitly where needed. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
812ff53c |
|
30-Oct-2019 |
Pankaj Bansal <pankaj.bansal@nxp.com> |
fsl-layerscape: fix warning if no hwconfig is defined While getting the 'subarg' of 'hwconfig' env variable in config_core_prefetch(), if no hwconfig variable is defined, below warning is received: WARNING: Calling __hwconfig without a buffer and before environment is ready Fix this by checking 'hwconfig' env variable. If not found return without further processing. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Tested-by: Michael Walle <michael@walle.cc> |
#
28f9393b |
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17-Oct-2019 |
Mathew McBride <matt@traverse.com.au> |
fsl-layerscape: do not use layerscape EFI reset if PSCI used If the secure world reset handlers are used (via CONFIG_PSCI_RESET), then do not use the layerscape-specific implementation. Signed-off-by: Mathew McBride <matt@traverse.com.au> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
6ed69523 |
|
18-Sep-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add more personalities support Add LS1027A, LS1018A and LS1017A personalities support to LS1028A SoC family. LS1028A is the prime personality of LS1028A SoC family. LS1027A is a lower funtionality version of QorIQ LS1028A which does not support the multimedia subsystems, such as LCD controller, GPU, and eDP PHY. The QorIQ LS1018A and LS1017A SoCs are single 64-bit Arm A72 core, low power versions of the QorIQ LS1028A and LS1027A SoCs respectively. Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
0490cab5 |
|
08-Aug-2019 |
Thomas Schaefer <thomas.schaefer@kontron.com> |
armv8: ls1028a: configure PMU's PCTBENR to enable WDT The SP805-WDT module on LS1028A requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. The watchdog clock needs to be enabled first. Signed-off-by: Thomas Schaefer <thomas.schaefer@kontron.com> Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
f3998fdc |
|
02-Aug-2019 |
Simon Glass <sjg@chromium.org> |
env: Rename environment.h to env_internal.h This file contains lots of internal details about the environment. Most code can include env.h instead, calling the functions there as needed. Rename this file and add a comment at the top to indicate its internal nature. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> [trini: Fixup apalis-tk1.c] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
3a7d5571 |
|
01-Aug-2019 |
Simon Glass <sjg@chromium.org> |
env: Move env_get_f() to env.h Move this function over to the new header file. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
d9532e80 |
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23-Apr-2019 |
Udit Agarwal <udit.agarwal@nxp.com> |
armv8: fsl-layerscape: Set env_loc to ENVL_NOWHERE with CONFIG_ENV_IS_NOWHERE. ENVL_NOWHERE is dependent on CONFIG_ENV_IS_NOWHERE and not on CONFIG_CHAIN_OF_TRUST so return ENVL_NOWHERE when CONFIG_ENV_IS_NOWHERE is enabled Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
059d9422 |
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08-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: lx2160a: add MMU table entries for PCIe The lx2160a have up to 6 PCIe controllers and have different address and size of PCIe region. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
8348e798 |
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08-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: layerscape: use PCIe address macro for precompile PCIe MMU entry Change to use PCIe address macro to determine if precompile the PCIe MMU table entry. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
10015025 |
|
03-May-2019 |
Trevor Woerner <trevor@toganlabs.com> |
CONFIG_SPL_SYS_[DI]CACHE_OFF: add While converting CONFIG_SYS_[DI]CACHE_OFF to Kconfig, there are instances where these configuration items are conditional on SPL. This commit adds SPL variants of these configuration items, uses CONFIG_IS_ENABLED(), and updates the configurations as required. Acked-by: Alexey Brodkin <abrodkin@synopsys.com> Signed-off-by: Trevor Woerner <trevor@toganlabs.com> [trini: Make the default depend on the setting for full U-Boot, update more zynq hardware] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
2e53759d |
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29-Oct-2018 |
Pankaj Bansal <pankaj.bansal@nxp.com> |
armv8: fsl-layerscape: reorder rgmii dpmacs' enablement some dpmacs in armv8a based freescale layerscape SOCs can be configured via both serdes(sgmii, xfi, xlaui etc) bits and via EC*_PMUX(rgmii) bits in RCW. e.g. dpmac 17 and 18 in LX2160A can be configured as SGMII from serdes bits and as RGMII via EC1_PMUX/EC2_PMUX bits Now if a dpmac is enabled by serdes bits then it takes precedence over EC*_PMUX bits. i.e. in LX2160A if we select serdes protocol that configures dpmac17 as SGMII and set the EC1_PMUX as RGMII, then the dpmac is SGMII and not RGMII. Therefore, move the fsl_rgmii_init after fsl_serdes_init. in fsl_rgmii_init function of SOC, we will check if the dpmac is enabled or not? if it is (fsl_serdes_init has already enabled the dpmac), then don't enable it. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
ec88ff80 |
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19-Dec-2018 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1043a: add SVR definitions for 23x23 package silicon LS1043A/LS1023A 23x23 package silicon has different SVR:VAR_PER. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
d23da2ae |
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26-Dec-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: fixes for TFABOOT framework Fixes for TFABOOT framework - update eMMC bootsrc to SD_MMC - Increase buffer size for mcinitcmd from 256 to 512 - Fix mcinitcmd and bootcmd for Secure Boot Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
4909b89e |
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29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
d6fdec21 |
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29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8:fsl-layerscape: Add support for Chassis 3.2 NXP layerscape architecture Chassis 3.2 builds upon chassis3 architecture with changes like DDR Memory map change, removal of IFC and support of upto 8 I2C controller. Patch add README.lsch3_2 and the above changes under macro CONFIG_NXP_LSCH3_2. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
56db948b |
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05-Nov-2018 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: Update parsing boot source Workaround of erratum A010539 clears the RCW source field in PORSR1 register, causing failure of detecting boot source using this method. Use SMC call if U-Boot runs at EL2. If SMC is not implemented or running at EL3, continue to read PORSR1 and presume QSPI as boot source if erratum workaround A010539 is enabled and RCW source is cleared. Signed-off-by: York Sun <york.sun@nxp.com> |
#
681d489e |
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05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: layerscape: add SMC calls for DDR size and bank info Adds SMC calls for getting DDR size and bank info for TFABOOT. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
2141d250 |
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05-Nov-2018 |
Pankit Garg <pankit.garg@nxp.com> |
armv8: fsl-layerscape: bootcmd identification for TFABOOT Adds bootcmd identificaton on basis on boot source, valid in TFABOOT configuration. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> [YS: remove unnecessary braces] Reviewed-by: York Sun <york.sun@nxp.com> |
#
4c417384 |
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05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com> |
#
535d76a1 |
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05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: layerscape: Add TFABOOT support Adds TFABOOT support config option and add generic code to enable execution from DDR. Signed-off-by: York Sun <york.sun@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> |
#
e3506480 |
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05-Nov-2018 |
Pankit Garg <pankit.garg@nxp.com> |
armv8: fsl-layerscape: change tlb base from OCRAM to DDR in EL < 3 Change tlb base address from OCRAM to DDR when exception level is less than 3. Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
d171c707 |
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05-Nov-2018 |
York Sun <york.sun@nxp.com> |
move data structure out of cpu.h Move static definitions to cpu.c file, as it doesn't allow the cpu.h file to be included in multiple c files. Signed-off-by: York Sun <york.sun@nxp.com> |
#
9b5e6396 |
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30-Aug-2018 |
Stephen Warren <swarren@nvidia.com> |
efi_loader: simplify ifdefs Use CONFIG_IS_ENABLED(EFI_LOADER) to avoid explicitly checking CONFIG_SPL too. This simplifies the conditional. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Alexander Graf <agraf@suse.de> |
#
9cce5663 |
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16-Jul-2018 |
Joe Hershberger <joe.hershberger@ni.com> |
arm: Prevent redefinition error in fsl-layerscape The include/phy.h will start including dm.h, which pulls in linux/compat.h after the attempted redefinition in arch/arm/include/asm/armv8/mmu.h, so move this include to allow redefinition. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> |
#
83d290c5 |
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06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
482fc90c |
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06-Feb-2018 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
efi_loader: add missing EFI_RESET_PLATFORM_SPECIFIC EFI_RESET_PLATFORM_SPECIFIC is one of the values that can be used for the EFI service ResetSystem. The missing definition is added. The value has to handled in efi_reset_system(). Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Alexander Graf <agraf@suse.de> |
#
22c793e6 |
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03-Mar-2018 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
efi_loader: exit status for efi_reset_system_init efi_reset_system_init provides the architecture or board specific initialization of the EFI subsystem. Errors should be caught and signalled by a return code. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Alexander Graf <agraf@suse.de> |
#
958b2ed5 |
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09-Jan-2018 |
Zhang Ying-22455 <ying.zhang22455@nxp.com> |
armv8/ls1088a: configure PMU's PCTBENR to enable WDT The SP805-WDT module on LS1088A requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. The watchdog clock needs to be enabled first. Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
44262327 |
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15-Dec-2017 |
Ahmed Mansour <ahmed.mansour@nxp.com> |
drivers/misc: Share qbman init between archs This patch adds changes necessary to move functionality present in PowerPC folders with ARM architectures that have DPAA1 QBMan hardware - Create new board/freescale/common/fsl_portals.c to house shared device tree fixups for DPAA1 devices with ARM and PowerPC cores - Add new header file to top includes directory to allow files in both architectures to grab the function prototypes - Port inhibit_portals() from PowerPC to ARM. This function is used in setup to disable interrupts on all QMan and BMan portals. It is needed because the interrupts are enabled by default for all portals including unused/uninitialised portals. When the kernel attempts to go to deep sleep the unused portals prevent it from doing so Signed-off-by: Ahmed Mansour <ahmed.mansour@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
a8f33034 |
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03-Dec-2017 |
Wenbin song <wenbin.song@nxp.com> |
armv8: ls1043a/ls2080a: check SoC by device ID Check LS1043A/LS2080a by device ID without using personality ID to determine revision number. This check applies to all various personalities of the same SoC family. Signed-off-by: Wenbin Song <wenbin.song@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
2db53cfe |
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09-Nov-2017 |
Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
armv8: fsl-layerscape: Add support of disabling core prefetch Instruction prefetch feature is by default enabled during core release. This patch add support of disabling instruction prefetch by setting core mask in PPA. Here each core mask bit represents a core and prefetch is disabled at the time of core release. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
7eb40f0f |
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28-Sep-2017 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: Avoid running dram_init_banksize again gd->ram_size is reduced in this function to reserve secure memory. Avoid running this function again to further reduce memory size. This fixes issue for SPL boot with PPA image loaded in which case secure memory is incorrectly allocated due to repeated calling. Signed-off-by: York Sun <york.sun@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
710d0cd7 |
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03-Oct-2017 |
Sumit Garg <sumit.garg@nxp.com> |
armv8: fsl-layerscape: Allocate Secure memory from first ddr region This change is required due to trusted OS (OP-TEE) not being position independent code, it requires compile time fixed base address. To take care of this it is assumed that all layerscape armv8 platforms has minimum 2G ddr in first region. So we can have fixed address space (66 MB -> (2MB for PPA + 64MB for trusted OS)) allocated from top of first 2G ddr region and compile trusted OS with this fixed base address. But one exception here is ls1012 where we have only 1G (rdb) or 512M (frdm) ddr memory. For those we can have different fixed compile time base addresses for trusted OS. Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
e9303a41 |
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07-Sep-2017 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: Fix MC reserved memory calculation In case high region memory doesn't have enough space for Management Complex (MC), the return value should indicate a failure so the caller can handle it accordingly. Signed-off-by: York Sun <york.sun@nxp.com> Reported-by: Ebony Zhu <ebony.zhu@nxp.com> |
#
17d066fc |
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31-Aug-2017 |
Ashish Kumar <Ashish.Kumar@nxp.com> |
armv8: fsl-layerscape: Support to add RGMII for ls1088aqds This patch adds support for RGMII protocol NXP's LDPAA2 support RGMII protocol. LS1088A is the first Soc supporting both RGMII and SGMII. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Amrita Kumari <amrita.kumari@nxp.com> Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
63b2316c |
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10-Aug-2017 |
Ashish Kumar <Ashish.Kumar@nxp.com> |
fsl-layerscape: Consolidate registers space defination for CCI-400 bus CoreLink Cache Coherent Interconnect (CCI) provides full cache coherency between two clusters of multi-core CPUs and I/O coherency for devices and I/O masters. This patch add new config option SYS_FSL_HAS_CCI400 and moves existing register space definaton of CCI-400 bus to fsl_immap to be shared. CONFIG_SYS_CCI400_ADDR is replaced with SYS_CCI400_OFFSET in Kconfig. Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> [YS: revised commit message, squashed patches for armv8 and armv7] Reviewed-by: York Sun <york.sun@nxp.com> |
#
6e2941d7 |
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17-May-2017 |
Simon Glass <sjg@chromium.org> |
common: freescale: Move arch-specific declarations The declarations should not be in common.h. Move them to the arch-specific headers. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Fixup thinko defined(FSL_LSCH3) -> defined(CONFIG_FSL_LSCH3)] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
399e2bb6 |
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15-May-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Make U-Boot EL2 safe When U-Boot boots from EL2, skip some lowlevel init code requiring EL3, including CCI-400/CCN-504, trust zone, GIC, etc. These initialization tasks are carried out before U-Boot runs. This applies to the RAM version image used for SPL boot if PPA is loaded first. Signed-off-by: York Sun <york.sun@nxp.com> |
#
1f55a938 |
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05-May-2017 |
Santan Kumar <santan.kumar@nxp.com> |
armv8: ls2080aqds: Add support for SD boot Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
e809e747 |
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27-Apr-2017 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: fsl-layerscape: Add NXP LS2081A, LS2041A SoC support The QorIQ LS2081A SoC has eight 64-bit ARM v8 Cortex A72 cores and is built on layerscape architecture. It is 40-pin derivative of LS2084A (non-AIOP personality of LS2088A). So feature-wise it is same as LS2084A. LS2041A is a 4-core personality of LS2081A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
026f30ec |
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18-Apr-2017 |
Yuantian Tang <andy.tang@nxp.com> |
arm: psci: make psci usable on single core socs PSCI can be used on both multiple and single core socs. Current implementation only allows PSCI to work on multiple core socs. This patch removes this restriction so that PSCI can work on single core socs as well. Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
4a3ab193 |
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27-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: ls2080a: Drop macro CONFIG_LS2080A Use CONFIG_ARCH_LS2080A instead. Signed-off-by: York Sun <york.sun@nxp.com> |
#
3eace37e |
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06-Apr-2017 |
Simon Glass <sjg@chromium.org> |
arm: freescale: Rename initdram() to fsl_initdram() This function name shadows a global name but is in fact different. This is very confusing. Rename it to help with the following refactoring. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
76b00aca |
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31-Mar-2017 |
Simon Glass <sjg@chromium.org> |
board_f: Drop setup_dram_config() wrapper By making dram_init_banksize() return an error code we can drop the wrapper. Adjust this and clean up all implementations. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
088454cd |
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31-Mar-2017 |
Simon Glass <sjg@chromium.org> |
board_f: Drop return value from initdram() At present we cannot use this function as an init sequence call without a wrapper, since it returns the RAM size. Adjust it to set the RAM size in global_data instead, and return 0 on success. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
52c41180 |
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31-Mar-2017 |
Simon Glass <sjg@chromium.org> |
board_f: Drop board_type parameter from initdram() It looks like only cm5200 and tqm8xx use this feature, so we don't really need it in generic code. Drop it and have the users access gd->board_type directly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
3d8553f0 |
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02-Mar-2017 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
pci: layerscape: add LS2088A series SoC pcie support The LS2088A series SoCs has different physical memory map address and CCSR registers address against LS2080A series SoCs. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
eea1cb77 |
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13-Feb-2017 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8/fsl-layerscape: Update erratum A009635 implementation Erratum A009635 is valid only for LS2080A SoC and its personality. Add SoC svr check. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
4961eafc |
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06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Update early MMU for DDR after initialization In early MMU table, DDR has to be mapped as device memory to avoid speculative access. After DDR is initialized, it needs to be updated to normal memory to allow code execution. To simplify the code, dram_init() is moved into a common file as a weak function. Signed-off-by: York Sun <york.sun@nxp.com> |
#
a045a0c3 |
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06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Fix the sequence of changing MMU table This patch follows the break-before-make process when making changes to MMU table. MMU is disabled before changing TTBR to avoid any potential race condition. Signed-off-by: York Sun <york.sun@nxp.com> |
#
24f55496 |
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06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Update MMU mapping with actual DDR size Update mapping with actual DDR size. Non-existing memory should not be mapped as "normal" memory to avoid speculative access. Signed-off-by: York Sun <york.sun@nxp.com> |
#
36cc0de0 |
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06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Rewrite memory reservation For ARMv8 Layerscape SoCs, secure memory and MC memorey are reserved at the end of DDR. DDR is spit into two or three banks. This patch reverts commit aabd7ddb and simplifies the calculation of reserved memory, and moves the code into common SoC file. Secure memory is carved out first. DDR bank size is reduced. Reserved memory is then allocated on the top of available memory. U-Boot still has access to reserved memory as data transferring is needed. Device tree is fixed with reduced memory size to hide the reserved memory from OS. The same region is reserved for efi_loader. Signed-off-by: York Sun <york.sun@nxp.com> |
#
daa92644 |
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16-Jan-2017 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
ARMv8/sec_firmware: relocated and renamed the config FSL_PPA_ARMV8_PSCI Moved the config FSL_PPA_ARMV8_PSCI from fsl-layerscape's Kconfig to Kconfig under armv8 and renamed it to SEC_FIRMWARE_ARMV8_PSCI. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
904110c7 |
|
10-Jan-2017 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8/fsl-lsch2: refactor the clock system initialization Up to now, there are 3 kind of SoCs under Layerscape Chassis 2, like LS1043A, LS1046A and LS1012A. But the clocks tree has a lot of differences, for instance, the IP modules have different dividers to derive its clock from Platform PLL. And the core cluster PLL and platform PLL maybe have different reference clocks, such as LS1012A. Another problem is which clock/PLL should be described by sys_info->freq_systembus, it is confused in Layerscape Chissis 2. This patch is to bind the sys_info->freq_systembus to the Platform PLL, and handle the different divider of IP modules separately between different SoCs, and separate reference clocks of core cluster PLL and platform PLL. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
2d16a1a6 |
|
07-Dec-2016 |
macro.wave.z@gmail.com <macro.wave.z@gmail.com> |
ARMv8: LS1043A: change macro CONFIG_ARMV8_PSCI definition NXP/Freescale uses macro CONFIG_ARMV8_PSCI to enable their private PSCI implementation in PPA firmware, but this macro naming too generic, so this patch replaces it with a specic one CONFIG_FSL_PPA_ARMV8_PSCI. And this macro CONFIG_ARMV8_PSCI will be used for a generic PSCI for ARMv8 which will be added in following patchs. Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
02fb2761 |
|
20-Nov-2016 |
Shengzhou Liu <Shengzhou.Liu@nxp.com> |
fsl/ddr: Add erratum_a009942_check_cpo and clean related erratum - add additional function erratum_a009942_check_cpo to check if the board needs tuning CPO calibration for optimal setting. - move ERRATUM_A009942(with revision to check cpo_sample option) from fsl_ddr_gen4.c to ctrl_regs.c for reuse on all DDR4/DDR3 parts. - move ERRATUM_A008378 from fsl_ddr_gen4.c to ctrl_regs.c - remove obsolete ERRATUM_A004934 which is replaced with ERRATUM_A009942. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> [YS: Replaced CONFIG_QEMU_E500 with CONFIG_ARCH_QEMU_E500] Reviewed-by: York Sun <york.sun@nxp.com> |
#
e87c673c |
|
16-Nov-2016 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8/fsl-lsch3: Update code to release secondary cores NXP ARMv8 SoC LS2080A release all secondary cores in one-go. But other new SoCs like LS2088A, LS1088A release secondary cores one by one. Update code to release secondary cores based on SoC SVR Add code to release cores one by one for non LS2080A SoCs Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> [YS: remove "inline" from declaration of initiator_type] Reviewed-by: York Sun <york.sun@nxp.com> |
#
f6b96ff6 |
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16-Nov-2016 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Use SVR based timer base address detection Timer controller base address has been changed from LS2080A SoC (and its personalities) to new SoCs like LS2088A, LS1088A. Use SVR based timer base address detection to avoid compile time #ifdef. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
f6a70b3a |
|
16-Nov-2016 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add generic get_svr() in assembly Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
78d57842 |
|
16-Nov-2016 |
Alexander Graf <agraf@csgraf.de> |
armv8: fsl-layerscape: Add support for efi_loader RTS reset When implementing efi loader support, we can expose runtime services for payloads. One such service is CPU reset. This patch implements RTS CPU reset support for layerscape systems. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: York Sun <york.sun@nxp.com> |
#
ef9a5fd8 |
|
13-Sep-2016 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: Fix "cpu status" command The core position is not continuous for some SoCs. For example, valid cores may present at position 0, 1, 4, 5, 8, 9, etc. Some registers (including boot release register) only count existing cores. Current implementation of cpu_mask() complies with the continuous numbering. However, command "cpu status" queries the spin table with actual core position. Add functions to calculate core position from core number, to correctly calculate offsets. Tested on LS2080ARDB and LS1043ARDB. Signed-off-by: York Sun <york.sun@nxp.com> |
#
5d1a7a9d |
|
13-Sep-2016 |
Wenbin Song <wenbin.song@nxp.com> |
armv8/fsl-layerscape: print SoC revsion number The exact SoC revsion number can be recognized from U-Boot log. Signed-off-by: Wenbin Song <wenbin.song@nxp.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
cbe7706a |
|
26-Sep-2016 |
Tom Rini <trini@konsulko.com> |
Merge git://git.denx.de/u-boot-fsl-qoriq trini: Drop local memset() from examples/standalone/mem_to_mem_idma2intr.c Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
1221ce45 |
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20-Sep-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
treewide: replace #include <asm/errno.h> with <linux/errno.h> Now, arch/${ARCH}/include/asm/errno.h and include/linux/errno.h have the same content. (both just wrap <asm-generic/errno.h>) Replace all include directives for <asm/errno.h> with <linux/errno.h>. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> [trini: Fixup include/clk.] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
b63a9506 |
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03-Aug-2016 |
York Sun <york.sun@nxp.com> |
armv8: ls2080a: Remove debug server support Debug server feature has been dropped from roadmap. Signed-off-by: York Sun <york.sun@nxp.com> |
#
ed7a3943 |
|
22-Jul-2016 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: mmu: Fix enabling MMU MMU bit in SCTLR needs to be set explicitly after tables are created. It isn't an issue for EL3 becuase this bit is already set by early MMU setup. But for other exception levels this bit was not set. Signed-off-by: York Sun <york.sun@nxp.com> |
#
79119a4d |
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05-Jul-2016 |
Alison Wang <b18965@freescale.com> |
armv8: fsl-layerscape: Add A72 core detection Add support to detect Cortex-A72 core for printing it out. The Initiator Version of A72 core should be 0x4. Signed-off-by: Alison Wang <alison.wang@nxp.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
032d5bb4 |
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28-Jun-2016 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
ARMv8/Layerscape: switch SMP method accordingly If the PSCI and PPA is ready, skip the fixup for spin-table and waking secondary cores. Otherwise, change SMP method to spin-table, and the device node of PSCI will be removed. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
85cdf38e |
|
28-Jun-2016 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: fsl-layerscape: add i/d-cache enable function to enable_caches This function assume that the d-cache and MMU has been enabled earlier, so it just created MMU table in main memory. But the assumption is not always correct, for example, the early setup is done in EL3, while enable_caches() is called when the PE has turned into another EL. Define the function mmu_setup() for fsl-layerscape to cover the weak one. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
5ad5823d |
|
24-Jun-2016 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Convert to use common MMU framework Drop platform code to create static MMU tables. Use common framework to create MMU tables on the run. Tested on LS2080ARDB with secure and non-secure ram scenarios. Signed-off-by: York Sun <york.sun@nxp.com> |
#
e61a7534 |
|
24-Jun-2016 |
York Sun <york.sun@nxp.com> |
armv8: Move secure_ram variable out of generic global data Secure_ram variable was put in generic global data. But only ARMv8 uses this variable. Move it to ARM specific data structure. Signed-off-by: York Sun <york.sun@nxp.com> |
#
a10a31ec |
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18-Jun-2016 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of git://git.denx.de/u-boot-usb Signed-off-by: Tom Rini <trini@konsulko.com> Conflicts: arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
|
#
6fb522dc |
|
12-Jun-2016 |
Sriram Dash <sriram.dash@nxp.com> |
arm64: fsl-layerscape: add get_svr and IS_SVR_REV helper Adds get_svr and IS_SVR_REV helpers for ARMv8 platforms, similar to PPC and ARMv7. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> |
#
a758177f |
|
07-Jun-2016 |
Yunhui Cui <yunhui.cui@nxp.com> |
armv8/ls2080a: configure PMU's PCTBENR to enable WDT The SP805-WDT module on LS2080A requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. The watchdog clock needs to be enabled first. Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
acb8f5e9 |
|
21-Apr-2016 |
Alison Wang <b18965@freescale.com> |
armv8: fsl-layerscape: Remove unnecessary flushing dcache As the issue about the stack will get corrupted when switching between the early and final mmu tables is fixed by commit 70e21b064, the workaround to flush dcache is unnecessary and should be removed. Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
3c1d218a |
|
04-Apr-2016 |
York Sun <york.sun@nxp.com> |
armv8: LS2080A: Consolidate LS2080A and LS2085A LS2080A is the primary SoC, and LS2085A is a personality with AIOP and DPAA DDR. The RDB and QDS boards support both personality. By detecting the SVR at runtime, a single image per board can support both SoCs. It gives users flexibility to swtich SoC without the need to reprogram the board. Signed-off-by: York Sun <york.sun@nxp.com> CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
c05016ab |
|
21-Mar-2016 |
Alexander Graf <agraf@csgraf.de> |
arm64: Fix layerscape mmu setup With commit 7985cdf we converted all systems except for the Layerscape SoCs to the generic descriptor table based page table setup. On the Layerscape SoCs however, we just provide an empty table stub and do the setup ourselves. To reserve enough memory for the tables, we need to override the default counting mechanism which would end up with an empty table because we have no maps. Fixes: 7985cdf Reported-by: York Sun <york.sun@nxp.com> CC: Alison Wang <alison.wang@nxp.com> CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Alexander Graf <agraf@suse.de> Tested-by: York Sun <york.sun@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
7985cdf7 |
|
03-Mar-2016 |
Alexander Graf <agraf@csgraf.de> |
arm64: Remove non-full-va map code By now the code to only have a single page table level with 64k page size and 42 bit address space is no longer used by any board in tree, so we can safely remove it. To clean up code, move the layerscape mmu code to the new defines, removing redundant field definitions. Signed-off-by: Alexander Graf <agraf@suse.de> |
#
c0492141 |
|
07-Dec-2015 |
York Sun <yorksun@freescale.com> |
armv8: fsl-layerscale: Rewrite reserving memory for MC and debug server MC and debug server are not board-specific. Move reserving memory to SoC file, using the new board_reserve_ram_top function. Reduce debug server memory by 2MB to make room for secure memory. In the system with MC and debug server, the top of u-boot memory is not the end of memory. PRAM is not used for this reservation. Signed-off-by: York Sun <yorksun@freescale.com> |
#
c107c0c0 |
|
04-Dec-2015 |
York Sun <yorksun@freescale.com> |
armv8: fsl-layerscape: Make DDR non secure in MMU tables DDR has been set as secure in MMU tables. Non-secure master such as SDHC DMA cannot access data correctly. Mixing secure and non- secure MMU entries requirs the MMU tables themselves in secure memory. This patch moves MMU tables into a secure DDR area. Early MMU tables are changed to set DDR as non-secure. A new table is added into final MMU tables so secure memory can have 2MB granuality. gd->secure_ram tracks the location of this secure memory. For ARMv8 SoCs, the RAM base is not zero and RAM is divided into several banks. gd->secure_ram needs to be maintained before using. This maintenance is board-specific, depending on the SoC and memory bank of the secure memory falls into. Signed-off-by: York Sun <yorksun@freescale.com> |
#
b4017364 |
|
04-Nov-2015 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
armv8: ls2085a: Add workaround of errata A009635 If the core runs at higher than x3 speed of the platform, there is possiblity about sev instruction to getting missed by other cores. This is because of SoC Run Control block may not able to sample the EVENTI(Sev) signals. Configure Run Control and EPU to periodically send out EVENTI signals to wake up A57 cores. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
d764129d |
|
04-Nov-2015 |
Alison Wang <b18965@freescale.com> |
armv8/layerscape: Update MMU table with execute-never bits For most device addresses excution shouldn't be allowed. Revise the MMU table to enforce execute-never bits. OCRAM, DDR and IFC are allowed for excution. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Alison Wang <alison.wang@freescale.com> Reported-by: Zhichun Hua <zhichun.hua@freescale.com> |
#
44937214 |
|
09-Nov-2015 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
armv8: LS2080A: Rename LS2085A to reflect LS2080A LS2080A is a prime personality of Freescale’s LS2085A. It is a non-AIOP personality without support of DP-DDR, L2 switch, 1588, PCIe endpoint etc. So renaming existing LS2085A code base to reflect LS2080A (Prime personality) Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> [York Sun: Dropped #ifdef in cpu.c for cpu_type_list] Reviewed-by: York Sun <yorksun@freescale.com> |
#
e8297341 |
|
26-Oct-2015 |
Shaohui Xie <Shaohui.Xie@freescale.com> |
armv8/ls1043a: Add Fman support Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
8281c58f |
|
26-Oct-2015 |
Mingkai Hu <Mingkai.Hu@freescale.com> |
armv8/fsl_lsch2: Add fsl_lsch2 SoC Freescale LayerScape with Chassis Generation 2 is a set of SoCs with ARMv8 cores and 2rd generation of Chassis. Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
9f3183d2 |
|
26-Oct-2015 |
Mingkai Hu <Mingkai.Hu@freescale.com> |
armv8/fsl_lsch3: Change arch to fsl-layerscape There are two LS series processors are built on ARMv8 Layersacpe architecture currently, LS2085A and LS1043A. They are based on ARMv8 core although use different chassis, so create fsl-layerscape to refactor the common code for the LS series processors which also paves the way for adding LS1043A platform. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
db41d65a |
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28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move hang() to the same header as panic() At present panic() is in the vsprintf.h header file. That does not seem like an obvious choice for hang(), even though it relates to panic(). So let's put hang() in its own header. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Migrate a few more files] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
9b4a205f |
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28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move RAM-sizing functions to init.h These functions relate to memory init so move them into the init header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
3499dd03 |
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27-Nov-2019 |
Alex Marginean <alexandru.marginean@nxp.com> |
ls1028a: Configure stream IDs for integrated PCI and fix up Linux DT Hardware comes out of reset with implicit values, but these are outside the accepted range for Layerscape gen 3 chassis spec used on LS1028A. Allocate different IDs and fix up Linux DT to use them. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
b5981474 |
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14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some CPU functions out of common.h These functions belong in cpu_func.h since they do not use driver model. Move them over. Don't bother adding comments since these functions should be deleted. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
68a6aa85 |
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14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move mii_init() function out of common.h This function belongs in mii.h so move it over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
2189d5f1 |
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14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
Move strtomhz() to vsprintf.h At present this function sits in its own file but it does not really justify it. There are similar string functions in vsprintf.h, so move it there. Also add the missing function comment. Use the vsprintf.h include file explicitly where needed. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
812ff53c |
|
30-Oct-2019 |
Pankaj Bansal <pankaj.bansal@nxp.com> |
fsl-layerscape: fix warning if no hwconfig is defined While getting the 'subarg' of 'hwconfig' env variable in config_core_prefetch(), if no hwconfig variable is defined, below warning is received: WARNING: Calling __hwconfig without a buffer and before environment is ready Fix this by checking 'hwconfig' env variable. If not found return without further processing. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Tested-by: Michael Walle <michael@walle.cc> |
#
28f9393b |
|
17-Oct-2019 |
Mathew McBride <matt@traverse.com.au> |
fsl-layerscape: do not use layerscape EFI reset if PSCI used If the secure world reset handlers are used (via CONFIG_PSCI_RESET), then do not use the layerscape-specific implementation. Signed-off-by: Mathew McBride <matt@traverse.com.au> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
6ed69523 |
|
18-Sep-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add more personalities support Add LS1027A, LS1018A and LS1017A personalities support to LS1028A SoC family. LS1028A is the prime personality of LS1028A SoC family. LS1027A is a lower funtionality version of QorIQ LS1028A which does not support the multimedia subsystems, such as LCD controller, GPU, and eDP PHY. The QorIQ LS1018A and LS1017A SoCs are single 64-bit Arm A72 core, low power versions of the QorIQ LS1028A and LS1027A SoCs respectively. Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
0490cab5 |
|
08-Aug-2019 |
Thomas Schaefer <thomas.schaefer@kontron.com> |
armv8: ls1028a: configure PMU's PCTBENR to enable WDT The SP805-WDT module on LS1028A requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. The watchdog clock needs to be enabled first. Signed-off-by: Thomas Schaefer <thomas.schaefer@kontron.com> Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
f3998fdc |
|
02-Aug-2019 |
Simon Glass <sjg@chromium.org> |
env: Rename environment.h to env_internal.h This file contains lots of internal details about the environment. Most code can include env.h instead, calling the functions there as needed. Rename this file and add a comment at the top to indicate its internal nature. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> [trini: Fixup apalis-tk1.c] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
3a7d5571 |
|
01-Aug-2019 |
Simon Glass <sjg@chromium.org> |
env: Move env_get_f() to env.h Move this function over to the new header file. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
d9532e80 |
|
23-Apr-2019 |
Udit Agarwal <udit.agarwal@nxp.com> |
armv8: fsl-layerscape: Set env_loc to ENVL_NOWHERE with CONFIG_ENV_IS_NOWHERE. ENVL_NOWHERE is dependent on CONFIG_ENV_IS_NOWHERE and not on CONFIG_CHAIN_OF_TRUST so return ENVL_NOWHERE when CONFIG_ENV_IS_NOWHERE is enabled Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
d4ad111d |
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10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
059d9422 |
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08-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: lx2160a: add MMU table entries for PCIe The lx2160a have up to 6 PCIe controllers and have different address and size of PCIe region. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
8348e798 |
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08-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: layerscape: use PCIe address macro for precompile PCIe MMU entry Change to use PCIe address macro to determine if precompile the PCIe MMU table entry. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
10015025 |
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03-May-2019 |
Trevor Woerner <trevor@toganlabs.com> |
CONFIG_SPL_SYS_[DI]CACHE_OFF: add While converting CONFIG_SYS_[DI]CACHE_OFF to Kconfig, there are instances where these configuration items are conditional on SPL. This commit adds SPL variants of these configuration items, uses CONFIG_IS_ENABLED(), and updates the configurations as required. Acked-by: Alexey Brodkin <abrodkin@synopsys.com> Signed-off-by: Trevor Woerner <trevor@toganlabs.com> [trini: Make the default depend on the setting for full U-Boot, update more zynq hardware] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
2e53759d |
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29-Oct-2018 |
Pankaj Bansal <pankaj.bansal@nxp.com> |
armv8: fsl-layerscape: reorder rgmii dpmacs' enablement some dpmacs in armv8a based freescale layerscape SOCs can be configured via both serdes(sgmii, xfi, xlaui etc) bits and via EC*_PMUX(rgmii) bits in RCW. e.g. dpmac 17 and 18 in LX2160A can be configured as SGMII from serdes bits and as RGMII via EC1_PMUX/EC2_PMUX bits Now if a dpmac is enabled by serdes bits then it takes precedence over EC*_PMUX bits. i.e. in LX2160A if we select serdes protocol that configures dpmac17 as SGMII and set the EC1_PMUX as RGMII, then the dpmac is SGMII and not RGMII. Therefore, move the fsl_rgmii_init after fsl_serdes_init. in fsl_rgmii_init function of SOC, we will check if the dpmac is enabled or not? if it is (fsl_serdes_init has already enabled the dpmac), then don't enable it. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
ec88ff80 |
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19-Dec-2018 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1043a: add SVR definitions for 23x23 package silicon LS1043A/LS1023A 23x23 package silicon has different SVR:VAR_PER. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
d23da2ae |
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26-Dec-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: fixes for TFABOOT framework Fixes for TFABOOT framework - update eMMC bootsrc to SD_MMC - Increase buffer size for mcinitcmd from 256 to 512 - Fix mcinitcmd and bootcmd for Secure Boot Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
4909b89e |
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29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
d6fdec21 |
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29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8:fsl-layerscape: Add support for Chassis 3.2 NXP layerscape architecture Chassis 3.2 builds upon chassis3 architecture with changes like DDR Memory map change, removal of IFC and support of upto 8 I2C controller. Patch add README.lsch3_2 and the above changes under macro CONFIG_NXP_LSCH3_2. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
56db948b |
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05-Nov-2018 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: Update parsing boot source Workaround of erratum A010539 clears the RCW source field in PORSR1 register, causing failure of detecting boot source using this method. Use SMC call if U-Boot runs at EL2. If SMC is not implemented or running at EL3, continue to read PORSR1 and presume QSPI as boot source if erratum workaround A010539 is enabled and RCW source is cleared. Signed-off-by: York Sun <york.sun@nxp.com> |
#
681d489e |
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05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: layerscape: add SMC calls for DDR size and bank info Adds SMC calls for getting DDR size and bank info for TFABOOT. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
2141d250 |
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05-Nov-2018 |
Pankit Garg <pankit.garg@nxp.com> |
armv8: fsl-layerscape: bootcmd identification for TFABOOT Adds bootcmd identificaton on basis on boot source, valid in TFABOOT configuration. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> [YS: remove unnecessary braces] Reviewed-by: York Sun <york.sun@nxp.com> |
#
4c417384 |
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05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com> |
#
535d76a1 |
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05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: layerscape: Add TFABOOT support Adds TFABOOT support config option and add generic code to enable execution from DDR. Signed-off-by: York Sun <york.sun@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> |
#
e3506480 |
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05-Nov-2018 |
Pankit Garg <pankit.garg@nxp.com> |
armv8: fsl-layerscape: change tlb base from OCRAM to DDR in EL < 3 Change tlb base address from OCRAM to DDR when exception level is less than 3. Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
d171c707 |
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05-Nov-2018 |
York Sun <york.sun@nxp.com> |
move data structure out of cpu.h Move static definitions to cpu.c file, as it doesn't allow the cpu.h file to be included in multiple c files. Signed-off-by: York Sun <york.sun@nxp.com> |
#
9b5e6396 |
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30-Aug-2018 |
Stephen Warren <swarren@nvidia.com> |
efi_loader: simplify ifdefs Use CONFIG_IS_ENABLED(EFI_LOADER) to avoid explicitly checking CONFIG_SPL too. This simplifies the conditional. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Alexander Graf <agraf@suse.de> |
#
9cce5663 |
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16-Jul-2018 |
Joe Hershberger <joe.hershberger@ni.com> |
arm: Prevent redefinition error in fsl-layerscape The include/phy.h will start including dm.h, which pulls in linux/compat.h after the attempted redefinition in arch/arm/include/asm/armv8/mmu.h, so move this include to allow redefinition. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> |
#
83d290c5 |
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06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
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482fc90c |
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06-Feb-2018 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
efi_loader: add missing EFI_RESET_PLATFORM_SPECIFIC EFI_RESET_PLATFORM_SPECIFIC is one of the values that can be used for the EFI service ResetSystem. The missing definition is added. The value has to handled in efi_reset_system(). Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Alexander Graf <agraf@suse.de> |
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22c793e6 |
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03-Mar-2018 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
efi_loader: exit status for efi_reset_system_init efi_reset_system_init provides the architecture or board specific initialization of the EFI subsystem. Errors should be caught and signalled by a return code. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Alexander Graf <agraf@suse.de> |
#
958b2ed5 |
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09-Jan-2018 |
Zhang Ying-22455 <ying.zhang22455@nxp.com> |
armv8/ls1088a: configure PMU's PCTBENR to enable WDT The SP805-WDT module on LS1088A requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. The watchdog clock needs to be enabled first. Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
44262327 |
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15-Dec-2017 |
Ahmed Mansour <ahmed.mansour@nxp.com> |
drivers/misc: Share qbman init between archs This patch adds changes necessary to move functionality present in PowerPC folders with ARM architectures that have DPAA1 QBMan hardware - Create new board/freescale/common/fsl_portals.c to house shared device tree fixups for DPAA1 devices with ARM and PowerPC cores - Add new header file to top includes directory to allow files in both architectures to grab the function prototypes - Port inhibit_portals() from PowerPC to ARM. This function is used in setup to disable interrupts on all QMan and BMan portals. It is needed because the interrupts are enabled by default for all portals including unused/uninitialised portals. When the kernel attempts to go to deep sleep the unused portals prevent it from doing so Signed-off-by: Ahmed Mansour <ahmed.mansour@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
a8f33034 |
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03-Dec-2017 |
Wenbin song <wenbin.song@nxp.com> |
armv8: ls1043a/ls2080a: check SoC by device ID Check LS1043A/LS2080a by device ID without using personality ID to determine revision number. This check applies to all various personalities of the same SoC family. Signed-off-by: Wenbin Song <wenbin.song@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
2db53cfe |
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09-Nov-2017 |
Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
armv8: fsl-layerscape: Add support of disabling core prefetch Instruction prefetch feature is by default enabled during core release. This patch add support of disabling instruction prefetch by setting core mask in PPA. Here each core mask bit represents a core and prefetch is disabled at the time of core release. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
7eb40f0f |
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28-Sep-2017 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: Avoid running dram_init_banksize again gd->ram_size is reduced in this function to reserve secure memory. Avoid running this function again to further reduce memory size. This fixes issue for SPL boot with PPA image loaded in which case secure memory is incorrectly allocated due to repeated calling. Signed-off-by: York Sun <york.sun@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
710d0cd7 |
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03-Oct-2017 |
Sumit Garg <sumit.garg@nxp.com> |
armv8: fsl-layerscape: Allocate Secure memory from first ddr region This change is required due to trusted OS (OP-TEE) not being position independent code, it requires compile time fixed base address. To take care of this it is assumed that all layerscape armv8 platforms has minimum 2G ddr in first region. So we can have fixed address space (66 MB -> (2MB for PPA + 64MB for trusted OS)) allocated from top of first 2G ddr region and compile trusted OS with this fixed base address. But one exception here is ls1012 where we have only 1G (rdb) or 512M (frdm) ddr memory. For those we can have different fixed compile time base addresses for trusted OS. Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
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e9303a41 |
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07-Sep-2017 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: Fix MC reserved memory calculation In case high region memory doesn't have enough space for Management Complex (MC), the return value should indicate a failure so the caller can handle it accordingly. Signed-off-by: York Sun <york.sun@nxp.com> Reported-by: Ebony Zhu <ebony.zhu@nxp.com> |
#
17d066fc |
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31-Aug-2017 |
Ashish Kumar <Ashish.Kumar@nxp.com> |
armv8: fsl-layerscape: Support to add RGMII for ls1088aqds This patch adds support for RGMII protocol NXP's LDPAA2 support RGMII protocol. LS1088A is the first Soc supporting both RGMII and SGMII. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Amrita Kumari <amrita.kumari@nxp.com> Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
63b2316c |
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10-Aug-2017 |
Ashish Kumar <Ashish.Kumar@nxp.com> |
fsl-layerscape: Consolidate registers space defination for CCI-400 bus CoreLink Cache Coherent Interconnect (CCI) provides full cache coherency between two clusters of multi-core CPUs and I/O coherency for devices and I/O masters. This patch add new config option SYS_FSL_HAS_CCI400 and moves existing register space definaton of CCI-400 bus to fsl_immap to be shared. CONFIG_SYS_CCI400_ADDR is replaced with SYS_CCI400_OFFSET in Kconfig. Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> [YS: revised commit message, squashed patches for armv8 and armv7] Reviewed-by: York Sun <york.sun@nxp.com> |
#
6e2941d7 |
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17-May-2017 |
Simon Glass <sjg@chromium.org> |
common: freescale: Move arch-specific declarations The declarations should not be in common.h. Move them to the arch-specific headers. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Fixup thinko defined(FSL_LSCH3) -> defined(CONFIG_FSL_LSCH3)] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
399e2bb6 |
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15-May-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Make U-Boot EL2 safe When U-Boot boots from EL2, skip some lowlevel init code requiring EL3, including CCI-400/CCN-504, trust zone, GIC, etc. These initialization tasks are carried out before U-Boot runs. This applies to the RAM version image used for SPL boot if PPA is loaded first. Signed-off-by: York Sun <york.sun@nxp.com> |
#
1f55a938 |
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05-May-2017 |
Santan Kumar <santan.kumar@nxp.com> |
armv8: ls2080aqds: Add support for SD boot Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
e809e747 |
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27-Apr-2017 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: fsl-layerscape: Add NXP LS2081A, LS2041A SoC support The QorIQ LS2081A SoC has eight 64-bit ARM v8 Cortex A72 cores and is built on layerscape architecture. It is 40-pin derivative of LS2084A (non-AIOP personality of LS2088A). So feature-wise it is same as LS2084A. LS2041A is a 4-core personality of LS2081A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
026f30ec |
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18-Apr-2017 |
Yuantian Tang <andy.tang@nxp.com> |
arm: psci: make psci usable on single core socs PSCI can be used on both multiple and single core socs. Current implementation only allows PSCI to work on multiple core socs. This patch removes this restriction so that PSCI can work on single core socs as well. Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
4a3ab193 |
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27-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: ls2080a: Drop macro CONFIG_LS2080A Use CONFIG_ARCH_LS2080A instead. Signed-off-by: York Sun <york.sun@nxp.com> |
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3eace37e |
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06-Apr-2017 |
Simon Glass <sjg@chromium.org> |
arm: freescale: Rename initdram() to fsl_initdram() This function name shadows a global name but is in fact different. This is very confusing. Rename it to help with the following refactoring. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
76b00aca |
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31-Mar-2017 |
Simon Glass <sjg@chromium.org> |
board_f: Drop setup_dram_config() wrapper By making dram_init_banksize() return an error code we can drop the wrapper. Adjust this and clean up all implementations. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
088454cd |
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31-Mar-2017 |
Simon Glass <sjg@chromium.org> |
board_f: Drop return value from initdram() At present we cannot use this function as an init sequence call without a wrapper, since it returns the RAM size. Adjust it to set the RAM size in global_data instead, and return 0 on success. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> |
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52c41180 |
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31-Mar-2017 |
Simon Glass <sjg@chromium.org> |
board_f: Drop board_type parameter from initdram() It looks like only cm5200 and tqm8xx use this feature, so we don't really need it in generic code. Drop it and have the users access gd->board_type directly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
3d8553f0 |
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02-Mar-2017 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
pci: layerscape: add LS2088A series SoC pcie support The LS2088A series SoCs has different physical memory map address and CCSR registers address against LS2080A series SoCs. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
eea1cb77 |
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13-Feb-2017 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8/fsl-layerscape: Update erratum A009635 implementation Erratum A009635 is valid only for LS2080A SoC and its personality. Add SoC svr check. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
4961eafc |
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06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Update early MMU for DDR after initialization In early MMU table, DDR has to be mapped as device memory to avoid speculative access. After DDR is initialized, it needs to be updated to normal memory to allow code execution. To simplify the code, dram_init() is moved into a common file as a weak function. Signed-off-by: York Sun <york.sun@nxp.com> |
#
a045a0c3 |
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06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Fix the sequence of changing MMU table This patch follows the break-before-make process when making changes to MMU table. MMU is disabled before changing TTBR to avoid any potential race condition. Signed-off-by: York Sun <york.sun@nxp.com> |
#
24f55496 |
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06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Update MMU mapping with actual DDR size Update mapping with actual DDR size. Non-existing memory should not be mapped as "normal" memory to avoid speculative access. Signed-off-by: York Sun <york.sun@nxp.com> |
#
36cc0de0 |
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06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Rewrite memory reservation For ARMv8 Layerscape SoCs, secure memory and MC memorey are reserved at the end of DDR. DDR is spit into two or three banks. This patch reverts commit aabd7ddb and simplifies the calculation of reserved memory, and moves the code into common SoC file. Secure memory is carved out first. DDR bank size is reduced. Reserved memory is then allocated on the top of available memory. U-Boot still has access to reserved memory as data transferring is needed. Device tree is fixed with reduced memory size to hide the reserved memory from OS. The same region is reserved for efi_loader. Signed-off-by: York Sun <york.sun@nxp.com> |
#
daa92644 |
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16-Jan-2017 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
ARMv8/sec_firmware: relocated and renamed the config FSL_PPA_ARMV8_PSCI Moved the config FSL_PPA_ARMV8_PSCI from fsl-layerscape's Kconfig to Kconfig under armv8 and renamed it to SEC_FIRMWARE_ARMV8_PSCI. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
904110c7 |
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10-Jan-2017 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8/fsl-lsch2: refactor the clock system initialization Up to now, there are 3 kind of SoCs under Layerscape Chassis 2, like LS1043A, LS1046A and LS1012A. But the clocks tree has a lot of differences, for instance, the IP modules have different dividers to derive its clock from Platform PLL. And the core cluster PLL and platform PLL maybe have different reference clocks, such as LS1012A. Another problem is which clock/PLL should be described by sys_info->freq_systembus, it is confused in Layerscape Chissis 2. This patch is to bind the sys_info->freq_systembus to the Platform PLL, and handle the different divider of IP modules separately between different SoCs, and separate reference clocks of core cluster PLL and platform PLL. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
2d16a1a6 |
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07-Dec-2016 |
macro.wave.z@gmail.com <macro.wave.z@gmail.com> |
ARMv8: LS1043A: change macro CONFIG_ARMV8_PSCI definition NXP/Freescale uses macro CONFIG_ARMV8_PSCI to enable their private PSCI implementation in PPA firmware, but this macro naming too generic, so this patch replaces it with a specic one CONFIG_FSL_PPA_ARMV8_PSCI. And this macro CONFIG_ARMV8_PSCI will be used for a generic PSCI for ARMv8 which will be added in following patchs. Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
02fb2761 |
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20-Nov-2016 |
Shengzhou Liu <Shengzhou.Liu@nxp.com> |
fsl/ddr: Add erratum_a009942_check_cpo and clean related erratum - add additional function erratum_a009942_check_cpo to check if the board needs tuning CPO calibration for optimal setting. - move ERRATUM_A009942(with revision to check cpo_sample option) from fsl_ddr_gen4.c to ctrl_regs.c for reuse on all DDR4/DDR3 parts. - move ERRATUM_A008378 from fsl_ddr_gen4.c to ctrl_regs.c - remove obsolete ERRATUM_A004934 which is replaced with ERRATUM_A009942. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> [YS: Replaced CONFIG_QEMU_E500 with CONFIG_ARCH_QEMU_E500] Reviewed-by: York Sun <york.sun@nxp.com> |
#
e87c673c |
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16-Nov-2016 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8/fsl-lsch3: Update code to release secondary cores NXP ARMv8 SoC LS2080A release all secondary cores in one-go. But other new SoCs like LS2088A, LS1088A release secondary cores one by one. Update code to release secondary cores based on SoC SVR Add code to release cores one by one for non LS2080A SoCs Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> [YS: remove "inline" from declaration of initiator_type] Reviewed-by: York Sun <york.sun@nxp.com> |
#
f6b96ff6 |
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16-Nov-2016 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Use SVR based timer base address detection Timer controller base address has been changed from LS2080A SoC (and its personalities) to new SoCs like LS2088A, LS1088A. Use SVR based timer base address detection to avoid compile time #ifdef. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
f6a70b3a |
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16-Nov-2016 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add generic get_svr() in assembly Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
78d57842 |
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16-Nov-2016 |
Alexander Graf <agraf@csgraf.de> |
armv8: fsl-layerscape: Add support for efi_loader RTS reset When implementing efi loader support, we can expose runtime services for payloads. One such service is CPU reset. This patch implements RTS CPU reset support for layerscape systems. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: York Sun <york.sun@nxp.com> |
#
ef9a5fd8 |
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13-Sep-2016 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: Fix "cpu status" command The core position is not continuous for some SoCs. For example, valid cores may present at position 0, 1, 4, 5, 8, 9, etc. Some registers (including boot release register) only count existing cores. Current implementation of cpu_mask() complies with the continuous numbering. However, command "cpu status" queries the spin table with actual core position. Add functions to calculate core position from core number, to correctly calculate offsets. Tested on LS2080ARDB and LS1043ARDB. Signed-off-by: York Sun <york.sun@nxp.com> |
#
5d1a7a9d |
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13-Sep-2016 |
Wenbin Song <wenbin.song@nxp.com> |
armv8/fsl-layerscape: print SoC revsion number The exact SoC revsion number can be recognized from U-Boot log. Signed-off-by: Wenbin Song <wenbin.song@nxp.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
cbe7706a |
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26-Sep-2016 |
Tom Rini <trini@konsulko.com> |
Merge git://git.denx.de/u-boot-fsl-qoriq trini: Drop local memset() from examples/standalone/mem_to_mem_idma2intr.c Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
1221ce45 |
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20-Sep-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
treewide: replace #include <asm/errno.h> with <linux/errno.h> Now, arch/${ARCH}/include/asm/errno.h and include/linux/errno.h have the same content. (both just wrap <asm-generic/errno.h>) Replace all include directives for <asm/errno.h> with <linux/errno.h>. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> [trini: Fixup include/clk.] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
b63a9506 |
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03-Aug-2016 |
York Sun <york.sun@nxp.com> |
armv8: ls2080a: Remove debug server support Debug server feature has been dropped from roadmap. Signed-off-by: York Sun <york.sun@nxp.com> |
#
ed7a3943 |
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22-Jul-2016 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: mmu: Fix enabling MMU MMU bit in SCTLR needs to be set explicitly after tables are created. It isn't an issue for EL3 becuase this bit is already set by early MMU setup. But for other exception levels this bit was not set. Signed-off-by: York Sun <york.sun@nxp.com> |
#
79119a4d |
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05-Jul-2016 |
Alison Wang <b18965@freescale.com> |
armv8: fsl-layerscape: Add A72 core detection Add support to detect Cortex-A72 core for printing it out. The Initiator Version of A72 core should be 0x4. Signed-off-by: Alison Wang <alison.wang@nxp.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
032d5bb4 |
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28-Jun-2016 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
ARMv8/Layerscape: switch SMP method accordingly If the PSCI and PPA is ready, skip the fixup for spin-table and waking secondary cores. Otherwise, change SMP method to spin-table, and the device node of PSCI will be removed. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
85cdf38e |
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28-Jun-2016 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: fsl-layerscape: add i/d-cache enable function to enable_caches This function assume that the d-cache and MMU has been enabled earlier, so it just created MMU table in main memory. But the assumption is not always correct, for example, the early setup is done in EL3, while enable_caches() is called when the PE has turned into another EL. Define the function mmu_setup() for fsl-layerscape to cover the weak one. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
5ad5823d |
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24-Jun-2016 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Convert to use common MMU framework Drop platform code to create static MMU tables. Use common framework to create MMU tables on the run. Tested on LS2080ARDB with secure and non-secure ram scenarios. Signed-off-by: York Sun <york.sun@nxp.com> |
#
e61a7534 |
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24-Jun-2016 |
York Sun <york.sun@nxp.com> |
armv8: Move secure_ram variable out of generic global data Secure_ram variable was put in generic global data. But only ARMv8 uses this variable. Move it to ARM specific data structure. Signed-off-by: York Sun <york.sun@nxp.com> |
#
a10a31ec |
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18-Jun-2016 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of git://git.denx.de/u-boot-usb Signed-off-by: Tom Rini <trini@konsulko.com> Conflicts: arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
|
#
6fb522dc |
|
12-Jun-2016 |
Sriram Dash <sriram.dash@nxp.com> |
arm64: fsl-layerscape: add get_svr and IS_SVR_REV helper Adds get_svr and IS_SVR_REV helpers for ARMv8 platforms, similar to PPC and ARMv7. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> |
#
a758177f |
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07-Jun-2016 |
Yunhui Cui <yunhui.cui@nxp.com> |
armv8/ls2080a: configure PMU's PCTBENR to enable WDT The SP805-WDT module on LS2080A requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. The watchdog clock needs to be enabled first. Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
acb8f5e9 |
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21-Apr-2016 |
Alison Wang <b18965@freescale.com> |
armv8: fsl-layerscape: Remove unnecessary flushing dcache As the issue about the stack will get corrupted when switching between the early and final mmu tables is fixed by commit 70e21b064, the workaround to flush dcache is unnecessary and should be removed. Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
3c1d218a |
|
04-Apr-2016 |
York Sun <york.sun@nxp.com> |
armv8: LS2080A: Consolidate LS2080A and LS2085A LS2080A is the primary SoC, and LS2085A is a personality with AIOP and DPAA DDR. The RDB and QDS boards support both personality. By detecting the SVR at runtime, a single image per board can support both SoCs. It gives users flexibility to swtich SoC without the need to reprogram the board. Signed-off-by: York Sun <york.sun@nxp.com> CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
c05016ab |
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21-Mar-2016 |
Alexander Graf <agraf@csgraf.de> |
arm64: Fix layerscape mmu setup With commit 7985cdf we converted all systems except for the Layerscape SoCs to the generic descriptor table based page table setup. On the Layerscape SoCs however, we just provide an empty table stub and do the setup ourselves. To reserve enough memory for the tables, we need to override the default counting mechanism which would end up with an empty table because we have no maps. Fixes: 7985cdf Reported-by: York Sun <york.sun@nxp.com> CC: Alison Wang <alison.wang@nxp.com> CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Alexander Graf <agraf@suse.de> Tested-by: York Sun <york.sun@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
7985cdf7 |
|
03-Mar-2016 |
Alexander Graf <agraf@csgraf.de> |
arm64: Remove non-full-va map code By now the code to only have a single page table level with 64k page size and 42 bit address space is no longer used by any board in tree, so we can safely remove it. To clean up code, move the layerscape mmu code to the new defines, removing redundant field definitions. Signed-off-by: Alexander Graf <agraf@suse.de> |
#
c0492141 |
|
07-Dec-2015 |
York Sun <yorksun@freescale.com> |
armv8: fsl-layerscale: Rewrite reserving memory for MC and debug server MC and debug server are not board-specific. Move reserving memory to SoC file, using the new board_reserve_ram_top function. Reduce debug server memory by 2MB to make room for secure memory. In the system with MC and debug server, the top of u-boot memory is not the end of memory. PRAM is not used for this reservation. Signed-off-by: York Sun <yorksun@freescale.com> |
#
c107c0c0 |
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04-Dec-2015 |
York Sun <yorksun@freescale.com> |
armv8: fsl-layerscape: Make DDR non secure in MMU tables DDR has been set as secure in MMU tables. Non-secure master such as SDHC DMA cannot access data correctly. Mixing secure and non- secure MMU entries requirs the MMU tables themselves in secure memory. This patch moves MMU tables into a secure DDR area. Early MMU tables are changed to set DDR as non-secure. A new table is added into final MMU tables so secure memory can have 2MB granuality. gd->secure_ram tracks the location of this secure memory. For ARMv8 SoCs, the RAM base is not zero and RAM is divided into several banks. gd->secure_ram needs to be maintained before using. This maintenance is board-specific, depending on the SoC and memory bank of the secure memory falls into. Signed-off-by: York Sun <yorksun@freescale.com> |
#
b4017364 |
|
04-Nov-2015 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
armv8: ls2085a: Add workaround of errata A009635 If the core runs at higher than x3 speed of the platform, there is possiblity about sev instruction to getting missed by other cores. This is because of SoC Run Control block may not able to sample the EVENTI(Sev) signals. Configure Run Control and EPU to periodically send out EVENTI signals to wake up A57 cores. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
d764129d |
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04-Nov-2015 |
Alison Wang <b18965@freescale.com> |
armv8/layerscape: Update MMU table with execute-never bits For most device addresses excution shouldn't be allowed. Revise the MMU table to enforce execute-never bits. OCRAM, DDR and IFC are allowed for excution. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Alison Wang <alison.wang@freescale.com> Reported-by: Zhichun Hua <zhichun.hua@freescale.com> |
#
44937214 |
|
09-Nov-2015 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
armv8: LS2080A: Rename LS2085A to reflect LS2080A LS2080A is a prime personality of Freescale’s LS2085A. It is a non-AIOP personality without support of DP-DDR, L2 switch, 1588, PCIe endpoint etc. So renaming existing LS2085A code base to reflect LS2080A (Prime personality) Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> [York Sun: Dropped #ifdef in cpu.c for cpu_type_list] Reviewed-by: York Sun <yorksun@freescale.com> |
#
e8297341 |
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26-Oct-2015 |
Shaohui Xie <Shaohui.Xie@freescale.com> |
armv8/ls1043a: Add Fman support Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
8281c58f |
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26-Oct-2015 |
Mingkai Hu <Mingkai.Hu@freescale.com> |
armv8/fsl_lsch2: Add fsl_lsch2 SoC Freescale LayerScape with Chassis Generation 2 is a set of SoCs with ARMv8 cores and 2rd generation of Chassis. Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
9f3183d2 |
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26-Oct-2015 |
Mingkai Hu <Mingkai.Hu@freescale.com> |
armv8/fsl_lsch3: Change arch to fsl-layerscape There are two LS series processors are built on ARMv8 Layersacpe architecture currently, LS2085A and LS1043A. They are based on ARMv8 core although use different chassis, so create fsl-layerscape to refactor the common code for the LS series processors which also paves the way for adding LS1043A platform. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
3499dd03 |
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27-Nov-2019 |
Alex Marginean <alexandru.marginean@nxp.com> |
ls1028a: Configure stream IDs for integrated PCI and fix up Linux DT Hardware comes out of reset with implicit values, but these are outside the accepted range for Layerscape gen 3 chassis spec used on LS1028A. Allocate different IDs and fix up Linux DT to use them. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
b5981474 |
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14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some CPU functions out of common.h These functions belong in cpu_func.h since they do not use driver model. Move them over. Don't bother adding comments since these functions should be deleted. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
68a6aa85 |
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14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move mii_init() function out of common.h This function belongs in mii.h so move it over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
2189d5f1 |
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14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
Move strtomhz() to vsprintf.h At present this function sits in its own file but it does not really justify it. There are similar string functions in vsprintf.h, so move it there. Also add the missing function comment. Use the vsprintf.h include file explicitly where needed. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
812ff53c |
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30-Oct-2019 |
Pankaj Bansal <pankaj.bansal@nxp.com> |
fsl-layerscape: fix warning if no hwconfig is defined While getting the 'subarg' of 'hwconfig' env variable in config_core_prefetch(), if no hwconfig variable is defined, below warning is received: WARNING: Calling __hwconfig without a buffer and before environment is ready Fix this by checking 'hwconfig' env variable. If not found return without further processing. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Tested-by: Michael Walle <michael@walle.cc> |
#
28f9393b |
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17-Oct-2019 |
Mathew McBride <matt@traverse.com.au> |
fsl-layerscape: do not use layerscape EFI reset if PSCI used If the secure world reset handlers are used (via CONFIG_PSCI_RESET), then do not use the layerscape-specific implementation. Signed-off-by: Mathew McBride <matt@traverse.com.au> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
6ed69523 |
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18-Sep-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add more personalities support Add LS1027A, LS1018A and LS1017A personalities support to LS1028A SoC family. LS1028A is the prime personality of LS1028A SoC family. LS1027A is a lower funtionality version of QorIQ LS1028A which does not support the multimedia subsystems, such as LCD controller, GPU, and eDP PHY. The QorIQ LS1018A and LS1017A SoCs are single 64-bit Arm A72 core, low power versions of the QorIQ LS1028A and LS1027A SoCs respectively. Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
0490cab5 |
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08-Aug-2019 |
Thomas Schaefer <thomas.schaefer@kontron.com> |
armv8: ls1028a: configure PMU's PCTBENR to enable WDT The SP805-WDT module on LS1028A requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. The watchdog clock needs to be enabled first. Signed-off-by: Thomas Schaefer <thomas.schaefer@kontron.com> Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
f3998fdc |
|
02-Aug-2019 |
Simon Glass <sjg@chromium.org> |
env: Rename environment.h to env_internal.h This file contains lots of internal details about the environment. Most code can include env.h instead, calling the functions there as needed. Rename this file and add a comment at the top to indicate its internal nature. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> [trini: Fixup apalis-tk1.c] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
3a7d5571 |
|
01-Aug-2019 |
Simon Glass <sjg@chromium.org> |
env: Move env_get_f() to env.h Move this function over to the new header file. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
d9532e80 |
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23-Apr-2019 |
Udit Agarwal <udit.agarwal@nxp.com> |
armv8: fsl-layerscape: Set env_loc to ENVL_NOWHERE with CONFIG_ENV_IS_NOWHERE. ENVL_NOWHERE is dependent on CONFIG_ENV_IS_NOWHERE and not on CONFIG_CHAIN_OF_TRUST so return ENVL_NOWHERE when CONFIG_ENV_IS_NOWHERE is enabled Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
059d9422 |
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08-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: lx2160a: add MMU table entries for PCIe The lx2160a have up to 6 PCIe controllers and have different address and size of PCIe region. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
8348e798 |
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08-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: layerscape: use PCIe address macro for precompile PCIe MMU entry Change to use PCIe address macro to determine if precompile the PCIe MMU table entry. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
10015025 |
|
03-May-2019 |
Trevor Woerner <trevor@toganlabs.com> |
CONFIG_SPL_SYS_[DI]CACHE_OFF: add While converting CONFIG_SYS_[DI]CACHE_OFF to Kconfig, there are instances where these configuration items are conditional on SPL. This commit adds SPL variants of these configuration items, uses CONFIG_IS_ENABLED(), and updates the configurations as required. Acked-by: Alexey Brodkin <abrodkin@synopsys.com> Signed-off-by: Trevor Woerner <trevor@toganlabs.com> [trini: Make the default depend on the setting for full U-Boot, update more zynq hardware] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
2e53759d |
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29-Oct-2018 |
Pankaj Bansal <pankaj.bansal@nxp.com> |
armv8: fsl-layerscape: reorder rgmii dpmacs' enablement some dpmacs in armv8a based freescale layerscape SOCs can be configured via both serdes(sgmii, xfi, xlaui etc) bits and via EC*_PMUX(rgmii) bits in RCW. e.g. dpmac 17 and 18 in LX2160A can be configured as SGMII from serdes bits and as RGMII via EC1_PMUX/EC2_PMUX bits Now if a dpmac is enabled by serdes bits then it takes precedence over EC*_PMUX bits. i.e. in LX2160A if we select serdes protocol that configures dpmac17 as SGMII and set the EC1_PMUX as RGMII, then the dpmac is SGMII and not RGMII. Therefore, move the fsl_rgmii_init after fsl_serdes_init. in fsl_rgmii_init function of SOC, we will check if the dpmac is enabled or not? if it is (fsl_serdes_init has already enabled the dpmac), then don't enable it. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
ec88ff80 |
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19-Dec-2018 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1043a: add SVR definitions for 23x23 package silicon LS1043A/LS1023A 23x23 package silicon has different SVR:VAR_PER. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
d23da2ae |
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26-Dec-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: fixes for TFABOOT framework Fixes for TFABOOT framework - update eMMC bootsrc to SD_MMC - Increase buffer size for mcinitcmd from 256 to 512 - Fix mcinitcmd and bootcmd for Secure Boot Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
4909b89e |
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29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
d6fdec21 |
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29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8:fsl-layerscape: Add support for Chassis 3.2 NXP layerscape architecture Chassis 3.2 builds upon chassis3 architecture with changes like DDR Memory map change, removal of IFC and support of upto 8 I2C controller. Patch add README.lsch3_2 and the above changes under macro CONFIG_NXP_LSCH3_2. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
56db948b |
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05-Nov-2018 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: Update parsing boot source Workaround of erratum A010539 clears the RCW source field in PORSR1 register, causing failure of detecting boot source using this method. Use SMC call if U-Boot runs at EL2. If SMC is not implemented or running at EL3, continue to read PORSR1 and presume QSPI as boot source if erratum workaround A010539 is enabled and RCW source is cleared. Signed-off-by: York Sun <york.sun@nxp.com> |
#
681d489e |
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05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: layerscape: add SMC calls for DDR size and bank info Adds SMC calls for getting DDR size and bank info for TFABOOT. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
2141d250 |
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05-Nov-2018 |
Pankit Garg <pankit.garg@nxp.com> |
armv8: fsl-layerscape: bootcmd identification for TFABOOT Adds bootcmd identificaton on basis on boot source, valid in TFABOOT configuration. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> [YS: remove unnecessary braces] Reviewed-by: York Sun <york.sun@nxp.com> |
#
4c417384 |
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05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com> |
#
535d76a1 |
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05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: layerscape: Add TFABOOT support Adds TFABOOT support config option and add generic code to enable execution from DDR. Signed-off-by: York Sun <york.sun@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> |
#
e3506480 |
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05-Nov-2018 |
Pankit Garg <pankit.garg@nxp.com> |
armv8: fsl-layerscape: change tlb base from OCRAM to DDR in EL < 3 Change tlb base address from OCRAM to DDR when exception level is less than 3. Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
d171c707 |
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05-Nov-2018 |
York Sun <york.sun@nxp.com> |
move data structure out of cpu.h Move static definitions to cpu.c file, as it doesn't allow the cpu.h file to be included in multiple c files. Signed-off-by: York Sun <york.sun@nxp.com> |
#
9b5e6396 |
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30-Aug-2018 |
Stephen Warren <swarren@nvidia.com> |
efi_loader: simplify ifdefs Use CONFIG_IS_ENABLED(EFI_LOADER) to avoid explicitly checking CONFIG_SPL too. This simplifies the conditional. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Alexander Graf <agraf@suse.de> |
#
9cce5663 |
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16-Jul-2018 |
Joe Hershberger <joe.hershberger@ni.com> |
arm: Prevent redefinition error in fsl-layerscape The include/phy.h will start including dm.h, which pulls in linux/compat.h after the attempted redefinition in arch/arm/include/asm/armv8/mmu.h, so move this include to allow redefinition. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> |
#
83d290c5 |
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06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
482fc90c |
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06-Feb-2018 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
efi_loader: add missing EFI_RESET_PLATFORM_SPECIFIC EFI_RESET_PLATFORM_SPECIFIC is one of the values that can be used for the EFI service ResetSystem. The missing definition is added. The value has to handled in efi_reset_system(). Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Alexander Graf <agraf@suse.de> |
#
22c793e6 |
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03-Mar-2018 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
efi_loader: exit status for efi_reset_system_init efi_reset_system_init provides the architecture or board specific initialization of the EFI subsystem. Errors should be caught and signalled by a return code. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Alexander Graf <agraf@suse.de> |
#
958b2ed5 |
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09-Jan-2018 |
Zhang Ying-22455 <ying.zhang22455@nxp.com> |
armv8/ls1088a: configure PMU's PCTBENR to enable WDT The SP805-WDT module on LS1088A requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. The watchdog clock needs to be enabled first. Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
44262327 |
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15-Dec-2017 |
Ahmed Mansour <ahmed.mansour@nxp.com> |
drivers/misc: Share qbman init between archs This patch adds changes necessary to move functionality present in PowerPC folders with ARM architectures that have DPAA1 QBMan hardware - Create new board/freescale/common/fsl_portals.c to house shared device tree fixups for DPAA1 devices with ARM and PowerPC cores - Add new header file to top includes directory to allow files in both architectures to grab the function prototypes - Port inhibit_portals() from PowerPC to ARM. This function is used in setup to disable interrupts on all QMan and BMan portals. It is needed because the interrupts are enabled by default for all portals including unused/uninitialised portals. When the kernel attempts to go to deep sleep the unused portals prevent it from doing so Signed-off-by: Ahmed Mansour <ahmed.mansour@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
a8f33034 |
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03-Dec-2017 |
Wenbin song <wenbin.song@nxp.com> |
armv8: ls1043a/ls2080a: check SoC by device ID Check LS1043A/LS2080a by device ID without using personality ID to determine revision number. This check applies to all various personalities of the same SoC family. Signed-off-by: Wenbin Song <wenbin.song@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
2db53cfe |
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09-Nov-2017 |
Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
armv8: fsl-layerscape: Add support of disabling core prefetch Instruction prefetch feature is by default enabled during core release. This patch add support of disabling instruction prefetch by setting core mask in PPA. Here each core mask bit represents a core and prefetch is disabled at the time of core release. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
7eb40f0f |
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28-Sep-2017 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: Avoid running dram_init_banksize again gd->ram_size is reduced in this function to reserve secure memory. Avoid running this function again to further reduce memory size. This fixes issue for SPL boot with PPA image loaded in which case secure memory is incorrectly allocated due to repeated calling. Signed-off-by: York Sun <york.sun@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
710d0cd7 |
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03-Oct-2017 |
Sumit Garg <sumit.garg@nxp.com> |
armv8: fsl-layerscape: Allocate Secure memory from first ddr region This change is required due to trusted OS (OP-TEE) not being position independent code, it requires compile time fixed base address. To take care of this it is assumed that all layerscape armv8 platforms has minimum 2G ddr in first region. So we can have fixed address space (66 MB -> (2MB for PPA + 64MB for trusted OS)) allocated from top of first 2G ddr region and compile trusted OS with this fixed base address. But one exception here is ls1012 where we have only 1G (rdb) or 512M (frdm) ddr memory. For those we can have different fixed compile time base addresses for trusted OS. Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
e9303a41 |
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07-Sep-2017 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: Fix MC reserved memory calculation In case high region memory doesn't have enough space for Management Complex (MC), the return value should indicate a failure so the caller can handle it accordingly. Signed-off-by: York Sun <york.sun@nxp.com> Reported-by: Ebony Zhu <ebony.zhu@nxp.com> |
#
17d066fc |
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31-Aug-2017 |
Ashish Kumar <Ashish.Kumar@nxp.com> |
armv8: fsl-layerscape: Support to add RGMII for ls1088aqds This patch adds support for RGMII protocol NXP's LDPAA2 support RGMII protocol. LS1088A is the first Soc supporting both RGMII and SGMII. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Amrita Kumari <amrita.kumari@nxp.com> Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
63b2316c |
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10-Aug-2017 |
Ashish Kumar <Ashish.Kumar@nxp.com> |
fsl-layerscape: Consolidate registers space defination for CCI-400 bus CoreLink Cache Coherent Interconnect (CCI) provides full cache coherency between two clusters of multi-core CPUs and I/O coherency for devices and I/O masters. This patch add new config option SYS_FSL_HAS_CCI400 and moves existing register space definaton of CCI-400 bus to fsl_immap to be shared. CONFIG_SYS_CCI400_ADDR is replaced with SYS_CCI400_OFFSET in Kconfig. Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> [YS: revised commit message, squashed patches for armv8 and armv7] Reviewed-by: York Sun <york.sun@nxp.com> |
#
6e2941d7 |
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17-May-2017 |
Simon Glass <sjg@chromium.org> |
common: freescale: Move arch-specific declarations The declarations should not be in common.h. Move them to the arch-specific headers. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Fixup thinko defined(FSL_LSCH3) -> defined(CONFIG_FSL_LSCH3)] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
399e2bb6 |
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15-May-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Make U-Boot EL2 safe When U-Boot boots from EL2, skip some lowlevel init code requiring EL3, including CCI-400/CCN-504, trust zone, GIC, etc. These initialization tasks are carried out before U-Boot runs. This applies to the RAM version image used for SPL boot if PPA is loaded first. Signed-off-by: York Sun <york.sun@nxp.com> |
#
1f55a938 |
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05-May-2017 |
Santan Kumar <santan.kumar@nxp.com> |
armv8: ls2080aqds: Add support for SD boot Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
e809e747 |
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27-Apr-2017 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: fsl-layerscape: Add NXP LS2081A, LS2041A SoC support The QorIQ LS2081A SoC has eight 64-bit ARM v8 Cortex A72 cores and is built on layerscape architecture. It is 40-pin derivative of LS2084A (non-AIOP personality of LS2088A). So feature-wise it is same as LS2084A. LS2041A is a 4-core personality of LS2081A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
026f30ec |
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18-Apr-2017 |
Yuantian Tang <andy.tang@nxp.com> |
arm: psci: make psci usable on single core socs PSCI can be used on both multiple and single core socs. Current implementation only allows PSCI to work on multiple core socs. This patch removes this restriction so that PSCI can work on single core socs as well. Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
4a3ab193 |
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27-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: ls2080a: Drop macro CONFIG_LS2080A Use CONFIG_ARCH_LS2080A instead. Signed-off-by: York Sun <york.sun@nxp.com> |
#
3eace37e |
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06-Apr-2017 |
Simon Glass <sjg@chromium.org> |
arm: freescale: Rename initdram() to fsl_initdram() This function name shadows a global name but is in fact different. This is very confusing. Rename it to help with the following refactoring. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
76b00aca |
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31-Mar-2017 |
Simon Glass <sjg@chromium.org> |
board_f: Drop setup_dram_config() wrapper By making dram_init_banksize() return an error code we can drop the wrapper. Adjust this and clean up all implementations. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
088454cd |
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31-Mar-2017 |
Simon Glass <sjg@chromium.org> |
board_f: Drop return value from initdram() At present we cannot use this function as an init sequence call without a wrapper, since it returns the RAM size. Adjust it to set the RAM size in global_data instead, and return 0 on success. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
52c41180 |
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31-Mar-2017 |
Simon Glass <sjg@chromium.org> |
board_f: Drop board_type parameter from initdram() It looks like only cm5200 and tqm8xx use this feature, so we don't really need it in generic code. Drop it and have the users access gd->board_type directly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
3d8553f0 |
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02-Mar-2017 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
pci: layerscape: add LS2088A series SoC pcie support The LS2088A series SoCs has different physical memory map address and CCSR registers address against LS2080A series SoCs. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
eea1cb77 |
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13-Feb-2017 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8/fsl-layerscape: Update erratum A009635 implementation Erratum A009635 is valid only for LS2080A SoC and its personality. Add SoC svr check. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
4961eafc |
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06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Update early MMU for DDR after initialization In early MMU table, DDR has to be mapped as device memory to avoid speculative access. After DDR is initialized, it needs to be updated to normal memory to allow code execution. To simplify the code, dram_init() is moved into a common file as a weak function. Signed-off-by: York Sun <york.sun@nxp.com> |
#
a045a0c3 |
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06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Fix the sequence of changing MMU table This patch follows the break-before-make process when making changes to MMU table. MMU is disabled before changing TTBR to avoid any potential race condition. Signed-off-by: York Sun <york.sun@nxp.com> |
#
24f55496 |
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06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Update MMU mapping with actual DDR size Update mapping with actual DDR size. Non-existing memory should not be mapped as "normal" memory to avoid speculative access. Signed-off-by: York Sun <york.sun@nxp.com> |
#
36cc0de0 |
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06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Rewrite memory reservation For ARMv8 Layerscape SoCs, secure memory and MC memorey are reserved at the end of DDR. DDR is spit into two or three banks. This patch reverts commit aabd7ddb and simplifies the calculation of reserved memory, and moves the code into common SoC file. Secure memory is carved out first. DDR bank size is reduced. Reserved memory is then allocated on the top of available memory. U-Boot still has access to reserved memory as data transferring is needed. Device tree is fixed with reduced memory size to hide the reserved memory from OS. The same region is reserved for efi_loader. Signed-off-by: York Sun <york.sun@nxp.com> |
#
daa92644 |
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16-Jan-2017 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
ARMv8/sec_firmware: relocated and renamed the config FSL_PPA_ARMV8_PSCI Moved the config FSL_PPA_ARMV8_PSCI from fsl-layerscape's Kconfig to Kconfig under armv8 and renamed it to SEC_FIRMWARE_ARMV8_PSCI. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
904110c7 |
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10-Jan-2017 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8/fsl-lsch2: refactor the clock system initialization Up to now, there are 3 kind of SoCs under Layerscape Chassis 2, like LS1043A, LS1046A and LS1012A. But the clocks tree has a lot of differences, for instance, the IP modules have different dividers to derive its clock from Platform PLL. And the core cluster PLL and platform PLL maybe have different reference clocks, such as LS1012A. Another problem is which clock/PLL should be described by sys_info->freq_systembus, it is confused in Layerscape Chissis 2. This patch is to bind the sys_info->freq_systembus to the Platform PLL, and handle the different divider of IP modules separately between different SoCs, and separate reference clocks of core cluster PLL and platform PLL. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
2d16a1a6 |
|
07-Dec-2016 |
macro.wave.z@gmail.com <macro.wave.z@gmail.com> |
ARMv8: LS1043A: change macro CONFIG_ARMV8_PSCI definition NXP/Freescale uses macro CONFIG_ARMV8_PSCI to enable their private PSCI implementation in PPA firmware, but this macro naming too generic, so this patch replaces it with a specic one CONFIG_FSL_PPA_ARMV8_PSCI. And this macro CONFIG_ARMV8_PSCI will be used for a generic PSCI for ARMv8 which will be added in following patchs. Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
02fb2761 |
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20-Nov-2016 |
Shengzhou Liu <Shengzhou.Liu@nxp.com> |
fsl/ddr: Add erratum_a009942_check_cpo and clean related erratum - add additional function erratum_a009942_check_cpo to check if the board needs tuning CPO calibration for optimal setting. - move ERRATUM_A009942(with revision to check cpo_sample option) from fsl_ddr_gen4.c to ctrl_regs.c for reuse on all DDR4/DDR3 parts. - move ERRATUM_A008378 from fsl_ddr_gen4.c to ctrl_regs.c - remove obsolete ERRATUM_A004934 which is replaced with ERRATUM_A009942. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> [YS: Replaced CONFIG_QEMU_E500 with CONFIG_ARCH_QEMU_E500] Reviewed-by: York Sun <york.sun@nxp.com> |
#
e87c673c |
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16-Nov-2016 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8/fsl-lsch3: Update code to release secondary cores NXP ARMv8 SoC LS2080A release all secondary cores in one-go. But other new SoCs like LS2088A, LS1088A release secondary cores one by one. Update code to release secondary cores based on SoC SVR Add code to release cores one by one for non LS2080A SoCs Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> [YS: remove "inline" from declaration of initiator_type] Reviewed-by: York Sun <york.sun@nxp.com> |
#
f6b96ff6 |
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16-Nov-2016 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Use SVR based timer base address detection Timer controller base address has been changed from LS2080A SoC (and its personalities) to new SoCs like LS2088A, LS1088A. Use SVR based timer base address detection to avoid compile time #ifdef. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
f6a70b3a |
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16-Nov-2016 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add generic get_svr() in assembly Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
78d57842 |
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16-Nov-2016 |
Alexander Graf <agraf@csgraf.de> |
armv8: fsl-layerscape: Add support for efi_loader RTS reset When implementing efi loader support, we can expose runtime services for payloads. One such service is CPU reset. This patch implements RTS CPU reset support for layerscape systems. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: York Sun <york.sun@nxp.com> |
#
ef9a5fd8 |
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13-Sep-2016 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: Fix "cpu status" command The core position is not continuous for some SoCs. For example, valid cores may present at position 0, 1, 4, 5, 8, 9, etc. Some registers (including boot release register) only count existing cores. Current implementation of cpu_mask() complies with the continuous numbering. However, command "cpu status" queries the spin table with actual core position. Add functions to calculate core position from core number, to correctly calculate offsets. Tested on LS2080ARDB and LS1043ARDB. Signed-off-by: York Sun <york.sun@nxp.com> |
#
5d1a7a9d |
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13-Sep-2016 |
Wenbin Song <wenbin.song@nxp.com> |
armv8/fsl-layerscape: print SoC revsion number The exact SoC revsion number can be recognized from U-Boot log. Signed-off-by: Wenbin Song <wenbin.song@nxp.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
cbe7706a |
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26-Sep-2016 |
Tom Rini <trini@konsulko.com> |
Merge git://git.denx.de/u-boot-fsl-qoriq trini: Drop local memset() from examples/standalone/mem_to_mem_idma2intr.c Signed-off-by: Tom Rini <trini@konsulko.com>
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#
1221ce45 |
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20-Sep-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
treewide: replace #include <asm/errno.h> with <linux/errno.h> Now, arch/${ARCH}/include/asm/errno.h and include/linux/errno.h have the same content. (both just wrap <asm-generic/errno.h>) Replace all include directives for <asm/errno.h> with <linux/errno.h>. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> [trini: Fixup include/clk.] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
b63a9506 |
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03-Aug-2016 |
York Sun <york.sun@nxp.com> |
armv8: ls2080a: Remove debug server support Debug server feature has been dropped from roadmap. Signed-off-by: York Sun <york.sun@nxp.com> |
#
ed7a3943 |
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22-Jul-2016 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: mmu: Fix enabling MMU MMU bit in SCTLR needs to be set explicitly after tables are created. It isn't an issue for EL3 becuase this bit is already set by early MMU setup. But for other exception levels this bit was not set. Signed-off-by: York Sun <york.sun@nxp.com> |
#
79119a4d |
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05-Jul-2016 |
Alison Wang <b18965@freescale.com> |
armv8: fsl-layerscape: Add A72 core detection Add support to detect Cortex-A72 core for printing it out. The Initiator Version of A72 core should be 0x4. Signed-off-by: Alison Wang <alison.wang@nxp.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
032d5bb4 |
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28-Jun-2016 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
ARMv8/Layerscape: switch SMP method accordingly If the PSCI and PPA is ready, skip the fixup for spin-table and waking secondary cores. Otherwise, change SMP method to spin-table, and the device node of PSCI will be removed. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
85cdf38e |
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28-Jun-2016 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: fsl-layerscape: add i/d-cache enable function to enable_caches This function assume that the d-cache and MMU has been enabled earlier, so it just created MMU table in main memory. But the assumption is not always correct, for example, the early setup is done in EL3, while enable_caches() is called when the PE has turned into another EL. Define the function mmu_setup() for fsl-layerscape to cover the weak one. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
5ad5823d |
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24-Jun-2016 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Convert to use common MMU framework Drop platform code to create static MMU tables. Use common framework to create MMU tables on the run. Tested on LS2080ARDB with secure and non-secure ram scenarios. Signed-off-by: York Sun <york.sun@nxp.com> |
#
e61a7534 |
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24-Jun-2016 |
York Sun <york.sun@nxp.com> |
armv8: Move secure_ram variable out of generic global data Secure_ram variable was put in generic global data. But only ARMv8 uses this variable. Move it to ARM specific data structure. Signed-off-by: York Sun <york.sun@nxp.com> |
#
a10a31ec |
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18-Jun-2016 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of git://git.denx.de/u-boot-usb Signed-off-by: Tom Rini <trini@konsulko.com> Conflicts: arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
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#
6fb522dc |
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12-Jun-2016 |
Sriram Dash <sriram.dash@nxp.com> |
arm64: fsl-layerscape: add get_svr and IS_SVR_REV helper Adds get_svr and IS_SVR_REV helpers for ARMv8 platforms, similar to PPC and ARMv7. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> |
#
a758177f |
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07-Jun-2016 |
Yunhui Cui <yunhui.cui@nxp.com> |
armv8/ls2080a: configure PMU's PCTBENR to enable WDT The SP805-WDT module on LS2080A requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. The watchdog clock needs to be enabled first. Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
acb8f5e9 |
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21-Apr-2016 |
Alison Wang <b18965@freescale.com> |
armv8: fsl-layerscape: Remove unnecessary flushing dcache As the issue about the stack will get corrupted when switching between the early and final mmu tables is fixed by commit 70e21b064, the workaround to flush dcache is unnecessary and should be removed. Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
3c1d218a |
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04-Apr-2016 |
York Sun <york.sun@nxp.com> |
armv8: LS2080A: Consolidate LS2080A and LS2085A LS2080A is the primary SoC, and LS2085A is a personality with AIOP and DPAA DDR. The RDB and QDS boards support both personality. By detecting the SVR at runtime, a single image per board can support both SoCs. It gives users flexibility to swtich SoC without the need to reprogram the board. Signed-off-by: York Sun <york.sun@nxp.com> CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
c05016ab |
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21-Mar-2016 |
Alexander Graf <agraf@csgraf.de> |
arm64: Fix layerscape mmu setup With commit 7985cdf we converted all systems except for the Layerscape SoCs to the generic descriptor table based page table setup. On the Layerscape SoCs however, we just provide an empty table stub and do the setup ourselves. To reserve enough memory for the tables, we need to override the default counting mechanism which would end up with an empty table because we have no maps. Fixes: 7985cdf Reported-by: York Sun <york.sun@nxp.com> CC: Alison Wang <alison.wang@nxp.com> CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Alexander Graf <agraf@suse.de> Tested-by: York Sun <york.sun@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
7985cdf7 |
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03-Mar-2016 |
Alexander Graf <agraf@csgraf.de> |
arm64: Remove non-full-va map code By now the code to only have a single page table level with 64k page size and 42 bit address space is no longer used by any board in tree, so we can safely remove it. To clean up code, move the layerscape mmu code to the new defines, removing redundant field definitions. Signed-off-by: Alexander Graf <agraf@suse.de> |
#
c0492141 |
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07-Dec-2015 |
York Sun <yorksun@freescale.com> |
armv8: fsl-layerscale: Rewrite reserving memory for MC and debug server MC and debug server are not board-specific. Move reserving memory to SoC file, using the new board_reserve_ram_top function. Reduce debug server memory by 2MB to make room for secure memory. In the system with MC and debug server, the top of u-boot memory is not the end of memory. PRAM is not used for this reservation. Signed-off-by: York Sun <yorksun@freescale.com> |
#
c107c0c0 |
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04-Dec-2015 |
York Sun <yorksun@freescale.com> |
armv8: fsl-layerscape: Make DDR non secure in MMU tables DDR has been set as secure in MMU tables. Non-secure master such as SDHC DMA cannot access data correctly. Mixing secure and non- secure MMU entries requirs the MMU tables themselves in secure memory. This patch moves MMU tables into a secure DDR area. Early MMU tables are changed to set DDR as non-secure. A new table is added into final MMU tables so secure memory can have 2MB granuality. gd->secure_ram tracks the location of this secure memory. For ARMv8 SoCs, the RAM base is not zero and RAM is divided into several banks. gd->secure_ram needs to be maintained before using. This maintenance is board-specific, depending on the SoC and memory bank of the secure memory falls into. Signed-off-by: York Sun <yorksun@freescale.com> |
#
b4017364 |
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04-Nov-2015 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
armv8: ls2085a: Add workaround of errata A009635 If the core runs at higher than x3 speed of the platform, there is possiblity about sev instruction to getting missed by other cores. This is because of SoC Run Control block may not able to sample the EVENTI(Sev) signals. Configure Run Control and EPU to periodically send out EVENTI signals to wake up A57 cores. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
d764129d |
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04-Nov-2015 |
Alison Wang <b18965@freescale.com> |
armv8/layerscape: Update MMU table with execute-never bits For most device addresses excution shouldn't be allowed. Revise the MMU table to enforce execute-never bits. OCRAM, DDR and IFC are allowed for excution. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Alison Wang <alison.wang@freescale.com> Reported-by: Zhichun Hua <zhichun.hua@freescale.com> |
#
44937214 |
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09-Nov-2015 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
armv8: LS2080A: Rename LS2085A to reflect LS2080A LS2080A is a prime personality of Freescale’s LS2085A. It is a non-AIOP personality without support of DP-DDR, L2 switch, 1588, PCIe endpoint etc. So renaming existing LS2085A code base to reflect LS2080A (Prime personality) Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> [York Sun: Dropped #ifdef in cpu.c for cpu_type_list] Reviewed-by: York Sun <yorksun@freescale.com> |
#
e8297341 |
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26-Oct-2015 |
Shaohui Xie <Shaohui.Xie@freescale.com> |
armv8/ls1043a: Add Fman support Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
8281c58f |
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26-Oct-2015 |
Mingkai Hu <Mingkai.Hu@freescale.com> |
armv8/fsl_lsch2: Add fsl_lsch2 SoC Freescale LayerScape with Chassis Generation 2 is a set of SoCs with ARMv8 cores and 2rd generation of Chassis. Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
9f3183d2 |
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26-Oct-2015 |
Mingkai Hu <Mingkai.Hu@freescale.com> |
armv8/fsl_lsch3: Change arch to fsl-layerscape There are two LS series processors are built on ARMv8 Layersacpe architecture currently, LS2085A and LS1043A. They are based on ARMv8 core although use different chassis, so create fsl-layerscape to refactor the common code for the LS series processors which also paves the way for adding LS1043A platform. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
b5981474 |
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14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some CPU functions out of common.h These functions belong in cpu_func.h since they do not use driver model. Move them over. Don't bother adding comments since these functions should be deleted. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
68a6aa85 |
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14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move mii_init() function out of common.h This function belongs in mii.h so move it over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
2189d5f1 |
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14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
Move strtomhz() to vsprintf.h At present this function sits in its own file but it does not really justify it. There are similar string functions in vsprintf.h, so move it there. Also add the missing function comment. Use the vsprintf.h include file explicitly where needed. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
812ff53c |
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30-Oct-2019 |
Pankaj Bansal <pankaj.bansal@nxp.com> |
fsl-layerscape: fix warning if no hwconfig is defined While getting the 'subarg' of 'hwconfig' env variable in config_core_prefetch(), if no hwconfig variable is defined, below warning is received: WARNING: Calling __hwconfig without a buffer and before environment is ready Fix this by checking 'hwconfig' env variable. If not found return without further processing. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Tested-by: Michael Walle <michael@walle.cc> |
#
28f9393b |
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17-Oct-2019 |
Mathew McBride <matt@traverse.com.au> |
fsl-layerscape: do not use layerscape EFI reset if PSCI used If the secure world reset handlers are used (via CONFIG_PSCI_RESET), then do not use the layerscape-specific implementation. Signed-off-by: Mathew McBride <matt@traverse.com.au> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
6ed69523 |
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18-Sep-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add more personalities support Add LS1027A, LS1018A and LS1017A personalities support to LS1028A SoC family. LS1028A is the prime personality of LS1028A SoC family. LS1027A is a lower funtionality version of QorIQ LS1028A which does not support the multimedia subsystems, such as LCD controller, GPU, and eDP PHY. The QorIQ LS1018A and LS1017A SoCs are single 64-bit Arm A72 core, low power versions of the QorIQ LS1028A and LS1027A SoCs respectively. Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
0490cab5 |
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08-Aug-2019 |
Thomas Schaefer <thomas.schaefer@kontron.com> |
armv8: ls1028a: configure PMU's PCTBENR to enable WDT The SP805-WDT module on LS1028A requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. The watchdog clock needs to be enabled first. Signed-off-by: Thomas Schaefer <thomas.schaefer@kontron.com> Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
f3998fdc |
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02-Aug-2019 |
Simon Glass <sjg@chromium.org> |
env: Rename environment.h to env_internal.h This file contains lots of internal details about the environment. Most code can include env.h instead, calling the functions there as needed. Rename this file and add a comment at the top to indicate its internal nature. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> [trini: Fixup apalis-tk1.c] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
3a7d5571 |
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01-Aug-2019 |
Simon Glass <sjg@chromium.org> |
env: Move env_get_f() to env.h Move this function over to the new header file. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
d9532e80 |
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23-Apr-2019 |
Udit Agarwal <udit.agarwal@nxp.com> |
armv8: fsl-layerscape: Set env_loc to ENVL_NOWHERE with CONFIG_ENV_IS_NOWHERE. ENVL_NOWHERE is dependent on CONFIG_ENV_IS_NOWHERE and not on CONFIG_CHAIN_OF_TRUST so return ENVL_NOWHERE when CONFIG_ENV_IS_NOWHERE is enabled Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
d4ad111d |
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10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
059d9422 |
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08-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: lx2160a: add MMU table entries for PCIe The lx2160a have up to 6 PCIe controllers and have different address and size of PCIe region. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
8348e798 |
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08-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: layerscape: use PCIe address macro for precompile PCIe MMU entry Change to use PCIe address macro to determine if precompile the PCIe MMU table entry. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
10015025 |
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03-May-2019 |
Trevor Woerner <trevor@toganlabs.com> |
CONFIG_SPL_SYS_[DI]CACHE_OFF: add While converting CONFIG_SYS_[DI]CACHE_OFF to Kconfig, there are instances where these configuration items are conditional on SPL. This commit adds SPL variants of these configuration items, uses CONFIG_IS_ENABLED(), and updates the configurations as required. Acked-by: Alexey Brodkin <abrodkin@synopsys.com> Signed-off-by: Trevor Woerner <trevor@toganlabs.com> [trini: Make the default depend on the setting for full U-Boot, update more zynq hardware] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
2e53759d |
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29-Oct-2018 |
Pankaj Bansal <pankaj.bansal@nxp.com> |
armv8: fsl-layerscape: reorder rgmii dpmacs' enablement some dpmacs in armv8a based freescale layerscape SOCs can be configured via both serdes(sgmii, xfi, xlaui etc) bits and via EC*_PMUX(rgmii) bits in RCW. e.g. dpmac 17 and 18 in LX2160A can be configured as SGMII from serdes bits and as RGMII via EC1_PMUX/EC2_PMUX bits Now if a dpmac is enabled by serdes bits then it takes precedence over EC*_PMUX bits. i.e. in LX2160A if we select serdes protocol that configures dpmac17 as SGMII and set the EC1_PMUX as RGMII, then the dpmac is SGMII and not RGMII. Therefore, move the fsl_rgmii_init after fsl_serdes_init. in fsl_rgmii_init function of SOC, we will check if the dpmac is enabled or not? if it is (fsl_serdes_init has already enabled the dpmac), then don't enable it. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
ec88ff80 |
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19-Dec-2018 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1043a: add SVR definitions for 23x23 package silicon LS1043A/LS1023A 23x23 package silicon has different SVR:VAR_PER. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
d23da2ae |
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26-Dec-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: fixes for TFABOOT framework Fixes for TFABOOT framework - update eMMC bootsrc to SD_MMC - Increase buffer size for mcinitcmd from 256 to 512 - Fix mcinitcmd and bootcmd for Secure Boot Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
4909b89e |
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29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
d6fdec21 |
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29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8:fsl-layerscape: Add support for Chassis 3.2 NXP layerscape architecture Chassis 3.2 builds upon chassis3 architecture with changes like DDR Memory map change, removal of IFC and support of upto 8 I2C controller. Patch add README.lsch3_2 and the above changes under macro CONFIG_NXP_LSCH3_2. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
56db948b |
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05-Nov-2018 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: Update parsing boot source Workaround of erratum A010539 clears the RCW source field in PORSR1 register, causing failure of detecting boot source using this method. Use SMC call if U-Boot runs at EL2. If SMC is not implemented or running at EL3, continue to read PORSR1 and presume QSPI as boot source if erratum workaround A010539 is enabled and RCW source is cleared. Signed-off-by: York Sun <york.sun@nxp.com> |
#
681d489e |
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05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: layerscape: add SMC calls for DDR size and bank info Adds SMC calls for getting DDR size and bank info for TFABOOT. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
2141d250 |
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05-Nov-2018 |
Pankit Garg <pankit.garg@nxp.com> |
armv8: fsl-layerscape: bootcmd identification for TFABOOT Adds bootcmd identificaton on basis on boot source, valid in TFABOOT configuration. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> [YS: remove unnecessary braces] Reviewed-by: York Sun <york.sun@nxp.com> |
#
4c417384 |
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05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com> |
#
535d76a1 |
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05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: layerscape: Add TFABOOT support Adds TFABOOT support config option and add generic code to enable execution from DDR. Signed-off-by: York Sun <york.sun@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> |
#
e3506480 |
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05-Nov-2018 |
Pankit Garg <pankit.garg@nxp.com> |
armv8: fsl-layerscape: change tlb base from OCRAM to DDR in EL < 3 Change tlb base address from OCRAM to DDR when exception level is less than 3. Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
d171c707 |
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05-Nov-2018 |
York Sun <york.sun@nxp.com> |
move data structure out of cpu.h Move static definitions to cpu.c file, as it doesn't allow the cpu.h file to be included in multiple c files. Signed-off-by: York Sun <york.sun@nxp.com> |
#
9b5e6396 |
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30-Aug-2018 |
Stephen Warren <swarren@nvidia.com> |
efi_loader: simplify ifdefs Use CONFIG_IS_ENABLED(EFI_LOADER) to avoid explicitly checking CONFIG_SPL too. This simplifies the conditional. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Alexander Graf <agraf@suse.de> |
#
9cce5663 |
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16-Jul-2018 |
Joe Hershberger <joe.hershberger@ni.com> |
arm: Prevent redefinition error in fsl-layerscape The include/phy.h will start including dm.h, which pulls in linux/compat.h after the attempted redefinition in arch/arm/include/asm/armv8/mmu.h, so move this include to allow redefinition. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> |
#
83d290c5 |
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06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
482fc90c |
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06-Feb-2018 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
efi_loader: add missing EFI_RESET_PLATFORM_SPECIFIC EFI_RESET_PLATFORM_SPECIFIC is one of the values that can be used for the EFI service ResetSystem. The missing definition is added. The value has to handled in efi_reset_system(). Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Alexander Graf <agraf@suse.de> |
#
22c793e6 |
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03-Mar-2018 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
efi_loader: exit status for efi_reset_system_init efi_reset_system_init provides the architecture or board specific initialization of the EFI subsystem. Errors should be caught and signalled by a return code. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Alexander Graf <agraf@suse.de> |
#
958b2ed5 |
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09-Jan-2018 |
Zhang Ying-22455 <ying.zhang22455@nxp.com> |
armv8/ls1088a: configure PMU's PCTBENR to enable WDT The SP805-WDT module on LS1088A requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. The watchdog clock needs to be enabled first. Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
44262327 |
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15-Dec-2017 |
Ahmed Mansour <ahmed.mansour@nxp.com> |
drivers/misc: Share qbman init between archs This patch adds changes necessary to move functionality present in PowerPC folders with ARM architectures that have DPAA1 QBMan hardware - Create new board/freescale/common/fsl_portals.c to house shared device tree fixups for DPAA1 devices with ARM and PowerPC cores - Add new header file to top includes directory to allow files in both architectures to grab the function prototypes - Port inhibit_portals() from PowerPC to ARM. This function is used in setup to disable interrupts on all QMan and BMan portals. It is needed because the interrupts are enabled by default for all portals including unused/uninitialised portals. When the kernel attempts to go to deep sleep the unused portals prevent it from doing so Signed-off-by: Ahmed Mansour <ahmed.mansour@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
a8f33034 |
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03-Dec-2017 |
Wenbin song <wenbin.song@nxp.com> |
armv8: ls1043a/ls2080a: check SoC by device ID Check LS1043A/LS2080a by device ID without using personality ID to determine revision number. This check applies to all various personalities of the same SoC family. Signed-off-by: Wenbin Song <wenbin.song@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
2db53cfe |
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09-Nov-2017 |
Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
armv8: fsl-layerscape: Add support of disabling core prefetch Instruction prefetch feature is by default enabled during core release. This patch add support of disabling instruction prefetch by setting core mask in PPA. Here each core mask bit represents a core and prefetch is disabled at the time of core release. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
7eb40f0f |
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28-Sep-2017 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: Avoid running dram_init_banksize again gd->ram_size is reduced in this function to reserve secure memory. Avoid running this function again to further reduce memory size. This fixes issue for SPL boot with PPA image loaded in which case secure memory is incorrectly allocated due to repeated calling. Signed-off-by: York Sun <york.sun@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
710d0cd7 |
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03-Oct-2017 |
Sumit Garg <sumit.garg@nxp.com> |
armv8: fsl-layerscape: Allocate Secure memory from first ddr region This change is required due to trusted OS (OP-TEE) not being position independent code, it requires compile time fixed base address. To take care of this it is assumed that all layerscape armv8 platforms has minimum 2G ddr in first region. So we can have fixed address space (66 MB -> (2MB for PPA + 64MB for trusted OS)) allocated from top of first 2G ddr region and compile trusted OS with this fixed base address. But one exception here is ls1012 where we have only 1G (rdb) or 512M (frdm) ddr memory. For those we can have different fixed compile time base addresses for trusted OS. Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
e9303a41 |
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07-Sep-2017 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: Fix MC reserved memory calculation In case high region memory doesn't have enough space for Management Complex (MC), the return value should indicate a failure so the caller can handle it accordingly. Signed-off-by: York Sun <york.sun@nxp.com> Reported-by: Ebony Zhu <ebony.zhu@nxp.com> |
#
17d066fc |
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31-Aug-2017 |
Ashish Kumar <Ashish.Kumar@nxp.com> |
armv8: fsl-layerscape: Support to add RGMII for ls1088aqds This patch adds support for RGMII protocol NXP's LDPAA2 support RGMII protocol. LS1088A is the first Soc supporting both RGMII and SGMII. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Amrita Kumari <amrita.kumari@nxp.com> Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
63b2316c |
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10-Aug-2017 |
Ashish Kumar <Ashish.Kumar@nxp.com> |
fsl-layerscape: Consolidate registers space defination for CCI-400 bus CoreLink Cache Coherent Interconnect (CCI) provides full cache coherency between two clusters of multi-core CPUs and I/O coherency for devices and I/O masters. This patch add new config option SYS_FSL_HAS_CCI400 and moves existing register space definaton of CCI-400 bus to fsl_immap to be shared. CONFIG_SYS_CCI400_ADDR is replaced with SYS_CCI400_OFFSET in Kconfig. Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> [YS: revised commit message, squashed patches for armv8 and armv7] Reviewed-by: York Sun <york.sun@nxp.com> |
#
6e2941d7 |
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17-May-2017 |
Simon Glass <sjg@chromium.org> |
common: freescale: Move arch-specific declarations The declarations should not be in common.h. Move them to the arch-specific headers. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Fixup thinko defined(FSL_LSCH3) -> defined(CONFIG_FSL_LSCH3)] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
399e2bb6 |
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15-May-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Make U-Boot EL2 safe When U-Boot boots from EL2, skip some lowlevel init code requiring EL3, including CCI-400/CCN-504, trust zone, GIC, etc. These initialization tasks are carried out before U-Boot runs. This applies to the RAM version image used for SPL boot if PPA is loaded first. Signed-off-by: York Sun <york.sun@nxp.com> |
#
1f55a938 |
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05-May-2017 |
Santan Kumar <santan.kumar@nxp.com> |
armv8: ls2080aqds: Add support for SD boot Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
e809e747 |
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27-Apr-2017 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: fsl-layerscape: Add NXP LS2081A, LS2041A SoC support The QorIQ LS2081A SoC has eight 64-bit ARM v8 Cortex A72 cores and is built on layerscape architecture. It is 40-pin derivative of LS2084A (non-AIOP personality of LS2088A). So feature-wise it is same as LS2084A. LS2041A is a 4-core personality of LS2081A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
026f30ec |
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18-Apr-2017 |
Yuantian Tang <andy.tang@nxp.com> |
arm: psci: make psci usable on single core socs PSCI can be used on both multiple and single core socs. Current implementation only allows PSCI to work on multiple core socs. This patch removes this restriction so that PSCI can work on single core socs as well. Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
4a3ab193 |
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27-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: ls2080a: Drop macro CONFIG_LS2080A Use CONFIG_ARCH_LS2080A instead. Signed-off-by: York Sun <york.sun@nxp.com> |
#
3eace37e |
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06-Apr-2017 |
Simon Glass <sjg@chromium.org> |
arm: freescale: Rename initdram() to fsl_initdram() This function name shadows a global name but is in fact different. This is very confusing. Rename it to help with the following refactoring. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
76b00aca |
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31-Mar-2017 |
Simon Glass <sjg@chromium.org> |
board_f: Drop setup_dram_config() wrapper By making dram_init_banksize() return an error code we can drop the wrapper. Adjust this and clean up all implementations. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
088454cd |
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31-Mar-2017 |
Simon Glass <sjg@chromium.org> |
board_f: Drop return value from initdram() At present we cannot use this function as an init sequence call without a wrapper, since it returns the RAM size. Adjust it to set the RAM size in global_data instead, and return 0 on success. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
52c41180 |
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31-Mar-2017 |
Simon Glass <sjg@chromium.org> |
board_f: Drop board_type parameter from initdram() It looks like only cm5200 and tqm8xx use this feature, so we don't really need it in generic code. Drop it and have the users access gd->board_type directly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
3d8553f0 |
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02-Mar-2017 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
pci: layerscape: add LS2088A series SoC pcie support The LS2088A series SoCs has different physical memory map address and CCSR registers address against LS2080A series SoCs. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
eea1cb77 |
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13-Feb-2017 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8/fsl-layerscape: Update erratum A009635 implementation Erratum A009635 is valid only for LS2080A SoC and its personality. Add SoC svr check. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
4961eafc |
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06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Update early MMU for DDR after initialization In early MMU table, DDR has to be mapped as device memory to avoid speculative access. After DDR is initialized, it needs to be updated to normal memory to allow code execution. To simplify the code, dram_init() is moved into a common file as a weak function. Signed-off-by: York Sun <york.sun@nxp.com> |
#
a045a0c3 |
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06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Fix the sequence of changing MMU table This patch follows the break-before-make process when making changes to MMU table. MMU is disabled before changing TTBR to avoid any potential race condition. Signed-off-by: York Sun <york.sun@nxp.com> |
#
24f55496 |
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06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Update MMU mapping with actual DDR size Update mapping with actual DDR size. Non-existing memory should not be mapped as "normal" memory to avoid speculative access. Signed-off-by: York Sun <york.sun@nxp.com> |
#
36cc0de0 |
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06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Rewrite memory reservation For ARMv8 Layerscape SoCs, secure memory and MC memorey are reserved at the end of DDR. DDR is spit into two or three banks. This patch reverts commit aabd7ddb and simplifies the calculation of reserved memory, and moves the code into common SoC file. Secure memory is carved out first. DDR bank size is reduced. Reserved memory is then allocated on the top of available memory. U-Boot still has access to reserved memory as data transferring is needed. Device tree is fixed with reduced memory size to hide the reserved memory from OS. The same region is reserved for efi_loader. Signed-off-by: York Sun <york.sun@nxp.com> |
#
daa92644 |
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16-Jan-2017 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
ARMv8/sec_firmware: relocated and renamed the config FSL_PPA_ARMV8_PSCI Moved the config FSL_PPA_ARMV8_PSCI from fsl-layerscape's Kconfig to Kconfig under armv8 and renamed it to SEC_FIRMWARE_ARMV8_PSCI. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
904110c7 |
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10-Jan-2017 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8/fsl-lsch2: refactor the clock system initialization Up to now, there are 3 kind of SoCs under Layerscape Chassis 2, like LS1043A, LS1046A and LS1012A. But the clocks tree has a lot of differences, for instance, the IP modules have different dividers to derive its clock from Platform PLL. And the core cluster PLL and platform PLL maybe have different reference clocks, such as LS1012A. Another problem is which clock/PLL should be described by sys_info->freq_systembus, it is confused in Layerscape Chissis 2. This patch is to bind the sys_info->freq_systembus to the Platform PLL, and handle the different divider of IP modules separately between different SoCs, and separate reference clocks of core cluster PLL and platform PLL. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
2d16a1a6 |
|
07-Dec-2016 |
macro.wave.z@gmail.com <macro.wave.z@gmail.com> |
ARMv8: LS1043A: change macro CONFIG_ARMV8_PSCI definition NXP/Freescale uses macro CONFIG_ARMV8_PSCI to enable their private PSCI implementation in PPA firmware, but this macro naming too generic, so this patch replaces it with a specic one CONFIG_FSL_PPA_ARMV8_PSCI. And this macro CONFIG_ARMV8_PSCI will be used for a generic PSCI for ARMv8 which will be added in following patchs. Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
02fb2761 |
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20-Nov-2016 |
Shengzhou Liu <Shengzhou.Liu@nxp.com> |
fsl/ddr: Add erratum_a009942_check_cpo and clean related erratum - add additional function erratum_a009942_check_cpo to check if the board needs tuning CPO calibration for optimal setting. - move ERRATUM_A009942(with revision to check cpo_sample option) from fsl_ddr_gen4.c to ctrl_regs.c for reuse on all DDR4/DDR3 parts. - move ERRATUM_A008378 from fsl_ddr_gen4.c to ctrl_regs.c - remove obsolete ERRATUM_A004934 which is replaced with ERRATUM_A009942. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> [YS: Replaced CONFIG_QEMU_E500 with CONFIG_ARCH_QEMU_E500] Reviewed-by: York Sun <york.sun@nxp.com> |
#
e87c673c |
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16-Nov-2016 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8/fsl-lsch3: Update code to release secondary cores NXP ARMv8 SoC LS2080A release all secondary cores in one-go. But other new SoCs like LS2088A, LS1088A release secondary cores one by one. Update code to release secondary cores based on SoC SVR Add code to release cores one by one for non LS2080A SoCs Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> [YS: remove "inline" from declaration of initiator_type] Reviewed-by: York Sun <york.sun@nxp.com> |
#
f6b96ff6 |
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16-Nov-2016 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Use SVR based timer base address detection Timer controller base address has been changed from LS2080A SoC (and its personalities) to new SoCs like LS2088A, LS1088A. Use SVR based timer base address detection to avoid compile time #ifdef. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
f6a70b3a |
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16-Nov-2016 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add generic get_svr() in assembly Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
78d57842 |
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16-Nov-2016 |
Alexander Graf <agraf@suse.de> |
armv8: fsl-layerscape: Add support for efi_loader RTS reset When implementing efi loader support, we can expose runtime services for payloads. One such service is CPU reset. This patch implements RTS CPU reset support for layerscape systems. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: York Sun <york.sun@nxp.com> |
#
ef9a5fd8 |
|
13-Sep-2016 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: Fix "cpu status" command The core position is not continuous for some SoCs. For example, valid cores may present at position 0, 1, 4, 5, 8, 9, etc. Some registers (including boot release register) only count existing cores. Current implementation of cpu_mask() complies with the continuous numbering. However, command "cpu status" queries the spin table with actual core position. Add functions to calculate core position from core number, to correctly calculate offsets. Tested on LS2080ARDB and LS1043ARDB. Signed-off-by: York Sun <york.sun@nxp.com> |
#
5d1a7a9d |
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13-Sep-2016 |
Wenbin Song <wenbin.song@nxp.com> |
armv8/fsl-layerscape: print SoC revsion number The exact SoC revsion number can be recognized from U-Boot log. Signed-off-by: Wenbin Song <wenbin.song@nxp.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
cbe7706a |
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26-Sep-2016 |
Tom Rini <trini@konsulko.com> |
Merge git://git.denx.de/u-boot-fsl-qoriq trini: Drop local memset() from examples/standalone/mem_to_mem_idma2intr.c Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
1221ce45 |
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20-Sep-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
treewide: replace #include <asm/errno.h> with <linux/errno.h> Now, arch/${ARCH}/include/asm/errno.h and include/linux/errno.h have the same content. (both just wrap <asm-generic/errno.h>) Replace all include directives for <asm/errno.h> with <linux/errno.h>. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> [trini: Fixup include/clk.] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
b63a9506 |
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03-Aug-2016 |
York Sun <york.sun@nxp.com> |
armv8: ls2080a: Remove debug server support Debug server feature has been dropped from roadmap. Signed-off-by: York Sun <york.sun@nxp.com> |
#
ed7a3943 |
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22-Jul-2016 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: mmu: Fix enabling MMU MMU bit in SCTLR needs to be set explicitly after tables are created. It isn't an issue for EL3 becuase this bit is already set by early MMU setup. But for other exception levels this bit was not set. Signed-off-by: York Sun <york.sun@nxp.com> |
#
79119a4d |
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05-Jul-2016 |
Alison Wang <b18965@freescale.com> |
armv8: fsl-layerscape: Add A72 core detection Add support to detect Cortex-A72 core for printing it out. The Initiator Version of A72 core should be 0x4. Signed-off-by: Alison Wang <alison.wang@nxp.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
032d5bb4 |
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28-Jun-2016 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
ARMv8/Layerscape: switch SMP method accordingly If the PSCI and PPA is ready, skip the fixup for spin-table and waking secondary cores. Otherwise, change SMP method to spin-table, and the device node of PSCI will be removed. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
85cdf38e |
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28-Jun-2016 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: fsl-layerscape: add i/d-cache enable function to enable_caches This function assume that the d-cache and MMU has been enabled earlier, so it just created MMU table in main memory. But the assumption is not always correct, for example, the early setup is done in EL3, while enable_caches() is called when the PE has turned into another EL. Define the function mmu_setup() for fsl-layerscape to cover the weak one. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
5ad5823d |
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24-Jun-2016 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Convert to use common MMU framework Drop platform code to create static MMU tables. Use common framework to create MMU tables on the run. Tested on LS2080ARDB with secure and non-secure ram scenarios. Signed-off-by: York Sun <york.sun@nxp.com> |
#
e61a7534 |
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24-Jun-2016 |
York Sun <york.sun@nxp.com> |
armv8: Move secure_ram variable out of generic global data Secure_ram variable was put in generic global data. But only ARMv8 uses this variable. Move it to ARM specific data structure. Signed-off-by: York Sun <york.sun@nxp.com> |
#
a10a31ec |
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18-Jun-2016 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of git://git.denx.de/u-boot-usb Signed-off-by: Tom Rini <trini@konsulko.com> Conflicts: arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
|
#
6fb522dc |
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12-Jun-2016 |
Sriram Dash <sriram.dash@nxp.com> |
arm64: fsl-layerscape: add get_svr and IS_SVR_REV helper Adds get_svr and IS_SVR_REV helpers for ARMv8 platforms, similar to PPC and ARMv7. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> |
#
a758177f |
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07-Jun-2016 |
Yunhui Cui <yunhui.cui@nxp.com> |
armv8/ls2080a: configure PMU's PCTBENR to enable WDT The SP805-WDT module on LS2080A requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. The watchdog clock needs to be enabled first. Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
acb8f5e9 |
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21-Apr-2016 |
Alison Wang <b18965@freescale.com> |
armv8: fsl-layerscape: Remove unnecessary flushing dcache As the issue about the stack will get corrupted when switching between the early and final mmu tables is fixed by commit 70e21b064, the workaround to flush dcache is unnecessary and should be removed. Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
3c1d218a |
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04-Apr-2016 |
York Sun <york.sun@nxp.com> |
armv8: LS2080A: Consolidate LS2080A and LS2085A LS2080A is the primary SoC, and LS2085A is a personality with AIOP and DPAA DDR. The RDB and QDS boards support both personality. By detecting the SVR at runtime, a single image per board can support both SoCs. It gives users flexibility to swtich SoC without the need to reprogram the board. Signed-off-by: York Sun <york.sun@nxp.com> CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
c05016ab |
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21-Mar-2016 |
Alexander Graf <agraf@suse.de> |
arm64: Fix layerscape mmu setup With commit 7985cdf we converted all systems except for the Layerscape SoCs to the generic descriptor table based page table setup. On the Layerscape SoCs however, we just provide an empty table stub and do the setup ourselves. To reserve enough memory for the tables, we need to override the default counting mechanism which would end up with an empty table because we have no maps. Fixes: 7985cdf Reported-by: York Sun <york.sun@nxp.com> CC: Alison Wang <alison.wang@nxp.com> CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Alexander Graf <agraf@suse.de> Tested-by: York Sun <york.sun@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
7985cdf7 |
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03-Mar-2016 |
Alexander Graf <agraf@suse.de> |
arm64: Remove non-full-va map code By now the code to only have a single page table level with 64k page size and 42 bit address space is no longer used by any board in tree, so we can safely remove it. To clean up code, move the layerscape mmu code to the new defines, removing redundant field definitions. Signed-off-by: Alexander Graf <agraf@suse.de> |
#
c0492141 |
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07-Dec-2015 |
York Sun <yorksun@freescale.com> |
armv8: fsl-layerscale: Rewrite reserving memory for MC and debug server MC and debug server are not board-specific. Move reserving memory to SoC file, using the new board_reserve_ram_top function. Reduce debug server memory by 2MB to make room for secure memory. In the system with MC and debug server, the top of u-boot memory is not the end of memory. PRAM is not used for this reservation. Signed-off-by: York Sun <yorksun@freescale.com> |
#
c107c0c0 |
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04-Dec-2015 |
York Sun <yorksun@freescale.com> |
armv8: fsl-layerscape: Make DDR non secure in MMU tables DDR has been set as secure in MMU tables. Non-secure master such as SDHC DMA cannot access data correctly. Mixing secure and non- secure MMU entries requirs the MMU tables themselves in secure memory. This patch moves MMU tables into a secure DDR area. Early MMU tables are changed to set DDR as non-secure. A new table is added into final MMU tables so secure memory can have 2MB granuality. gd->secure_ram tracks the location of this secure memory. For ARMv8 SoCs, the RAM base is not zero and RAM is divided into several banks. gd->secure_ram needs to be maintained before using. This maintenance is board-specific, depending on the SoC and memory bank of the secure memory falls into. Signed-off-by: York Sun <yorksun@freescale.com> |
#
b4017364 |
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04-Nov-2015 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
armv8: ls2085a: Add workaround of errata A009635 If the core runs at higher than x3 speed of the platform, there is possiblity about sev instruction to getting missed by other cores. This is because of SoC Run Control block may not able to sample the EVENTI(Sev) signals. Configure Run Control and EPU to periodically send out EVENTI signals to wake up A57 cores. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
d764129d |
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04-Nov-2015 |
Alison Wang <b18965@freescale.com> |
armv8/layerscape: Update MMU table with execute-never bits For most device addresses excution shouldn't be allowed. Revise the MMU table to enforce execute-never bits. OCRAM, DDR and IFC are allowed for excution. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Alison Wang <alison.wang@freescale.com> Reported-by: Zhichun Hua <zhichun.hua@freescale.com> |
#
44937214 |
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09-Nov-2015 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
armv8: LS2080A: Rename LS2085A to reflect LS2080A LS2080A is a prime personality of Freescale’s LS2085A. It is a non-AIOP personality without support of DP-DDR, L2 switch, 1588, PCIe endpoint etc. So renaming existing LS2085A code base to reflect LS2080A (Prime personality) Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> [York Sun: Dropped #ifdef in cpu.c for cpu_type_list] Reviewed-by: York Sun <yorksun@freescale.com> |
#
e8297341 |
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26-Oct-2015 |
Shaohui Xie <Shaohui.Xie@freescale.com> |
armv8/ls1043a: Add Fman support Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
8281c58f |
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26-Oct-2015 |
Mingkai Hu <Mingkai.Hu@freescale.com> |
armv8/fsl_lsch2: Add fsl_lsch2 SoC Freescale LayerScape with Chassis Generation 2 is a set of SoCs with ARMv8 cores and 2rd generation of Chassis. Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
9f3183d2 |
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26-Oct-2015 |
Mingkai Hu <Mingkai.Hu@freescale.com> |
armv8/fsl_lsch3: Change arch to fsl-layerscape There are two LS series processors are built on ARMv8 Layersacpe architecture currently, LS2085A and LS1043A. They are based on ARMv8 core although use different chassis, so create fsl-layerscape to refactor the common code for the LS series processors which also paves the way for adding LS1043A platform. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
812ff53c |
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30-Oct-2019 |
Pankaj Bansal <pankaj.bansal@nxp.com> |
fsl-layerscape: fix warning if no hwconfig is defined While getting the 'subarg' of 'hwconfig' env variable in config_core_prefetch(), if no hwconfig variable is defined, below warning is received: WARNING: Calling __hwconfig without a buffer and before environment is ready Fix this by checking 'hwconfig' env variable. If not found return without further processing. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Tested-by: Michael Walle <michael@walle.cc> |
#
28f9393b |
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17-Oct-2019 |
Mathew McBride <matt@traverse.com.au> |
fsl-layerscape: do not use layerscape EFI reset if PSCI used If the secure world reset handlers are used (via CONFIG_PSCI_RESET), then do not use the layerscape-specific implementation. Signed-off-by: Mathew McBride <matt@traverse.com.au> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
6ed69523 |
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18-Sep-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add more personalities support Add LS1027A, LS1018A and LS1017A personalities support to LS1028A SoC family. LS1028A is the prime personality of LS1028A SoC family. LS1027A is a lower funtionality version of QorIQ LS1028A which does not support the multimedia subsystems, such as LCD controller, GPU, and eDP PHY. The QorIQ LS1018A and LS1017A SoCs are single 64-bit Arm A72 core, low power versions of the QorIQ LS1028A and LS1027A SoCs respectively. Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
0490cab5 |
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08-Aug-2019 |
Thomas Schaefer <thomas.schaefer@kontron.com> |
armv8: ls1028a: configure PMU's PCTBENR to enable WDT The SP805-WDT module on LS1028A requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. The watchdog clock needs to be enabled first. Signed-off-by: Thomas Schaefer <thomas.schaefer@kontron.com> Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
f3998fdc |
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02-Aug-2019 |
Simon Glass <sjg@chromium.org> |
env: Rename environment.h to env_internal.h This file contains lots of internal details about the environment. Most code can include env.h instead, calling the functions there as needed. Rename this file and add a comment at the top to indicate its internal nature. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> [trini: Fixup apalis-tk1.c] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
3a7d5571 |
|
01-Aug-2019 |
Simon Glass <sjg@chromium.org> |
env: Move env_get_f() to env.h Move this function over to the new header file. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
d9532e80 |
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23-Apr-2019 |
Udit Agarwal <udit.agarwal@nxp.com> |
armv8: fsl-layerscape: Set env_loc to ENVL_NOWHERE with CONFIG_ENV_IS_NOWHERE. ENVL_NOWHERE is dependent on CONFIG_ENV_IS_NOWHERE and not on CONFIG_CHAIN_OF_TRUST so return ENVL_NOWHERE when CONFIG_ENV_IS_NOWHERE is enabled Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
d4ad111d |
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10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
059d9422 |
|
08-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: lx2160a: add MMU table entries for PCIe The lx2160a have up to 6 PCIe controllers and have different address and size of PCIe region. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
8348e798 |
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08-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: layerscape: use PCIe address macro for precompile PCIe MMU entry Change to use PCIe address macro to determine if precompile the PCIe MMU table entry. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
10015025 |
|
03-May-2019 |
Trevor Woerner <trevor@toganlabs.com> |
CONFIG_SPL_SYS_[DI]CACHE_OFF: add While converting CONFIG_SYS_[DI]CACHE_OFF to Kconfig, there are instances where these configuration items are conditional on SPL. This commit adds SPL variants of these configuration items, uses CONFIG_IS_ENABLED(), and updates the configurations as required. Acked-by: Alexey Brodkin <abrodkin@synopsys.com> Signed-off-by: Trevor Woerner <trevor@toganlabs.com> [trini: Make the default depend on the setting for full U-Boot, update more zynq hardware] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
2e53759d |
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29-Oct-2018 |
Pankaj Bansal <pankaj.bansal@nxp.com> |
armv8: fsl-layerscape: reorder rgmii dpmacs' enablement some dpmacs in armv8a based freescale layerscape SOCs can be configured via both serdes(sgmii, xfi, xlaui etc) bits and via EC*_PMUX(rgmii) bits in RCW. e.g. dpmac 17 and 18 in LX2160A can be configured as SGMII from serdes bits and as RGMII via EC1_PMUX/EC2_PMUX bits Now if a dpmac is enabled by serdes bits then it takes precedence over EC*_PMUX bits. i.e. in LX2160A if we select serdes protocol that configures dpmac17 as SGMII and set the EC1_PMUX as RGMII, then the dpmac is SGMII and not RGMII. Therefore, move the fsl_rgmii_init after fsl_serdes_init. in fsl_rgmii_init function of SOC, we will check if the dpmac is enabled or not? if it is (fsl_serdes_init has already enabled the dpmac), then don't enable it. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
ec88ff80 |
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19-Dec-2018 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1043a: add SVR definitions for 23x23 package silicon LS1043A/LS1023A 23x23 package silicon has different SVR:VAR_PER. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
d23da2ae |
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26-Dec-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: fixes for TFABOOT framework Fixes for TFABOOT framework - update eMMC bootsrc to SD_MMC - Increase buffer size for mcinitcmd from 256 to 512 - Fix mcinitcmd and bootcmd for Secure Boot Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
d6fdec21 |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8:fsl-layerscape: Add support for Chassis 3.2 NXP layerscape architecture Chassis 3.2 builds upon chassis3 architecture with changes like DDR Memory map change, removal of IFC and support of upto 8 I2C controller. Patch add README.lsch3_2 and the above changes under macro CONFIG_NXP_LSCH3_2. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
56db948b |
|
05-Nov-2018 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: Update parsing boot source Workaround of erratum A010539 clears the RCW source field in PORSR1 register, causing failure of detecting boot source using this method. Use SMC call if U-Boot runs at EL2. If SMC is not implemented or running at EL3, continue to read PORSR1 and presume QSPI as boot source if erratum workaround A010539 is enabled and RCW source is cleared. Signed-off-by: York Sun <york.sun@nxp.com> |
#
681d489e |
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05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: layerscape: add SMC calls for DDR size and bank info Adds SMC calls for getting DDR size and bank info for TFABOOT. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
2141d250 |
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05-Nov-2018 |
Pankit Garg <pankit.garg@nxp.com> |
armv8: fsl-layerscape: bootcmd identification for TFABOOT Adds bootcmd identificaton on basis on boot source, valid in TFABOOT configuration. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> [YS: remove unnecessary braces] Reviewed-by: York Sun <york.sun@nxp.com> |
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com> |
#
535d76a1 |
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05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: layerscape: Add TFABOOT support Adds TFABOOT support config option and add generic code to enable execution from DDR. Signed-off-by: York Sun <york.sun@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> |
#
e3506480 |
|
05-Nov-2018 |
Pankit Garg <pankit.garg@nxp.com> |
armv8: fsl-layerscape: change tlb base from OCRAM to DDR in EL < 3 Change tlb base address from OCRAM to DDR when exception level is less than 3. Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
d171c707 |
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05-Nov-2018 |
York Sun <york.sun@nxp.com> |
move data structure out of cpu.h Move static definitions to cpu.c file, as it doesn't allow the cpu.h file to be included in multiple c files. Signed-off-by: York Sun <york.sun@nxp.com> |
#
9b5e6396 |
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30-Aug-2018 |
Stephen Warren <swarren@nvidia.com> |
efi_loader: simplify ifdefs Use CONFIG_IS_ENABLED(EFI_LOADER) to avoid explicitly checking CONFIG_SPL too. This simplifies the conditional. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Alexander Graf <agraf@suse.de> |
#
9cce5663 |
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16-Jul-2018 |
Joe Hershberger <joe.hershberger@ni.com> |
arm: Prevent redefinition error in fsl-layerscape The include/phy.h will start including dm.h, which pulls in linux/compat.h after the attempted redefinition in arch/arm/include/asm/armv8/mmu.h, so move this include to allow redefinition. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> |
#
83d290c5 |
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06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
482fc90c |
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06-Feb-2018 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
efi_loader: add missing EFI_RESET_PLATFORM_SPECIFIC EFI_RESET_PLATFORM_SPECIFIC is one of the values that can be used for the EFI service ResetSystem. The missing definition is added. The value has to handled in efi_reset_system(). Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Alexander Graf <agraf@suse.de> |
#
22c793e6 |
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03-Mar-2018 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
efi_loader: exit status for efi_reset_system_init efi_reset_system_init provides the architecture or board specific initialization of the EFI subsystem. Errors should be caught and signalled by a return code. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Alexander Graf <agraf@suse.de> |
#
958b2ed5 |
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09-Jan-2018 |
Zhang Ying-22455 <ying.zhang22455@nxp.com> |
armv8/ls1088a: configure PMU's PCTBENR to enable WDT The SP805-WDT module on LS1088A requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. The watchdog clock needs to be enabled first. Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
44262327 |
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15-Dec-2017 |
Ahmed Mansour <ahmed.mansour@nxp.com> |
drivers/misc: Share qbman init between archs This patch adds changes necessary to move functionality present in PowerPC folders with ARM architectures that have DPAA1 QBMan hardware - Create new board/freescale/common/fsl_portals.c to house shared device tree fixups for DPAA1 devices with ARM and PowerPC cores - Add new header file to top includes directory to allow files in both architectures to grab the function prototypes - Port inhibit_portals() from PowerPC to ARM. This function is used in setup to disable interrupts on all QMan and BMan portals. It is needed because the interrupts are enabled by default for all portals including unused/uninitialised portals. When the kernel attempts to go to deep sleep the unused portals prevent it from doing so Signed-off-by: Ahmed Mansour <ahmed.mansour@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
a8f33034 |
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03-Dec-2017 |
Wenbin song <wenbin.song@nxp.com> |
armv8: ls1043a/ls2080a: check SoC by device ID Check LS1043A/LS2080a by device ID without using personality ID to determine revision number. This check applies to all various personalities of the same SoC family. Signed-off-by: Wenbin Song <wenbin.song@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
2db53cfe |
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09-Nov-2017 |
Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
armv8: fsl-layerscape: Add support of disabling core prefetch Instruction prefetch feature is by default enabled during core release. This patch add support of disabling instruction prefetch by setting core mask in PPA. Here each core mask bit represents a core and prefetch is disabled at the time of core release. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
7eb40f0f |
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28-Sep-2017 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: Avoid running dram_init_banksize again gd->ram_size is reduced in this function to reserve secure memory. Avoid running this function again to further reduce memory size. This fixes issue for SPL boot with PPA image loaded in which case secure memory is incorrectly allocated due to repeated calling. Signed-off-by: York Sun <york.sun@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
710d0cd7 |
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03-Oct-2017 |
Sumit Garg <sumit.garg@nxp.com> |
armv8: fsl-layerscape: Allocate Secure memory from first ddr region This change is required due to trusted OS (OP-TEE) not being position independent code, it requires compile time fixed base address. To take care of this it is assumed that all layerscape armv8 platforms has minimum 2G ddr in first region. So we can have fixed address space (66 MB -> (2MB for PPA + 64MB for trusted OS)) allocated from top of first 2G ddr region and compile trusted OS with this fixed base address. But one exception here is ls1012 where we have only 1G (rdb) or 512M (frdm) ddr memory. For those we can have different fixed compile time base addresses for trusted OS. Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
e9303a41 |
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07-Sep-2017 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: Fix MC reserved memory calculation In case high region memory doesn't have enough space for Management Complex (MC), the return value should indicate a failure so the caller can handle it accordingly. Signed-off-by: York Sun <york.sun@nxp.com> Reported-by: Ebony Zhu <ebony.zhu@nxp.com> |
#
17d066fc |
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31-Aug-2017 |
Ashish Kumar <Ashish.Kumar@nxp.com> |
armv8: fsl-layerscape: Support to add RGMII for ls1088aqds This patch adds support for RGMII protocol NXP's LDPAA2 support RGMII protocol. LS1088A is the first Soc supporting both RGMII and SGMII. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Amrita Kumari <amrita.kumari@nxp.com> Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
63b2316c |
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10-Aug-2017 |
Ashish Kumar <Ashish.Kumar@nxp.com> |
fsl-layerscape: Consolidate registers space defination for CCI-400 bus CoreLink Cache Coherent Interconnect (CCI) provides full cache coherency between two clusters of multi-core CPUs and I/O coherency for devices and I/O masters. This patch add new config option SYS_FSL_HAS_CCI400 and moves existing register space definaton of CCI-400 bus to fsl_immap to be shared. CONFIG_SYS_CCI400_ADDR is replaced with SYS_CCI400_OFFSET in Kconfig. Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> [YS: revised commit message, squashed patches for armv8 and armv7] Reviewed-by: York Sun <york.sun@nxp.com> |
#
6e2941d7 |
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17-May-2017 |
Simon Glass <sjg@chromium.org> |
common: freescale: Move arch-specific declarations The declarations should not be in common.h. Move them to the arch-specific headers. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Fixup thinko defined(FSL_LSCH3) -> defined(CONFIG_FSL_LSCH3)] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
399e2bb6 |
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15-May-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Make U-Boot EL2 safe When U-Boot boots from EL2, skip some lowlevel init code requiring EL3, including CCI-400/CCN-504, trust zone, GIC, etc. These initialization tasks are carried out before U-Boot runs. This applies to the RAM version image used for SPL boot if PPA is loaded first. Signed-off-by: York Sun <york.sun@nxp.com> |
#
1f55a938 |
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05-May-2017 |
Santan Kumar <santan.kumar@nxp.com> |
armv8: ls2080aqds: Add support for SD boot Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
e809e747 |
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27-Apr-2017 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: fsl-layerscape: Add NXP LS2081A, LS2041A SoC support The QorIQ LS2081A SoC has eight 64-bit ARM v8 Cortex A72 cores and is built on layerscape architecture. It is 40-pin derivative of LS2084A (non-AIOP personality of LS2088A). So feature-wise it is same as LS2084A. LS2041A is a 4-core personality of LS2081A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
026f30ec |
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18-Apr-2017 |
Yuantian Tang <andy.tang@nxp.com> |
arm: psci: make psci usable on single core socs PSCI can be used on both multiple and single core socs. Current implementation only allows PSCI to work on multiple core socs. This patch removes this restriction so that PSCI can work on single core socs as well. Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
4a3ab193 |
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27-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: ls2080a: Drop macro CONFIG_LS2080A Use CONFIG_ARCH_LS2080A instead. Signed-off-by: York Sun <york.sun@nxp.com> |
#
3eace37e |
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06-Apr-2017 |
Simon Glass <sjg@chromium.org> |
arm: freescale: Rename initdram() to fsl_initdram() This function name shadows a global name but is in fact different. This is very confusing. Rename it to help with the following refactoring. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
76b00aca |
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31-Mar-2017 |
Simon Glass <sjg@chromium.org> |
board_f: Drop setup_dram_config() wrapper By making dram_init_banksize() return an error code we can drop the wrapper. Adjust this and clean up all implementations. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
088454cd |
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31-Mar-2017 |
Simon Glass <sjg@chromium.org> |
board_f: Drop return value from initdram() At present we cannot use this function as an init sequence call without a wrapper, since it returns the RAM size. Adjust it to set the RAM size in global_data instead, and return 0 on success. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
52c41180 |
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31-Mar-2017 |
Simon Glass <sjg@chromium.org> |
board_f: Drop board_type parameter from initdram() It looks like only cm5200 and tqm8xx use this feature, so we don't really need it in generic code. Drop it and have the users access gd->board_type directly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
3d8553f0 |
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02-Mar-2017 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
pci: layerscape: add LS2088A series SoC pcie support The LS2088A series SoCs has different physical memory map address and CCSR registers address against LS2080A series SoCs. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
eea1cb77 |
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13-Feb-2017 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8/fsl-layerscape: Update erratum A009635 implementation Erratum A009635 is valid only for LS2080A SoC and its personality. Add SoC svr check. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
4961eafc |
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06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Update early MMU for DDR after initialization In early MMU table, DDR has to be mapped as device memory to avoid speculative access. After DDR is initialized, it needs to be updated to normal memory to allow code execution. To simplify the code, dram_init() is moved into a common file as a weak function. Signed-off-by: York Sun <york.sun@nxp.com> |
#
a045a0c3 |
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06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Fix the sequence of changing MMU table This patch follows the break-before-make process when making changes to MMU table. MMU is disabled before changing TTBR to avoid any potential race condition. Signed-off-by: York Sun <york.sun@nxp.com> |
#
24f55496 |
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06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Update MMU mapping with actual DDR size Update mapping with actual DDR size. Non-existing memory should not be mapped as "normal" memory to avoid speculative access. Signed-off-by: York Sun <york.sun@nxp.com> |
#
36cc0de0 |
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06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Rewrite memory reservation For ARMv8 Layerscape SoCs, secure memory and MC memorey are reserved at the end of DDR. DDR is spit into two or three banks. This patch reverts commit aabd7ddb and simplifies the calculation of reserved memory, and moves the code into common SoC file. Secure memory is carved out first. DDR bank size is reduced. Reserved memory is then allocated on the top of available memory. U-Boot still has access to reserved memory as data transferring is needed. Device tree is fixed with reduced memory size to hide the reserved memory from OS. The same region is reserved for efi_loader. Signed-off-by: York Sun <york.sun@nxp.com> |
#
daa92644 |
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16-Jan-2017 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
ARMv8/sec_firmware: relocated and renamed the config FSL_PPA_ARMV8_PSCI Moved the config FSL_PPA_ARMV8_PSCI from fsl-layerscape's Kconfig to Kconfig under armv8 and renamed it to SEC_FIRMWARE_ARMV8_PSCI. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
904110c7 |
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10-Jan-2017 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8/fsl-lsch2: refactor the clock system initialization Up to now, there are 3 kind of SoCs under Layerscape Chassis 2, like LS1043A, LS1046A and LS1012A. But the clocks tree has a lot of differences, for instance, the IP modules have different dividers to derive its clock from Platform PLL. And the core cluster PLL and platform PLL maybe have different reference clocks, such as LS1012A. Another problem is which clock/PLL should be described by sys_info->freq_systembus, it is confused in Layerscape Chissis 2. This patch is to bind the sys_info->freq_systembus to the Platform PLL, and handle the different divider of IP modules separately between different SoCs, and separate reference clocks of core cluster PLL and platform PLL. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
2d16a1a6 |
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07-Dec-2016 |
macro.wave.z@gmail.com <macro.wave.z@gmail.com> |
ARMv8: LS1043A: change macro CONFIG_ARMV8_PSCI definition NXP/Freescale uses macro CONFIG_ARMV8_PSCI to enable their private PSCI implementation in PPA firmware, but this macro naming too generic, so this patch replaces it with a specic one CONFIG_FSL_PPA_ARMV8_PSCI. And this macro CONFIG_ARMV8_PSCI will be used for a generic PSCI for ARMv8 which will be added in following patchs. Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
02fb2761 |
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20-Nov-2016 |
Shengzhou Liu <Shengzhou.Liu@nxp.com> |
fsl/ddr: Add erratum_a009942_check_cpo and clean related erratum - add additional function erratum_a009942_check_cpo to check if the board needs tuning CPO calibration for optimal setting. - move ERRATUM_A009942(with revision to check cpo_sample option) from fsl_ddr_gen4.c to ctrl_regs.c for reuse on all DDR4/DDR3 parts. - move ERRATUM_A008378 from fsl_ddr_gen4.c to ctrl_regs.c - remove obsolete ERRATUM_A004934 which is replaced with ERRATUM_A009942. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> [YS: Replaced CONFIG_QEMU_E500 with CONFIG_ARCH_QEMU_E500] Reviewed-by: York Sun <york.sun@nxp.com> |
#
e87c673c |
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16-Nov-2016 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8/fsl-lsch3: Update code to release secondary cores NXP ARMv8 SoC LS2080A release all secondary cores in one-go. But other new SoCs like LS2088A, LS1088A release secondary cores one by one. Update code to release secondary cores based on SoC SVR Add code to release cores one by one for non LS2080A SoCs Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> [YS: remove "inline" from declaration of initiator_type] Reviewed-by: York Sun <york.sun@nxp.com> |
#
f6b96ff6 |
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16-Nov-2016 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Use SVR based timer base address detection Timer controller base address has been changed from LS2080A SoC (and its personalities) to new SoCs like LS2088A, LS1088A. Use SVR based timer base address detection to avoid compile time #ifdef. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
f6a70b3a |
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16-Nov-2016 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add generic get_svr() in assembly Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
78d57842 |
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16-Nov-2016 |
Alexander Graf <agraf@suse.de> |
armv8: fsl-layerscape: Add support for efi_loader RTS reset When implementing efi loader support, we can expose runtime services for payloads. One such service is CPU reset. This patch implements RTS CPU reset support for layerscape systems. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: York Sun <york.sun@nxp.com> |
#
ef9a5fd8 |
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13-Sep-2016 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: Fix "cpu status" command The core position is not continuous for some SoCs. For example, valid cores may present at position 0, 1, 4, 5, 8, 9, etc. Some registers (including boot release register) only count existing cores. Current implementation of cpu_mask() complies with the continuous numbering. However, command "cpu status" queries the spin table with actual core position. Add functions to calculate core position from core number, to correctly calculate offsets. Tested on LS2080ARDB and LS1043ARDB. Signed-off-by: York Sun <york.sun@nxp.com> |
#
5d1a7a9d |
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13-Sep-2016 |
Wenbin Song <wenbin.song@nxp.com> |
armv8/fsl-layerscape: print SoC revsion number The exact SoC revsion number can be recognized from U-Boot log. Signed-off-by: Wenbin Song <wenbin.song@nxp.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
cbe7706a |
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26-Sep-2016 |
Tom Rini <trini@konsulko.com> |
Merge git://git.denx.de/u-boot-fsl-qoriq trini: Drop local memset() from examples/standalone/mem_to_mem_idma2intr.c Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
1221ce45 |
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20-Sep-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
treewide: replace #include <asm/errno.h> with <linux/errno.h> Now, arch/${ARCH}/include/asm/errno.h and include/linux/errno.h have the same content. (both just wrap <asm-generic/errno.h>) Replace all include directives for <asm/errno.h> with <linux/errno.h>. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> [trini: Fixup include/clk.] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
b63a9506 |
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03-Aug-2016 |
York Sun <york.sun@nxp.com> |
armv8: ls2080a: Remove debug server support Debug server feature has been dropped from roadmap. Signed-off-by: York Sun <york.sun@nxp.com> |
#
ed7a3943 |
|
22-Jul-2016 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: mmu: Fix enabling MMU MMU bit in SCTLR needs to be set explicitly after tables are created. It isn't an issue for EL3 becuase this bit is already set by early MMU setup. But for other exception levels this bit was not set. Signed-off-by: York Sun <york.sun@nxp.com> |
#
79119a4d |
|
05-Jul-2016 |
Alison Wang <b18965@freescale.com> |
armv8: fsl-layerscape: Add A72 core detection Add support to detect Cortex-A72 core for printing it out. The Initiator Version of A72 core should be 0x4. Signed-off-by: Alison Wang <alison.wang@nxp.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
032d5bb4 |
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28-Jun-2016 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
ARMv8/Layerscape: switch SMP method accordingly If the PSCI and PPA is ready, skip the fixup for spin-table and waking secondary cores. Otherwise, change SMP method to spin-table, and the device node of PSCI will be removed. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
85cdf38e |
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28-Jun-2016 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: fsl-layerscape: add i/d-cache enable function to enable_caches This function assume that the d-cache and MMU has been enabled earlier, so it just created MMU table in main memory. But the assumption is not always correct, for example, the early setup is done in EL3, while enable_caches() is called when the PE has turned into another EL. Define the function mmu_setup() for fsl-layerscape to cover the weak one. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
5ad5823d |
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24-Jun-2016 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Convert to use common MMU framework Drop platform code to create static MMU tables. Use common framework to create MMU tables on the run. Tested on LS2080ARDB with secure and non-secure ram scenarios. Signed-off-by: York Sun <york.sun@nxp.com> |
#
e61a7534 |
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24-Jun-2016 |
York Sun <york.sun@nxp.com> |
armv8: Move secure_ram variable out of generic global data Secure_ram variable was put in generic global data. But only ARMv8 uses this variable. Move it to ARM specific data structure. Signed-off-by: York Sun <york.sun@nxp.com> |
#
a10a31ec |
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18-Jun-2016 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of git://git.denx.de/u-boot-usb Signed-off-by: Tom Rini <trini@konsulko.com> Conflicts: arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
|
#
6fb522dc |
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12-Jun-2016 |
Sriram Dash <sriram.dash@nxp.com> |
arm64: fsl-layerscape: add get_svr and IS_SVR_REV helper Adds get_svr and IS_SVR_REV helpers for ARMv8 platforms, similar to PPC and ARMv7. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> |
#
a758177f |
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07-Jun-2016 |
Yunhui Cui <yunhui.cui@nxp.com> |
armv8/ls2080a: configure PMU's PCTBENR to enable WDT The SP805-WDT module on LS2080A requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. The watchdog clock needs to be enabled first. Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
acb8f5e9 |
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21-Apr-2016 |
Alison Wang <b18965@freescale.com> |
armv8: fsl-layerscape: Remove unnecessary flushing dcache As the issue about the stack will get corrupted when switching between the early and final mmu tables is fixed by commit 70e21b064, the workaround to flush dcache is unnecessary and should be removed. Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
3c1d218a |
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04-Apr-2016 |
York Sun <york.sun@nxp.com> |
armv8: LS2080A: Consolidate LS2080A and LS2085A LS2080A is the primary SoC, and LS2085A is a personality with AIOP and DPAA DDR. The RDB and QDS boards support both personality. By detecting the SVR at runtime, a single image per board can support both SoCs. It gives users flexibility to swtich SoC without the need to reprogram the board. Signed-off-by: York Sun <york.sun@nxp.com> CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
c05016ab |
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21-Mar-2016 |
Alexander Graf <agraf@suse.de> |
arm64: Fix layerscape mmu setup With commit 7985cdf we converted all systems except for the Layerscape SoCs to the generic descriptor table based page table setup. On the Layerscape SoCs however, we just provide an empty table stub and do the setup ourselves. To reserve enough memory for the tables, we need to override the default counting mechanism which would end up with an empty table because we have no maps. Fixes: 7985cdf Reported-by: York Sun <york.sun@nxp.com> CC: Alison Wang <alison.wang@nxp.com> CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Alexander Graf <agraf@suse.de> Tested-by: York Sun <york.sun@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
7985cdf7 |
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03-Mar-2016 |
Alexander Graf <agraf@suse.de> |
arm64: Remove non-full-va map code By now the code to only have a single page table level with 64k page size and 42 bit address space is no longer used by any board in tree, so we can safely remove it. To clean up code, move the layerscape mmu code to the new defines, removing redundant field definitions. Signed-off-by: Alexander Graf <agraf@suse.de> |
#
c0492141 |
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07-Dec-2015 |
York Sun <yorksun@freescale.com> |
armv8: fsl-layerscale: Rewrite reserving memory for MC and debug server MC and debug server are not board-specific. Move reserving memory to SoC file, using the new board_reserve_ram_top function. Reduce debug server memory by 2MB to make room for secure memory. In the system with MC and debug server, the top of u-boot memory is not the end of memory. PRAM is not used for this reservation. Signed-off-by: York Sun <yorksun@freescale.com> |
#
c107c0c0 |
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04-Dec-2015 |
York Sun <yorksun@freescale.com> |
armv8: fsl-layerscape: Make DDR non secure in MMU tables DDR has been set as secure in MMU tables. Non-secure master such as SDHC DMA cannot access data correctly. Mixing secure and non- secure MMU entries requirs the MMU tables themselves in secure memory. This patch moves MMU tables into a secure DDR area. Early MMU tables are changed to set DDR as non-secure. A new table is added into final MMU tables so secure memory can have 2MB granuality. gd->secure_ram tracks the location of this secure memory. For ARMv8 SoCs, the RAM base is not zero and RAM is divided into several banks. gd->secure_ram needs to be maintained before using. This maintenance is board-specific, depending on the SoC and memory bank of the secure memory falls into. Signed-off-by: York Sun <yorksun@freescale.com> |
#
b4017364 |
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04-Nov-2015 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
armv8: ls2085a: Add workaround of errata A009635 If the core runs at higher than x3 speed of the platform, there is possiblity about sev instruction to getting missed by other cores. This is because of SoC Run Control block may not able to sample the EVENTI(Sev) signals. Configure Run Control and EPU to periodically send out EVENTI signals to wake up A57 cores. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
d764129d |
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04-Nov-2015 |
Alison Wang <b18965@freescale.com> |
armv8/layerscape: Update MMU table with execute-never bits For most device addresses excution shouldn't be allowed. Revise the MMU table to enforce execute-never bits. OCRAM, DDR and IFC are allowed for excution. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Alison Wang <alison.wang@freescale.com> Reported-by: Zhichun Hua <zhichun.hua@freescale.com> |
#
44937214 |
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09-Nov-2015 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
armv8: LS2080A: Rename LS2085A to reflect LS2080A LS2080A is a prime personality of Freescale’s LS2085A. It is a non-AIOP personality without support of DP-DDR, L2 switch, 1588, PCIe endpoint etc. So renaming existing LS2085A code base to reflect LS2080A (Prime personality) Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> [York Sun: Dropped #ifdef in cpu.c for cpu_type_list] Reviewed-by: York Sun <yorksun@freescale.com> |
#
e8297341 |
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26-Oct-2015 |
Shaohui Xie <Shaohui.Xie@freescale.com> |
armv8/ls1043a: Add Fman support Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
8281c58f |
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26-Oct-2015 |
Mingkai Hu <Mingkai.Hu@freescale.com> |
armv8/fsl_lsch2: Add fsl_lsch2 SoC Freescale LayerScape with Chassis Generation 2 is a set of SoCs with ARMv8 cores and 2rd generation of Chassis. Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
9f3183d2 |
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26-Oct-2015 |
Mingkai Hu <Mingkai.Hu@freescale.com> |
armv8/fsl_lsch3: Change arch to fsl-layerscape There are two LS series processors are built on ARMv8 Layersacpe architecture currently, LS2085A and LS1043A. They are based on ARMv8 core although use different chassis, so create fsl-layerscape to refactor the common code for the LS series processors which also paves the way for adding LS1043A platform. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
6ed69523 |
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18-Sep-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add more personalities support Add LS1027A, LS1018A and LS1017A personalities support to LS1028A SoC family. LS1028A is the prime personality of LS1028A SoC family. LS1027A is a lower funtionality version of QorIQ LS1028A which does not support the multimedia subsystems, such as LCD controller, GPU, and eDP PHY. The QorIQ LS1018A and LS1017A SoCs are single 64-bit Arm A72 core, low power versions of the QorIQ LS1028A and LS1027A SoCs respectively. Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
0490cab5 |
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08-Aug-2019 |
Thomas Schaefer <thomas.schaefer@kontron.com> |
armv8: ls1028a: configure PMU's PCTBENR to enable WDT The SP805-WDT module on LS1028A requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. The watchdog clock needs to be enabled first. Signed-off-by: Thomas Schaefer <thomas.schaefer@kontron.com> Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
f3998fdc |
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02-Aug-2019 |
Simon Glass <sjg@chromium.org> |
env: Rename environment.h to env_internal.h This file contains lots of internal details about the environment. Most code can include env.h instead, calling the functions there as needed. Rename this file and add a comment at the top to indicate its internal nature. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> [trini: Fixup apalis-tk1.c] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
3a7d5571 |
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01-Aug-2019 |
Simon Glass <sjg@chromium.org> |
env: Move env_get_f() to env.h Move this function over to the new header file. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
d9532e80 |
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23-Apr-2019 |
Udit Agarwal <udit.agarwal@nxp.com> |
armv8: fsl-layerscape: Set env_loc to ENVL_NOWHERE with CONFIG_ENV_IS_NOWHERE. ENVL_NOWHERE is dependent on CONFIG_ENV_IS_NOWHERE and not on CONFIG_CHAIN_OF_TRUST so return ENVL_NOWHERE when CONFIG_ENV_IS_NOWHERE is enabled Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
d4ad111d |
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10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
059d9422 |
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08-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: lx2160a: add MMU table entries for PCIe The lx2160a have up to 6 PCIe controllers and have different address and size of PCIe region. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
8348e798 |
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08-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: layerscape: use PCIe address macro for precompile PCIe MMU entry Change to use PCIe address macro to determine if precompile the PCIe MMU table entry. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
10015025 |
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03-May-2019 |
Trevor Woerner <trevor@toganlabs.com> |
CONFIG_SPL_SYS_[DI]CACHE_OFF: add While converting CONFIG_SYS_[DI]CACHE_OFF to Kconfig, there are instances where these configuration items are conditional on SPL. This commit adds SPL variants of these configuration items, uses CONFIG_IS_ENABLED(), and updates the configurations as required. Acked-by: Alexey Brodkin <abrodkin@synopsys.com> Signed-off-by: Trevor Woerner <trevor@toganlabs.com> [trini: Make the default depend on the setting for full U-Boot, update more zynq hardware] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
2e53759d |
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29-Oct-2018 |
Pankaj Bansal <pankaj.bansal@nxp.com> |
armv8: fsl-layerscape: reorder rgmii dpmacs' enablement some dpmacs in armv8a based freescale layerscape SOCs can be configured via both serdes(sgmii, xfi, xlaui etc) bits and via EC*_PMUX(rgmii) bits in RCW. e.g. dpmac 17 and 18 in LX2160A can be configured as SGMII from serdes bits and as RGMII via EC1_PMUX/EC2_PMUX bits Now if a dpmac is enabled by serdes bits then it takes precedence over EC*_PMUX bits. i.e. in LX2160A if we select serdes protocol that configures dpmac17 as SGMII and set the EC1_PMUX as RGMII, then the dpmac is SGMII and not RGMII. Therefore, move the fsl_rgmii_init after fsl_serdes_init. in fsl_rgmii_init function of SOC, we will check if the dpmac is enabled or not? if it is (fsl_serdes_init has already enabled the dpmac), then don't enable it. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
ec88ff80 |
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19-Dec-2018 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1043a: add SVR definitions for 23x23 package silicon LS1043A/LS1023A 23x23 package silicon has different SVR:VAR_PER. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
d23da2ae |
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26-Dec-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: fixes for TFABOOT framework Fixes for TFABOOT framework - update eMMC bootsrc to SD_MMC - Increase buffer size for mcinitcmd from 256 to 512 - Fix mcinitcmd and bootcmd for Secure Boot Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
4909b89e |
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29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
d6fdec21 |
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29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8:fsl-layerscape: Add support for Chassis 3.2 NXP layerscape architecture Chassis 3.2 builds upon chassis3 architecture with changes like DDR Memory map change, removal of IFC and support of upto 8 I2C controller. Patch add README.lsch3_2 and the above changes under macro CONFIG_NXP_LSCH3_2. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
56db948b |
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05-Nov-2018 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: Update parsing boot source Workaround of erratum A010539 clears the RCW source field in PORSR1 register, causing failure of detecting boot source using this method. Use SMC call if U-Boot runs at EL2. If SMC is not implemented or running at EL3, continue to read PORSR1 and presume QSPI as boot source if erratum workaround A010539 is enabled and RCW source is cleared. Signed-off-by: York Sun <york.sun@nxp.com> |
#
681d489e |
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05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: layerscape: add SMC calls for DDR size and bank info Adds SMC calls for getting DDR size and bank info for TFABOOT. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
2141d250 |
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05-Nov-2018 |
Pankit Garg <pankit.garg@nxp.com> |
armv8: fsl-layerscape: bootcmd identification for TFABOOT Adds bootcmd identificaton on basis on boot source, valid in TFABOOT configuration. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> [YS: remove unnecessary braces] Reviewed-by: York Sun <york.sun@nxp.com> |
#
4c417384 |
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05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com> |
#
535d76a1 |
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05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: layerscape: Add TFABOOT support Adds TFABOOT support config option and add generic code to enable execution from DDR. Signed-off-by: York Sun <york.sun@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> |
#
e3506480 |
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05-Nov-2018 |
Pankit Garg <pankit.garg@nxp.com> |
armv8: fsl-layerscape: change tlb base from OCRAM to DDR in EL < 3 Change tlb base address from OCRAM to DDR when exception level is less than 3. Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
d171c707 |
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05-Nov-2018 |
York Sun <york.sun@nxp.com> |
move data structure out of cpu.h Move static definitions to cpu.c file, as it doesn't allow the cpu.h file to be included in multiple c files. Signed-off-by: York Sun <york.sun@nxp.com> |
#
9b5e6396 |
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30-Aug-2018 |
Stephen Warren <swarren@nvidia.com> |
efi_loader: simplify ifdefs Use CONFIG_IS_ENABLED(EFI_LOADER) to avoid explicitly checking CONFIG_SPL too. This simplifies the conditional. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Alexander Graf <agraf@suse.de> |
#
9cce5663 |
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16-Jul-2018 |
Joe Hershberger <joe.hershberger@ni.com> |
arm: Prevent redefinition error in fsl-layerscape The include/phy.h will start including dm.h, which pulls in linux/compat.h after the attempted redefinition in arch/arm/include/asm/armv8/mmu.h, so move this include to allow redefinition. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> |
#
83d290c5 |
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06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
482fc90c |
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06-Feb-2018 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
efi_loader: add missing EFI_RESET_PLATFORM_SPECIFIC EFI_RESET_PLATFORM_SPECIFIC is one of the values that can be used for the EFI service ResetSystem. The missing definition is added. The value has to handled in efi_reset_system(). Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Alexander Graf <agraf@suse.de> |
#
22c793e6 |
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03-Mar-2018 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
efi_loader: exit status for efi_reset_system_init efi_reset_system_init provides the architecture or board specific initialization of the EFI subsystem. Errors should be caught and signalled by a return code. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Alexander Graf <agraf@suse.de> |
#
958b2ed5 |
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09-Jan-2018 |
Zhang Ying-22455 <ying.zhang22455@nxp.com> |
armv8/ls1088a: configure PMU's PCTBENR to enable WDT The SP805-WDT module on LS1088A requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. The watchdog clock needs to be enabled first. Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
44262327 |
|
15-Dec-2017 |
Ahmed Mansour <ahmed.mansour@nxp.com> |
drivers/misc: Share qbman init between archs This patch adds changes necessary to move functionality present in PowerPC folders with ARM architectures that have DPAA1 QBMan hardware - Create new board/freescale/common/fsl_portals.c to house shared device tree fixups for DPAA1 devices with ARM and PowerPC cores - Add new header file to top includes directory to allow files in both architectures to grab the function prototypes - Port inhibit_portals() from PowerPC to ARM. This function is used in setup to disable interrupts on all QMan and BMan portals. It is needed because the interrupts are enabled by default for all portals including unused/uninitialised portals. When the kernel attempts to go to deep sleep the unused portals prevent it from doing so Signed-off-by: Ahmed Mansour <ahmed.mansour@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
a8f33034 |
|
03-Dec-2017 |
Wenbin song <wenbin.song@nxp.com> |
armv8: ls1043a/ls2080a: check SoC by device ID Check LS1043A/LS2080a by device ID without using personality ID to determine revision number. This check applies to all various personalities of the same SoC family. Signed-off-by: Wenbin Song <wenbin.song@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
2db53cfe |
|
09-Nov-2017 |
Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
armv8: fsl-layerscape: Add support of disabling core prefetch Instruction prefetch feature is by default enabled during core release. This patch add support of disabling instruction prefetch by setting core mask in PPA. Here each core mask bit represents a core and prefetch is disabled at the time of core release. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
7eb40f0f |
|
28-Sep-2017 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: Avoid running dram_init_banksize again gd->ram_size is reduced in this function to reserve secure memory. Avoid running this function again to further reduce memory size. This fixes issue for SPL boot with PPA image loaded in which case secure memory is incorrectly allocated due to repeated calling. Signed-off-by: York Sun <york.sun@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
710d0cd7 |
|
03-Oct-2017 |
Sumit Garg <sumit.garg@nxp.com> |
armv8: fsl-layerscape: Allocate Secure memory from first ddr region This change is required due to trusted OS (OP-TEE) not being position independent code, it requires compile time fixed base address. To take care of this it is assumed that all layerscape armv8 platforms has minimum 2G ddr in first region. So we can have fixed address space (66 MB -> (2MB for PPA + 64MB for trusted OS)) allocated from top of first 2G ddr region and compile trusted OS with this fixed base address. But one exception here is ls1012 where we have only 1G (rdb) or 512M (frdm) ddr memory. For those we can have different fixed compile time base addresses for trusted OS. Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
e9303a41 |
|
07-Sep-2017 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: Fix MC reserved memory calculation In case high region memory doesn't have enough space for Management Complex (MC), the return value should indicate a failure so the caller can handle it accordingly. Signed-off-by: York Sun <york.sun@nxp.com> Reported-by: Ebony Zhu <ebony.zhu@nxp.com> |
#
17d066fc |
|
31-Aug-2017 |
Ashish Kumar <Ashish.Kumar@nxp.com> |
armv8: fsl-layerscape: Support to add RGMII for ls1088aqds This patch adds support for RGMII protocol NXP's LDPAA2 support RGMII protocol. LS1088A is the first Soc supporting both RGMII and SGMII. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Amrita Kumari <amrita.kumari@nxp.com> Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
63b2316c |
|
10-Aug-2017 |
Ashish Kumar <Ashish.Kumar@nxp.com> |
fsl-layerscape: Consolidate registers space defination for CCI-400 bus CoreLink Cache Coherent Interconnect (CCI) provides full cache coherency between two clusters of multi-core CPUs and I/O coherency for devices and I/O masters. This patch add new config option SYS_FSL_HAS_CCI400 and moves existing register space definaton of CCI-400 bus to fsl_immap to be shared. CONFIG_SYS_CCI400_ADDR is replaced with SYS_CCI400_OFFSET in Kconfig. Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> [YS: revised commit message, squashed patches for armv8 and armv7] Reviewed-by: York Sun <york.sun@nxp.com> |
#
6e2941d7 |
|
17-May-2017 |
Simon Glass <sjg@chromium.org> |
common: freescale: Move arch-specific declarations The declarations should not be in common.h. Move them to the arch-specific headers. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Fixup thinko defined(FSL_LSCH3) -> defined(CONFIG_FSL_LSCH3)] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
399e2bb6 |
|
15-May-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Make U-Boot EL2 safe When U-Boot boots from EL2, skip some lowlevel init code requiring EL3, including CCI-400/CCN-504, trust zone, GIC, etc. These initialization tasks are carried out before U-Boot runs. This applies to the RAM version image used for SPL boot if PPA is loaded first. Signed-off-by: York Sun <york.sun@nxp.com> |
#
1f55a938 |
|
05-May-2017 |
Santan Kumar <santan.kumar@nxp.com> |
armv8: ls2080aqds: Add support for SD boot Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
e809e747 |
|
27-Apr-2017 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: fsl-layerscape: Add NXP LS2081A, LS2041A SoC support The QorIQ LS2081A SoC has eight 64-bit ARM v8 Cortex A72 cores and is built on layerscape architecture. It is 40-pin derivative of LS2084A (non-AIOP personality of LS2088A). So feature-wise it is same as LS2084A. LS2041A is a 4-core personality of LS2081A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
026f30ec |
|
18-Apr-2017 |
Yuantian Tang <andy.tang@nxp.com> |
arm: psci: make psci usable on single core socs PSCI can be used on both multiple and single core socs. Current implementation only allows PSCI to work on multiple core socs. This patch removes this restriction so that PSCI can work on single core socs as well. Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
4a3ab193 |
|
27-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: ls2080a: Drop macro CONFIG_LS2080A Use CONFIG_ARCH_LS2080A instead. Signed-off-by: York Sun <york.sun@nxp.com> |
#
3eace37e |
|
06-Apr-2017 |
Simon Glass <sjg@chromium.org> |
arm: freescale: Rename initdram() to fsl_initdram() This function name shadows a global name but is in fact different. This is very confusing. Rename it to help with the following refactoring. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
76b00aca |
|
31-Mar-2017 |
Simon Glass <sjg@chromium.org> |
board_f: Drop setup_dram_config() wrapper By making dram_init_banksize() return an error code we can drop the wrapper. Adjust this and clean up all implementations. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
088454cd |
|
31-Mar-2017 |
Simon Glass <sjg@chromium.org> |
board_f: Drop return value from initdram() At present we cannot use this function as an init sequence call without a wrapper, since it returns the RAM size. Adjust it to set the RAM size in global_data instead, and return 0 on success. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
52c41180 |
|
31-Mar-2017 |
Simon Glass <sjg@chromium.org> |
board_f: Drop board_type parameter from initdram() It looks like only cm5200 and tqm8xx use this feature, so we don't really need it in generic code. Drop it and have the users access gd->board_type directly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
3d8553f0 |
|
02-Mar-2017 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
pci: layerscape: add LS2088A series SoC pcie support The LS2088A series SoCs has different physical memory map address and CCSR registers address against LS2080A series SoCs. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
eea1cb77 |
|
13-Feb-2017 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8/fsl-layerscape: Update erratum A009635 implementation Erratum A009635 is valid only for LS2080A SoC and its personality. Add SoC svr check. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
4961eafc |
|
06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Update early MMU for DDR after initialization In early MMU table, DDR has to be mapped as device memory to avoid speculative access. After DDR is initialized, it needs to be updated to normal memory to allow code execution. To simplify the code, dram_init() is moved into a common file as a weak function. Signed-off-by: York Sun <york.sun@nxp.com> |
#
a045a0c3 |
|
06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Fix the sequence of changing MMU table This patch follows the break-before-make process when making changes to MMU table. MMU is disabled before changing TTBR to avoid any potential race condition. Signed-off-by: York Sun <york.sun@nxp.com> |
#
24f55496 |
|
06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Update MMU mapping with actual DDR size Update mapping with actual DDR size. Non-existing memory should not be mapped as "normal" memory to avoid speculative access. Signed-off-by: York Sun <york.sun@nxp.com> |
#
36cc0de0 |
|
06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Rewrite memory reservation For ARMv8 Layerscape SoCs, secure memory and MC memorey are reserved at the end of DDR. DDR is spit into two or three banks. This patch reverts commit aabd7ddb and simplifies the calculation of reserved memory, and moves the code into common SoC file. Secure memory is carved out first. DDR bank size is reduced. Reserved memory is then allocated on the top of available memory. U-Boot still has access to reserved memory as data transferring is needed. Device tree is fixed with reduced memory size to hide the reserved memory from OS. The same region is reserved for efi_loader. Signed-off-by: York Sun <york.sun@nxp.com> |
#
daa92644 |
|
16-Jan-2017 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
ARMv8/sec_firmware: relocated and renamed the config FSL_PPA_ARMV8_PSCI Moved the config FSL_PPA_ARMV8_PSCI from fsl-layerscape's Kconfig to Kconfig under armv8 and renamed it to SEC_FIRMWARE_ARMV8_PSCI. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
904110c7 |
|
10-Jan-2017 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8/fsl-lsch2: refactor the clock system initialization Up to now, there are 3 kind of SoCs under Layerscape Chassis 2, like LS1043A, LS1046A and LS1012A. But the clocks tree has a lot of differences, for instance, the IP modules have different dividers to derive its clock from Platform PLL. And the core cluster PLL and platform PLL maybe have different reference clocks, such as LS1012A. Another problem is which clock/PLL should be described by sys_info->freq_systembus, it is confused in Layerscape Chissis 2. This patch is to bind the sys_info->freq_systembus to the Platform PLL, and handle the different divider of IP modules separately between different SoCs, and separate reference clocks of core cluster PLL and platform PLL. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
2d16a1a6 |
|
07-Dec-2016 |
macro.wave.z@gmail.com <macro.wave.z@gmail.com> |
ARMv8: LS1043A: change macro CONFIG_ARMV8_PSCI definition NXP/Freescale uses macro CONFIG_ARMV8_PSCI to enable their private PSCI implementation in PPA firmware, but this macro naming too generic, so this patch replaces it with a specic one CONFIG_FSL_PPA_ARMV8_PSCI. And this macro CONFIG_ARMV8_PSCI will be used for a generic PSCI for ARMv8 which will be added in following patchs. Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
02fb2761 |
|
20-Nov-2016 |
Shengzhou Liu <Shengzhou.Liu@nxp.com> |
fsl/ddr: Add erratum_a009942_check_cpo and clean related erratum - add additional function erratum_a009942_check_cpo to check if the board needs tuning CPO calibration for optimal setting. - move ERRATUM_A009942(with revision to check cpo_sample option) from fsl_ddr_gen4.c to ctrl_regs.c for reuse on all DDR4/DDR3 parts. - move ERRATUM_A008378 from fsl_ddr_gen4.c to ctrl_regs.c - remove obsolete ERRATUM_A004934 which is replaced with ERRATUM_A009942. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> [YS: Replaced CONFIG_QEMU_E500 with CONFIG_ARCH_QEMU_E500] Reviewed-by: York Sun <york.sun@nxp.com> |
#
e87c673c |
|
16-Nov-2016 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8/fsl-lsch3: Update code to release secondary cores NXP ARMv8 SoC LS2080A release all secondary cores in one-go. But other new SoCs like LS2088A, LS1088A release secondary cores one by one. Update code to release secondary cores based on SoC SVR Add code to release cores one by one for non LS2080A SoCs Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> [YS: remove "inline" from declaration of initiator_type] Reviewed-by: York Sun <york.sun@nxp.com> |
#
f6b96ff6 |
|
16-Nov-2016 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Use SVR based timer base address detection Timer controller base address has been changed from LS2080A SoC (and its personalities) to new SoCs like LS2088A, LS1088A. Use SVR based timer base address detection to avoid compile time #ifdef. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
f6a70b3a |
|
16-Nov-2016 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add generic get_svr() in assembly Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
78d57842 |
|
16-Nov-2016 |
Alexander Graf <agraf@suse.de> |
armv8: fsl-layerscape: Add support for efi_loader RTS reset When implementing efi loader support, we can expose runtime services for payloads. One such service is CPU reset. This patch implements RTS CPU reset support for layerscape systems. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: York Sun <york.sun@nxp.com> |
#
ef9a5fd8 |
|
13-Sep-2016 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: Fix "cpu status" command The core position is not continuous for some SoCs. For example, valid cores may present at position 0, 1, 4, 5, 8, 9, etc. Some registers (including boot release register) only count existing cores. Current implementation of cpu_mask() complies with the continuous numbering. However, command "cpu status" queries the spin table with actual core position. Add functions to calculate core position from core number, to correctly calculate offsets. Tested on LS2080ARDB and LS1043ARDB. Signed-off-by: York Sun <york.sun@nxp.com> |
#
5d1a7a9d |
|
13-Sep-2016 |
Wenbin Song <wenbin.song@nxp.com> |
armv8/fsl-layerscape: print SoC revsion number The exact SoC revsion number can be recognized from U-Boot log. Signed-off-by: Wenbin Song <wenbin.song@nxp.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
cbe7706a |
|
26-Sep-2016 |
Tom Rini <trini@konsulko.com> |
Merge git://git.denx.de/u-boot-fsl-qoriq trini: Drop local memset() from examples/standalone/mem_to_mem_idma2intr.c Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
1221ce45 |
|
20-Sep-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
treewide: replace #include <asm/errno.h> with <linux/errno.h> Now, arch/${ARCH}/include/asm/errno.h and include/linux/errno.h have the same content. (both just wrap <asm-generic/errno.h>) Replace all include directives for <asm/errno.h> with <linux/errno.h>. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> [trini: Fixup include/clk.] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
b63a9506 |
|
03-Aug-2016 |
York Sun <york.sun@nxp.com> |
armv8: ls2080a: Remove debug server support Debug server feature has been dropped from roadmap. Signed-off-by: York Sun <york.sun@nxp.com> |
#
ed7a3943 |
|
22-Jul-2016 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: mmu: Fix enabling MMU MMU bit in SCTLR needs to be set explicitly after tables are created. It isn't an issue for EL3 becuase this bit is already set by early MMU setup. But for other exception levels this bit was not set. Signed-off-by: York Sun <york.sun@nxp.com> |
#
79119a4d |
|
05-Jul-2016 |
Alison Wang <b18965@freescale.com> |
armv8: fsl-layerscape: Add A72 core detection Add support to detect Cortex-A72 core for printing it out. The Initiator Version of A72 core should be 0x4. Signed-off-by: Alison Wang <alison.wang@nxp.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
032d5bb4 |
|
28-Jun-2016 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
ARMv8/Layerscape: switch SMP method accordingly If the PSCI and PPA is ready, skip the fixup for spin-table and waking secondary cores. Otherwise, change SMP method to spin-table, and the device node of PSCI will be removed. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
85cdf38e |
|
28-Jun-2016 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: fsl-layerscape: add i/d-cache enable function to enable_caches This function assume that the d-cache and MMU has been enabled earlier, so it just created MMU table in main memory. But the assumption is not always correct, for example, the early setup is done in EL3, while enable_caches() is called when the PE has turned into another EL. Define the function mmu_setup() for fsl-layerscape to cover the weak one. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
5ad5823d |
|
24-Jun-2016 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Convert to use common MMU framework Drop platform code to create static MMU tables. Use common framework to create MMU tables on the run. Tested on LS2080ARDB with secure and non-secure ram scenarios. Signed-off-by: York Sun <york.sun@nxp.com> |
#
e61a7534 |
|
24-Jun-2016 |
York Sun <york.sun@nxp.com> |
armv8: Move secure_ram variable out of generic global data Secure_ram variable was put in generic global data. But only ARMv8 uses this variable. Move it to ARM specific data structure. Signed-off-by: York Sun <york.sun@nxp.com> |
#
a10a31ec |
|
18-Jun-2016 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of git://git.denx.de/u-boot-usb Signed-off-by: Tom Rini <trini@konsulko.com> Conflicts: arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
|
#
6fb522dc |
|
12-Jun-2016 |
Sriram Dash <sriram.dash@nxp.com> |
arm64: fsl-layerscape: add get_svr and IS_SVR_REV helper Adds get_svr and IS_SVR_REV helpers for ARMv8 platforms, similar to PPC and ARMv7. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> |
#
a758177f |
|
07-Jun-2016 |
Yunhui Cui <yunhui.cui@nxp.com> |
armv8/ls2080a: configure PMU's PCTBENR to enable WDT The SP805-WDT module on LS2080A requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. The watchdog clock needs to be enabled first. Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
acb8f5e9 |
|
21-Apr-2016 |
Alison Wang <b18965@freescale.com> |
armv8: fsl-layerscape: Remove unnecessary flushing dcache As the issue about the stack will get corrupted when switching between the early and final mmu tables is fixed by commit 70e21b064, the workaround to flush dcache is unnecessary and should be removed. Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
3c1d218a |
|
04-Apr-2016 |
York Sun <york.sun@nxp.com> |
armv8: LS2080A: Consolidate LS2080A and LS2085A LS2080A is the primary SoC, and LS2085A is a personality with AIOP and DPAA DDR. The RDB and QDS boards support both personality. By detecting the SVR at runtime, a single image per board can support both SoCs. It gives users flexibility to swtich SoC without the need to reprogram the board. Signed-off-by: York Sun <york.sun@nxp.com> CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
c05016ab |
|
21-Mar-2016 |
Alexander Graf <agraf@suse.de> |
arm64: Fix layerscape mmu setup With commit 7985cdf we converted all systems except for the Layerscape SoCs to the generic descriptor table based page table setup. On the Layerscape SoCs however, we just provide an empty table stub and do the setup ourselves. To reserve enough memory for the tables, we need to override the default counting mechanism which would end up with an empty table because we have no maps. Fixes: 7985cdf Reported-by: York Sun <york.sun@nxp.com> CC: Alison Wang <alison.wang@nxp.com> CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Alexander Graf <agraf@suse.de> Tested-by: York Sun <york.sun@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
7985cdf7 |
|
03-Mar-2016 |
Alexander Graf <agraf@suse.de> |
arm64: Remove non-full-va map code By now the code to only have a single page table level with 64k page size and 42 bit address space is no longer used by any board in tree, so we can safely remove it. To clean up code, move the layerscape mmu code to the new defines, removing redundant field definitions. Signed-off-by: Alexander Graf <agraf@suse.de> |
#
c0492141 |
|
07-Dec-2015 |
York Sun <yorksun@freescale.com> |
armv8: fsl-layerscale: Rewrite reserving memory for MC and debug server MC and debug server are not board-specific. Move reserving memory to SoC file, using the new board_reserve_ram_top function. Reduce debug server memory by 2MB to make room for secure memory. In the system with MC and debug server, the top of u-boot memory is not the end of memory. PRAM is not used for this reservation. Signed-off-by: York Sun <yorksun@freescale.com> |
#
c107c0c0 |
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04-Dec-2015 |
York Sun <yorksun@freescale.com> |
armv8: fsl-layerscape: Make DDR non secure in MMU tables DDR has been set as secure in MMU tables. Non-secure master such as SDHC DMA cannot access data correctly. Mixing secure and non- secure MMU entries requirs the MMU tables themselves in secure memory. This patch moves MMU tables into a secure DDR area. Early MMU tables are changed to set DDR as non-secure. A new table is added into final MMU tables so secure memory can have 2MB granuality. gd->secure_ram tracks the location of this secure memory. For ARMv8 SoCs, the RAM base is not zero and RAM is divided into several banks. gd->secure_ram needs to be maintained before using. This maintenance is board-specific, depending on the SoC and memory bank of the secure memory falls into. Signed-off-by: York Sun <yorksun@freescale.com> |
#
b4017364 |
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04-Nov-2015 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
armv8: ls2085a: Add workaround of errata A009635 If the core runs at higher than x3 speed of the platform, there is possiblity about sev instruction to getting missed by other cores. This is because of SoC Run Control block may not able to sample the EVENTI(Sev) signals. Configure Run Control and EPU to periodically send out EVENTI signals to wake up A57 cores. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
d764129d |
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04-Nov-2015 |
Alison Wang <b18965@freescale.com> |
armv8/layerscape: Update MMU table with execute-never bits For most device addresses excution shouldn't be allowed. Revise the MMU table to enforce execute-never bits. OCRAM, DDR and IFC are allowed for excution. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Alison Wang <alison.wang@freescale.com> Reported-by: Zhichun Hua <zhichun.hua@freescale.com> |
#
44937214 |
|
09-Nov-2015 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
armv8: LS2080A: Rename LS2085A to reflect LS2080A LS2080A is a prime personality of Freescale’s LS2085A. It is a non-AIOP personality without support of DP-DDR, L2 switch, 1588, PCIe endpoint etc. So renaming existing LS2085A code base to reflect LS2080A (Prime personality) Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> [York Sun: Dropped #ifdef in cpu.c for cpu_type_list] Reviewed-by: York Sun <yorksun@freescale.com> |
#
e8297341 |
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26-Oct-2015 |
Shaohui Xie <Shaohui.Xie@freescale.com> |
armv8/ls1043a: Add Fman support Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
8281c58f |
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26-Oct-2015 |
Mingkai Hu <Mingkai.Hu@freescale.com> |
armv8/fsl_lsch2: Add fsl_lsch2 SoC Freescale LayerScape with Chassis Generation 2 is a set of SoCs with ARMv8 cores and 2rd generation of Chassis. Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
9f3183d2 |
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26-Oct-2015 |
Mingkai Hu <Mingkai.Hu@freescale.com> |
armv8/fsl_lsch3: Change arch to fsl-layerscape There are two LS series processors are built on ARMv8 Layersacpe architecture currently, LS2085A and LS1043A. They are based on ARMv8 core although use different chassis, so create fsl-layerscape to refactor the common code for the LS series processors which also paves the way for adding LS1043A platform. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
0490cab5 |
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08-Aug-2019 |
Thomas Schaefer <thomas.schaefer@kontron.com> |
armv8: ls1028a: configure PMU's PCTBENR to enable WDT The SP805-WDT module on LS1028A requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. The watchdog clock needs to be enabled first. Signed-off-by: Thomas Schaefer <thomas.schaefer@kontron.com> Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
f3998fdc |
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02-Aug-2019 |
Simon Glass <sjg@chromium.org> |
env: Rename environment.h to env_internal.h This file contains lots of internal details about the environment. Most code can include env.h instead, calling the functions there as needed. Rename this file and add a comment at the top to indicate its internal nature. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> [trini: Fixup apalis-tk1.c] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
3a7d5571 |
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01-Aug-2019 |
Simon Glass <sjg@chromium.org> |
env: Move env_get_f() to env.h Move this function over to the new header file. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
d9532e80 |
|
23-Apr-2019 |
Udit Agarwal <udit.agarwal@nxp.com> |
armv8: fsl-layerscape: Set env_loc to ENVL_NOWHERE with CONFIG_ENV_IS_NOWHERE. ENVL_NOWHERE is dependent on CONFIG_ENV_IS_NOWHERE and not on CONFIG_CHAIN_OF_TRUST so return ENVL_NOWHERE when CONFIG_ENV_IS_NOWHERE is enabled Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
d4ad111d |
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10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
059d9422 |
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08-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: lx2160a: add MMU table entries for PCIe The lx2160a have up to 6 PCIe controllers and have different address and size of PCIe region. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
8348e798 |
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08-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: layerscape: use PCIe address macro for precompile PCIe MMU entry Change to use PCIe address macro to determine if precompile the PCIe MMU table entry. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
10015025 |
|
03-May-2019 |
Trevor Woerner <trevor@toganlabs.com> |
CONFIG_SPL_SYS_[DI]CACHE_OFF: add While converting CONFIG_SYS_[DI]CACHE_OFF to Kconfig, there are instances where these configuration items are conditional on SPL. This commit adds SPL variants of these configuration items, uses CONFIG_IS_ENABLED(), and updates the configurations as required. Acked-by: Alexey Brodkin <abrodkin@synopsys.com> Signed-off-by: Trevor Woerner <trevor@toganlabs.com> [trini: Make the default depend on the setting for full U-Boot, update more zynq hardware] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
2e53759d |
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29-Oct-2018 |
Pankaj Bansal <pankaj.bansal@nxp.com> |
armv8: fsl-layerscape: reorder rgmii dpmacs' enablement some dpmacs in armv8a based freescale layerscape SOCs can be configured via both serdes(sgmii, xfi, xlaui etc) bits and via EC*_PMUX(rgmii) bits in RCW. e.g. dpmac 17 and 18 in LX2160A can be configured as SGMII from serdes bits and as RGMII via EC1_PMUX/EC2_PMUX bits Now if a dpmac is enabled by serdes bits then it takes precedence over EC*_PMUX bits. i.e. in LX2160A if we select serdes protocol that configures dpmac17 as SGMII and set the EC1_PMUX as RGMII, then the dpmac is SGMII and not RGMII. Therefore, move the fsl_rgmii_init after fsl_serdes_init. in fsl_rgmii_init function of SOC, we will check if the dpmac is enabled or not? if it is (fsl_serdes_init has already enabled the dpmac), then don't enable it. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
ec88ff80 |
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19-Dec-2018 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1043a: add SVR definitions for 23x23 package silicon LS1043A/LS1023A 23x23 package silicon has different SVR:VAR_PER. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
d23da2ae |
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26-Dec-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: fixes for TFABOOT framework Fixes for TFABOOT framework - update eMMC bootsrc to SD_MMC - Increase buffer size for mcinitcmd from 256 to 512 - Fix mcinitcmd and bootcmd for Secure Boot Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
4909b89e |
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29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
d6fdec21 |
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29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8:fsl-layerscape: Add support for Chassis 3.2 NXP layerscape architecture Chassis 3.2 builds upon chassis3 architecture with changes like DDR Memory map change, removal of IFC and support of upto 8 I2C controller. Patch add README.lsch3_2 and the above changes under macro CONFIG_NXP_LSCH3_2. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
56db948b |
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05-Nov-2018 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: Update parsing boot source Workaround of erratum A010539 clears the RCW source field in PORSR1 register, causing failure of detecting boot source using this method. Use SMC call if U-Boot runs at EL2. If SMC is not implemented or running at EL3, continue to read PORSR1 and presume QSPI as boot source if erratum workaround A010539 is enabled and RCW source is cleared. Signed-off-by: York Sun <york.sun@nxp.com> |
#
681d489e |
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05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: layerscape: add SMC calls for DDR size and bank info Adds SMC calls for getting DDR size and bank info for TFABOOT. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
2141d250 |
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05-Nov-2018 |
Pankit Garg <pankit.garg@nxp.com> |
armv8: fsl-layerscape: bootcmd identification for TFABOOT Adds bootcmd identificaton on basis on boot source, valid in TFABOOT configuration. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> [YS: remove unnecessary braces] Reviewed-by: York Sun <york.sun@nxp.com> |
#
4c417384 |
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05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com> |
#
535d76a1 |
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05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: layerscape: Add TFABOOT support Adds TFABOOT support config option and add generic code to enable execution from DDR. Signed-off-by: York Sun <york.sun@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> |
#
e3506480 |
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05-Nov-2018 |
Pankit Garg <pankit.garg@nxp.com> |
armv8: fsl-layerscape: change tlb base from OCRAM to DDR in EL < 3 Change tlb base address from OCRAM to DDR when exception level is less than 3. Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
d171c707 |
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05-Nov-2018 |
York Sun <york.sun@nxp.com> |
move data structure out of cpu.h Move static definitions to cpu.c file, as it doesn't allow the cpu.h file to be included in multiple c files. Signed-off-by: York Sun <york.sun@nxp.com> |
#
9b5e6396 |
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30-Aug-2018 |
Stephen Warren <swarren@nvidia.com> |
efi_loader: simplify ifdefs Use CONFIG_IS_ENABLED(EFI_LOADER) to avoid explicitly checking CONFIG_SPL too. This simplifies the conditional. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Alexander Graf <agraf@suse.de> |
#
9cce5663 |
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16-Jul-2018 |
Joe Hershberger <joe.hershberger@ni.com> |
arm: Prevent redefinition error in fsl-layerscape The include/phy.h will start including dm.h, which pulls in linux/compat.h after the attempted redefinition in arch/arm/include/asm/armv8/mmu.h, so move this include to allow redefinition. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> |
#
83d290c5 |
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06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
482fc90c |
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06-Feb-2018 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
efi_loader: add missing EFI_RESET_PLATFORM_SPECIFIC EFI_RESET_PLATFORM_SPECIFIC is one of the values that can be used for the EFI service ResetSystem. The missing definition is added. The value has to handled in efi_reset_system(). Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Alexander Graf <agraf@suse.de> |
#
22c793e6 |
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03-Mar-2018 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
efi_loader: exit status for efi_reset_system_init efi_reset_system_init provides the architecture or board specific initialization of the EFI subsystem. Errors should be caught and signalled by a return code. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Alexander Graf <agraf@suse.de> |
#
958b2ed5 |
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09-Jan-2018 |
Zhang Ying-22455 <ying.zhang22455@nxp.com> |
armv8/ls1088a: configure PMU's PCTBENR to enable WDT The SP805-WDT module on LS1088A requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. The watchdog clock needs to be enabled first. Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
44262327 |
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15-Dec-2017 |
Ahmed Mansour <ahmed.mansour@nxp.com> |
drivers/misc: Share qbman init between archs This patch adds changes necessary to move functionality present in PowerPC folders with ARM architectures that have DPAA1 QBMan hardware - Create new board/freescale/common/fsl_portals.c to house shared device tree fixups for DPAA1 devices with ARM and PowerPC cores - Add new header file to top includes directory to allow files in both architectures to grab the function prototypes - Port inhibit_portals() from PowerPC to ARM. This function is used in setup to disable interrupts on all QMan and BMan portals. It is needed because the interrupts are enabled by default for all portals including unused/uninitialised portals. When the kernel attempts to go to deep sleep the unused portals prevent it from doing so Signed-off-by: Ahmed Mansour <ahmed.mansour@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
a8f33034 |
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03-Dec-2017 |
Wenbin song <wenbin.song@nxp.com> |
armv8: ls1043a/ls2080a: check SoC by device ID Check LS1043A/LS2080a by device ID without using personality ID to determine revision number. This check applies to all various personalities of the same SoC family. Signed-off-by: Wenbin Song <wenbin.song@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
2db53cfe |
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09-Nov-2017 |
Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
armv8: fsl-layerscape: Add support of disabling core prefetch Instruction prefetch feature is by default enabled during core release. This patch add support of disabling instruction prefetch by setting core mask in PPA. Here each core mask bit represents a core and prefetch is disabled at the time of core release. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
7eb40f0f |
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28-Sep-2017 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: Avoid running dram_init_banksize again gd->ram_size is reduced in this function to reserve secure memory. Avoid running this function again to further reduce memory size. This fixes issue for SPL boot with PPA image loaded in which case secure memory is incorrectly allocated due to repeated calling. Signed-off-by: York Sun <york.sun@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
710d0cd7 |
|
03-Oct-2017 |
Sumit Garg <sumit.garg@nxp.com> |
armv8: fsl-layerscape: Allocate Secure memory from first ddr region This change is required due to trusted OS (OP-TEE) not being position independent code, it requires compile time fixed base address. To take care of this it is assumed that all layerscape armv8 platforms has minimum 2G ddr in first region. So we can have fixed address space (66 MB -> (2MB for PPA + 64MB for trusted OS)) allocated from top of first 2G ddr region and compile trusted OS with this fixed base address. But one exception here is ls1012 where we have only 1G (rdb) or 512M (frdm) ddr memory. For those we can have different fixed compile time base addresses for trusted OS. Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
e9303a41 |
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07-Sep-2017 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: Fix MC reserved memory calculation In case high region memory doesn't have enough space for Management Complex (MC), the return value should indicate a failure so the caller can handle it accordingly. Signed-off-by: York Sun <york.sun@nxp.com> Reported-by: Ebony Zhu <ebony.zhu@nxp.com> |
#
17d066fc |
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31-Aug-2017 |
Ashish Kumar <Ashish.Kumar@nxp.com> |
armv8: fsl-layerscape: Support to add RGMII for ls1088aqds This patch adds support for RGMII protocol NXP's LDPAA2 support RGMII protocol. LS1088A is the first Soc supporting both RGMII and SGMII. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Amrita Kumari <amrita.kumari@nxp.com> Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
63b2316c |
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10-Aug-2017 |
Ashish Kumar <Ashish.Kumar@nxp.com> |
fsl-layerscape: Consolidate registers space defination for CCI-400 bus CoreLink Cache Coherent Interconnect (CCI) provides full cache coherency between two clusters of multi-core CPUs and I/O coherency for devices and I/O masters. This patch add new config option SYS_FSL_HAS_CCI400 and moves existing register space definaton of CCI-400 bus to fsl_immap to be shared. CONFIG_SYS_CCI400_ADDR is replaced with SYS_CCI400_OFFSET in Kconfig. Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> [YS: revised commit message, squashed patches for armv8 and armv7] Reviewed-by: York Sun <york.sun@nxp.com> |
#
6e2941d7 |
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17-May-2017 |
Simon Glass <sjg@chromium.org> |
common: freescale: Move arch-specific declarations The declarations should not be in common.h. Move them to the arch-specific headers. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Fixup thinko defined(FSL_LSCH3) -> defined(CONFIG_FSL_LSCH3)] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
399e2bb6 |
|
15-May-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Make U-Boot EL2 safe When U-Boot boots from EL2, skip some lowlevel init code requiring EL3, including CCI-400/CCN-504, trust zone, GIC, etc. These initialization tasks are carried out before U-Boot runs. This applies to the RAM version image used for SPL boot if PPA is loaded first. Signed-off-by: York Sun <york.sun@nxp.com> |
#
1f55a938 |
|
05-May-2017 |
Santan Kumar <santan.kumar@nxp.com> |
armv8: ls2080aqds: Add support for SD boot Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
e809e747 |
|
27-Apr-2017 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: fsl-layerscape: Add NXP LS2081A, LS2041A SoC support The QorIQ LS2081A SoC has eight 64-bit ARM v8 Cortex A72 cores and is built on layerscape architecture. It is 40-pin derivative of LS2084A (non-AIOP personality of LS2088A). So feature-wise it is same as LS2084A. LS2041A is a 4-core personality of LS2081A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
026f30ec |
|
18-Apr-2017 |
Yuantian Tang <andy.tang@nxp.com> |
arm: psci: make psci usable on single core socs PSCI can be used on both multiple and single core socs. Current implementation only allows PSCI to work on multiple core socs. This patch removes this restriction so that PSCI can work on single core socs as well. Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
4a3ab193 |
|
27-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: ls2080a: Drop macro CONFIG_LS2080A Use CONFIG_ARCH_LS2080A instead. Signed-off-by: York Sun <york.sun@nxp.com> |
#
3eace37e |
|
06-Apr-2017 |
Simon Glass <sjg@chromium.org> |
arm: freescale: Rename initdram() to fsl_initdram() This function name shadows a global name but is in fact different. This is very confusing. Rename it to help with the following refactoring. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
76b00aca |
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31-Mar-2017 |
Simon Glass <sjg@chromium.org> |
board_f: Drop setup_dram_config() wrapper By making dram_init_banksize() return an error code we can drop the wrapper. Adjust this and clean up all implementations. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
088454cd |
|
31-Mar-2017 |
Simon Glass <sjg@chromium.org> |
board_f: Drop return value from initdram() At present we cannot use this function as an init sequence call without a wrapper, since it returns the RAM size. Adjust it to set the RAM size in global_data instead, and return 0 on success. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
52c41180 |
|
31-Mar-2017 |
Simon Glass <sjg@chromium.org> |
board_f: Drop board_type parameter from initdram() It looks like only cm5200 and tqm8xx use this feature, so we don't really need it in generic code. Drop it and have the users access gd->board_type directly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
3d8553f0 |
|
02-Mar-2017 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
pci: layerscape: add LS2088A series SoC pcie support The LS2088A series SoCs has different physical memory map address and CCSR registers address against LS2080A series SoCs. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
eea1cb77 |
|
13-Feb-2017 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8/fsl-layerscape: Update erratum A009635 implementation Erratum A009635 is valid only for LS2080A SoC and its personality. Add SoC svr check. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
4961eafc |
|
06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Update early MMU for DDR after initialization In early MMU table, DDR has to be mapped as device memory to avoid speculative access. After DDR is initialized, it needs to be updated to normal memory to allow code execution. To simplify the code, dram_init() is moved into a common file as a weak function. Signed-off-by: York Sun <york.sun@nxp.com> |
#
a045a0c3 |
|
06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Fix the sequence of changing MMU table This patch follows the break-before-make process when making changes to MMU table. MMU is disabled before changing TTBR to avoid any potential race condition. Signed-off-by: York Sun <york.sun@nxp.com> |
#
24f55496 |
|
06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Update MMU mapping with actual DDR size Update mapping with actual DDR size. Non-existing memory should not be mapped as "normal" memory to avoid speculative access. Signed-off-by: York Sun <york.sun@nxp.com> |
#
36cc0de0 |
|
06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Rewrite memory reservation For ARMv8 Layerscape SoCs, secure memory and MC memorey are reserved at the end of DDR. DDR is spit into two or three banks. This patch reverts commit aabd7ddb and simplifies the calculation of reserved memory, and moves the code into common SoC file. Secure memory is carved out first. DDR bank size is reduced. Reserved memory is then allocated on the top of available memory. U-Boot still has access to reserved memory as data transferring is needed. Device tree is fixed with reduced memory size to hide the reserved memory from OS. The same region is reserved for efi_loader. Signed-off-by: York Sun <york.sun@nxp.com> |
#
daa92644 |
|
16-Jan-2017 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
ARMv8/sec_firmware: relocated and renamed the config FSL_PPA_ARMV8_PSCI Moved the config FSL_PPA_ARMV8_PSCI from fsl-layerscape's Kconfig to Kconfig under armv8 and renamed it to SEC_FIRMWARE_ARMV8_PSCI. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
904110c7 |
|
10-Jan-2017 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8/fsl-lsch2: refactor the clock system initialization Up to now, there are 3 kind of SoCs under Layerscape Chassis 2, like LS1043A, LS1046A and LS1012A. But the clocks tree has a lot of differences, for instance, the IP modules have different dividers to derive its clock from Platform PLL. And the core cluster PLL and platform PLL maybe have different reference clocks, such as LS1012A. Another problem is which clock/PLL should be described by sys_info->freq_systembus, it is confused in Layerscape Chissis 2. This patch is to bind the sys_info->freq_systembus to the Platform PLL, and handle the different divider of IP modules separately between different SoCs, and separate reference clocks of core cluster PLL and platform PLL. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
2d16a1a6 |
|
07-Dec-2016 |
macro.wave.z@gmail.com <macro.wave.z@gmail.com> |
ARMv8: LS1043A: change macro CONFIG_ARMV8_PSCI definition NXP/Freescale uses macro CONFIG_ARMV8_PSCI to enable their private PSCI implementation in PPA firmware, but this macro naming too generic, so this patch replaces it with a specic one CONFIG_FSL_PPA_ARMV8_PSCI. And this macro CONFIG_ARMV8_PSCI will be used for a generic PSCI for ARMv8 which will be added in following patchs. Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
02fb2761 |
|
20-Nov-2016 |
Shengzhou Liu <Shengzhou.Liu@nxp.com> |
fsl/ddr: Add erratum_a009942_check_cpo and clean related erratum - add additional function erratum_a009942_check_cpo to check if the board needs tuning CPO calibration for optimal setting. - move ERRATUM_A009942(with revision to check cpo_sample option) from fsl_ddr_gen4.c to ctrl_regs.c for reuse on all DDR4/DDR3 parts. - move ERRATUM_A008378 from fsl_ddr_gen4.c to ctrl_regs.c - remove obsolete ERRATUM_A004934 which is replaced with ERRATUM_A009942. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> [YS: Replaced CONFIG_QEMU_E500 with CONFIG_ARCH_QEMU_E500] Reviewed-by: York Sun <york.sun@nxp.com> |
#
e87c673c |
|
16-Nov-2016 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8/fsl-lsch3: Update code to release secondary cores NXP ARMv8 SoC LS2080A release all secondary cores in one-go. But other new SoCs like LS2088A, LS1088A release secondary cores one by one. Update code to release secondary cores based on SoC SVR Add code to release cores one by one for non LS2080A SoCs Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> [YS: remove "inline" from declaration of initiator_type] Reviewed-by: York Sun <york.sun@nxp.com> |
#
f6b96ff6 |
|
16-Nov-2016 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Use SVR based timer base address detection Timer controller base address has been changed from LS2080A SoC (and its personalities) to new SoCs like LS2088A, LS1088A. Use SVR based timer base address detection to avoid compile time #ifdef. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
f6a70b3a |
|
16-Nov-2016 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add generic get_svr() in assembly Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
78d57842 |
|
16-Nov-2016 |
Alexander Graf <agraf@suse.de> |
armv8: fsl-layerscape: Add support for efi_loader RTS reset When implementing efi loader support, we can expose runtime services for payloads. One such service is CPU reset. This patch implements RTS CPU reset support for layerscape systems. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: York Sun <york.sun@nxp.com> |
#
ef9a5fd8 |
|
13-Sep-2016 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: Fix "cpu status" command The core position is not continuous for some SoCs. For example, valid cores may present at position 0, 1, 4, 5, 8, 9, etc. Some registers (including boot release register) only count existing cores. Current implementation of cpu_mask() complies with the continuous numbering. However, command "cpu status" queries the spin table with actual core position. Add functions to calculate core position from core number, to correctly calculate offsets. Tested on LS2080ARDB and LS1043ARDB. Signed-off-by: York Sun <york.sun@nxp.com> |
#
5d1a7a9d |
|
13-Sep-2016 |
Wenbin Song <wenbin.song@nxp.com> |
armv8/fsl-layerscape: print SoC revsion number The exact SoC revsion number can be recognized from U-Boot log. Signed-off-by: Wenbin Song <wenbin.song@nxp.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
cbe7706a |
|
26-Sep-2016 |
Tom Rini <trini@konsulko.com> |
Merge git://git.denx.de/u-boot-fsl-qoriq trini: Drop local memset() from examples/standalone/mem_to_mem_idma2intr.c Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
1221ce45 |
|
20-Sep-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
treewide: replace #include <asm/errno.h> with <linux/errno.h> Now, arch/${ARCH}/include/asm/errno.h and include/linux/errno.h have the same content. (both just wrap <asm-generic/errno.h>) Replace all include directives for <asm/errno.h> with <linux/errno.h>. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> [trini: Fixup include/clk.] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
b63a9506 |
|
03-Aug-2016 |
York Sun <york.sun@nxp.com> |
armv8: ls2080a: Remove debug server support Debug server feature has been dropped from roadmap. Signed-off-by: York Sun <york.sun@nxp.com> |
#
ed7a3943 |
|
22-Jul-2016 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: mmu: Fix enabling MMU MMU bit in SCTLR needs to be set explicitly after tables are created. It isn't an issue for EL3 becuase this bit is already set by early MMU setup. But for other exception levels this bit was not set. Signed-off-by: York Sun <york.sun@nxp.com> |
#
79119a4d |
|
05-Jul-2016 |
Alison Wang <b18965@freescale.com> |
armv8: fsl-layerscape: Add A72 core detection Add support to detect Cortex-A72 core for printing it out. The Initiator Version of A72 core should be 0x4. Signed-off-by: Alison Wang <alison.wang@nxp.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
032d5bb4 |
|
28-Jun-2016 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
ARMv8/Layerscape: switch SMP method accordingly If the PSCI and PPA is ready, skip the fixup for spin-table and waking secondary cores. Otherwise, change SMP method to spin-table, and the device node of PSCI will be removed. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
85cdf38e |
|
28-Jun-2016 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: fsl-layerscape: add i/d-cache enable function to enable_caches This function assume that the d-cache and MMU has been enabled earlier, so it just created MMU table in main memory. But the assumption is not always correct, for example, the early setup is done in EL3, while enable_caches() is called when the PE has turned into another EL. Define the function mmu_setup() for fsl-layerscape to cover the weak one. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
5ad5823d |
|
24-Jun-2016 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Convert to use common MMU framework Drop platform code to create static MMU tables. Use common framework to create MMU tables on the run. Tested on LS2080ARDB with secure and non-secure ram scenarios. Signed-off-by: York Sun <york.sun@nxp.com> |
#
e61a7534 |
|
24-Jun-2016 |
York Sun <york.sun@nxp.com> |
armv8: Move secure_ram variable out of generic global data Secure_ram variable was put in generic global data. But only ARMv8 uses this variable. Move it to ARM specific data structure. Signed-off-by: York Sun <york.sun@nxp.com> |
#
a10a31ec |
|
18-Jun-2016 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of git://git.denx.de/u-boot-usb Signed-off-by: Tom Rini <trini@konsulko.com> Conflicts: arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
|
#
6fb522dc |
|
12-Jun-2016 |
Sriram Dash <sriram.dash@nxp.com> |
arm64: fsl-layerscape: add get_svr and IS_SVR_REV helper Adds get_svr and IS_SVR_REV helpers for ARMv8 platforms, similar to PPC and ARMv7. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> |
#
a758177f |
|
07-Jun-2016 |
Yunhui Cui <yunhui.cui@nxp.com> |
armv8/ls2080a: configure PMU's PCTBENR to enable WDT The SP805-WDT module on LS2080A requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. The watchdog clock needs to be enabled first. Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
acb8f5e9 |
|
21-Apr-2016 |
Alison Wang <b18965@freescale.com> |
armv8: fsl-layerscape: Remove unnecessary flushing dcache As the issue about the stack will get corrupted when switching between the early and final mmu tables is fixed by commit 70e21b064, the workaround to flush dcache is unnecessary and should be removed. Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
3c1d218a |
|
04-Apr-2016 |
York Sun <york.sun@nxp.com> |
armv8: LS2080A: Consolidate LS2080A and LS2085A LS2080A is the primary SoC, and LS2085A is a personality with AIOP and DPAA DDR. The RDB and QDS boards support both personality. By detecting the SVR at runtime, a single image per board can support both SoCs. It gives users flexibility to swtich SoC without the need to reprogram the board. Signed-off-by: York Sun <york.sun@nxp.com> CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
c05016ab |
|
21-Mar-2016 |
Alexander Graf <agraf@suse.de> |
arm64: Fix layerscape mmu setup With commit 7985cdf we converted all systems except for the Layerscape SoCs to the generic descriptor table based page table setup. On the Layerscape SoCs however, we just provide an empty table stub and do the setup ourselves. To reserve enough memory for the tables, we need to override the default counting mechanism which would end up with an empty table because we have no maps. Fixes: 7985cdf Reported-by: York Sun <york.sun@nxp.com> CC: Alison Wang <alison.wang@nxp.com> CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Alexander Graf <agraf@suse.de> Tested-by: York Sun <york.sun@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
7985cdf7 |
|
03-Mar-2016 |
Alexander Graf <agraf@suse.de> |
arm64: Remove non-full-va map code By now the code to only have a single page table level with 64k page size and 42 bit address space is no longer used by any board in tree, so we can safely remove it. To clean up code, move the layerscape mmu code to the new defines, removing redundant field definitions. Signed-off-by: Alexander Graf <agraf@suse.de> |
#
c0492141 |
|
07-Dec-2015 |
York Sun <yorksun@freescale.com> |
armv8: fsl-layerscale: Rewrite reserving memory for MC and debug server MC and debug server are not board-specific. Move reserving memory to SoC file, using the new board_reserve_ram_top function. Reduce debug server memory by 2MB to make room for secure memory. In the system with MC and debug server, the top of u-boot memory is not the end of memory. PRAM is not used for this reservation. Signed-off-by: York Sun <yorksun@freescale.com> |
#
c107c0c0 |
|
04-Dec-2015 |
York Sun <yorksun@freescale.com> |
armv8: fsl-layerscape: Make DDR non secure in MMU tables DDR has been set as secure in MMU tables. Non-secure master such as SDHC DMA cannot access data correctly. Mixing secure and non- secure MMU entries requirs the MMU tables themselves in secure memory. This patch moves MMU tables into a secure DDR area. Early MMU tables are changed to set DDR as non-secure. A new table is added into final MMU tables so secure memory can have 2MB granuality. gd->secure_ram tracks the location of this secure memory. For ARMv8 SoCs, the RAM base is not zero and RAM is divided into several banks. gd->secure_ram needs to be maintained before using. This maintenance is board-specific, depending on the SoC and memory bank of the secure memory falls into. Signed-off-by: York Sun <yorksun@freescale.com> |
#
b4017364 |
|
04-Nov-2015 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
armv8: ls2085a: Add workaround of errata A009635 If the core runs at higher than x3 speed of the platform, there is possiblity about sev instruction to getting missed by other cores. This is because of SoC Run Control block may not able to sample the EVENTI(Sev) signals. Configure Run Control and EPU to periodically send out EVENTI signals to wake up A57 cores. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
d764129d |
|
04-Nov-2015 |
Alison Wang <b18965@freescale.com> |
armv8/layerscape: Update MMU table with execute-never bits For most device addresses excution shouldn't be allowed. Revise the MMU table to enforce execute-never bits. OCRAM, DDR and IFC are allowed for excution. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Alison Wang <alison.wang@freescale.com> Reported-by: Zhichun Hua <zhichun.hua@freescale.com> |
#
44937214 |
|
09-Nov-2015 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
armv8: LS2080A: Rename LS2085A to reflect LS2080A LS2080A is a prime personality of Freescale’s LS2085A. It is a non-AIOP personality without support of DP-DDR, L2 switch, 1588, PCIe endpoint etc. So renaming existing LS2085A code base to reflect LS2080A (Prime personality) Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> [York Sun: Dropped #ifdef in cpu.c for cpu_type_list] Reviewed-by: York Sun <yorksun@freescale.com> |
#
e8297341 |
|
26-Oct-2015 |
Shaohui Xie <Shaohui.Xie@freescale.com> |
armv8/ls1043a: Add Fman support Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
8281c58f |
|
26-Oct-2015 |
Mingkai Hu <Mingkai.Hu@freescale.com> |
armv8/fsl_lsch2: Add fsl_lsch2 SoC Freescale LayerScape with Chassis Generation 2 is a set of SoCs with ARMv8 cores and 2rd generation of Chassis. Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
9f3183d2 |
|
26-Oct-2015 |
Mingkai Hu <Mingkai.Hu@freescale.com> |
armv8/fsl_lsch3: Change arch to fsl-layerscape There are two LS series processors are built on ARMv8 Layersacpe architecture currently, LS2085A and LS1043A. They are based on ARMv8 core although use different chassis, so create fsl-layerscape to refactor the common code for the LS series processors which also paves the way for adding LS1043A platform. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
9b5e6396 |
|
30-Aug-2018 |
Stephen Warren <swarren@nvidia.com> |
efi_loader: simplify ifdefs Use CONFIG_IS_ENABLED(EFI_LOADER) to avoid explicitly checking CONFIG_SPL too. This simplifies the conditional. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Alexander Graf <agraf@suse.de>
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#
9cce5663 |
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16-Jul-2018 |
Joe Hershberger <joe.hershberger@ni.com> |
arm: Prevent redefinition error in fsl-layerscape The include/phy.h will start including dm.h, which pulls in linux/compat.h after the attempted redefinition in arch/arm/include/asm/armv8/mmu.h, so move this include to allow redefinition. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
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83d290c5 |
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06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
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482fc90c |
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06-Feb-2018 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
efi_loader: add missing EFI_RESET_PLATFORM_SPECIFIC EFI_RESET_PLATFORM_SPECIFIC is one of the values that can be used for the EFI service ResetSystem. The missing definition is added. The value has to handled in efi_reset_system(). Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Alexander Graf <agraf@suse.de>
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22c793e6 |
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03-Mar-2018 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
efi_loader: exit status for efi_reset_system_init efi_reset_system_init provides the architecture or board specific initialization of the EFI subsystem. Errors should be caught and signalled by a return code. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Alexander Graf <agraf@suse.de>
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958b2ed5 |
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09-Jan-2018 |
Zhang Ying-22455 <ying.zhang22455@nxp.com> |
armv8/ls1088a: configure PMU's PCTBENR to enable WDT The SP805-WDT module on LS1088A requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. The watchdog clock needs to be enabled first. Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
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44262327 |
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15-Dec-2017 |
Ahmed Mansour <ahmed.mansour@nxp.com> |
drivers/misc: Share qbman init between archs This patch adds changes necessary to move functionality present in PowerPC folders with ARM architectures that have DPAA1 QBMan hardware - Create new board/freescale/common/fsl_portals.c to house shared device tree fixups for DPAA1 devices with ARM and PowerPC cores - Add new header file to top includes directory to allow files in both architectures to grab the function prototypes - Port inhibit_portals() from PowerPC to ARM. This function is used in setup to disable interrupts on all QMan and BMan portals. It is needed because the interrupts are enabled by default for all portals including unused/uninitialised portals. When the kernel attempts to go to deep sleep the unused portals prevent it from doing so Signed-off-by: Ahmed Mansour <ahmed.mansour@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
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a8f33034 |
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03-Dec-2017 |
Wenbin song <wenbin.song@nxp.com> |
armv8: ls1043a/ls2080a: check SoC by device ID Check LS1043A/LS2080a by device ID without using personality ID to determine revision number. This check applies to all various personalities of the same SoC family. Signed-off-by: Wenbin Song <wenbin.song@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
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2db53cfe |
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09-Nov-2017 |
Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
armv8: fsl-layerscape: Add support of disabling core prefetch Instruction prefetch feature is by default enabled during core release. This patch add support of disabling instruction prefetch by setting core mask in PPA. Here each core mask bit represents a core and prefetch is disabled at the time of core release. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
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7eb40f0f |
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28-Sep-2017 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: Avoid running dram_init_banksize again gd->ram_size is reduced in this function to reserve secure memory. Avoid running this function again to further reduce memory size. This fixes issue for SPL boot with PPA image loaded in which case secure memory is incorrectly allocated due to repeated calling. Signed-off-by: York Sun <york.sun@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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710d0cd7 |
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03-Oct-2017 |
Sumit Garg <sumit.garg@nxp.com> |
armv8: fsl-layerscape: Allocate Secure memory from first ddr region This change is required due to trusted OS (OP-TEE) not being position independent code, it requires compile time fixed base address. To take care of this it is assumed that all layerscape armv8 platforms has minimum 2G ddr in first region. So we can have fixed address space (66 MB -> (2MB for PPA + 64MB for trusted OS)) allocated from top of first 2G ddr region and compile trusted OS with this fixed base address. But one exception here is ls1012 where we have only 1G (rdb) or 512M (frdm) ddr memory. For those we can have different fixed compile time base addresses for trusted OS. Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
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e9303a41 |
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07-Sep-2017 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: Fix MC reserved memory calculation In case high region memory doesn't have enough space for Management Complex (MC), the return value should indicate a failure so the caller can handle it accordingly. Signed-off-by: York Sun <york.sun@nxp.com> Reported-by: Ebony Zhu <ebony.zhu@nxp.com>
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17d066fc |
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31-Aug-2017 |
Ashish Kumar <Ashish.Kumar@nxp.com> |
armv8: fsl-layerscape: Support to add RGMII for ls1088aqds This patch adds support for RGMII protocol NXP's LDPAA2 support RGMII protocol. LS1088A is the first Soc supporting both RGMII and SGMII. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Amrita Kumari <amrita.kumari@nxp.com> Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
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63b2316c |
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10-Aug-2017 |
Ashish Kumar <Ashish.Kumar@nxp.com> |
fsl-layerscape: Consolidate registers space defination for CCI-400 bus CoreLink Cache Coherent Interconnect (CCI) provides full cache coherency between two clusters of multi-core CPUs and I/O coherency for devices and I/O masters. This patch add new config option SYS_FSL_HAS_CCI400 and moves existing register space definaton of CCI-400 bus to fsl_immap to be shared. CONFIG_SYS_CCI400_ADDR is replaced with SYS_CCI400_OFFSET in Kconfig. Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> [YS: revised commit message, squashed patches for armv8 and armv7] Reviewed-by: York Sun <york.sun@nxp.com>
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6e2941d7 |
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17-May-2017 |
Simon Glass <sjg@chromium.org> |
common: freescale: Move arch-specific declarations The declarations should not be in common.h. Move them to the arch-specific headers. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Fixup thinko defined(FSL_LSCH3) -> defined(CONFIG_FSL_LSCH3)] Signed-off-by: Tom Rini <trini@konsulko.com>
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399e2bb6 |
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15-May-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Make U-Boot EL2 safe When U-Boot boots from EL2, skip some lowlevel init code requiring EL3, including CCI-400/CCN-504, trust zone, GIC, etc. These initialization tasks are carried out before U-Boot runs. This applies to the RAM version image used for SPL boot if PPA is loaded first. Signed-off-by: York Sun <york.sun@nxp.com>
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1f55a938 |
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05-May-2017 |
Santan Kumar <santan.kumar@nxp.com> |
armv8: ls2080aqds: Add support for SD boot Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
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e809e747 |
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27-Apr-2017 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: fsl-layerscape: Add NXP LS2081A, LS2041A SoC support The QorIQ LS2081A SoC has eight 64-bit ARM v8 Cortex A72 cores and is built on layerscape architecture. It is 40-pin derivative of LS2084A (non-AIOP personality of LS2088A). So feature-wise it is same as LS2084A. LS2041A is a 4-core personality of LS2081A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
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026f30ec |
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18-Apr-2017 |
Yuantian Tang <andy.tang@nxp.com> |
arm: psci: make psci usable on single core socs PSCI can be used on both multiple and single core socs. Current implementation only allows PSCI to work on multiple core socs. This patch removes this restriction so that PSCI can work on single core socs as well. Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
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4a3ab193 |
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27-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: ls2080a: Drop macro CONFIG_LS2080A Use CONFIG_ARCH_LS2080A instead. Signed-off-by: York Sun <york.sun@nxp.com>
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3eace37e |
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06-Apr-2017 |
Simon Glass <sjg@chromium.org> |
arm: freescale: Rename initdram() to fsl_initdram() This function name shadows a global name but is in fact different. This is very confusing. Rename it to help with the following refactoring. Signed-off-by: Simon Glass <sjg@chromium.org>
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76b00aca |
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31-Mar-2017 |
Simon Glass <sjg@chromium.org> |
board_f: Drop setup_dram_config() wrapper By making dram_init_banksize() return an error code we can drop the wrapper. Adjust this and clean up all implementations. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de>
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088454cd |
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31-Mar-2017 |
Simon Glass <sjg@chromium.org> |
board_f: Drop return value from initdram() At present we cannot use this function as an init sequence call without a wrapper, since it returns the RAM size. Adjust it to set the RAM size in global_data instead, and return 0 on success. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de>
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52c41180 |
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31-Mar-2017 |
Simon Glass <sjg@chromium.org> |
board_f: Drop board_type parameter from initdram() It looks like only cm5200 and tqm8xx use this feature, so we don't really need it in generic code. Drop it and have the users access gd->board_type directly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de>
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3d8553f0 |
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02-Mar-2017 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
pci: layerscape: add LS2088A series SoC pcie support The LS2088A series SoCs has different physical memory map address and CCSR registers address against LS2080A series SoCs. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
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eea1cb77 |
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13-Feb-2017 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8/fsl-layerscape: Update erratum A009635 implementation Erratum A009635 is valid only for LS2080A SoC and its personality. Add SoC svr check. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
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4961eafc |
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06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Update early MMU for DDR after initialization In early MMU table, DDR has to be mapped as device memory to avoid speculative access. After DDR is initialized, it needs to be updated to normal memory to allow code execution. To simplify the code, dram_init() is moved into a common file as a weak function. Signed-off-by: York Sun <york.sun@nxp.com>
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a045a0c3 |
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06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Fix the sequence of changing MMU table This patch follows the break-before-make process when making changes to MMU table. MMU is disabled before changing TTBR to avoid any potential race condition. Signed-off-by: York Sun <york.sun@nxp.com>
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24f55496 |
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06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Update MMU mapping with actual DDR size Update mapping with actual DDR size. Non-existing memory should not be mapped as "normal" memory to avoid speculative access. Signed-off-by: York Sun <york.sun@nxp.com>
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36cc0de0 |
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06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Rewrite memory reservation For ARMv8 Layerscape SoCs, secure memory and MC memorey are reserved at the end of DDR. DDR is spit into two or three banks. This patch reverts commit aabd7ddb and simplifies the calculation of reserved memory, and moves the code into common SoC file. Secure memory is carved out first. DDR bank size is reduced. Reserved memory is then allocated on the top of available memory. U-Boot still has access to reserved memory as data transferring is needed. Device tree is fixed with reduced memory size to hide the reserved memory from OS. The same region is reserved for efi_loader. Signed-off-by: York Sun <york.sun@nxp.com>
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daa92644 |
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16-Jan-2017 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
ARMv8/sec_firmware: relocated and renamed the config FSL_PPA_ARMV8_PSCI Moved the config FSL_PPA_ARMV8_PSCI from fsl-layerscape's Kconfig to Kconfig under armv8 and renamed it to SEC_FIRMWARE_ARMV8_PSCI. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
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904110c7 |
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10-Jan-2017 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8/fsl-lsch2: refactor the clock system initialization Up to now, there are 3 kind of SoCs under Layerscape Chassis 2, like LS1043A, LS1046A and LS1012A. But the clocks tree has a lot of differences, for instance, the IP modules have different dividers to derive its clock from Platform PLL. And the core cluster PLL and platform PLL maybe have different reference clocks, such as LS1012A. Another problem is which clock/PLL should be described by sys_info->freq_systembus, it is confused in Layerscape Chissis 2. This patch is to bind the sys_info->freq_systembus to the Platform PLL, and handle the different divider of IP modules separately between different SoCs, and separate reference clocks of core cluster PLL and platform PLL. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
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2d16a1a6 |
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07-Dec-2016 |
macro.wave.z@gmail.com <macro.wave.z@gmail.com> |
ARMv8: LS1043A: change macro CONFIG_ARMV8_PSCI definition NXP/Freescale uses macro CONFIG_ARMV8_PSCI to enable their private PSCI implementation in PPA firmware, but this macro naming too generic, so this patch replaces it with a specic one CONFIG_FSL_PPA_ARMV8_PSCI. And this macro CONFIG_ARMV8_PSCI will be used for a generic PSCI for ARMv8 which will be added in following patchs. Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <york.sun@nxp.com>
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02fb2761 |
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20-Nov-2016 |
Shengzhou Liu <Shengzhou.Liu@nxp.com> |
fsl/ddr: Add erratum_a009942_check_cpo and clean related erratum - add additional function erratum_a009942_check_cpo to check if the board needs tuning CPO calibration for optimal setting. - move ERRATUM_A009942(with revision to check cpo_sample option) from fsl_ddr_gen4.c to ctrl_regs.c for reuse on all DDR4/DDR3 parts. - move ERRATUM_A008378 from fsl_ddr_gen4.c to ctrl_regs.c - remove obsolete ERRATUM_A004934 which is replaced with ERRATUM_A009942. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> [YS: Replaced CONFIG_QEMU_E500 with CONFIG_ARCH_QEMU_E500] Reviewed-by: York Sun <york.sun@nxp.com>
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e87c673c |
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16-Nov-2016 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8/fsl-lsch3: Update code to release secondary cores NXP ARMv8 SoC LS2080A release all secondary cores in one-go. But other new SoCs like LS2088A, LS1088A release secondary cores one by one. Update code to release secondary cores based on SoC SVR Add code to release cores one by one for non LS2080A SoCs Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> [YS: remove "inline" from declaration of initiator_type] Reviewed-by: York Sun <york.sun@nxp.com>
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f6b96ff6 |
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16-Nov-2016 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Use SVR based timer base address detection Timer controller base address has been changed from LS2080A SoC (and its personalities) to new SoCs like LS2088A, LS1088A. Use SVR based timer base address detection to avoid compile time #ifdef. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
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f6a70b3a |
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16-Nov-2016 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add generic get_svr() in assembly Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
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78d57842 |
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16-Nov-2016 |
Alexander Graf <agraf@suse.de> |
armv8: fsl-layerscape: Add support for efi_loader RTS reset When implementing efi loader support, we can expose runtime services for payloads. One such service is CPU reset. This patch implements RTS CPU reset support for layerscape systems. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: York Sun <york.sun@nxp.com>
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ef9a5fd8 |
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13-Sep-2016 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: Fix "cpu status" command The core position is not continuous for some SoCs. For example, valid cores may present at position 0, 1, 4, 5, 8, 9, etc. Some registers (including boot release register) only count existing cores. Current implementation of cpu_mask() complies with the continuous numbering. However, command "cpu status" queries the spin table with actual core position. Add functions to calculate core position from core number, to correctly calculate offsets. Tested on LS2080ARDB and LS1043ARDB. Signed-off-by: York Sun <york.sun@nxp.com>
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5d1a7a9d |
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13-Sep-2016 |
Wenbin Song <wenbin.song@nxp.com> |
armv8/fsl-layerscape: print SoC revsion number The exact SoC revsion number can be recognized from U-Boot log. Signed-off-by: Wenbin Song <wenbin.song@nxp.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
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1221ce45 |
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20-Sep-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
treewide: replace #include <asm/errno.h> with <linux/errno.h> Now, arch/${ARCH}/include/asm/errno.h and include/linux/errno.h have the same content. (both just wrap <asm-generic/errno.h>) Replace all include directives for <asm/errno.h> with <linux/errno.h>. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> [trini: Fixup include/clk.] Signed-off-by: Tom Rini <trini@konsulko.com>
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b63a9506 |
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03-Aug-2016 |
York Sun <york.sun@nxp.com> |
armv8: ls2080a: Remove debug server support Debug server feature has been dropped from roadmap. Signed-off-by: York Sun <york.sun@nxp.com>
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#
ed7a3943 |
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22-Jul-2016 |
York Sun <york.sun@nxp.com> |
armv8: fsl-layerscape: mmu: Fix enabling MMU MMU bit in SCTLR needs to be set explicitly after tables are created. It isn't an issue for EL3 becuase this bit is already set by early MMU setup. But for other exception levels this bit was not set. Signed-off-by: York Sun <york.sun@nxp.com>
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79119a4d |
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05-Jul-2016 |
Alison Wang <b18965@freescale.com> |
armv8: fsl-layerscape: Add A72 core detection Add support to detect Cortex-A72 core for printing it out. The Initiator Version of A72 core should be 0x4. Signed-off-by: Alison Wang <alison.wang@nxp.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
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#
032d5bb4 |
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28-Jun-2016 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
ARMv8/Layerscape: switch SMP method accordingly If the PSCI and PPA is ready, skip the fixup for spin-table and waking secondary cores. Otherwise, change SMP method to spin-table, and the device node of PSCI will be removed. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
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#
85cdf38e |
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28-Jun-2016 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: fsl-layerscape: add i/d-cache enable function to enable_caches This function assume that the d-cache and MMU has been enabled earlier, so it just created MMU table in main memory. But the assumption is not always correct, for example, the early setup is done in EL3, while enable_caches() is called when the PE has turned into another EL. Define the function mmu_setup() for fsl-layerscape to cover the weak one. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
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#
5ad5823d |
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24-Jun-2016 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Convert to use common MMU framework Drop platform code to create static MMU tables. Use common framework to create MMU tables on the run. Tested on LS2080ARDB with secure and non-secure ram scenarios. Signed-off-by: York Sun <york.sun@nxp.com>
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#
e61a7534 |
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24-Jun-2016 |
York Sun <york.sun@nxp.com> |
armv8: Move secure_ram variable out of generic global data Secure_ram variable was put in generic global data. But only ARMv8 uses this variable. Move it to ARM specific data structure. Signed-off-by: York Sun <york.sun@nxp.com>
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#
6fb522dc |
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12-Jun-2016 |
Sriram Dash <sriram.dash@nxp.com> |
arm64: fsl-layerscape: add get_svr and IS_SVR_REV helper Adds get_svr and IS_SVR_REV helpers for ARMv8 platforms, similar to PPC and ARMv7. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
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#
a758177f |
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07-Jun-2016 |
Yunhui Cui <yunhui.cui@nxp.com> |
armv8/ls2080a: configure PMU's PCTBENR to enable WDT The SP805-WDT module on LS2080A requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. The watchdog clock needs to be enabled first. Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
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#
acb8f5e9 |
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21-Apr-2016 |
Alison Wang <b18965@freescale.com> |
armv8: fsl-layerscape: Remove unnecessary flushing dcache As the issue about the stack will get corrupted when switching between the early and final mmu tables is fixed by commit 70e21b064, the workaround to flush dcache is unnecessary and should be removed. Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
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3c1d218a |
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04-Apr-2016 |
York Sun <york.sun@nxp.com> |
armv8: LS2080A: Consolidate LS2080A and LS2085A LS2080A is the primary SoC, and LS2085A is a personality with AIOP and DPAA DDR. The RDB and QDS boards support both personality. By detecting the SVR at runtime, a single image per board can support both SoCs. It gives users flexibility to swtich SoC without the need to reprogram the board. Signed-off-by: York Sun <york.sun@nxp.com> CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
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c05016ab |
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21-Mar-2016 |
Alexander Graf <agraf@suse.de> |
arm64: Fix layerscape mmu setup With commit 7985cdf we converted all systems except for the Layerscape SoCs to the generic descriptor table based page table setup. On the Layerscape SoCs however, we just provide an empty table stub and do the setup ourselves. To reserve enough memory for the tables, we need to override the default counting mechanism which would end up with an empty table because we have no maps. Fixes: 7985cdf Reported-by: York Sun <york.sun@nxp.com> CC: Alison Wang <alison.wang@nxp.com> CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Alexander Graf <agraf@suse.de> Tested-by: York Sun <york.sun@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
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7985cdf7 |
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03-Mar-2016 |
Alexander Graf <agraf@suse.de> |
arm64: Remove non-full-va map code By now the code to only have a single page table level with 64k page size and 42 bit address space is no longer used by any board in tree, so we can safely remove it. To clean up code, move the layerscape mmu code to the new defines, removing redundant field definitions. Signed-off-by: Alexander Graf <agraf@suse.de>
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c0492141 |
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07-Dec-2015 |
York Sun <yorksun@freescale.com> |
armv8: fsl-layerscale: Rewrite reserving memory for MC and debug server MC and debug server are not board-specific. Move reserving memory to SoC file, using the new board_reserve_ram_top function. Reduce debug server memory by 2MB to make room for secure memory. In the system with MC and debug server, the top of u-boot memory is not the end of memory. PRAM is not used for this reservation. Signed-off-by: York Sun <yorksun@freescale.com>
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c107c0c0 |
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04-Dec-2015 |
York Sun <yorksun@freescale.com> |
armv8: fsl-layerscape: Make DDR non secure in MMU tables DDR has been set as secure in MMU tables. Non-secure master such as SDHC DMA cannot access data correctly. Mixing secure and non- secure MMU entries requirs the MMU tables themselves in secure memory. This patch moves MMU tables into a secure DDR area. Early MMU tables are changed to set DDR as non-secure. A new table is added into final MMU tables so secure memory can have 2MB granuality. gd->secure_ram tracks the location of this secure memory. For ARMv8 SoCs, the RAM base is not zero and RAM is divided into several banks. gd->secure_ram needs to be maintained before using. This maintenance is board-specific, depending on the SoC and memory bank of the secure memory falls into. Signed-off-by: York Sun <yorksun@freescale.com>
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b4017364 |
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04-Nov-2015 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
armv8: ls2085a: Add workaround of errata A009635 If the core runs at higher than x3 speed of the platform, there is possiblity about sev instruction to getting missed by other cores. This is because of SoC Run Control block may not able to sample the EVENTI(Sev) signals. Configure Run Control and EPU to periodically send out EVENTI signals to wake up A57 cores. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
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d764129d |
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04-Nov-2015 |
Alison Wang <b18965@freescale.com> |
armv8/layerscape: Update MMU table with execute-never bits For most device addresses excution shouldn't be allowed. Revise the MMU table to enforce execute-never bits. OCRAM, DDR and IFC are allowed for excution. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Alison Wang <alison.wang@freescale.com> Reported-by: Zhichun Hua <zhichun.hua@freescale.com>
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44937214 |
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09-Nov-2015 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
armv8: LS2080A: Rename LS2085A to reflect LS2080A LS2080A is a prime personality of Freescale’s LS2085A. It is a non-AIOP personality without support of DP-DDR, L2 switch, 1588, PCIe endpoint etc. So renaming existing LS2085A code base to reflect LS2080A (Prime personality) Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> [York Sun: Dropped #ifdef in cpu.c for cpu_type_list] Reviewed-by: York Sun <yorksun@freescale.com>
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e8297341 |
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26-Oct-2015 |
Shaohui Xie <Shaohui.Xie@freescale.com> |
armv8/ls1043a: Add Fman support Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
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8281c58f |
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26-Oct-2015 |
Mingkai Hu <Mingkai.Hu@freescale.com> |
armv8/fsl_lsch2: Add fsl_lsch2 SoC Freescale LayerScape with Chassis Generation 2 is a set of SoCs with ARMv8 cores and 2rd generation of Chassis. Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
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9f3183d2 |
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26-Oct-2015 |
Mingkai Hu <Mingkai.Hu@freescale.com> |
armv8/fsl_lsch3: Change arch to fsl-layerscape There are two LS series processors are built on ARMv8 Layersacpe architecture currently, LS2085A and LS1043A. They are based on ARMv8 core although use different chassis, so create fsl-layerscape to refactor the common code for the LS series processors which also paves the way for adding LS1043A platform. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
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