| /linux-master/arch/powerpc/platforms/powernv/ |
| H A D | subcore-asm.S | 25 ori r4,r4,MSR_EE|MSR_SE|MSR_BE|MSR_RI
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| /linux-master/arch/powerpc/include/asm/ |
| H A D | hw_irq.h | 71 __mtmsrd(MSR_EE | MSR_RI, 1);
83 __mtmsrd(MSR_RI, 1);
97 mtmsr(mfmsr() & ~(MSR_EE | MSR_RI)); local
108 __mtmsrd(MSR_RI, 1);
110 mtmsr(mfmsr() | MSR_RI);
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| H A D | ptrace.h | 318 return unlikely(cpu_has_msr_ri() && !(regs->msr & MSR_RI));
324 regs_set_return_msr(regs, regs->msr | MSR_RI);
330 regs_set_return_msr(regs, regs->msr & ~MSR_RI);
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| H A D | reg.h | 112 #define MSR_RI __MASK(MSR_RI_LG) /* Recoverable Exception */ macro
134 #define __MSR (MSR_ME | MSR_RI | MSR_IR | MSR_DR | MSR_HV)
147 #define MSR_KERNEL (MSR_ME|MSR_RI|MSR_IR|MSR_DR)
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| H A D | reg_booke.h | 41 #define MSR_ (MSR_ME | MSR_RI | MSR_CE)
46 #define MSR_KERNEL (MSR_ME|MSR_RI|MSR_IR|MSR_DR|MSR_CE)
49 #define MSR_KERNEL (MSR_ME|MSR_RI|MSR_CE)
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| /linux-master/arch/powerpc/kernel/ |
| H A D | entry_32.S | 218 andi. r10,r9,MSR_RI /* check for recoverable interrupt */
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| H A D | exceptions-64s.S | 399 xori r10,r10,MSR_RI
402 xori r10,r10,MSR_RI
887 * - MSR_EE|MSR_RI is clear (no reentrant exceptions)
1064 * enable MSR_RI, then SLB or MCE will be able to recover, but a nested
1080 /* Clear MSR_RI before setting SRR0 and SRR1. */
1085 * MSR_RI is clear, now we can decrement paca->in_nmi.
1172 /* Clear MSR_RI before setting SRR0 and SRR1. */\
1174 mtmsrd r9,1; /* Clear MSR_RI */ \
1273 andi. r11,r12,MSR_RI
1362 li r10,0 /* clear MSR_RI */
[all...] |
| H A D | fpu.S | 98 ori r5,r5,MSR_FP|MSR_RI
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| H A D | head_32.h | 66 LOAD_REG_IMMEDIATE(r11, MSR_KERNEL & ~MSR_RI) /* re-enable MMU */
102 mtspr SPRN_EID, r2 /* Set MSR_RI */
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| H A D | head_64.S | 155 ori r24,r24,MSR_RI
794 ori r3,r3,MSR_RI
982 ori r6,r6,MSR_RI
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| H A D | head_8xx.S | 697 li r12, MSR_KERNEL & ~(MSR_IR | MSR_DR | MSR_RI)
698 rlwinm r0, r10, 0, ~MSR_RI
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| H A D | head_book3s_32.S | 202 ori r0,r0,MSR_DR|MSR_IR|MSR_RI
1092 rlwinm r0, r6, 0, ~MSR_RI
1114 li r3, MSR_KERNEL & ~(MSR_IR | MSR_DR | MSR_RI)
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| H A D | interrupt_64.S | 278 li r12,-1 /* Set MSR_EE and MSR_RI */
400 andi. r0,r5,MSR_RI
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| H A D | kvm_emul.S | 57 /* Put MSR & ~(MSR_EE|MSR_RI) in r31 */
59 lis r30, (~(MSR_EE | MSR_RI))@h
60 ori r30, r30, (~(MSR_EE | MSR_RI))@l
63 /* OR the register's (MSR_EE|MSR_RI) on MSR */
66 andi. r30, r30, (MSR_EE|MSR_RI)
115 #define MSR_SAFE_BITS (MSR_EE | MSR_RI)
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| H A D | mce.c | 117 if (handled && (regs->msr & MSR_RI))
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| H A D | misc_64.S | 362 1: li r9,MSR_RI
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| H A D | process.c | 1492 {MSR_RI, "RI"},
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| H A D | rtas.c | 725 BUG_ON(!(msr & MSR_RI));
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| H A D | rtas_entry.S | 116 LOAD_REG_IMMEDIATE(r6, MSR_ME | MSR_RI)
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| H A D | tm.S | 164 * At this point we can't take an SLB miss since we have MSR_RI
192 * clobbered by an exception once we turn on MSR_RI below.
205 li r11, MSR_RI
506 * At this point we can't take an SLB miss since we have MSR_RI
532 li r4, MSR_RI
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| H A D | traps.c | 403 if (!(regs->msr & MSR_RI))
437 regs->msr &= ~MSR_RI;
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| H A D | vector.S | 54 ori r5,r5,MSR_RI
138 li r5,MSR_RI
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| /linux-master/arch/powerpc/kexec/ |
| H A D | relocate_32.S | 412 ori r8, r8, MSR_RI|MSR_ME
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| /linux-master/arch/powerpc/kvm/ |
| H A D | book3s_64_entry.S | 401 * MSR_RI in r12 ([H]SRR1) so the handler won't try to return.
405 li r10,MSR_RI
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| H A D | book3s_emulate.c | 302 new_msr &= ~(MSR_RI | MSR_EE);
303 new_msr |= rs_val & (MSR_RI | MSR_EE);
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