1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Contains the definition of registers common to all PowerPC variants. 4 * If a register definition has been changed in a different PowerPC 5 * variant, we will case it in #ifndef XXX ... #endif, and have the 6 * number used in the Programming Environments Manual For 32-Bit 7 * Implementations of the PowerPC Architecture (a.k.a. Green Book) here. 8 */ 9 10#ifndef _ASM_POWERPC_REG_H 11#define _ASM_POWERPC_REG_H 12#ifdef __KERNEL__ 13 14#include <linux/stringify.h> 15#include <linux/const.h> 16#include <asm/cputable.h> 17#include <asm/asm-const.h> 18#include <asm/feature-fixups.h> 19 20/* Pickup Book E specific registers. */ 21#ifdef CONFIG_BOOKE_OR_40x 22#include <asm/reg_booke.h> 23#endif 24 25#ifdef CONFIG_FSL_EMB_PERFMON 26#include <asm/reg_fsl_emb.h> 27#endif 28 29#include <asm/reg_8xx.h> 30 31#define MSR_SF_LG 63 /* Enable 64 bit mode */ 32#define MSR_HV_LG 60 /* Hypervisor state */ 33#define MSR_TS_T_LG 34 /* Trans Mem state: Transactional */ 34#define MSR_TS_S_LG 33 /* Trans Mem state: Suspended */ 35#define MSR_TS_LG 33 /* Trans Mem state (2 bits) */ 36#define MSR_TM_LG 32 /* Trans Mem Available */ 37#define MSR_VEC_LG 25 /* Enable AltiVec */ 38#define MSR_VSX_LG 23 /* Enable VSX */ 39#define MSR_S_LG 22 /* Secure state */ 40#define MSR_POW_LG 18 /* Enable Power Management */ 41#define MSR_WE_LG 18 /* Wait State Enable */ 42#define MSR_TGPR_LG 17 /* TLB Update registers in use */ 43#define MSR_CE_LG 17 /* Critical Interrupt Enable */ 44#define MSR_ILE_LG 16 /* Interrupt Little Endian */ 45#define MSR_EE_LG 15 /* External Interrupt Enable */ 46#define MSR_PR_LG 14 /* Problem State / Privilege Level */ 47#define MSR_FP_LG 13 /* Floating Point enable */ 48#define MSR_ME_LG 12 /* Machine Check Enable */ 49#define MSR_FE0_LG 11 /* Floating Exception mode 0 */ 50#define MSR_SE_LG 10 /* Single Step */ 51#define MSR_BE_LG 9 /* Branch Trace */ 52#define MSR_DE_LG 9 /* Debug Exception Enable */ 53#define MSR_FE1_LG 8 /* Floating Exception mode 1 */ 54#define MSR_IP_LG 6 /* Exception prefix 0x000/0xFFF */ 55#define MSR_IR_LG 5 /* Instruction Relocate */ 56#define MSR_DR_LG 4 /* Data Relocate */ 57#define MSR_PE_LG 3 /* Protection Enable */ 58#define MSR_PX_LG 2 /* Protection Exclusive Mode */ 59#define MSR_PMM_LG 2 /* Performance monitor */ 60#define MSR_RI_LG 1 /* Recoverable Exception */ 61#define MSR_LE_LG 0 /* Little Endian */ 62 63#ifdef __ASSEMBLY__ 64#define __MASK(X) (1<<(X)) 65#else 66#define __MASK(X) (1UL<<(X)) 67#endif 68 69#ifdef CONFIG_PPC64 70#define MSR_SF __MASK(MSR_SF_LG) /* Enable 64 bit mode */ 71#define MSR_HV __MASK(MSR_HV_LG) /* Hypervisor state */ 72#define MSR_S __MASK(MSR_S_LG) /* Secure state */ 73#else 74/* so tests for these bits fail on 32-bit */ 75#define MSR_SF 0 76#define MSR_HV 0 77#define MSR_S 0 78#endif 79 80/* 81 * To be used in shared book E/book S, this avoids needing to worry about 82 * book S/book E in shared code 83 */ 84#ifndef MSR_SPE 85#define MSR_SPE 0 86#endif 87 88#define MSR_VEC __MASK(MSR_VEC_LG) /* Enable AltiVec */ 89#define MSR_VSX __MASK(MSR_VSX_LG) /* Enable VSX */ 90#define MSR_POW __MASK(MSR_POW_LG) /* Enable Power Management */ 91#define MSR_WE __MASK(MSR_WE_LG) /* Wait State Enable */ 92#define MSR_TGPR __MASK(MSR_TGPR_LG) /* TLB Update registers in use */ 93#define MSR_CE __MASK(MSR_CE_LG) /* Critical Interrupt Enable */ 94#define MSR_ILE __MASK(MSR_ILE_LG) /* Interrupt Little Endian */ 95#define MSR_EE __MASK(MSR_EE_LG) /* External Interrupt Enable */ 96#define MSR_PR __MASK(MSR_PR_LG) /* Problem State / Privilege Level */ 97#define MSR_FP __MASK(MSR_FP_LG) /* Floating Point enable */ 98#define MSR_ME __MASK(MSR_ME_LG) /* Machine Check Enable */ 99#define MSR_FE0 __MASK(MSR_FE0_LG) /* Floating Exception mode 0 */ 100#define MSR_SE __MASK(MSR_SE_LG) /* Single Step */ 101#define MSR_BE __MASK(MSR_BE_LG) /* Branch Trace */ 102#define MSR_DE __MASK(MSR_DE_LG) /* Debug Exception Enable */ 103#define MSR_FE1 __MASK(MSR_FE1_LG) /* Floating Exception mode 1 */ 104#define MSR_IP __MASK(MSR_IP_LG) /* Exception prefix 0x000/0xFFF */ 105#define MSR_IR __MASK(MSR_IR_LG) /* Instruction Relocate */ 106#define MSR_DR __MASK(MSR_DR_LG) /* Data Relocate */ 107#define MSR_PE __MASK(MSR_PE_LG) /* Protection Enable */ 108#define MSR_PX __MASK(MSR_PX_LG) /* Protection Exclusive Mode */ 109#ifndef MSR_PMM 110#define MSR_PMM __MASK(MSR_PMM_LG) /* Performance monitor */ 111#endif 112#define MSR_RI __MASK(MSR_RI_LG) /* Recoverable Exception */ 113#define MSR_LE __MASK(MSR_LE_LG) /* Little Endian */ 114 115#define MSR_TM __MASK(MSR_TM_LG) /* Transactional Mem Available */ 116#define MSR_TS_N 0 /* Non-transactional */ 117#define MSR_TS_S __MASK(MSR_TS_S_LG) /* Transaction Suspended */ 118#define MSR_TS_T __MASK(MSR_TS_T_LG) /* Transaction Transactional */ 119#define MSR_TS_MASK (MSR_TS_T | MSR_TS_S) /* Transaction State bits */ 120#define MSR_TM_RESV(x) (((x) & MSR_TS_MASK) == MSR_TS_MASK) /* Reserved */ 121#define MSR_TM_TRANSACTIONAL(x) (((x) & MSR_TS_MASK) == MSR_TS_T) 122#define MSR_TM_SUSPENDED(x) (((x) & MSR_TS_MASK) == MSR_TS_S) 123 124#ifdef CONFIG_PPC_TRANSACTIONAL_MEM 125#define MSR_TM_ACTIVE(x) (((x) & MSR_TS_MASK) != 0) /* Transaction active? */ 126#else 127#define MSR_TM_ACTIVE(x) ((void)(x), 0) 128#endif 129 130#if defined(CONFIG_PPC_BOOK3S_64) 131#define MSR_64BIT MSR_SF 132 133/* Server variant */ 134#define __MSR (MSR_ME | MSR_RI | MSR_IR | MSR_DR | MSR_HV) 135#ifdef __BIG_ENDIAN__ 136#define MSR_ __MSR 137#define MSR_IDLE (MSR_ME | MSR_SF | MSR_HV) 138#else 139#define MSR_ (__MSR | MSR_LE) 140#define MSR_IDLE (MSR_ME | MSR_SF | MSR_HV | MSR_LE) 141#endif 142#define MSR_KERNEL (MSR_ | MSR_64BIT) 143#define MSR_USER32 (MSR_ | MSR_PR | MSR_EE) 144#define MSR_USER64 (MSR_USER32 | MSR_64BIT) 145#elif defined(CONFIG_PPC_BOOK3S_32) || defined(CONFIG_PPC_8xx) 146/* Default MSR for kernel mode. */ 147#define MSR_KERNEL (MSR_ME|MSR_RI|MSR_IR|MSR_DR) 148#define MSR_USER (MSR_KERNEL|MSR_PR|MSR_EE) 149#endif 150 151#ifndef MSR_64BIT 152#define MSR_64BIT 0 153#endif 154 155/* Condition Register related */ 156#define CR0_SHIFT 28 157#define CR0_MASK 0xF 158#define CR0_TBEGIN_FAILURE (0x2 << 28) /* 0b0010 */ 159 160 161/* Power Management - Processor Stop Status and Control Register Fields */ 162#define PSSCR_RL_MASK 0x0000000F /* Requested Level */ 163#define PSSCR_MTL_MASK 0x000000F0 /* Maximum Transition Level */ 164#define PSSCR_TR_MASK 0x00000300 /* Transition State */ 165#define PSSCR_PSLL_MASK 0x000F0000 /* Power-Saving Level Limit */ 166#define PSSCR_EC 0x00100000 /* Exit Criterion */ 167#define PSSCR_ESL 0x00200000 /* Enable State Loss */ 168#define PSSCR_SD 0x00400000 /* Status Disable */ 169#define PSSCR_PLS 0xf000000000000000 /* Power-saving Level Status */ 170#define PSSCR_PLS_SHIFT 60 171#define PSSCR_GUEST_VIS 0xf0000000000003ffUL /* Guest-visible PSSCR fields */ 172#define PSSCR_FAKE_SUSPEND 0x00000400 /* Fake-suspend bit (P9 DD2.2) */ 173#define PSSCR_FAKE_SUSPEND_LG 10 /* Fake-suspend bit position */ 174 175/* Floating Point Status and Control Register (FPSCR) Fields */ 176#define FPSCR_FX 0x80000000 /* FPU exception summary */ 177#define FPSCR_FEX 0x40000000 /* FPU enabled exception summary */ 178#define FPSCR_VX 0x20000000 /* Invalid operation summary */ 179#define FPSCR_OX 0x10000000 /* Overflow exception summary */ 180#define FPSCR_UX 0x08000000 /* Underflow exception summary */ 181#define FPSCR_ZX 0x04000000 /* Zero-divide exception summary */ 182#define FPSCR_XX 0x02000000 /* Inexact exception summary */ 183#define FPSCR_VXSNAN 0x01000000 /* Invalid op for SNaN */ 184#define FPSCR_VXISI 0x00800000 /* Invalid op for Inv - Inv */ 185#define FPSCR_VXIDI 0x00400000 /* Invalid op for Inv / Inv */ 186#define FPSCR_VXZDZ 0x00200000 /* Invalid op for Zero / Zero */ 187#define FPSCR_VXIMZ 0x00100000 /* Invalid op for Inv * Zero */ 188#define FPSCR_VXVC 0x00080000 /* Invalid op for Compare */ 189#define FPSCR_FR 0x00040000 /* Fraction rounded */ 190#define FPSCR_FI 0x00020000 /* Fraction inexact */ 191#define FPSCR_FPRF 0x0001f000 /* FPU Result Flags */ 192#define FPSCR_FPCC 0x0000f000 /* FPU Condition Codes */ 193#define FPSCR_VXSOFT 0x00000400 /* Invalid op for software request */ 194#define FPSCR_VXSQRT 0x00000200 /* Invalid op for square root */ 195#define FPSCR_VXCVI 0x00000100 /* Invalid op for integer convert */ 196#define FPSCR_VE 0x00000080 /* Invalid op exception enable */ 197#define FPSCR_OE 0x00000040 /* IEEE overflow exception enable */ 198#define FPSCR_UE 0x00000020 /* IEEE underflow exception enable */ 199#define FPSCR_ZE 0x00000010 /* IEEE zero divide exception enable */ 200#define FPSCR_XE 0x00000008 /* FP inexact exception enable */ 201#define FPSCR_NI 0x00000004 /* FPU non IEEE-Mode */ 202#define FPSCR_RN 0x00000003 /* FPU rounding control */ 203 204/* Bit definitions for SPEFSCR. */ 205#define SPEFSCR_SOVH 0x80000000 /* Summary integer overflow high */ 206#define SPEFSCR_OVH 0x40000000 /* Integer overflow high */ 207#define SPEFSCR_FGH 0x20000000 /* Embedded FP guard bit high */ 208#define SPEFSCR_FXH 0x10000000 /* Embedded FP sticky bit high */ 209#define SPEFSCR_FINVH 0x08000000 /* Embedded FP invalid operation high */ 210#define SPEFSCR_FDBZH 0x04000000 /* Embedded FP div by zero high */ 211#define SPEFSCR_FUNFH 0x02000000 /* Embedded FP underflow high */ 212#define SPEFSCR_FOVFH 0x01000000 /* Embedded FP overflow high */ 213#define SPEFSCR_FINXS 0x00200000 /* Embedded FP inexact sticky */ 214#define SPEFSCR_FINVS 0x00100000 /* Embedded FP invalid op. sticky */ 215#define SPEFSCR_FDBZS 0x00080000 /* Embedded FP div by zero sticky */ 216#define SPEFSCR_FUNFS 0x00040000 /* Embedded FP underflow sticky */ 217#define SPEFSCR_FOVFS 0x00020000 /* Embedded FP overflow sticky */ 218#define SPEFSCR_MODE 0x00010000 /* Embedded FP mode */ 219#define SPEFSCR_SOV 0x00008000 /* Integer summary overflow */ 220#define SPEFSCR_OV 0x00004000 /* Integer overflow */ 221#define SPEFSCR_FG 0x00002000 /* Embedded FP guard bit */ 222#define SPEFSCR_FX 0x00001000 /* Embedded FP sticky bit */ 223#define SPEFSCR_FINV 0x00000800 /* Embedded FP invalid operation */ 224#define SPEFSCR_FDBZ 0x00000400 /* Embedded FP div by zero */ 225#define SPEFSCR_FUNF 0x00000200 /* Embedded FP underflow */ 226#define SPEFSCR_FOVF 0x00000100 /* Embedded FP overflow */ 227#define SPEFSCR_FINXE 0x00000040 /* Embedded FP inexact enable */ 228#define SPEFSCR_FINVE 0x00000020 /* Embedded FP invalid op. enable */ 229#define SPEFSCR_FDBZE 0x00000010 /* Embedded FP div by zero enable */ 230#define SPEFSCR_FUNFE 0x00000008 /* Embedded FP underflow enable */ 231#define SPEFSCR_FOVFE 0x00000004 /* Embedded FP overflow enable */ 232#define SPEFSCR_FRMC 0x00000003 /* Embedded FP rounding mode control */ 233 234/* Special Purpose Registers (SPRNs)*/ 235 236#ifdef CONFIG_40x 237#define SPRN_PID 0x3B1 /* Process ID */ 238#else 239#define SPRN_PID 0x030 /* Process ID */ 240#ifdef CONFIG_BOOKE 241#define SPRN_PID0 SPRN_PID/* Process ID Register 0 */ 242#endif 243#endif 244 245#define SPRN_CTR 0x009 /* Count Register */ 246#define SPRN_DSCR 0x11 247#define SPRN_CFAR 0x1c /* Come From Address Register */ 248#define SPRN_AMR 0x1d /* Authority Mask Register */ 249#define SPRN_UAMOR 0x9d /* User Authority Mask Override Register */ 250#define SPRN_AMOR 0x15d /* Authority Mask Override Register */ 251#define SPRN_ACOP 0x1F /* Available Coprocessor Register */ 252#define SPRN_TFIAR 0x81 /* Transaction Failure Inst Addr */ 253#define SPRN_TEXASR 0x82 /* Transaction EXception & Summary */ 254#define SPRN_TEXASRU 0x83 /* '' '' '' Upper 32 */ 255 256#define TEXASR_FC_LG (63 - 7) /* Failure Code */ 257#define TEXASR_AB_LG (63 - 31) /* Abort */ 258#define TEXASR_SU_LG (63 - 32) /* Suspend */ 259#define TEXASR_HV_LG (63 - 34) /* Hypervisor state*/ 260#define TEXASR_PR_LG (63 - 35) /* Privilege level */ 261#define TEXASR_FS_LG (63 - 36) /* failure summary */ 262#define TEXASR_EX_LG (63 - 37) /* TFIAR exact bit */ 263#define TEXASR_ROT_LG (63 - 38) /* ROT bit */ 264 265#define TEXASR_ABORT __MASK(TEXASR_AB_LG) /* terminated by tabort or treclaim */ 266#define TEXASR_SUSP __MASK(TEXASR_SU_LG) /* tx failed in suspended state */ 267#define TEXASR_HV __MASK(TEXASR_HV_LG) /* MSR[HV] when failure occurred */ 268#define TEXASR_PR __MASK(TEXASR_PR_LG) /* MSR[PR] when failure occurred */ 269#define TEXASR_FS __MASK(TEXASR_FS_LG) /* TEXASR Failure Summary */ 270#define TEXASR_EXACT __MASK(TEXASR_EX_LG) /* TFIAR value is exact */ 271#define TEXASR_ROT __MASK(TEXASR_ROT_LG) 272#define TEXASR_FC (ASM_CONST(0xFF) << TEXASR_FC_LG) 273 274#define SPRN_TFHAR 0x80 /* Transaction Failure Handler Addr */ 275 276#define SPRN_TIDR 144 /* Thread ID register */ 277#define SPRN_CTRLF 0x088 278#define SPRN_CTRLT 0x098 279#define CTRL_CT 0xc0000000 /* current thread */ 280#define CTRL_CT0 0x80000000 /* thread 0 */ 281#define CTRL_CT1 0x40000000 /* thread 1 */ 282#define CTRL_TE 0x00c00000 /* thread enable */ 283#define CTRL_RUNLATCH 0x1 284#define SPRN_DAWR0 0xB4 285#define SPRN_DAWR1 0xB5 286#define SPRN_RPR 0xBA /* Relative Priority Register */ 287#define SPRN_CIABR 0xBB 288#define CIABR_PRIV 0x3 289#define CIABR_PRIV_USER 1 290#define CIABR_PRIV_SUPER 2 291#define CIABR_PRIV_HYPER 3 292#define SPRN_DAWRX0 0xBC 293#define SPRN_DAWRX1 0xBD 294#define DAWRX_USER __MASK(0) 295#define DAWRX_KERNEL __MASK(1) 296#define DAWRX_HYP __MASK(2) 297#define DAWRX_WTI __MASK(3) 298#define DAWRX_WT __MASK(4) 299#define DAWRX_DR __MASK(5) 300#define DAWRX_DW __MASK(6) 301#define SPRN_DABR 0x3F5 /* Data Address Breakpoint Register */ 302#define SPRN_DABR2 0x13D /* e300 */ 303#define SPRN_DABRX 0x3F7 /* Data Address Breakpoint Register Extension */ 304#define DABRX_USER __MASK(0) 305#define DABRX_KERNEL __MASK(1) 306#define DABRX_HYP __MASK(2) 307#define DABRX_BTI __MASK(3) 308#define DABRX_ALL (DABRX_BTI | DABRX_HYP | DABRX_KERNEL | DABRX_USER) 309#define SPRN_DAR 0x013 /* Data Address Register */ 310#define SPRN_DBCR 0x136 /* e300 Data Breakpoint Control Reg */ 311#define SPRN_DSISR 0x012 /* Data Storage Interrupt Status Register */ 312#define DSISR_BAD_DIRECT_ST 0x80000000 /* Obsolete: Direct store error */ 313#define DSISR_NOHPTE 0x40000000 /* no translation found */ 314#define DSISR_ATTR_CONFLICT 0x20000000 /* P9: Process vs. Partition attr */ 315#define DSISR_NOEXEC_OR_G 0x10000000 /* Alias of SRR1 bit, see below */ 316#define DSISR_PROTFAULT 0x08000000 /* protection fault */ 317#define DSISR_BADACCESS 0x04000000 /* bad access to CI or G */ 318#define DSISR_ISSTORE 0x02000000 /* access was a store */ 319#define DSISR_DABRMATCH 0x00400000 /* hit data breakpoint */ 320#define DSISR_NOSEGMENT 0x00200000 /* STAB miss (unsupported) */ 321#define DSISR_KEYFAULT 0x00200000 /* Storage Key fault */ 322#define DSISR_BAD_EXT_CTRL 0x00100000 /* Obsolete: External ctrl error */ 323#define DSISR_UNSUPP_MMU 0x00080000 /* P9: Unsupported MMU config */ 324#define DSISR_SET_RC 0x00040000 /* P9: Failed setting of R/C bits */ 325#define DSISR_PRTABLE_FAULT 0x00020000 /* P9: Fault on process table */ 326#define DSISR_ICSWX_NO_CT 0x00004000 /* P7: icswx unavailable cp type */ 327#define DSISR_BAD_COPYPASTE 0x00000008 /* P9: Copy/Paste on wrong memtype */ 328#define DSISR_BAD_AMO 0x00000004 /* P9: Incorrect AMO opcode */ 329#define DSISR_BAD_CI_LDST 0x00000002 /* P8: Bad HV CI load/store */ 330 331/* 332 * DSISR_NOEXEC_OR_G doesn't actually exist. This bit is always 333 * 0 on DSIs. However, on ISIs, the corresponding bit in SRR1 334 * indicates an attempt at executing from a no-execute PTE 335 * or segment or from a guarded page. 336 * 337 * We add a definition here for completeness as we alias 338 * DSISR and SRR1 in do_page_fault. 339 */ 340 341/* 342 * DSISR bits that are treated as a fault. Any bit set 343 * here will skip hash_page, and cause do_page_fault to 344 * trigger a SIGBUS or SIGSEGV: 345 */ 346#define DSISR_BAD_FAULT_32S (DSISR_BAD_DIRECT_ST | \ 347 DSISR_BADACCESS | \ 348 DSISR_BAD_EXT_CTRL) 349#define DSISR_BAD_FAULT_64S (DSISR_BAD_FAULT_32S | \ 350 DSISR_ATTR_CONFLICT | \ 351 DSISR_UNSUPP_MMU | \ 352 DSISR_PRTABLE_FAULT | \ 353 DSISR_ICSWX_NO_CT | \ 354 DSISR_BAD_COPYPASTE | \ 355 DSISR_BAD_AMO | \ 356 DSISR_BAD_CI_LDST) 357/* 358 * These bits are equivalent in SRR1 and DSISR for 0x400 359 * instruction access interrupts on Book3S 360 */ 361#define DSISR_SRR1_MATCH_32S (DSISR_NOHPTE | \ 362 DSISR_NOEXEC_OR_G | \ 363 DSISR_PROTFAULT) 364#define DSISR_SRR1_MATCH_64S (DSISR_SRR1_MATCH_32S | \ 365 DSISR_KEYFAULT | \ 366 DSISR_UNSUPP_MMU | \ 367 DSISR_SET_RC | \ 368 DSISR_PRTABLE_FAULT) 369 370#define SPRN_TBRL 0x10C /* Time Base Read Lower Register (user, R/O) */ 371#define SPRN_TBRU 0x10D /* Time Base Read Upper Register (user, R/O) */ 372#define SPRN_CIR 0x11B /* Chip Information Register (hyper, R/0) */ 373#define SPRN_TBWL 0x11C /* Time Base Lower Register (super, R/W) */ 374#define SPRN_TBWU 0x11D /* Time Base Upper Register (super, R/W) */ 375#define SPRN_TBU40 0x11E /* Timebase upper 40 bits (hyper, R/W) */ 376#define SPRN_SPURR 0x134 /* Scaled PURR */ 377#define SPRN_HSPRG0 0x130 /* Hypervisor Scratch 0 */ 378#define SPRN_HSPRG1 0x131 /* Hypervisor Scratch 1 */ 379#define SPRN_HDSISR 0x132 380#define SPRN_HDAR 0x133 381#define SPRN_HDEC 0x136 /* Hypervisor Decrementer */ 382#define SPRN_HIOR 0x137 /* 970 Hypervisor interrupt offset */ 383#define SPRN_RMOR 0x138 /* Real mode offset register */ 384#define SPRN_HRMOR 0x139 /* Real mode offset register */ 385#define SPRN_HDEXCR_RO 0x1C7 /* Hypervisor DEXCR (non-privileged, readonly) */ 386#define SPRN_HASHKEYR 0x1D4 /* Non-privileged hashst/hashchk key register */ 387#define SPRN_HDEXCR 0x1D7 /* Hypervisor dynamic execution control register */ 388#define SPRN_DEXCR_RO 0x32C /* DEXCR (non-privileged, readonly) */ 389#define SPRN_ASDR 0x330 /* Access segment descriptor register */ 390#define SPRN_DEXCR 0x33C /* Dynamic execution control register */ 391#define DEXCR_PR_SBHE 0x80000000UL /* 0: Speculative Branch Hint Enable */ 392#define DEXCR_PR_IBRTPD 0x10000000UL /* 3: Indirect Branch Recurrent Target Prediction Disable */ 393#define DEXCR_PR_SRAPD 0x08000000UL /* 4: Subroutine Return Address Prediction Disable */ 394#define DEXCR_PR_NPHIE 0x04000000UL /* 5: Non-Privileged Hash Instruction Enable */ 395#define DEXCR_INIT DEXCR_PR_NPHIE /* Fixed DEXCR value to initialise all CPUs with */ 396#define SPRN_IC 0x350 /* Virtual Instruction Count */ 397#define SPRN_VTB 0x351 /* Virtual Time Base */ 398#define SPRN_LDBAR 0x352 /* LD Base Address Register */ 399#define SPRN_PMICR 0x354 /* Power Management Idle Control Reg */ 400#define SPRN_PMSR 0x355 /* Power Management Status Reg */ 401#define SPRN_PMMAR 0x356 /* Power Management Memory Activity Register */ 402#define SPRN_PSSCR 0x357 /* Processor Stop Status and Control Register (ISA 3.0) */ 403#define SPRN_PSSCR_PR 0x337 /* PSSCR ISA 3.0, privileged mode access */ 404#define SPRN_TRIG2 0x372 405#define SPRN_PMCR 0x374 /* Power Management Control Register */ 406#define SPRN_RWMR 0x375 /* Region-Weighting Mode Register */ 407 408/* HFSCR and FSCR bit numbers are the same */ 409#define FSCR_PREFIX_LG 13 /* Enable Prefix Instructions */ 410#define FSCR_SCV_LG 12 /* Enable System Call Vectored */ 411#define FSCR_MSGP_LG 10 /* Enable MSGP */ 412#define FSCR_TAR_LG 8 /* Enable Target Address Register */ 413#define FSCR_EBB_LG 7 /* Enable Event Based Branching */ 414#define FSCR_TM_LG 5 /* Enable Transactional Memory */ 415#define FSCR_BHRB_LG 4 /* Enable Branch History Rolling Buffer*/ 416#define FSCR_PM_LG 3 /* Enable prob/priv access to PMU SPRs */ 417#define FSCR_DSCR_LG 2 /* Enable Data Stream Control Register */ 418#define FSCR_VECVSX_LG 1 /* Enable VMX/VSX */ 419#define FSCR_FP_LG 0 /* Enable Floating Point */ 420#define SPRN_FSCR 0x099 /* Facility Status & Control Register */ 421#define FSCR_PREFIX __MASK(FSCR_PREFIX_LG) 422#define FSCR_SCV __MASK(FSCR_SCV_LG) 423#define FSCR_TAR __MASK(FSCR_TAR_LG) 424#define FSCR_EBB __MASK(FSCR_EBB_LG) 425#define FSCR_DSCR __MASK(FSCR_DSCR_LG) 426#define FSCR_INTR_CAUSE (ASM_CONST(0xFF) << 56) /* interrupt cause */ 427#define SPRN_HFSCR 0xbe /* HV=1 Facility Status & Control Register */ 428#define HFSCR_PREFIX __MASK(FSCR_PREFIX_LG) 429#define HFSCR_MSGP __MASK(FSCR_MSGP_LG) 430#define HFSCR_TAR __MASK(FSCR_TAR_LG) 431#define HFSCR_EBB __MASK(FSCR_EBB_LG) 432#define HFSCR_TM __MASK(FSCR_TM_LG) 433#define HFSCR_PM __MASK(FSCR_PM_LG) 434#define HFSCR_BHRB __MASK(FSCR_BHRB_LG) 435#define HFSCR_DSCR __MASK(FSCR_DSCR_LG) 436#define HFSCR_VECVSX __MASK(FSCR_VECVSX_LG) 437#define HFSCR_FP __MASK(FSCR_FP_LG) 438#define HFSCR_INTR_CAUSE FSCR_INTR_CAUSE 439#define SPRN_TAR 0x32f /* Target Address Register */ 440#define SPRN_LPCR 0x13E /* LPAR Control Register */ 441#define LPCR_VPM0 ASM_CONST(0x8000000000000000) 442#define LPCR_VPM1 ASM_CONST(0x4000000000000000) 443#define LPCR_ISL ASM_CONST(0x2000000000000000) 444#define LPCR_VC_SH 61 445#define LPCR_DPFD_SH 52 446#define LPCR_DPFD (ASM_CONST(7) << LPCR_DPFD_SH) 447#define LPCR_VRMASD_SH 47 448#define LPCR_VRMASD (ASM_CONST(0x1f) << LPCR_VRMASD_SH) 449#define LPCR_VRMA_L ASM_CONST(0x0008000000000000) 450#define LPCR_VRMA_LP0 ASM_CONST(0x0001000000000000) 451#define LPCR_VRMA_LP1 ASM_CONST(0x0000800000000000) 452#define LPCR_RMLS 0x1C000000 /* Implementation dependent RMO limit sel */ 453#define LPCR_RMLS_SH 26 454#define LPCR_HAIL ASM_CONST(0x0000000004000000) /* HV AIL (ISAv3.1) */ 455#define LPCR_ILE ASM_CONST(0x0000000002000000) /* !HV irqs set MSR:LE */ 456#define LPCR_AIL ASM_CONST(0x0000000001800000) /* Alternate interrupt location */ 457#define LPCR_AIL_0 ASM_CONST(0x0000000000000000) /* MMU off exception offset 0x0 */ 458#define LPCR_AIL_3 ASM_CONST(0x0000000001800000) /* MMU on exception offset 0xc00...4xxx */ 459#define LPCR_ONL ASM_CONST(0x0000000000040000) /* online - PURR/SPURR count */ 460#define LPCR_LD ASM_CONST(0x0000000000020000) /* large decremeter */ 461#define LPCR_PECE ASM_CONST(0x000000000001f000) /* powersave exit cause enable */ 462#define LPCR_PECEDP ASM_CONST(0x0000000000010000) /* directed priv dbells cause exit */ 463#define LPCR_PECEDH ASM_CONST(0x0000000000008000) /* directed hyp dbells cause exit */ 464#define LPCR_PECE0 ASM_CONST(0x0000000000004000) /* ext. exceptions can cause exit */ 465#define LPCR_PECE1 ASM_CONST(0x0000000000002000) /* decrementer can cause exit */ 466#define LPCR_PECE2 ASM_CONST(0x0000000000001000) /* machine check etc can cause exit */ 467#define LPCR_PECE_HVEE ASM_CONST(0x0000400000000000) /* P9 Wakeup on HV interrupts */ 468#define LPCR_MER ASM_CONST(0x0000000000000800) /* Mediated External Exception */ 469#define LPCR_MER_SH 11 470#define LPCR_GTSE ASM_CONST(0x0000000000000400) /* Guest Translation Shootdown Enable */ 471#define LPCR_TC ASM_CONST(0x0000000000000200) /* Translation control */ 472#define LPCR_HEIC ASM_CONST(0x0000000000000010) /* Hypervisor External Interrupt Control */ 473#define LPCR_LPES 0x0000000c 474#define LPCR_LPES0 ASM_CONST(0x0000000000000008) /* LPAR Env selector 0 */ 475#define LPCR_LPES1 ASM_CONST(0x0000000000000004) /* LPAR Env selector 1 */ 476#define LPCR_LPES_SH 2 477#define LPCR_RMI ASM_CONST(0x0000000000000002) /* real mode is cache inhibit */ 478#define LPCR_HVICE ASM_CONST(0x0000000000000002) /* P9: HV interrupt enable */ 479#define LPCR_HDICE ASM_CONST(0x0000000000000001) /* Hyp Decr enable (HV,PR,EE) */ 480#define LPCR_UPRT ASM_CONST(0x0000000000400000) /* Use Process Table (ISA 3) */ 481#define LPCR_HR ASM_CONST(0x0000000000100000) 482#ifndef SPRN_LPID 483#define SPRN_LPID 0x13F /* Logical Partition Identifier */ 484#endif 485#define SPRN_HMER 0x150 /* Hypervisor maintenance exception reg */ 486#define HMER_DEBUG_TRIG (1ul << (63 - 17)) /* Debug trigger */ 487#define SPRN_HMEER 0x151 /* Hyp maintenance exception enable reg */ 488#define SPRN_PCR 0x152 /* Processor compatibility register */ 489#define PCR_VEC_DIS (__MASK(63-0)) /* Vec. disable (bit NA since POWER8) */ 490#define PCR_VSX_DIS (__MASK(63-1)) /* VSX disable (bit NA since POWER8) */ 491#define PCR_TM_DIS (__MASK(63-2)) /* Trans. memory disable (POWER8) */ 492#define PCR_MMA_DIS (__MASK(63-3)) /* Matrix-Multiply Accelerator */ 493#define PCR_HIGH_BITS (PCR_MMA_DIS | PCR_VEC_DIS | PCR_VSX_DIS | PCR_TM_DIS) 494/* 495 * These bits are used in the function kvmppc_set_arch_compat() to specify and 496 * determine both the compatibility level which we want to emulate and the 497 * compatibility level which the host is capable of emulating. 498 */ 499#define PCR_ARCH_300 0x10 /* Architecture 3.00 */ 500#define PCR_ARCH_207 0x8 /* Architecture 2.07 */ 501#define PCR_ARCH_206 0x4 /* Architecture 2.06 */ 502#define PCR_ARCH_205 0x2 /* Architecture 2.05 */ 503#define PCR_LOW_BITS (PCR_ARCH_207 | PCR_ARCH_206 | PCR_ARCH_205 | PCR_ARCH_300) 504#define PCR_MASK ~(PCR_HIGH_BITS | PCR_LOW_BITS) /* PCR Reserved Bits */ 505#define SPRN_HEIR 0x153 /* Hypervisor Emulated Instruction Register */ 506#define SPRN_TLBINDEXR 0x154 /* P7 TLB control register */ 507#define SPRN_TLBVPNR 0x155 /* P7 TLB control register */ 508#define SPRN_TLBRPNR 0x156 /* P7 TLB control register */ 509#define SPRN_TLBLPIDR 0x157 /* P7 TLB control register */ 510#define SPRN_DBAT0L 0x219 /* Data BAT 0 Lower Register */ 511#define SPRN_DBAT0U 0x218 /* Data BAT 0 Upper Register */ 512#define SPRN_DBAT1L 0x21B /* Data BAT 1 Lower Register */ 513#define SPRN_DBAT1U 0x21A /* Data BAT 1 Upper Register */ 514#define SPRN_DBAT2L 0x21D /* Data BAT 2 Lower Register */ 515#define SPRN_DBAT2U 0x21C /* Data BAT 2 Upper Register */ 516#define SPRN_DBAT3L 0x21F /* Data BAT 3 Lower Register */ 517#define SPRN_DBAT3U 0x21E /* Data BAT 3 Upper Register */ 518#define SPRN_DBAT4L 0x239 /* Data BAT 4 Lower Register */ 519#define SPRN_DBAT4U 0x238 /* Data BAT 4 Upper Register */ 520#define SPRN_DBAT5L 0x23B /* Data BAT 5 Lower Register */ 521#define SPRN_DBAT5U 0x23A /* Data BAT 5 Upper Register */ 522#define SPRN_DBAT6L 0x23D /* Data BAT 6 Lower Register */ 523#define SPRN_DBAT6U 0x23C /* Data BAT 6 Upper Register */ 524#define SPRN_DBAT7L 0x23F /* Data BAT 7 Lower Register */ 525#define SPRN_DBAT7U 0x23E /* Data BAT 7 Upper Register */ 526#define SPRN_PPR 0x380 /* SMT Thread status Register */ 527#define SPRN_TSCR 0x399 /* Thread Switch Control Register */ 528 529#define SPRN_DEC 0x016 /* Decrement Register */ 530#define SPRN_PIT 0x3DB /* Programmable Interval Timer (40x/BOOKE) */ 531 532#define SPRN_DER 0x095 /* Debug Enable Register */ 533#define DER_RSTE 0x40000000 /* Reset Interrupt */ 534#define DER_CHSTPE 0x20000000 /* Check Stop */ 535#define DER_MCIE 0x10000000 /* Machine Check Interrupt */ 536#define DER_EXTIE 0x02000000 /* External Interrupt */ 537#define DER_ALIE 0x01000000 /* Alignment Interrupt */ 538#define DER_PRIE 0x00800000 /* Program Interrupt */ 539#define DER_FPUVIE 0x00400000 /* FP Unavailable Interrupt */ 540#define DER_DECIE 0x00200000 /* Decrementer Interrupt */ 541#define DER_SYSIE 0x00040000 /* System Call Interrupt */ 542#define DER_TRE 0x00020000 /* Trace Interrupt */ 543#define DER_SEIE 0x00004000 /* FP SW Emulation Interrupt */ 544#define DER_ITLBMSE 0x00002000 /* Imp. Spec. Instruction TLB Miss */ 545#define DER_ITLBERE 0x00001000 /* Imp. Spec. Instruction TLB Error */ 546#define DER_DTLBMSE 0x00000800 /* Imp. Spec. Data TLB Miss */ 547#define DER_DTLBERE 0x00000400 /* Imp. Spec. Data TLB Error */ 548#define DER_LBRKE 0x00000008 /* Load/Store Breakpoint Interrupt */ 549#define DER_IBRKE 0x00000004 /* Instruction Breakpoint Interrupt */ 550#define DER_EBRKE 0x00000002 /* External Breakpoint Interrupt */ 551#define DER_DPIE 0x00000001 /* Dev. Port Nonmaskable Request */ 552#define SPRN_DMISS 0x3D0 /* Data TLB Miss Register */ 553#define SPRN_DHDES 0x0B1 /* Directed Hyp. Doorbell Exc. State */ 554#define SPRN_DPDES 0x0B0 /* Directed Priv. Doorbell Exc. State */ 555#define SPRN_EAR 0x11A /* External Address Register */ 556#define SPRN_HASH1 0x3D2 /* Primary Hash Address Register */ 557#define SPRN_HASH2 0x3D3 /* Secondary Hash Address Register */ 558#define SPRN_HID0 0x3F0 /* Hardware Implementation Register 0 */ 559#define HID0_HDICE_SH (63 - 23) /* 970 HDEC interrupt enable */ 560#define HID0_EMCP (1<<31) /* Enable Machine Check pin */ 561#define HID0_EBA (1<<29) /* Enable Bus Address Parity */ 562#define HID0_EBD (1<<28) /* Enable Bus Data Parity */ 563#define HID0_SBCLK (1<<27) 564#define HID0_EICE (1<<26) 565#define HID0_TBEN (1<<26) /* Timebase enable - 745x */ 566#define HID0_ECLK (1<<25) 567#define HID0_PAR (1<<24) 568#define HID0_STEN (1<<24) /* Software table search enable - 745x */ 569#define HID0_HIGH_BAT (1<<23) /* Enable high BATs - 7455 */ 570#define HID0_DOZE (1<<23) 571#define HID0_NAP (1<<22) 572#define HID0_SLEEP (1<<21) 573#define HID0_DPM (1<<20) 574#define HID0_BHTCLR (1<<18) /* Clear branch history table - 7450 */ 575#define HID0_XAEN (1<<17) /* Extended addressing enable - 7450 */ 576#define HID0_NHR (1<<16) /* Not hard reset (software bit-7450)*/ 577#define HID0_ICE (1<<15) /* Instruction Cache Enable */ 578#define HID0_DCE (1<<14) /* Data Cache Enable */ 579#define HID0_ILOCK (1<<13) /* Instruction Cache Lock */ 580#define HID0_DLOCK (1<<12) /* Data Cache Lock */ 581#define HID0_ICFI (1<<11) /* Instr. Cache Flash Invalidate */ 582#define HID0_DCI (1<<10) /* Data Cache Invalidate */ 583#define HID0_SPD (1<<9) /* Speculative disable */ 584#define HID0_DAPUEN (1<<8) /* Debug APU enable */ 585#define HID0_SGE (1<<7) /* Store Gathering Enable */ 586#define HID0_SIED (1<<7) /* Serial Instr. Execution [Disable] */ 587#define HID0_DCFA (1<<6) /* Data Cache Flush Assist */ 588#define HID0_LRSTK (1<<4) /* Link register stack - 745x */ 589#define HID0_BTIC (1<<5) /* Branch Target Instr Cache Enable */ 590#define HID0_ABE (1<<3) /* Address Broadcast Enable */ 591#define HID0_FOLD (1<<3) /* Branch Folding enable - 745x */ 592#define HID0_BHTE (1<<2) /* Branch History Table Enable */ 593#define HID0_BTCD (1<<1) /* Branch target cache disable */ 594#define HID0_NOPDST (1<<1) /* No-op dst, dstt, etc. instr. */ 595#define HID0_NOPTI (1<<0) /* No-op dcbt and dcbst instr. */ 596/* POWER8 HID0 bits */ 597#define HID0_POWER8_4LPARMODE __MASK(61) 598#define HID0_POWER8_2LPARMODE __MASK(57) 599#define HID0_POWER8_1TO2LPAR __MASK(52) 600#define HID0_POWER8_1TO4LPAR __MASK(51) 601#define HID0_POWER8_DYNLPARDIS __MASK(48) 602 603/* POWER9 HID0 bits */ 604#define HID0_POWER9_RADIX __MASK(63 - 8) 605 606#define SPRN_HID1 0x3F1 /* Hardware Implementation Register 1 */ 607#ifdef CONFIG_PPC_BOOK3S_32 608#define HID1_EMCP (1<<31) /* 7450 Machine Check Pin Enable */ 609#define HID1_DFS (1<<22) /* 7447A Dynamic Frequency Scaling */ 610#define HID1_PC0 (1<<16) /* 7450 PLL_CFG[0] */ 611#define HID1_PC1 (1<<15) /* 7450 PLL_CFG[1] */ 612#define HID1_PC2 (1<<14) /* 7450 PLL_CFG[2] */ 613#define HID1_PC3 (1<<13) /* 7450 PLL_CFG[3] */ 614#define HID1_SYNCBE (1<<11) /* 7450 ABE for sync, eieio */ 615#define HID1_ABE (1<<10) /* 7450 Address Broadcast Enable */ 616#define HID1_PS (1<<16) /* 750FX PLL selection */ 617#endif 618#define SPRN_HID2 0x3F8 /* Hardware Implementation Register 2 */ 619#define SPRN_HID2_GEKKO 0x398 /* Gekko HID2 Register */ 620#define SPRN_HID2_G2_LE 0x3F3 /* G2_LE HID2 Register */ 621#define HID2_G2_LE_HBE (1<<18) /* High BAT Enable (G2_LE) */ 622#define SPRN_IABR 0x3F2 /* Instruction Address Breakpoint Register */ 623#define SPRN_IABR2 0x3FA /* 83xx */ 624#define SPRN_IBCR 0x135 /* 83xx Insn Breakpoint Control Reg */ 625#define SPRN_IAMR 0x03D /* Instr. Authority Mask Reg */ 626#define SPRN_HID4 0x3F4 /* 970 HID4 */ 627#define HID4_LPES0 (1ul << (63-0)) /* LPAR env. sel. bit 0 */ 628#define HID4_RMLS2_SH (63 - 2) /* Real mode limit bottom 2 bits */ 629#define HID4_LPID5_SH (63 - 6) /* partition ID bottom 4 bits */ 630#define HID4_RMOR_SH (63 - 22) /* real mode offset (16 bits) */ 631#define HID4_RMOR (0xFFFFul << HID4_RMOR_SH) 632#define HID4_LPES1 (1 << (63-57)) /* LPAR env. sel. bit 1 */ 633#define HID4_RMLS0_SH (63 - 58) /* Real mode limit top bit */ 634#define HID4_LPID1_SH 0 /* partition ID top 2 bits */ 635#define SPRN_HID4_GEKKO 0x3F3 /* Gekko HID4 */ 636#define SPRN_HID5 0x3F6 /* 970 HID5 */ 637#define SPRN_HID6 0x3F9 /* BE HID 6 */ 638#define HID6_LB (0x0F<<12) /* Concurrent Large Page Modes */ 639#define HID6_DLP (1<<20) /* Disable all large page modes (4K only) */ 640#define SPRN_TSC_CELL 0x399 /* Thread switch control on Cell */ 641#define TSC_CELL_DEC_ENABLE_0 0x400000 /* Decrementer Interrupt */ 642#define TSC_CELL_DEC_ENABLE_1 0x200000 /* Decrementer Interrupt */ 643#define TSC_CELL_EE_ENABLE 0x100000 /* External Interrupt */ 644#define TSC_CELL_EE_BOOST 0x080000 /* External Interrupt Boost */ 645#define SPRN_TSC 0x3FD /* Thread switch control on others */ 646#define SPRN_TST 0x3FC /* Thread switch timeout on others */ 647#if !defined(SPRN_IAC1) && !defined(SPRN_IAC2) 648#define SPRN_IAC1 0x3F4 /* Instruction Address Compare 1 */ 649#define SPRN_IAC2 0x3F5 /* Instruction Address Compare 2 */ 650#endif 651#define SPRN_IBAT0L 0x211 /* Instruction BAT 0 Lower Register */ 652#define SPRN_IBAT0U 0x210 /* Instruction BAT 0 Upper Register */ 653#define SPRN_IBAT1L 0x213 /* Instruction BAT 1 Lower Register */ 654#define SPRN_IBAT1U 0x212 /* Instruction BAT 1 Upper Register */ 655#define SPRN_IBAT2L 0x215 /* Instruction BAT 2 Lower Register */ 656#define SPRN_IBAT2U 0x214 /* Instruction BAT 2 Upper Register */ 657#define SPRN_IBAT3L 0x217 /* Instruction BAT 3 Lower Register */ 658#define SPRN_IBAT3U 0x216 /* Instruction BAT 3 Upper Register */ 659#define SPRN_IBAT4L 0x231 /* Instruction BAT 4 Lower Register */ 660#define SPRN_IBAT4U 0x230 /* Instruction BAT 4 Upper Register */ 661#define SPRN_IBAT5L 0x233 /* Instruction BAT 5 Lower Register */ 662#define SPRN_IBAT5U 0x232 /* Instruction BAT 5 Upper Register */ 663#define SPRN_IBAT6L 0x235 /* Instruction BAT 6 Lower Register */ 664#define SPRN_IBAT6U 0x234 /* Instruction BAT 6 Upper Register */ 665#define SPRN_IBAT7L 0x237 /* Instruction BAT 7 Lower Register */ 666#define SPRN_IBAT7U 0x236 /* Instruction BAT 7 Upper Register */ 667#define SPRN_ICMP 0x3D5 /* Instruction TLB Compare Register */ 668#define SPRN_ICTC 0x3FB /* Instruction Cache Throttling Control Reg */ 669#ifndef SPRN_ICTRL 670#define SPRN_ICTRL 0x3F3 /* 1011 7450 icache and interrupt ctrl */ 671#endif 672#define ICTRL_EICE 0x08000000 /* enable icache parity errs */ 673#define ICTRL_EDC 0x04000000 /* enable dcache parity errs */ 674#define ICTRL_EICP 0x00000100 /* enable icache par. check */ 675#define SPRN_IMISS 0x3D4 /* Instruction TLB Miss Register */ 676#define SPRN_IMMR 0x27E /* Internal Memory Map Register */ 677#define SPRN_L2CR 0x3F9 /* Level 2 Cache Control Register */ 678#define SPRN_L2CR2 0x3f8 679#define L2CR_L2E 0x80000000 /* L2 enable */ 680#define L2CR_L2PE 0x40000000 /* L2 parity enable */ 681#define L2CR_L2SIZ_MASK 0x30000000 /* L2 size mask */ 682#define L2CR_L2SIZ_256KB 0x10000000 /* L2 size 256KB */ 683#define L2CR_L2SIZ_512KB 0x20000000 /* L2 size 512KB */ 684#define L2CR_L2SIZ_1MB 0x30000000 /* L2 size 1MB */ 685#define L2CR_L2CLK_MASK 0x0e000000 /* L2 clock mask */ 686#define L2CR_L2CLK_DISABLED 0x00000000 /* L2 clock disabled */ 687#define L2CR_L2CLK_DIV1 0x02000000 /* L2 clock / 1 */ 688#define L2CR_L2CLK_DIV1_5 0x04000000 /* L2 clock / 1.5 */ 689#define L2CR_L2CLK_DIV2 0x08000000 /* L2 clock / 2 */ 690#define L2CR_L2CLK_DIV2_5 0x0a000000 /* L2 clock / 2.5 */ 691#define L2CR_L2CLK_DIV3 0x0c000000 /* L2 clock / 3 */ 692#define L2CR_L2RAM_MASK 0x01800000 /* L2 RAM type mask */ 693#define L2CR_L2RAM_FLOW 0x00000000 /* L2 RAM flow through */ 694#define L2CR_L2RAM_PIPE 0x01000000 /* L2 RAM pipelined */ 695#define L2CR_L2RAM_PIPE_LW 0x01800000 /* L2 RAM pipelined latewr */ 696#define L2CR_L2DO 0x00400000 /* L2 data only */ 697#define L2CR_L2I 0x00200000 /* L2 global invalidate */ 698#define L2CR_L2CTL 0x00100000 /* L2 RAM control */ 699#define L2CR_L2WT 0x00080000 /* L2 write-through */ 700#define L2CR_L2TS 0x00040000 /* L2 test support */ 701#define L2CR_L2OH_MASK 0x00030000 /* L2 output hold mask */ 702#define L2CR_L2OH_0_5 0x00000000 /* L2 output hold 0.5 ns */ 703#define L2CR_L2OH_1_0 0x00010000 /* L2 output hold 1.0 ns */ 704#define L2CR_L2SL 0x00008000 /* L2 DLL slow */ 705#define L2CR_L2DF 0x00004000 /* L2 differential clock */ 706#define L2CR_L2BYP 0x00002000 /* L2 DLL bypass */ 707#define L2CR_L2IP 0x00000001 /* L2 GI in progress */ 708#define L2CR_L2IO_745x 0x00100000 /* L2 instr. only (745x) */ 709#define L2CR_L2DO_745x 0x00010000 /* L2 data only (745x) */ 710#define L2CR_L2REP_745x 0x00001000 /* L2 repl. algorithm (745x) */ 711#define L2CR_L2HWF_745x 0x00000800 /* L2 hardware flush (745x) */ 712#define SPRN_L3CR 0x3FA /* Level 3 Cache Control Register */ 713#define L3CR_L3E 0x80000000 /* L3 enable */ 714#define L3CR_L3PE 0x40000000 /* L3 data parity enable */ 715#define L3CR_L3APE 0x20000000 /* L3 addr parity enable */ 716#define L3CR_L3SIZ 0x10000000 /* L3 size */ 717#define L3CR_L3CLKEN 0x08000000 /* L3 clock enable */ 718#define L3CR_L3RES 0x04000000 /* L3 special reserved bit */ 719#define L3CR_L3CLKDIV 0x03800000 /* L3 clock divisor */ 720#define L3CR_L3IO 0x00400000 /* L3 instruction only */ 721#define L3CR_L3SPO 0x00040000 /* L3 sample point override */ 722#define L3CR_L3CKSP 0x00030000 /* L3 clock sample point */ 723#define L3CR_L3PSP 0x0000e000 /* L3 P-clock sample point */ 724#define L3CR_L3REP 0x00001000 /* L3 replacement algorithm */ 725#define L3CR_L3HWF 0x00000800 /* L3 hardware flush */ 726#define L3CR_L3I 0x00000400 /* L3 global invalidate */ 727#define L3CR_L3RT 0x00000300 /* L3 SRAM type */ 728#define L3CR_L3NIRCA 0x00000080 /* L3 non-integer ratio clock adj. */ 729#define L3CR_L3DO 0x00000040 /* L3 data only mode */ 730#define L3CR_PMEN 0x00000004 /* L3 private memory enable */ 731#define L3CR_PMSIZ 0x00000001 /* L3 private memory size */ 732 733#define SPRN_MSSCR0 0x3f6 /* Memory Subsystem Control Register 0 */ 734#define SPRN_MSSSR0 0x3f7 /* Memory Subsystem Status Register 1 */ 735#define SPRN_LDSTCR 0x3f8 /* Load/Store control register */ 736#define SPRN_LDSTDB 0x3f4 /* */ 737#define SPRN_LR 0x008 /* Link Register */ 738#ifndef SPRN_PIR 739#define SPRN_PIR 0x3FF /* Processor Identification Register */ 740#endif 741#define SPRN_TIR 0x1BE /* Thread Identification Register */ 742#define SPRN_PTCR 0x1D0 /* Partition table control Register */ 743#define SPRN_PSPB 0x09F /* Problem State Priority Boost reg */ 744#define SPRN_PTEHI 0x3D5 /* 981 7450 PTE HI word (S/W TLB load) */ 745#define SPRN_PTELO 0x3D6 /* 982 7450 PTE LO word (S/W TLB load) */ 746#define SPRN_PURR 0x135 /* Processor Utilization of Resources Reg */ 747#define SPRN_PVR 0x11F /* Processor Version Register */ 748#define SPRN_RPA 0x3D6 /* Required Physical Address Register */ 749#define SPRN_SDA 0x3BF /* Sampled Data Address Register */ 750#define SPRN_SDR1 0x019 /* MMU Hash Base Register */ 751#define SPRN_ASR 0x118 /* Address Space Register */ 752#define SPRN_SIA 0x3BB /* Sampled Instruction Address Register */ 753#define SPRN_SPRG0 0x110 /* Special Purpose Register General 0 */ 754#define SPRN_SPRG1 0x111 /* Special Purpose Register General 1 */ 755#define SPRN_SPRG2 0x112 /* Special Purpose Register General 2 */ 756#define SPRN_SPRG3 0x113 /* Special Purpose Register General 3 */ 757#define SPRN_USPRG3 0x103 /* SPRG3 userspace read */ 758#define SPRN_SPRG4 0x114 /* Special Purpose Register General 4 */ 759#define SPRN_USPRG4 0x104 /* SPRG4 userspace read */ 760#define SPRN_SPRG5 0x115 /* Special Purpose Register General 5 */ 761#define SPRN_USPRG5 0x105 /* SPRG5 userspace read */ 762#define SPRN_SPRG6 0x116 /* Special Purpose Register General 6 */ 763#define SPRN_USPRG6 0x106 /* SPRG6 userspace read */ 764#define SPRN_SPRG7 0x117 /* Special Purpose Register General 7 */ 765#define SPRN_USPRG7 0x107 /* SPRG7 userspace read */ 766#define SPRN_SRR0 0x01A /* Save/Restore Register 0 */ 767#define SPRN_SRR1 0x01B /* Save/Restore Register 1 */ 768 769#ifdef CONFIG_PPC_BOOK3S 770/* 771 * Bits loaded from MSR upon interrupt. 772 * PPC (64-bit) bits 33-36,42-47 are interrupt dependent, the others are 773 * loaded from MSR. The exception is that SRESET and MCE do not always load 774 * bit 62 (RI) from MSR. Don't use PPC_BITMASK for this because 32-bit uses 775 * it. 776 */ 777#define SRR1_MSR_BITS (~0x783f0000UL) 778#endif 779 780#define SRR1_ISI_NOPT 0x40000000 /* ISI: Not found in hash */ 781#define SRR1_ISI_N_G_OR_CIP 0x10000000 /* ISI: Access is no-exec or G or CI for a prefixed instruction */ 782#define SRR1_ISI_PROT 0x08000000 /* ISI: Other protection fault */ 783#define SRR1_WAKEMASK 0x00380000 /* reason for wakeup */ 784#define SRR1_WAKEMASK_P8 0x003c0000 /* reason for wakeup on POWER8 and 9 */ 785#define SRR1_WAKEMCE_RESVD 0x003c0000 /* Unused/reserved value used by MCE wakeup to indicate cause to idle wakeup handler */ 786#define SRR1_WAKESYSERR 0x00300000 /* System error */ 787#define SRR1_WAKEEE 0x00200000 /* External interrupt */ 788#define SRR1_WAKEHVI 0x00240000 /* Hypervisor Virtualization Interrupt (P9) */ 789#define SRR1_WAKEMT 0x00280000 /* mtctrl */ 790#define SRR1_WAKEHMI 0x00280000 /* Hypervisor maintenance */ 791#define SRR1_WAKEDEC 0x00180000 /* Decrementer interrupt */ 792#define SRR1_WAKEDBELL 0x00140000 /* Privileged doorbell on P8 */ 793#define SRR1_WAKETHERM 0x00100000 /* Thermal management interrupt */ 794#define SRR1_WAKERESET 0x00100000 /* System reset */ 795#define SRR1_WAKEHDBELL 0x000c0000 /* Hypervisor doorbell on P8 */ 796#define SRR1_WAKESTATE 0x00030000 /* Powersave exit mask [46:47] */ 797#define SRR1_WS_HVLOSS 0x00030000 /* HV resources not maintained */ 798#define SRR1_WS_GPRLOSS 0x00020000 /* GPRs not maintained */ 799#define SRR1_WS_NOLOSS 0x00010000 /* All resources maintained */ 800#define SRR1_PROGTM 0x00200000 /* TM Bad Thing */ 801#define SRR1_PROGFPE 0x00100000 /* Floating Point Enabled */ 802#define SRR1_PROGILL 0x00080000 /* Illegal instruction */ 803#define SRR1_PROGPRIV 0x00040000 /* Privileged instruction */ 804#define SRR1_PROGTRAP 0x00020000 /* Trap */ 805#define SRR1_PROGADDR 0x00010000 /* SRR0 contains subsequent addr */ 806 807#define SRR1_MCE_MCP 0x00080000 /* Machine check signal caused interrupt */ 808#define SRR1_BOUNDARY 0x10000000 /* Prefixed instruction crosses 64-byte boundary */ 809#define SRR1_PREFIXED 0x20000000 /* Exception caused by prefixed instruction */ 810 811#define SPRN_HSRR0 0x13A /* Save/Restore Register 0 */ 812#define SPRN_HSRR1 0x13B /* Save/Restore Register 1 */ 813#define HSRR1_DENORM 0x00100000 /* Denorm exception */ 814#define HSRR1_HISI_WRITE 0x00010000 /* HISI bcs couldn't update mem */ 815 816#define SPRN_TBCTL 0x35f /* PA6T Timebase control register */ 817#define TBCTL_FREEZE 0x0000000000000000ull /* Freeze all tbs */ 818#define TBCTL_RESTART 0x0000000100000000ull /* Restart all tbs */ 819#define TBCTL_UPDATE_UPPER 0x0000000200000000ull /* Set upper 32 bits */ 820#define TBCTL_UPDATE_LOWER 0x0000000300000000ull /* Set lower 32 bits */ 821 822#ifndef SPRN_SVR 823#define SPRN_SVR 0x11E /* System Version Register */ 824#endif 825#define SPRN_THRM1 0x3FC /* Thermal Management Register 1 */ 826/* these bits were defined in inverted endian sense originally, ugh, confusing */ 827#define THRM1_TIN (1 << 31) 828#define THRM1_TIV (1 << 30) 829#define THRM1_THRES(x) ((x&0x7f)<<23) 830#define THRM3_SITV(x) ((x & 0x1fff) << 1) 831#define THRM1_TID (1<<2) 832#define THRM1_TIE (1<<1) 833#define THRM1_V (1<<0) 834#define SPRN_THRM2 0x3FD /* Thermal Management Register 2 */ 835#define SPRN_THRM3 0x3FE /* Thermal Management Register 3 */ 836#define THRM3_E (1<<0) 837#define SPRN_TLBMISS 0x3D4 /* 980 7450 TLB Miss Register */ 838#define SPRN_UMMCR0 0x3A8 /* User Monitor Mode Control Register 0 */ 839#define SPRN_UMMCR1 0x3AC /* User Monitor Mode Control Register 0 */ 840#define SPRN_UPMC1 0x3A9 /* User Performance Counter Register 1 */ 841#define SPRN_UPMC2 0x3AA /* User Performance Counter Register 2 */ 842#define SPRN_UPMC3 0x3AD /* User Performance Counter Register 3 */ 843#define SPRN_UPMC4 0x3AE /* User Performance Counter Register 4 */ 844#define SPRN_USIA 0x3AB /* User Sampled Instruction Address Register */ 845#define SPRN_VRSAVE 0x100 /* Vector Register Save Register */ 846#define SPRN_XER 0x001 /* Fixed Point Exception Register */ 847 848#define SPRN_MMCR0_GEKKO 0x3B8 /* Gekko Monitor Mode Control Register 0 */ 849#define SPRN_MMCR1_GEKKO 0x3BC /* Gekko Monitor Mode Control Register 1 */ 850#define SPRN_PMC1_GEKKO 0x3B9 /* Gekko Performance Monitor Control 1 */ 851#define SPRN_PMC2_GEKKO 0x3BA /* Gekko Performance Monitor Control 2 */ 852#define SPRN_PMC3_GEKKO 0x3BD /* Gekko Performance Monitor Control 3 */ 853#define SPRN_PMC4_GEKKO 0x3BE /* Gekko Performance Monitor Control 4 */ 854#define SPRN_WPAR_GEKKO 0x399 /* Gekko Write Pipe Address Register */ 855 856#define SPRN_SCOMC 0x114 /* SCOM Access Control */ 857#define SPRN_SCOMD 0x115 /* SCOM Access DATA */ 858 859/* Performance monitor SPRs */ 860#ifdef CONFIG_PPC64 861#define SPRN_MMCR0 795 862#define MMCR0_FC 0x80000000UL /* freeze counters */ 863#define MMCR0_FCS 0x40000000UL /* freeze in supervisor state */ 864#define MMCR0_KERNEL_DISABLE MMCR0_FCS 865#define MMCR0_FCP 0x20000000UL /* freeze in problem state */ 866#define MMCR0_PROBLEM_DISABLE MMCR0_FCP 867#define MMCR0_FCM1 0x10000000UL /* freeze counters while MSR mark = 1 */ 868#define MMCR0_FCM0 0x08000000UL /* freeze counters while MSR mark = 0 */ 869#define MMCR0_PMXE ASM_CONST(0x04000000) /* perf mon exception enable */ 870#define MMCR0_FCECE ASM_CONST(0x02000000) /* freeze ctrs on enabled cond or event */ 871#define MMCR0_TBEE 0x00400000UL /* time base exception enable */ 872#define MMCR0_BHRBA 0x00200000UL /* BHRB Access allowed in userspace */ 873#define MMCR0_EBE 0x00100000UL /* Event based branch enable */ 874#define MMCR0_PMCC 0x000c0000UL /* PMC control */ 875#define MMCR0_PMCCEXT ASM_CONST(0x00000200) /* PMCCEXT control */ 876#define MMCR0_PMCC_U6 0x00080000UL /* PMC1-6 are R/W by user (PR) */ 877#define MMCR0_PMC1CE 0x00008000UL /* PMC1 count enable*/ 878#define MMCR0_PMCjCE ASM_CONST(0x00004000) /* PMCj count enable*/ 879#define MMCR0_TRIGGER 0x00002000UL /* TRIGGER enable */ 880#define MMCR0_PMAO_SYNC ASM_CONST(0x00000800) /* PMU intr is synchronous */ 881#define MMCR0_C56RUN ASM_CONST(0x00000100) /* PMC5/6 count when RUN=0 */ 882/* performance monitor alert has occurred, set to 0 after handling exception */ 883#define MMCR0_PMAO ASM_CONST(0x00000080) 884#define MMCR0_SHRFC 0x00000040UL /* SHRre freeze conditions between threads */ 885#define MMCR0_FC56 0x00000010UL /* freeze counters 5 and 6 */ 886#define MMCR0_FCTI 0x00000008UL /* freeze counters in tags inactive mode */ 887#define MMCR0_FCTA 0x00000004UL /* freeze counters in tags active mode */ 888#define MMCR0_FCWAIT 0x00000002UL /* freeze counter in WAIT state */ 889#define MMCR0_FCHV 0x00000001UL /* freeze conditions in hypervisor mode */ 890#define SPRN_MMCR1 798 891#define SPRN_MMCR2 785 892#define SPRN_MMCR3 754 893#define SPRN_UMMCR2 769 894#define SPRN_UMMCR3 738 895#define SPRN_MMCRA 0x312 896#define MMCRA_SDSYNC 0x80000000UL /* SDAR synced with SIAR */ 897#define MMCRA_SDAR_DCACHE_MISS 0x40000000UL 898#define MMCRA_SDAR_ERAT_MISS 0x20000000UL 899#define MMCRA_SIHV 0x10000000UL /* state of MSR HV when SIAR set */ 900#define MMCRA_SIPR 0x08000000UL /* state of MSR PR when SIAR set */ 901#define MMCRA_SLOT 0x07000000UL /* SLOT bits (37-39) */ 902#define MMCRA_SLOT_SHIFT 24 903#define MMCRA_SAMPLE_ENABLE 0x00000001UL /* enable sampling */ 904#define MMCRA_BHRB_DISABLE _UL(0x2000000000) // BHRB disable bit for ISA v3.1 905#define POWER6_MMCRA_SDSYNC 0x0000080000000000ULL /* SDAR/SIAR synced */ 906#define POWER6_MMCRA_SIHV 0x0000040000000000ULL 907#define POWER6_MMCRA_SIPR 0x0000020000000000ULL 908#define POWER6_MMCRA_THRM 0x00000020UL 909#define POWER6_MMCRA_OTHER 0x0000000EUL 910 911#define POWER7P_MMCRA_SIAR_VALID 0x10000000 /* P7+ SIAR contents valid */ 912#define POWER7P_MMCRA_SDAR_VALID 0x08000000 /* P7+ SDAR contents valid */ 913 914#define SPRN_MMCRH 316 /* Hypervisor monitor mode control register */ 915#define SPRN_MMCRS 894 /* Supervisor monitor mode control register */ 916#define SPRN_MMCRC 851 /* Core monitor mode control register */ 917#define SPRN_EBBHR 804 /* Event based branch handler register */ 918#define SPRN_EBBRR 805 /* Event based branch return register */ 919#define SPRN_BESCR 806 /* Branch event status and control register */ 920#define BESCR_GE 0x8000000000000000ULL /* Global Enable */ 921#define SPRN_WORT 895 /* Workload optimization register - thread */ 922#define SPRN_WORC 863 /* Workload optimization register - core */ 923 924#define SPRN_PMC1 787 925#define SPRN_PMC2 788 926#define SPRN_PMC3 789 927#define SPRN_PMC4 790 928#define SPRN_PMC5 791 929#define SPRN_PMC6 792 930#define SPRN_PMC7 793 931#define SPRN_PMC8 794 932#define SPRN_SIER 784 933#define SIER_SIPR 0x2000000 /* Sampled MSR_PR */ 934#define SIER_SIHV 0x1000000 /* Sampled MSR_HV */ 935#define SIER_SIAR_VALID 0x0400000 /* SIAR contents valid */ 936#define SIER_SDAR_VALID 0x0200000 /* SDAR contents valid */ 937#define SPRN_SIER2 752 938#define SPRN_SIER3 753 939#define SPRN_USIER2 736 940#define SPRN_USIER3 737 941#define SPRN_SIAR 796 942#define SPRN_SDAR 797 943#define SPRN_TACR 888 944#define SPRN_TCSCR 889 945#define SPRN_CSIGR 890 946#define SPRN_SPMC1 892 947#define SPRN_SPMC2 893 948 949/* When EBB is enabled, some of MMCR0/MMCR2/SIER are user accessible */ 950#define MMCR0_USER_MASK (MMCR0_FC | MMCR0_PMXE | MMCR0_PMAO) 951#define MMCR2_USER_MASK 0x4020100804020000UL /* (FC1P|FC2P|FC3P|FC4P|FC5P|FC6P) */ 952#define SIER_USER_MASK 0x7fffffUL 953 954#define SPRN_PA6T_MMCR0 795 955#define PA6T_MMCR0_EN0 0x0000000000000001UL 956#define PA6T_MMCR0_EN1 0x0000000000000002UL 957#define PA6T_MMCR0_EN2 0x0000000000000004UL 958#define PA6T_MMCR0_EN3 0x0000000000000008UL 959#define PA6T_MMCR0_EN4 0x0000000000000010UL 960#define PA6T_MMCR0_EN5 0x0000000000000020UL 961#define PA6T_MMCR0_SUPEN 0x0000000000000040UL 962#define PA6T_MMCR0_PREN 0x0000000000000080UL 963#define PA6T_MMCR0_HYPEN 0x0000000000000100UL 964#define PA6T_MMCR0_FCM0 0x0000000000000200UL 965#define PA6T_MMCR0_FCM1 0x0000000000000400UL 966#define PA6T_MMCR0_INTGEN 0x0000000000000800UL 967#define PA6T_MMCR0_INTEN0 0x0000000000001000UL 968#define PA6T_MMCR0_INTEN1 0x0000000000002000UL 969#define PA6T_MMCR0_INTEN2 0x0000000000004000UL 970#define PA6T_MMCR0_INTEN3 0x0000000000008000UL 971#define PA6T_MMCR0_INTEN4 0x0000000000010000UL 972#define PA6T_MMCR0_INTEN5 0x0000000000020000UL 973#define PA6T_MMCR0_DISCNT 0x0000000000040000UL 974#define PA6T_MMCR0_UOP 0x0000000000080000UL 975#define PA6T_MMCR0_TRG 0x0000000000100000UL 976#define PA6T_MMCR0_TRGEN 0x0000000000200000UL 977#define PA6T_MMCR0_TRGREG 0x0000000001600000UL 978#define PA6T_MMCR0_SIARLOG 0x0000000002000000UL 979#define PA6T_MMCR0_SDARLOG 0x0000000004000000UL 980#define PA6T_MMCR0_PROEN 0x0000000008000000UL 981#define PA6T_MMCR0_PROLOG 0x0000000010000000UL 982#define PA6T_MMCR0_DAMEN2 0x0000000020000000UL 983#define PA6T_MMCR0_DAMEN3 0x0000000040000000UL 984#define PA6T_MMCR0_DAMEN4 0x0000000080000000UL 985#define PA6T_MMCR0_DAMEN5 0x0000000100000000UL 986#define PA6T_MMCR0_DAMSEL2 0x0000000200000000UL 987#define PA6T_MMCR0_DAMSEL3 0x0000000400000000UL 988#define PA6T_MMCR0_DAMSEL4 0x0000000800000000UL 989#define PA6T_MMCR0_DAMSEL5 0x0000001000000000UL 990#define PA6T_MMCR0_HANDDIS 0x0000002000000000UL 991#define PA6T_MMCR0_PCTEN 0x0000004000000000UL 992#define PA6T_MMCR0_SOCEN 0x0000008000000000UL 993#define PA6T_MMCR0_SOCMOD 0x0000010000000000UL 994 995#define SPRN_PA6T_MMCR1 798 996#define PA6T_MMCR1_ES2 0x00000000000000ffUL 997#define PA6T_MMCR1_ES3 0x000000000000ff00UL 998#define PA6T_MMCR1_ES4 0x0000000000ff0000UL 999#define PA6T_MMCR1_ES5 0x00000000ff000000UL 1000 1001#define SPRN_PA6T_UPMC0 771 /* User PerfMon Counter 0 */ 1002#define SPRN_PA6T_UPMC1 772 /* ... */ 1003#define SPRN_PA6T_UPMC2 773 1004#define SPRN_PA6T_UPMC3 774 1005#define SPRN_PA6T_UPMC4 775 1006#define SPRN_PA6T_UPMC5 776 1007#define SPRN_PA6T_UMMCR0 779 /* User Monitor Mode Control Register 0 */ 1008#define SPRN_PA6T_SIAR 780 /* Sampled Instruction Address */ 1009#define SPRN_PA6T_UMMCR1 782 /* User Monitor Mode Control Register 1 */ 1010#define SPRN_PA6T_SIER 785 /* Sampled Instruction Event Register */ 1011#define SPRN_PA6T_PMC0 787 1012#define SPRN_PA6T_PMC1 788 1013#define SPRN_PA6T_PMC2 789 1014#define SPRN_PA6T_PMC3 790 1015#define SPRN_PA6T_PMC4 791 1016#define SPRN_PA6T_PMC5 792 1017#define SPRN_PA6T_TSR0 793 /* Timestamp Register 0 */ 1018#define SPRN_PA6T_TSR1 794 /* Timestamp Register 1 */ 1019#define SPRN_PA6T_TSR2 799 /* Timestamp Register 2 */ 1020#define SPRN_PA6T_TSR3 784 /* Timestamp Register 3 */ 1021 1022#define SPRN_PA6T_IER 981 /* Icache Error Register */ 1023#define SPRN_PA6T_DER 982 /* Dcache Error Register */ 1024#define SPRN_PA6T_BER 862 /* BIU Error Address Register */ 1025#define SPRN_PA6T_MER 849 /* MMU Error Register */ 1026 1027#define SPRN_PA6T_IMA0 880 /* Instruction Match Array 0 */ 1028#define SPRN_PA6T_IMA1 881 /* ... */ 1029#define SPRN_PA6T_IMA2 882 1030#define SPRN_PA6T_IMA3 883 1031#define SPRN_PA6T_IMA4 884 1032#define SPRN_PA6T_IMA5 885 1033#define SPRN_PA6T_IMA6 886 1034#define SPRN_PA6T_IMA7 887 1035#define SPRN_PA6T_IMA8 888 1036#define SPRN_PA6T_IMA9 889 1037#define SPRN_PA6T_BTCR 978 /* Breakpoint and Tagging Control Register */ 1038#define SPRN_PA6T_IMAAT 979 /* Instruction Match Array Action Table */ 1039#define SPRN_PA6T_PCCR 1019 /* Power Counter Control Register */ 1040#define SPRN_BKMK 1020 /* Cell Bookmark Register */ 1041#define SPRN_PA6T_RPCCR 1021 /* Retire PC Trace Control Register */ 1042 1043 1044#else /* 32-bit */ 1045#define SPRN_MMCR0 952 /* Monitor Mode Control Register 0 */ 1046#define MMCR0_FC 0x80000000UL /* freeze counters */ 1047#define MMCR0_FCS 0x40000000UL /* freeze in supervisor state */ 1048#define MMCR0_FCP 0x20000000UL /* freeze in problem state */ 1049#define MMCR0_FCM1 0x10000000UL /* freeze counters while MSR mark = 1 */ 1050#define MMCR0_FCM0 0x08000000UL /* freeze counters while MSR mark = 0 */ 1051#define MMCR0_PMXE 0x04000000UL /* performance monitor exception enable */ 1052#define MMCR0_FCECE 0x02000000UL /* freeze ctrs on enabled cond or event */ 1053#define MMCR0_TBEE 0x00400000UL /* time base exception enable */ 1054#define MMCR0_PMC1CE 0x00008000UL /* PMC1 count enable*/ 1055#define MMCR0_PMCnCE 0x00004000UL /* count enable for all but PMC 1*/ 1056#define MMCR0_TRIGGER 0x00002000UL /* TRIGGER enable */ 1057#define MMCR0_PMC1SEL 0x00001fc0UL /* PMC 1 Event */ 1058#define MMCR0_PMC2SEL 0x0000003fUL /* PMC 2 Event */ 1059 1060#define SPRN_MMCR1 956 1061#define MMCR1_PMC3SEL 0xf8000000UL /* PMC 3 Event */ 1062#define MMCR1_PMC4SEL 0x07c00000UL /* PMC 4 Event */ 1063#define MMCR1_PMC5SEL 0x003e0000UL /* PMC 5 Event */ 1064#define MMCR1_PMC6SEL 0x0001f800UL /* PMC 6 Event */ 1065#define SPRN_MMCR2 944 1066#define SPRN_PMC1 953 /* Performance Counter Register 1 */ 1067#define SPRN_PMC2 954 /* Performance Counter Register 2 */ 1068#define SPRN_PMC3 957 /* Performance Counter Register 3 */ 1069#define SPRN_PMC4 958 /* Performance Counter Register 4 */ 1070#define SPRN_PMC5 945 /* Performance Counter Register 5 */ 1071#define SPRN_PMC6 946 /* Performance Counter Register 6 */ 1072 1073#define SPRN_SIAR 955 /* Sampled Instruction Address Register */ 1074 1075/* Bit definitions for MMCR0 and PMC1 / PMC2. */ 1076#define MMCR0_PMC1_CYCLES (1 << 7) 1077#define MMCR0_PMC1_ICACHEMISS (5 << 7) 1078#define MMCR0_PMC1_DTLB (6 << 7) 1079#define MMCR0_PMC2_DCACHEMISS 0x6 1080#define MMCR0_PMC2_CYCLES 0x1 1081#define MMCR0_PMC2_ITLB 0x7 1082#define MMCR0_PMC2_LOADMISSTIME 0x5 1083#endif 1084 1085/* 1086 * SPRG usage: 1087 * 1088 * All 64-bit: 1089 * - SPRG1 stores PACA pointer except 64-bit server in 1090 * HV mode in which case it is HSPRG0 1091 * 1092 * 64-bit server: 1093 * - SPRG0 scratch for TM recheckpoint/reclaim (reserved for HV on Power4) 1094 * - SPRG2 scratch for exception vectors 1095 * - SPRG3 CPU and NUMA node for VDSO getcpu (user visible) 1096 * - HSPRG0 stores PACA in HV mode 1097 * - HSPRG1 scratch for "HV" exceptions 1098 * 1099 * 64-bit embedded 1100 * - SPRG0 generic exception scratch 1101 * - SPRG2 TLB exception stack 1102 * - SPRG3 critical exception scratch (user visible, sorry!) 1103 * - SPRG4 unused (user visible) 1104 * - SPRG6 TLB miss scratch (user visible, sorry !) 1105 * - SPRG7 CPU and NUMA node for VDSO getcpu (user visible) 1106 * - SPRG8 machine check exception scratch 1107 * - SPRG9 debug exception scratch 1108 * 1109 * All 32-bit: 1110 * - SPRG3 current thread_struct physical addr pointer 1111 * (virtual on BookE, physical on others) 1112 * 1113 * 32-bit classic: 1114 * - SPRG0 scratch for exception vectors 1115 * - SPRG1 scratch for exception vectors 1116 * - SPRG2 indicator that we are in RTAS 1117 * - SPRG4 (603 only) pseudo TLB LRU data 1118 * 1119 * 32-bit 40x: 1120 * - SPRG0 scratch for exception vectors 1121 * - SPRG1 scratch for exception vectors 1122 * - SPRG2 scratch for exception vectors 1123 * - SPRG4 scratch for exception vectors (not 403) 1124 * - SPRG5 scratch for exception vectors (not 403) 1125 * - SPRG6 scratch for exception vectors (not 403) 1126 * - SPRG7 scratch for exception vectors (not 403) 1127 * 1128 * 32-bit 440 and FSL BookE: 1129 * - SPRG0 scratch for exception vectors 1130 * - SPRG1 scratch for exception vectors (*) 1131 * - SPRG2 scratch for crit interrupts handler 1132 * - SPRG4 scratch for exception vectors 1133 * - SPRG5 scratch for exception vectors 1134 * - SPRG6 scratch for machine check handler 1135 * - SPRG7 scratch for exception vectors 1136 * - SPRG9 scratch for debug vectors (e500 only) 1137 * 1138 * Additionally, BookE separates "read" and "write" 1139 * of those registers. That allows to use the userspace 1140 * readable variant for reads, which can avoid a fault 1141 * with KVM type virtualization. 1142 * 1143 * 32-bit 8xx: 1144 * - SPRG0 scratch for exception vectors 1145 * - SPRG1 scratch for exception vectors 1146 * - SPRG2 scratch for exception vectors 1147 * 1148 */ 1149#ifdef CONFIG_PPC64 1150#define SPRN_SPRG_PACA SPRN_SPRG1 1151#else 1152#define SPRN_SPRG_THREAD SPRN_SPRG3 1153#endif 1154 1155#ifdef CONFIG_PPC_BOOK3S_64 1156#define SPRN_SPRG_SCRATCH0 SPRN_SPRG2 1157#define SPRN_SPRG_HPACA SPRN_HSPRG0 1158#define SPRN_SPRG_HSCRATCH0 SPRN_HSPRG1 1159#define SPRN_SPRG_VDSO_READ SPRN_USPRG3 1160#define SPRN_SPRG_VDSO_WRITE SPRN_SPRG3 1161 1162#define GET_PACA(rX) \ 1163 BEGIN_FTR_SECTION_NESTED(66); \ 1164 mfspr rX,SPRN_SPRG_PACA; \ 1165 FTR_SECTION_ELSE_NESTED(66); \ 1166 mfspr rX,SPRN_SPRG_HPACA; \ 1167 ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_HVMODE, 66) 1168 1169#define SET_PACA(rX) \ 1170 BEGIN_FTR_SECTION_NESTED(66); \ 1171 mtspr SPRN_SPRG_PACA,rX; \ 1172 FTR_SECTION_ELSE_NESTED(66); \ 1173 mtspr SPRN_SPRG_HPACA,rX; \ 1174 ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_HVMODE, 66) 1175 1176#define GET_SCRATCH0(rX) \ 1177 BEGIN_FTR_SECTION_NESTED(66); \ 1178 mfspr rX,SPRN_SPRG_SCRATCH0; \ 1179 FTR_SECTION_ELSE_NESTED(66); \ 1180 mfspr rX,SPRN_SPRG_HSCRATCH0; \ 1181 ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_HVMODE, 66) 1182 1183#define SET_SCRATCH0(rX) \ 1184 BEGIN_FTR_SECTION_NESTED(66); \ 1185 mtspr SPRN_SPRG_SCRATCH0,rX; \ 1186 FTR_SECTION_ELSE_NESTED(66); \ 1187 mtspr SPRN_SPRG_HSCRATCH0,rX; \ 1188 ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_HVMODE, 66) 1189 1190#else /* CONFIG_PPC_BOOK3S_64 */ 1191#define GET_SCRATCH0(rX) mfspr rX,SPRN_SPRG_SCRATCH0 1192#define SET_SCRATCH0(rX) mtspr SPRN_SPRG_SCRATCH0,rX 1193 1194#endif 1195 1196#ifdef CONFIG_PPC_BOOK3E_64 1197#define SPRN_SPRG_MC_SCRATCH SPRN_SPRG8 1198#define SPRN_SPRG_CRIT_SCRATCH SPRN_SPRG3 1199#define SPRN_SPRG_DBG_SCRATCH SPRN_SPRG9 1200#define SPRN_SPRG_TLB_EXFRAME SPRN_SPRG2 1201#define SPRN_SPRG_TLB_SCRATCH SPRN_SPRG6 1202#define SPRN_SPRG_GEN_SCRATCH SPRN_SPRG0 1203#define SPRN_SPRG_GDBELL_SCRATCH SPRN_SPRG_GEN_SCRATCH 1204#define SPRN_SPRG_VDSO_READ SPRN_USPRG7 1205#define SPRN_SPRG_VDSO_WRITE SPRN_SPRG7 1206 1207#define SET_PACA(rX) mtspr SPRN_SPRG_PACA,rX 1208#define GET_PACA(rX) mfspr rX,SPRN_SPRG_PACA 1209 1210#endif 1211 1212#ifdef CONFIG_PPC_BOOK3S_32 1213#define SPRN_SPRG_SCRATCH0 SPRN_SPRG0 1214#define SPRN_SPRG_SCRATCH1 SPRN_SPRG1 1215#define SPRN_SPRG_SCRATCH2 SPRN_SPRG2 1216#define SPRN_SPRG_603_LRU SPRN_SPRG4 1217#endif 1218 1219#ifdef CONFIG_40x 1220#define SPRN_SPRG_SCRATCH0 SPRN_SPRG0 1221#define SPRN_SPRG_SCRATCH1 SPRN_SPRG1 1222#define SPRN_SPRG_SCRATCH2 SPRN_SPRG2 1223#define SPRN_SPRG_SCRATCH3 SPRN_SPRG4 1224#define SPRN_SPRG_SCRATCH4 SPRN_SPRG5 1225#define SPRN_SPRG_SCRATCH5 SPRN_SPRG6 1226#define SPRN_SPRG_SCRATCH6 SPRN_SPRG7 1227#endif 1228 1229#ifdef CONFIG_BOOKE 1230#define SPRN_SPRG_RSCRATCH0 SPRN_SPRG0 1231#define SPRN_SPRG_WSCRATCH0 SPRN_SPRG0 1232#define SPRN_SPRG_RSCRATCH1 SPRN_SPRG1 1233#define SPRN_SPRG_WSCRATCH1 SPRN_SPRG1 1234#define SPRN_SPRG_RSCRATCH_CRIT SPRN_SPRG2 1235#define SPRN_SPRG_WSCRATCH_CRIT SPRN_SPRG2 1236#define SPRN_SPRG_RSCRATCH2 SPRN_SPRG4R 1237#define SPRN_SPRG_WSCRATCH2 SPRN_SPRG4W 1238#define SPRN_SPRG_RSCRATCH3 SPRN_SPRG5R 1239#define SPRN_SPRG_WSCRATCH3 SPRN_SPRG5W 1240#define SPRN_SPRG_RSCRATCH_MC SPRN_SPRG1 1241#define SPRN_SPRG_WSCRATCH_MC SPRN_SPRG1 1242#define SPRN_SPRG_RSCRATCH4 SPRN_SPRG7R 1243#define SPRN_SPRG_WSCRATCH4 SPRN_SPRG7W 1244#define SPRN_SPRG_RSCRATCH_DBG SPRN_SPRG9 1245#define SPRN_SPRG_WSCRATCH_DBG SPRN_SPRG9 1246#endif 1247 1248#ifdef CONFIG_PPC_8xx 1249#define SPRN_SPRG_SCRATCH0 SPRN_SPRG0 1250#define SPRN_SPRG_SCRATCH1 SPRN_SPRG1 1251#define SPRN_SPRG_SCRATCH2 SPRN_SPRG2 1252#endif 1253 1254 1255 1256/* 1257 * An mtfsf instruction with the L bit set. On CPUs that support this a 1258 * full 64bits of FPSCR is restored and on other CPUs the L bit is ignored. 1259 * 1260 * Until binutils gets the new form of mtfsf, hardwire the instruction. 1261 */ 1262#ifdef CONFIG_PPC64 1263#define MTFSF_L(REG) \ 1264 .long (0xfc00058e | ((0xff) << 17) | ((REG) << 11) | (1 << 25)) 1265#else 1266#define MTFSF_L(REG) mtfsf 0xff, (REG) 1267#endif 1268 1269/* Processor Version Register (PVR) field extraction */ 1270 1271#define PVR_VER(pvr) (((pvr) >> 16) & 0xFFFF) /* Version field */ 1272#define PVR_REV(pvr) (((pvr) >> 0) & 0xFFFF) /* Revison field */ 1273 1274#define pvr_version_is(pvr) (PVR_VER(mfspr(SPRN_PVR)) == (pvr)) 1275 1276/* 1277 * IBM has further subdivided the standard PowerPC 16-bit version and 1278 * revision subfields of the PVR for the PowerPC 403s into the following: 1279 */ 1280 1281#define PVR_FAM(pvr) (((pvr) >> 20) & 0xFFF) /* Family field */ 1282#define PVR_MEM(pvr) (((pvr) >> 16) & 0xF) /* Member field */ 1283#define PVR_CORE(pvr) (((pvr) >> 12) & 0xF) /* Core field */ 1284#define PVR_CFG(pvr) (((pvr) >> 8) & 0xF) /* Configuration field */ 1285#define PVR_MAJ(pvr) (((pvr) >> 4) & 0xF) /* Major revision field */ 1286#define PVR_MIN(pvr) (((pvr) >> 0) & 0xF) /* Minor revision field */ 1287 1288/* Processor Version Numbers */ 1289 1290#define PVR_403GA 0x00200000 1291#define PVR_403GB 0x00200100 1292#define PVR_403GC 0x00200200 1293#define PVR_403GCX 0x00201400 1294#define PVR_405GP 0x40110000 1295#define PVR_476 0x11a52000 1296#define PVR_476FPE 0x7ff50000 1297#define PVR_STB03XXX 0x40310000 1298#define PVR_NP405H 0x41410000 1299#define PVR_NP405L 0x41610000 1300#define PVR_601 0x00010000 1301#define PVR_602 0x00050000 1302#define PVR_603 0x00030000 1303#define PVR_603e 0x00060000 1304#define PVR_603ev 0x00070000 1305#define PVR_603r 0x00071000 1306#define PVR_604 0x00040000 1307#define PVR_604e 0x00090000 1308#define PVR_604r 0x000A0000 1309#define PVR_620 0x00140000 1310#define PVR_740 0x00080000 1311#define PVR_750 PVR_740 1312#define PVR_740P 0x10080000 1313#define PVR_750P PVR_740P 1314#define PVR_7400 0x000C0000 1315#define PVR_7410 0x800C0000 1316#define PVR_7450 0x80000000 1317#define PVR_8540 0x80200000 1318#define PVR_8560 0x80200000 1319#define PVR_VER_E500V1 0x8020 1320#define PVR_VER_E500V2 0x8021 1321#define PVR_VER_E500MC 0x8023 1322#define PVR_VER_E5500 0x8024 1323#define PVR_VER_E6500 0x8040 1324#define PVR_VER_7450 0x8000 1325#define PVR_VER_7455 0x8001 1326#define PVR_VER_7447 0x8002 1327#define PVR_VER_7447A 0x8003 1328#define PVR_VER_7448 0x8004 1329 1330/* 1331 * For the 8xx processors, all of them report the same PVR family for 1332 * the PowerPC core. The various versions of these processors must be 1333 * differentiated by the version number in the Communication Processor 1334 * Module (CPM). 1335 */ 1336#define PVR_8xx 0x00500000 1337 1338#define PVR_8240 0x00810100 1339#define PVR_8245 0x80811014 1340#define PVR_8260 PVR_8240 1341 1342/* 476 Simulator seems to currently have the PVR of the 602... */ 1343#define PVR_476_ISS 0x00052000 1344 1345/* 64-bit processors */ 1346#define PVR_NORTHSTAR 0x0033 1347#define PVR_PULSAR 0x0034 1348#define PVR_POWER4 0x0035 1349#define PVR_ICESTAR 0x0036 1350#define PVR_SSTAR 0x0037 1351#define PVR_POWER4p 0x0038 1352#define PVR_970 0x0039 1353#define PVR_POWER5 0x003A 1354#define PVR_POWER5p 0x003B 1355#define PVR_970FX 0x003C 1356#define PVR_POWER6 0x003E 1357#define PVR_POWER7 0x003F 1358#define PVR_630 0x0040 1359#define PVR_630p 0x0041 1360#define PVR_970MP 0x0044 1361#define PVR_970GX 0x0045 1362#define PVR_POWER7p 0x004A 1363#define PVR_POWER8E 0x004B 1364#define PVR_POWER8NVL 0x004C 1365#define PVR_POWER8 0x004D 1366#define PVR_HX_C2000 0x0066 1367#define PVR_POWER9 0x004E 1368#define PVR_POWER10 0x0080 1369#define PVR_POWER11 0x0082 1370#define PVR_BE 0x0070 1371#define PVR_PA6T 0x0090 1372 1373/* "Logical" PVR values defined in PAPR, representing architecture levels */ 1374#define PVR_ARCH_204 0x0f000001 1375#define PVR_ARCH_205 0x0f000002 1376#define PVR_ARCH_206 0x0f000003 1377#define PVR_ARCH_206p 0x0f100003 1378#define PVR_ARCH_207 0x0f000004 1379#define PVR_ARCH_300 0x0f000005 1380#define PVR_ARCH_31 0x0f000006 1381#define PVR_ARCH_31_P11 0x0f000007 1382 1383/* Macros for setting and retrieving special purpose registers */ 1384#ifndef __ASSEMBLY__ 1385 1386#if defined(CONFIG_PPC64) || defined(__CHECKER__) 1387typedef struct { 1388 u32 val; 1389#ifdef CONFIG_PPC64 1390 u32 suffix; 1391#endif 1392} __packed ppc_inst_t; 1393#else 1394typedef u32 ppc_inst_t; 1395#endif 1396 1397#define mfmsr() ({unsigned long rval; \ 1398 asm volatile("mfmsr %0" : "=r" (rval) : \ 1399 : "memory"); rval;}) 1400#ifdef CONFIG_PPC_BOOK3S_64 1401#define __mtmsrd(v, l) asm volatile("mtmsrd %0," __stringify(l) \ 1402 : : "r" (v) : "memory") 1403#define mtmsr(v) __mtmsrd((v), 0) 1404#define __MTMSR "mtmsrd" 1405#else 1406#define mtmsr(v) asm volatile("mtmsr %0" : \ 1407 : "r" ((unsigned long)(v)) \ 1408 : "memory") 1409#define __mtmsrd(v, l) BUILD_BUG() 1410#define __MTMSR "mtmsr" 1411#endif 1412 1413static inline void mtmsr_isync(unsigned long val) 1414{ 1415 asm volatile(__MTMSR " %0; " ASM_FTR_IFCLR("isync", "nop", %1) : : 1416 "r" (val), "i" (CPU_FTR_ARCH_206) : "memory"); 1417} 1418 1419#define mfspr(rn) ({unsigned long rval; \ 1420 asm volatile("mfspr %0," __stringify(rn) \ 1421 : "=r" (rval)); rval;}) 1422#define mtspr(rn, v) asm volatile("mtspr " __stringify(rn) ",%0" : \ 1423 : "r" ((unsigned long)(v)) \ 1424 : "memory") 1425#define wrtspr(rn) asm volatile("mtspr " __stringify(rn) ",2" : : : "memory") 1426 1427static inline void wrtee(unsigned long val) 1428{ 1429 if (__builtin_constant_p(val)) 1430 asm volatile("wrteei %0" : : "i" ((val & MSR_EE) ? 1 : 0) : "memory"); 1431 else 1432 asm volatile("wrtee %0" : : "r" (val) : "memory"); 1433} 1434 1435extern unsigned long msr_check_and_set(unsigned long bits); 1436extern bool strict_msr_control; 1437extern void __msr_check_and_clear(unsigned long bits); 1438static inline void msr_check_and_clear(unsigned long bits) 1439{ 1440 if (strict_msr_control) 1441 __msr_check_and_clear(bits); 1442} 1443 1444#ifdef CONFIG_PPC32 1445static inline u32 mfsr(u32 idx) 1446{ 1447 u32 val; 1448 1449 if (__builtin_constant_p(idx)) 1450 asm volatile("mfsr %0, %1" : "=r" (val): "i" (idx >> 28)); 1451 else 1452 asm volatile("mfsrin %0, %1" : "=r" (val): "r" (idx)); 1453 1454 return val; 1455} 1456 1457static inline void mtsr(u32 val, u32 idx) 1458{ 1459 if (__builtin_constant_p(idx)) 1460 asm volatile("mtsr %1, %0" : : "r" (val), "i" (idx >> 28)); 1461 else 1462 asm volatile("mtsrin %0, %1" : : "r" (val), "r" (idx)); 1463} 1464#endif 1465 1466extern unsigned long current_stack_frame(void); 1467 1468register unsigned long current_stack_pointer asm("r1"); 1469 1470extern unsigned long scom970_read(unsigned int address); 1471extern void scom970_write(unsigned int address, unsigned long value); 1472 1473struct pt_regs; 1474 1475extern void ppc_save_regs(struct pt_regs *regs); 1476#endif /* __ASSEMBLY__ */ 1477#endif /* __KERNEL__ */ 1478#endif /* _ASM_POWERPC_REG_H */ 1479