/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.cpp | 216 for (auto Opcode : {ISD::ABS, ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX}) 269 setOperationAction(ISD::ABS, VT, Legal); 1489 setTargetDAGCombine(ISD::ABS); 3737 return DAG.getNode(ISD::ABS, SDLoc(Op), Op.getValueType(), 9467 case ISD::ABS: 10746 case ARM::ABS: 10748 // To insert an ABS instruction, we have to insert the 10754 // V1 = ABS V0 10758 // RSBBB: V3 = RSBri V2, 0 (compute ABS if V2 < 0) 10811 // reuse ABSDstReg to not change uses of ABS instructio [all...] |
H A D | ARMISelDAGToDAG.cpp | 280 // Select special operations if node forms integer ABS pattern 2961 /// which represent Integer ABS into: 2964 /// ARM::ABS or ARM::t2ABS machine node. 2987 unsigned Opcode = Subtarget->isThumb2() ? ARM::t2ABS : ARM::ABS; 3165 // Select special operations if XOR node forms integer ABS pattern
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCISelLowering.cpp | 706 setOperationAction(ISD::ABS, VT, Custom); 737 // But ABS custom lowering requires SMAX support. 739 setOperationAction(ISD::ABS, MVT::v2i64, Expand); 1207 setTargetDAGCombine(ISD::ABS); 10340 assert(Op.getOpcode() == ISD::ABS && "Should only be called for ISD::ABS"); 10505 case ISD::ABS: return LowerABS(Op, DAG); 14182 return DAG.getNode(ISD::ABS, dl, V2.getValueType(), V2); 14188 return DAG.getNode(ISD::ABS, dl, V1.getValueType(), V1); 14194 return DAG.getNode(ISD::ABS, d [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86ISelLowering.cpp | 202 setOperationAction(ISD::ABS , MVT::i16 , Custom); 203 setOperationAction(ISD::ABS , MVT::i32 , Custom); 205 setOperationAction(ISD::ABS , MVT::i64 , Custom); 931 setOperationAction(ISD::ABS, VT, Custom); 1053 setOperationAction(ISD::ABS, MVT::v16i8, Legal); 1054 setOperationAction(ISD::ABS, MVT::v8i16, Legal); 1055 setOperationAction(ISD::ABS, MVT::v4i32, Legal); 1283 setOperationAction(ISD::ABS, MVT::v4i64, Custom); 1299 setOperationAction(ISD::ABS, VT, HasInt256 ? Legal : Custom); 1563 setOperationAction(ISD::ABS, V [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
H A D | LegalizeIntegerTypes.cpp | 166 case ISD::ABS: Res = PromoteIntRes_ABS(N); break; 1135 return DAG.getNode(ISD::ABS, SDLoc(N), Op0.getValueType(), Op0); 1820 case ISD::ABS: ExpandIntRes_ABS(N, Lo, Hi); break;
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H A D | DAGCombiner.cpp | 1553 case ISD::ABS: return visitABS(N); 3216 if (TLI.isOperationLegalOrCustom(ISD::ABS, VT)) { 3224 return DAG.getNode(ISD::ABS, SDLoc(N), VT, S0); 7168 if (TLI.isOperationLegalOrCustom(ISD::ABS, VT)) { 7178 return DAG.getNode(ISD::ABS, DL, VT, S0); 8205 return DAG.getNode(ISD::ABS, SDLoc(N), VT, N0); 8207 if (N0.getOpcode() == ISD::ABS) 8908 if (TLI.isOperationLegalOrCustom(ISD::ABS, VT)) 8909 return DAG.getNode(ISD::ABS, DL, VT, LHS);
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H A D | SelectionDAGDumper.cpp | 392 case ISD::ABS: return "abs";
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H A D | SelectionDAGBuilder.cpp | 3366 Opc = ISD::ABS;
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H A D | SelectionDAG.cpp | 3314 case ISD::ABS: { 4416 case ISD::ABS: 4538 case ISD::ABS: 4698 case ISD::ABS: 4700 "Invalid ABS!");
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H A D | LegalizeVectorTypes.cpp | 71 case ISD::ABS: 865 case ISD::ABS: 2836 case ISD::ABS:
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H A D | LegalizeVectorOps.cpp | 392 case ISD::ABS: 884 case ISD::ABS:
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/freebsd-11-stable/contrib/ntp/ntpd/ |
H A D | refclock_parse.c | 237 #undef ABS macro 238 #define ABS(_X_) (((_X_) < 0) ? -(_X_) : (_X_)) macro 3409 parse->maxunsync = (u_long)ABS(in->fudgetime2); 4480 (long) ABS(antinfo.delta_t) / 10000, 4481 (long) ABS(antinfo.delta_t) % 10000);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
H A D | NVPTXISelLowering.cpp | 496 setOperationAction(ISD::ABS, Ty, Legal);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonISelLowering.cpp | 1390 setOperationAction(ISD::ABS, MVT::i32, Legal); 1391 setOperationAction(ISD::ABS, MVT::i64, Legal);
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H A D | HexagonBitSimplify.cpp | 2803 RegisterSet ABS; // Available registers for BS. 2805 Changed |= visitBlock(Entry, BitS, ABS);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | SIPeepholeSDWA.cpp | 346 Mods |= Abs ? SISrcMods::ABS : 0u;
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H A D | SIDefines.h | 183 ABS = 1 << 1, // Floating-point absolute modifier 185 NEG_HI = ABS, // Floating-point negate high packed component modifier.
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H A D | GCNDPPCombine.cpp | 199 assert(0LL == (Mod0->getImm() & ~(SISrcMods::ABS | SISrcMods::NEG))); 222 assert(0LL == (Mod1->getImm() & ~(SISrcMods::ABS | SISrcMods::NEG))); 496 const int64_t Mask = ~(SISrcMods::ABS | SISrcMods::NEG);
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H A D | AMDGPUInstructionSelector.cpp | 1887 Mods |= SISrcMods::ABS;
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H A D | AMDGPUISelDAGToDAG.cpp | 2407 Mods |= SISrcMods::ABS; 2584 if ((Mods & SISrcMods::ABS) == 0) { 2591 if ((ModsTmp & SISrcMods::ABS) != 0) 2592 Mods |= SISrcMods::ABS;
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/MCTargetDesc/ |
H A D | AMDGPUInstPrinter.cpp | 634 (InputModifiers & SISrcMods::ABS) == 0) { 645 if (InputModifiers & SISrcMods::ABS) 648 if (InputModifiers & SISrcMods::ABS)
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/AsmParser/ |
H A D | AMDGPUAsmParser.cpp | 106 Operand |= Abs ? SISrcMods::ABS : 0u;
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelLowering.cpp | 924 setOperationAction(ISD::ABS, VT, Legal); 2957 Result = DAG.getNode(ISD::ABS, dl, MVT::v1i64, Result); 2960 return DAG.getNode(ISD::ABS, dl, Ty, Op.getOperand(1));
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/MC/ |
H A D | MCDwarf.cpp | 300 MCSymbol *ABS = Context.createTempSymbol(); 301 OS.EmitAssignment(ABS, Expr); 302 return MCSymbolRefExpr::create(ABS, Context); 306 const MCExpr *ABS = forceExpAbs(OS, Value); local 307 OS.EmitValue(ABS, Size);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
H A D | TargetLoweringBase.cpp | 650 setOperationAction(ISD::ABS, VT, Expand);
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