Searched refs:zero (Results 1 - 25 of 47) sorted by path

12

/broadcom-cfe-1.4.2/cfe/applets/
H A Dminicrt0.S84 1: sw zero,0(t0)
/broadcom-cfe-1.4.2/cfe/arch/mips/board/bcm1250cpci/src/
H A Dcpu1test.S148 mtc0 zero,C0_COUNT
162 mtc0 zero,C0_COUNT
/broadcom-cfe-1.4.2/cfe/arch/mips/board/bcm91125e/src/
H A Dbcm91125e_init.S210 sd zero, R_MC_CS_START(t0)
211 sd zero, R_MC_CS_END(t0)
212 sd zero, R_MC_CS_INTERLEAVE(t0)
213 sd zero, R_MC_CS_ATTR(t0)
214 sd zero, R_MC_TEST_DATA(t0)
215 sd zero, R_MC_TEST_ECC(t0)
222 * to zero it.)
226 sd zero, R_MAC_ETHERNET_ADDR(t0)
325 sd zero,(t0)
/broadcom-cfe-1.4.2/cfe/arch/mips/board/bcm91125f/src/
H A Dbcm91125f_init.S198 sd zero, R_MC_CS_START(t0)
199 sd zero, R_MC_CS_END(t0)
200 sd zero, R_MC_CS_INTERLEAVE(t0)
201 sd zero, R_MC_CS_ATTR(t0)
202 sd zero, R_MC_TEST_DATA(t0)
203 sd zero, R_MC_TEST_ECC(t0)
210 * to zero it.)
214 sd zero, R_MAC_ETHERNET_ADDR(t0)
313 sd zero,(t0)
/broadcom-cfe-1.4.2/cfe/arch/mips/board/bcm91280e/src/
H A Dbcm91280e_init.S137 sd zero,(t0)
139 sd zero,(t0)
194 nor t1, zero, zero
261 sd zero, 0(t0) # disable half.
267 ld zero, 0(t0)
446 bne t1,zero,1b
H A Dcpu1test.S136 mtc0 zero,C0_COUNT
/broadcom-cfe-1.4.2/cfe/arch/mips/board/bcm91480b/src/
H A Dbcm91480b_init.S160 sd zero,(t0)
162 sd zero,(t0)
300 nor t1, zero, zero
367 sd zero, 0(t0) # disable half.
373 ld zero, 0(t0)
581 bne t1,zero,1b
H A Dcpu1test.S136 mtc0 zero,C0_COUNT
/broadcom-cfe-1.4.2/cfe/arch/mips/board/bcm91480ht/src/
H A Dbcm91480ht_init.S137 sd zero,(t0)
139 sd zero,(t0)
226 nor t1, zero, zero
421 bne t1,zero,1b
H A Dcpu1test.S135 mtc0 zero,C0_COUNT
/broadcom-cfe-1.4.2/cfe/arch/mips/board/lausanne/src/
H A Dcpu1test.S148 mtc0 zero,C0_COUNT
162 mtc0 zero,C0_COUNT
/broadcom-cfe-1.4.2/cfe/arch/mips/board/sentosa/src/
H A Dsentosa_init.S147 nor t1, zero, zero
/broadcom-cfe-1.4.2/cfe/arch/mips/board/swarm/src/
H A Dcpu1test.S150 mtc0 zero,C0_COUNT
164 mtc0 zero,C0_COUNT
H A Dswarm_init.S134 move t3, zero
395 move v0,zero # auto configure
/broadcom-cfe-1.4.2/cfe/arch/mips/board/vcs/src/
H A Dvcs_init.S119 move v0,zero
/broadcom-cfe-1.4.2/cfe/arch/mips/chipset/bcmsb/src/
H A Dsbmemc.S76 move v0,zero # auto configure
259 move pass_count,zero
260 move wrsum,zero
261 move rdsum,zero
262 move gsum,zero
274 beqz dll,szmem # If zero, leave the default values
284 sub wr,zero,dll # Negate dll as initial value
322 sub g,zero,dll
329 sub rd,zero,dll
342 div zero,wrsu
[all...]
/broadcom-cfe-1.4.2/cfe/arch/mips/chipset/sibyte/include/
H A Dsbmips.h182 #define zero $0 macro
628 /* define a zero-fill common block (BSS if not overridden) with a global name */
632 /* define a zero-fill common block (BSS if not overridden) with a local name */
/broadcom-cfe-1.4.2/cfe/arch/mips/chipset/sibyte/src/
H A Dsb1250_memcpy.S109 #define USE(x) lbu AT,x; xor zero, AT, zero
243 xor zero, AT, zero
244 xor zero, t0, zero
248 ADD zero, 1 # L1 NOP
249 xor zero, AT, zero
349 SUB mask, zero,
[all...]
/broadcom-cfe-1.4.2/cfe/arch/mips/common/include/
H A Dmipsmacros.h181 * this instruction in little-endian is: "bne zero,zero,.+0x44"
340 bne reg2,zero,1b ; \
343 beq reg2,zero,1b ; \
362 sw zero,0(reg1)
/broadcom-cfe-1.4.2/cfe/arch/mips/common/src/
H A Dapientry.S489 lw zero,0(t0)
501 * a0 - flags (CFE_CACHE_xxx flags, or zero for a default)
H A Ddev_flashop_engine.S114 * else less than zero, # of failing instructions
169 bgt reg_cnt,zero,1b
179 beq t0,zero,1f /* no odd byte to worry about */
194 1: beq reg_cnt,zero,nextinst
213 beq reg_cnt,zero,nextinst /* no straggler */
248 bgt reg_cnt,zero,1b
270 bgt reg_cnt,zero,1b
292 bgt reg_cnt,zero,1b
307 bgt reg_cnt,zero,1b
653 beq t0,zero,
[all...]
H A Dexception.S121 * from r0(zero) to store registers we need to use
127 SR k0,CFE_LOCORE_GLOBAL_K0TMP(zero)
128 SR k1,CFE_LOCORE_GLOBAL_K1TMP(zero)
129 SR ra,CFE_LOCORE_GLOBAL_RATMP(zero)
130 SR gp,CFE_LOCORE_GLOBAL_GPTMP(zero)
132 LR k0,CFE_LOCORE_GLOBAL_CERRH(zero)
136 LR k0,CFE_LOCORE_GLOBAL_K0TMP(zero)
137 LR k1,CFE_LOCORE_GLOBAL_K1TMP(zero)
138 LR ra,CFE_LOCORE_GLOBAL_RATMP(zero)
139 LR gp,CFE_LOCORE_GLOBAL_GPTMP(zero)
[all...]
H A Dinit_mips.S355 move gp,zero # start with no GP.
382 sll k0,k0,3 # k0 bits now zero
517 bne k0,zero,have_ram
699 bge t0,zero,1f # and second entry if high bit set
812 1: SR zero,0(v0) # Zero one cacheline at a time
813 SR zero,(REGSIZE*1)(v0)
814 SR zero,(REGSIZE*2)(v0)
815 SR zero,(REGSIZE*3)(v0)
896 move v0,zero
1079 move a1,zero # A
[all...]
H A Dinit_ram.S269 move a0,zero /* not relocating */
304 1: SR zero,0(v0) # Zero one cacheline at a time
305 SR zero,(REGSIZE*1)(v0)
306 SR zero,(REGSIZE*2)(v0)
307 SR zero,(REGSIZE*3)(v0)
330 SR zero,mem_datareloc
332 move v0,zero
345 SR zero,mem_textreloc
365 move a0,zero
468 move a1,zero # A
[all...]
H A Dlib_physio.S92 beq t0,zero,1f ; \

Completed in 95 milliseconds

12