Searched refs:writel_relaxed (Results 1 - 17 of 17) sorted by path

/u-boot/arch/arc/include/asm/
H A Dio.h172 #define writel_relaxed(v, c) ((void)__arch_putl((__force u32)cpu_to_le32(v), (c))) macro
194 #define writel(v, c) ({ __iowmb(); writel_relaxed(v, c); })
/u-boot/arch/arm/include/asm/
H A Dio.h127 #define writel_relaxed(v, c) ((void)__raw_writel((__force u32) \ macro
/u-boot/arch/arm/mach-sunxi/
H A Ddram_sun50i_h616.c54 writel_relaxed(cfg0, &mctl_com->master[port].cfg0);
55 writel_relaxed(cfg1, &mctl_com->master[port].cfg1);
266 writel_relaxed(MASK_BYTE(val_lo, 0), SUNXI_DRAM_PHY0_BASE + 0x388);
267 writel_relaxed(MASK_BYTE(val_hi, 0), SUNXI_DRAM_PHY0_BASE + 0x38c);
268 writel_relaxed(MASK_BYTE(val_lo, 1), SUNXI_DRAM_PHY0_BASE + 0x3c8);
269 writel_relaxed(MASK_BYTE(val_hi, 1), SUNXI_DRAM_PHY0_BASE + 0x3cc);
270 writel_relaxed(MASK_BYTE(val_lo, 2), SUNXI_DRAM_PHY0_BASE + 0x408);
271 writel_relaxed(MASK_BYTE(val_hi, 2), SUNXI_DRAM_PHY0_BASE + 0x40c);
272 writel_relaxed(MASK_BYTE(val_lo, 3), SUNXI_DRAM_PHY0_BASE + 0x448);
273 writel_relaxed(MASK_BYT
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/u-boot/arch/mips/include/asm/
H A Dio.h384 #define writel_relaxed writel macro
/u-boot/arch/riscv/include/asm/
H A Dio.h378 #define writel_relaxed(v, c) ({ __io_rbw(); writel_cpu((v), (c)); __io_raw(); }) macro
/u-boot/drivers/clk/imx/
H A Dclk-fracn-gppll.c236 writel_relaxed(tmp, pll->base + PLL_CTRL);
241 writel_relaxed(tmp, pll->base + PLL_CTRL);
245 writel_relaxed(tmp, pll->base + PLL_CTRL);
249 writel_relaxed(tmp, pll->base + PLL_CTRL);
253 writel_relaxed(pll_div, pll->base + PLL_DIV);
255 writel_relaxed(rate->mfd, pll->base + PLL_DENOMINATOR);
256 writel_relaxed(FIELD_PREP(PLL_MFN_MASK, rate->mfn), pll->base + PLL_NUMERATOR);
264 writel_relaxed(tmp, pll->base + PLL_CTRL);
273 writel_relaxed(tmp, pll->base + PLL_CTRL);
294 writel_relaxed(va
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/u-boot/drivers/memory/
H A Dti-gpmc.c63 writel_relaxed(val, gpmc_base + idx);
76 writel_relaxed(val, reg_addr);
/u-boot/drivers/mtd/nand/raw/atmel/
H A Dpmecc.c643 writel_relaxed(smu[(strength + 1) * num + i],
/u-boot/drivers/mtd/nand/raw/brcmnand/
H A Dbrcmnand.h53 writel_relaxed(val, addr);
/u-boot/drivers/net/
H A Dbcmgenet.c244 writel_relaxed(reg, priv->mac_reg + UMAC_MAC0);
247 writel_relaxed(reg, priv->mac_reg + UMAC_MAC1);
550 writel_relaxed(val, priv->mac_reg + MDIO_CMD);
568 writel_relaxed(val, priv->mac_reg + MDIO_CMD);
/u-boot/drivers/pci/
H A Dpcie_apple.c162 writel_relaxed(readl_relaxed(addr) | set, addr);
167 writel_relaxed(readl_relaxed(addr) & ~clr, addr);
315 writel_relaxed(PORT_LTSSMCTL_START, port->base + PORT_LTSSMCTL);
/u-boot/drivers/phy/qcom/
H A Dphy-qcom-snps-eusb2.c139 writel_relaxed(reg, base + offset);
H A Dphy-qcom-snps-femto-v2.c83 writel_relaxed(reg, base + offset);
/u-boot/drivers/rng/
H A Dmeson-rng.c84 writel_relaxed(readl_relaxed(cfg_addr) | SEED_READY_STS_BIT, cfg_addr);
H A Dstm32_rng.c99 writel_relaxed(cr | RNG_CR_CONDRST, pdata->base + RNG_CR);
100 writel_relaxed(cr & ~RNG_CR_CONDRST, pdata->base + RNG_CR);
103 writel_relaxed(sr & ~RNG_SR_SEIS, pdata->base + RNG_SR);
146 writel_relaxed(sr & ~RNG_SR_SEIS, pdata->base + RNG_SR);
198 writel_relaxed(0, pdata->base + RNG_SR);
279 writel_relaxed(pdata->data->htcr, pdata->base + RNG_HTCR);
280 writel_relaxed(pdata->data->nscr & RNG_NSCR_MASK, pdata->base + RNG_NSCR);
/u-boot/drivers/timer/
H A Dtegra-timer.c101 writel_relaxed(value | TEGRA_OSC_SET_CLK_ENB_TMR,
104 writel_relaxed(usec_config, TEGRA_TIMER_USEC_CFG);
/u-boot/drivers/usb/isp1760/
H A Disp1760-hcd.c488 writel_relaxed(*src, dst);
509 writel_relaxed(*src, dst);

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