1/* SPDX-License-Identifier: GPL-2.0+ */
2
3#ifndef __BRCMNAND_H__
4#define __BRCMNAND_H__
5
6#include <linux/types.h>
7#include <linux/io.h>
8
9struct brcmnand_soc {
10	bool (*ctlrdy_ack)(struct brcmnand_soc *soc);
11	void (*ctlrdy_set_enabled)(struct brcmnand_soc *soc, bool en);
12	void (*prepare_data_bus)(struct brcmnand_soc *soc, bool prepare,
13				 bool is_param);
14	void *ctrl;
15};
16
17static inline void brcmnand_soc_data_bus_prepare(struct brcmnand_soc *soc,
18						 bool is_param)
19{
20	if (soc && soc->prepare_data_bus)
21		soc->prepare_data_bus(soc, true, is_param);
22}
23
24static inline void brcmnand_soc_data_bus_unprepare(struct brcmnand_soc *soc,
25						   bool is_param)
26{
27	if (soc && soc->prepare_data_bus)
28		soc->prepare_data_bus(soc, false, is_param);
29}
30
31static inline u32 brcmnand_readl(void __iomem *addr)
32{
33	/*
34	 * MIPS endianness is configured by boot strap, which also reverses all
35	 * bus endianness (i.e., big-endian CPU + big endian bus ==> native
36	 * endian I/O).
37	 *
38	 * Other architectures (e.g., ARM) either do not support big endian, or
39	 * else leave I/O in little endian mode.
40	 */
41	if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_SYS_BIG_ENDIAN))
42		return __raw_readl(addr);
43	else
44		return readl_relaxed(addr);
45}
46
47static inline void brcmnand_writel(u32 val, void __iomem *addr)
48{
49	/* See brcmnand_readl() comments */
50	if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_SYS_BIG_ENDIAN))
51		__raw_writel(val, addr);
52	else
53		writel_relaxed(val, addr);
54}
55
56int brcmnand_probe(struct udevice *dev, struct brcmnand_soc *soc);
57int brcmnand_remove(struct udevice *dev);
58
59#ifndef __UBOOT__
60extern const struct dev_pm_ops brcmnand_pm_ops;
61#endif /* __UBOOT__ */
62
63#endif /* __BRCMNAND_H__ */
64