Searched refs:wptr (Results 1 - 25 of 137) sorted by relevance

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/linux-master/drivers/media/usb/pvrusb2/
H A Dpvrusb2-debugifc.c55 const char *wptr; local
60 wptr = NULL;
68 wptr = buf;
73 *wstrPtr = wptr;
182 const char *wptr; local
186 scnt = debugifc_isolate_word(buf,count,&wptr,&wlen);
189 if (!wptr) return 0;
191 pvr2_trace(PVR2_TRACE_DEBUGIFC,"debugifc cmd: \"%.*s\"",wlen,wptr);
192 if (debugifc_match_keyword(wptr,wlen,"reset")) {
193 scnt = debugifc_isolate_word(buf,count,&wptr,
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/linux-master/drivers/media/platform/amphion/
H A Dvpu_rpc.c39 ptr1 = desc->wptr;
43 ptr2 = desc->wptr;
61 u32 wptr; local
70 wptr = desc->wptr;
71 data = (u32 *)(shared->cmd_mem_vir + desc->wptr - desc->start);
76 wptr += 4;
78 if (wptr >= desc->end) {
79 wptr = desc->start;
85 wptr
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H A Dvpu_helpers.c271 u32 *wptr, u32 size, void *src)
278 if (!stream_buffer || !wptr || !src)
284 offset = *wptr;
298 *wptr = vpu_helper_step_walk(stream_buffer, offset, size);
304 u32 *wptr, u8 val, u32 size)
311 if (!stream_buffer || !wptr)
317 offset = *wptr;
335 *wptr = offset;
347 if (desc.rptr > desc.wptr)
348 return desc.rptr - desc.wptr;
270 vpu_helper_copy_to_stream_buffer(struct vpu_buffer *stream_buffer, u32 *wptr, u32 size, void *src) argument
303 vpu_helper_memset_stream_buffer(struct vpu_buffer *stream_buffer, u32 *wptr, u8 val, u32 size) argument
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H A Dvpu_malone.c187 u32 wptr; member in struct:vpu_malone_str_buffer
318 u32 wptr; member in struct:malone_scode_t
375 iface->cmd_buffer_desc.buffer.wptr = phy_addr;
383 iface->msg_buffer_desc.buffer.wptr =
427 iface->eng_access_buff_desc[i].buffer.wptr =
450 iface->debug_buffer_desc.buffer.wptr =
502 writel(buf->phys, &str_buf->wptr);
519 desc->wptr = readl(&str_buf->wptr);
528 static void vpu_malone_update_wptr(struct vpu_malone_str_buffer __iomem *str_buf, u32 wptr) argument
1057 u32 wptr; local
1533 u32 wptr = readl(&str_buf->wptr); local
1587 u32 wptr = readl(&str_buf->wptr); local
1659 u32 wptr = desc->wptr; local
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/linux-master/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_ih.c61 /* add 8 bytes for the rptr/wptr shadows and
124 /* add 8 bytes for the rptr/wptr shadows and
146 * Writes an IV to the ring buffer using the CPU and increment the wptr.
152 uint32_t wptr = le32_to_cpu(*ih->wptr_cpu) >> 2; local
156 ih->ring[wptr++] = cpu_to_le32(iv[i]);
158 wptr <<= 2;
159 wptr &= ih->ptr_mask;
161 /* Only commit the new wptr if we don't overflow */
162 if (wptr != READ_ONCE(ih->rptr)) {
164 WRITE_ONCE(*ih->wptr_cpu, cpu_to_le32(wptr));
211 u32 wptr; local
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H A Damdgpu_amdkfd_arcturus.h24 uint32_t __user *wptr, struct mm_struct *mm);
H A Dtonga_ih.c42 * host is currently reading, and a wptr (write pointer)
46 * wptr. When there is an interrupt, the host then starts
84 /* set rptr, wptr to 0 */
141 /* set rptr, wptr to 0 */
181 * tonga_ih_get_wptr - get the IH ring buffer wptr
184 * @ih: IH ring buffer to fetch wptr
186 * Get the IH ring buffer wptr from either the register
190 * Returns the value of the wptr.
195 u32 wptr, tmp; local
197 wptr
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H A Diceland_ih.c42 * host is currently reading, and a wptr (write pointer)
46 * wptr. When there is an interrupt, the host then starts
88 /* set rptr, wptr to 0 */
143 /* set rptr, wptr to 0 */
179 * iceland_ih_get_wptr - get the IH ring buffer wptr
182 * @ih: IH ring buffer to fetch wptr
184 * Get the IH ring buffer wptr from either the register
188 * Returns the value of the wptr.
193 u32 wptr, tmp; local
195 wptr
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H A Dcz_ih.c42 * host is currently reading, and a wptr (write pointer)
46 * wptr. When there is an interrupt, the host then starts
88 /* set rptr, wptr to 0 */
143 /* set rptr, wptr to 0 */
179 * cz_ih_get_wptr - get the IH ring buffer wptr
182 * @ih: IH ring buffer to fetch wptr
184 * Get the IH ring buffer wptr from either the register
188 * Returns the value of the wptr.
193 u32 wptr, tmp; local
195 wptr
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H A Dsi_ih.c110 u32 wptr, tmp; local
112 wptr = le32_to_cpu(*ih->wptr_cpu);
114 if (wptr & IH_RB_WPTR__RB_OVERFLOW_MASK) {
115 wptr &= ~IH_RB_WPTR__RB_OVERFLOW_MASK;
117 wptr, ih->rptr, (wptr + 16) & ih->ptr_mask);
118 ih->rptr = (wptr + 16) & ih->ptr_mask;
129 return (wptr & ih->ptr_mask);
H A Dcik_ih.c42 * host is currently reading, and a wptr (write pointer)
46 * wptr. When there is an interrupt, the host then starts
88 /* set rptr, wptr to 0 */
141 /* set rptr, wptr to 0 */
177 * cik_ih_get_wptr - get the IH ring buffer wptr
180 * @ih: IH ring buffer to fetch wptr
182 * Get the IH ring buffer wptr from either the register
186 * Returns the value of the wptr.
191 u32 wptr, tmp; local
193 wptr
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H A Dsdma_v4_4_2.c174 * Get the current wptr from the hardware.
179 u64 wptr; local
183 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs]));
184 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr);
186 wptr = RREG32_SDMA(ring->me, regSDMA_GFX_RB_WPTR_HI);
187 wptr = wptr << 32;
188 wptr |= RREG32_SDMA(ring->me, regSDMA_GFX_RB_WPTR);
189 DRM_DEBUG("wptr befor
248 u64 wptr; local
280 uint64_t wptr = ring->wptr << 2; local
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H A Damdgpu_vpe.c588 ret = ring->wptr & ring->buf_mask;
685 uint64_t wptr; local
688 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr);
689 dev_dbg(adev->dev, "wptr/doorbell before shift == 0x%016llx\n", wptr);
691 wptr = RREG32(vpe_get_reg_offset(vpe, ring->me, vpe->regs.queue0_rb_wptr_hi));
692 wptr = wptr << 32;
693 wptr |= RREG32(vpe_get_reg_offset(vpe, ring->me, vpe->regs.queue0_rb_wptr_lo));
694 dev_dbg(adev->dev, "wptr befor
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H A Dih_v6_0.c78 * force_update_wptr_for_self_int - Force update the wptr for self interrupt
81 * @threshold: threshold to trigger the wptr reporting
82 * @timeout: timeout to trigger the wptr reporting
90 * Force update wptr for self interrupt ( >= SIENNA_CICHLID).
152 /* set rptr, wptr to 0 */
273 /* set rptr, wptr to 0 */
355 /* enable wptr force update for self int */
381 * ih_v6_0_get_wptr - get the IH ring buffer wptr
386 * Get the IH ring buffer wptr from either the register
389 * Returns the value of the wptr
394 u32 wptr, tmp; local
496 uint32_t wptr = cpu_to_le32(entry->src_data[0]); local
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H A Dih_v6_1.c78 * force_update_wptr_for_self_int - Force update the wptr for self interrupt
81 * @threshold: threshold to trigger the wptr reporting
82 * @timeout: timeout to trigger the wptr reporting
90 * Force update wptr for self interrupt ( >= SIENNA_CICHLID).
152 /* set rptr, wptr to 0 */
273 /* set rptr, wptr to 0 */
355 /* enable wptr force update for self int */
381 * ih_v6_1_get_wptr - get the IH ring buffer wptr
386 * Get the IH ring buffer wptr from either the register
389 * Returns the value of the wptr
394 u32 wptr, tmp; local
497 uint32_t wptr = cpu_to_le32(entry->src_data[0]); local
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H A Dih_v7_0.c78 * force_update_wptr_for_self_int - Force update the wptr for self interrupt
81 * @threshold: threshold to trigger the wptr reporting
82 * @timeout: timeout to trigger the wptr reporting
90 * Force update wptr for self interrupt ( >= SIENNA_CICHLID).
152 /* set rptr, wptr to 0 */
273 /* set rptr, wptr to 0 */
355 /* enable wptr force update for self int */
381 * ih_v7_0_get_wptr() - get the IH ring buffer wptr
384 * @ih: IH ring buffer to fetch wptr
386 * Get the IH ring buffer wptr fro
394 u32 wptr, tmp; local
494 uint32_t wptr = cpu_to_le32(entry->src_data[0]); local
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/linux-master/drivers/gpu/drm/radeon/
H A Dradeon_ring.c41 * GPU is currently reading, and a wptr (write pointer)
45 * wptr. The GPU then starts fetching commands and executes
87 ring->ring_free_dw -= ring->wptr;
128 ring->wptr_old = ring->wptr;
164 * Update the wptr (write pointer) to tell the GPU to
176 while (ring->wptr & ring->align_mask) {
206 * radeon_ring_undo - reset the wptr
210 * Reset the driver's copy of the wptr (all asics).
214 ring->wptr = ring->wptr_old;
218 * radeon_ring_unlock_undo - reset the wptr an
470 uint32_t rptr, wptr, rptr_next; local
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/linux-master/drivers/gpu/drm/amd/amdkfd/
H A Dkfd_kernel_queue.c233 uint32_t wptr, rptr; local
237 /* When rptr == wptr, the buffer is empty.
238 * When rptr == wptr + 1, the buffer is full.
239 * It is always rptr that advances to the position of wptr, rather than
243 wptr = kq->pending_wptr;
249 pr_debug("wptr: %d\n", wptr);
252 available_size = (rptr + queue_size_dwords - 1 - wptr) %
263 if (wptr + packet_size_in_dwords >= queue_size_dwords) {
271 while (wptr >
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/linux-master/drivers/net/ppp/
H A Dbsd_comp.c580 unsigned char *wptr; local
586 if (wptr) \
588 *wptr++ = (unsigned char) (v); \
591 wptr = NULL; \
630 wptr = obuf;
639 if (wptr)
641 *wptr++ = PPP_ADDRESS(rptr);
642 *wptr++ = PPP_CONTROL(rptr);
643 *wptr++ = 0;
644 *wptr
843 unsigned char *wptr; local
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H A Dppp_deflate.c190 unsigned char *wptr; local
204 wptr = obuf;
209 wptr[0] = PPP_ADDRESS(rptr);
210 wptr[1] = PPP_CONTROL(rptr);
211 put_unaligned_be16(PPP_COMP, wptr + 2);
212 wptr += PPP_HDRLEN;
213 put_unaligned_be16(state->seqno, wptr);
214 wptr += DEFLATE_OVHD;
216 state->strm.next_out = wptr;
/linux-master/drivers/crypto/ccp/
H A Dtee-dev.c104 tee->rb_mgr.wptr = 0;
230 (tee->rb_mgr.ring_start + tee->rb_mgr.wptr);
237 if (!(tee->rb_mgr.wptr + sizeof(struct tee_ring_cmd) == rptr ||
241 dev_dbg(tee->dev, "tee: ring buffer full. rptr = %u wptr = %u\n",
242 rptr, tee->rb_mgr.wptr);
252 (tee->rb_mgr.wptr + sizeof(struct tee_ring_cmd) == rptr ||
254 dev_err(tee->dev, "tee: ring buffer full. rptr = %u wptr = %u response flag %u\n",
255 rptr, tee->rb_mgr.wptr, cmd->flag);
278 tee->rb_mgr.wptr += sizeof(struct tee_ring_cmd);
279 if (tee->rb_mgr.wptr >
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H A Dtee-dev.h43 * @wptr: index to the last written entry in ring buffer
50 u32 wptr; member in struct:ring_buf_manager
/linux-master/drivers/video/fbdev/
H A Dmaxinefb.c67 unsigned char *wptr; local
69 wptr = regs + 0xa0000 + (regno << 4);
71 *((volatile unsigned short *) (wptr)) = val;
/linux-master/drivers/net/ethernet/tehuti/
H A Dtehuti.c171 f->wptr = 0;
1101 rxfd = (struct rxf_desc *)(f->m.va + f->m.wptr);
1109 f->m.wptr += sizeof(struct rxf_desc);
1110 delta = f->m.wptr - f->m.memsz;
1112 f->m.wptr = delta;
1120 /*TBD: to do - delayed rxf wptr like in txd */
1121 WRITE_REG(priv, f->m.reg_WPTR, f->m.wptr & TXF_WPTR_WR_PTR);
1156 rxfd = (struct rxf_desc *)(f->m.va + f->m.wptr);
1164 f->m.wptr += sizeof(struct rxf_desc);
1165 delta = f->m.wptr
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/linux-master/drivers/gpu/drm/msm/adreno/
H A Da5xx_preempt.c39 /* Write the most recent wptr for the given ring into the hardware */
43 uint32_t wptr; local
49 wptr = get_wptr(ring);
52 gpu_write(gpu, REG_A5XX_CP_RB_WPTR, wptr);
112 * one do nothing except to update the wptr to the latest and greatest
133 /* Make sure the wptr doesn't update while we're in motion */
135 a5xx_gpu->preempt[ring->id]->wptr = get_wptr(ring);
207 a5xx_gpu->preempt[i]->wptr = 0;

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