amd/amdgpu/sdma_v4_4_2.c

174  * Get the current wptr from the hardware.
179 	u64 wptr;
183 		wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs]));
184 		DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr);
186 		wptr = RREG32_SDMA(ring->me, regSDMA_GFX_RB_WPTR_HI);
187 		wptr = wptr << 32;
188 		wptr |= RREG32_SDMA(ring->me, regSDMA_GFX_RB_WPTR);
189 		DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n",
190 				ring->me, wptr);
193 	return wptr >> 2;
201  * Write the wptr back to the hardware.
213 				"lower_32_bits(ring->wptr) << 2 == 0x%08x "
214 				"upper_32_bits(ring->wptr) << 2 == 0x%08x\n",
216 				lower_32_bits(ring->wptr << 2),
217 				upper_32_bits(ring->wptr << 2));
219 		WRITE_ONCE(*wb, (ring->wptr << 2));
221 				ring->doorbell_index, ring->wptr << 2);
222 		WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
228 				lower_32_bits(ring->wptr << 2),
230 				upper_32_bits(ring->wptr << 2));
232 			    lower_32_bits(ring->wptr << 2));
234 			    upper_32_bits(ring->wptr << 2));
243  * Get the current wptr from the hardware.
248 	u64 wptr;
252 		wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs]));
254 		wptr = RREG32_SDMA(ring->me, regSDMA_PAGE_RB_WPTR_HI);
255 		wptr = wptr << 32;
256 		wptr |= RREG32_SDMA(ring->me, regSDMA_PAGE_RB_WPTR);
259 	return wptr >> 2;
267  * Write the wptr back to the hardware.
277 		WRITE_ONCE(*wb, (ring->wptr << 2));
278 		WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
280 		uint64_t wptr = ring->wptr << 2;
283 			    lower_32_bits(wptr));
285 			    upper_32_bits(wptr));
320 	sdma_v4_4_2_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7);
647 	ring->wptr = 0;
649 	/* before programing wptr to a less value, need set minor_ptr_update first */
671 	/* set minor_ptr_update to 0 after wptr programed */
674 	/* setup the wptr shadow polling */
741 	ring->wptr = 0;
743 	/* before programing wptr to a less value, need set minor_ptr_update first */
760 	/* set minor_ptr_update to 0 after wptr programed */
763 	/* setup the wptr shadow polling */