amd/amdgpu/iceland_ih.c

42  * host is currently reading, and a wptr (write pointer)
46  * wptr.  When there is an interrupt, the host then starts
88 	/* set rptr, wptr to 0 */
143 	/* set rptr, wptr to 0 */
179  * iceland_ih_get_wptr - get the IH ring buffer wptr
182  * @ih: IH ring buffer to fetch wptr
184  * Get the IH ring buffer wptr from either the register
188  * Returns the value of the wptr.
193 	u32 wptr, tmp;
195 	wptr = le32_to_cpu(*ih->wptr_cpu);
197 	if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW))
201 	wptr = RREG32(mmIH_RB_WPTR);
203 	if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW))
206 	wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0);
208 	 * from the last not overwritten vector (wptr + 16). Hopefully
212 		wptr, ih->rptr, (wptr + 16) & ih->ptr_mask);
213 	ih->rptr = (wptr + 16) & ih->ptr_mask;
225 	return (wptr & ih->ptr_mask);
242 	/* wptr/rptr are in bytes! */
258 	/* wptr/rptr are in bytes! */