Searched refs:vce (Results 1 - 19 of 19) sorted by relevance

/linux-master/drivers/gpu/drm/radeon/
H A Dradeon_vce.c50 * radeon_vce_init - allocate memory, load vce firmware
65 INIT_DELAYED_WORK(&rdev->vce.idle_work, radeon_vce_idle_work_handler);
121 if (sscanf(c, "%2u]", &rdev->vce.fb_version) != 1)
125 start, mid, end, rdev->vce.fb_version);
127 rdev->vce.fw_version = (start << 24) | (mid << 16) | (end << 8);
130 if ((rdev->vce.fw_version != ((40 << 24) | (2 << 16) | (2 << 8))) &&
131 (rdev->vce.fw_version != ((50 << 24) | (0 << 16) | (1 << 8))) &&
132 (rdev->vce.fw_version != ((50 << 24) | (1 << 16) | (2 << 8))))
143 &rdev->vce.vcpu_bo);
149 r = radeon_bo_reserve(rdev->vce
[all...]
H A Dvce_v1_0.c33 #include "vce.h"
205 rdev->vce.keyselect = le32_to_cpu(sign->val[i].keyselect);
218 uint64_t addr = rdev->vce.gpu_addr;
254 WREG32(VCE_LMI_FW_START_KEYSEL, rdev->vce.keyselect);
H A Dvce_v2_0.c33 #include "vce.h"
160 uint64_t addr = rdev->vce.gpu_addr;
H A Dradeon_drv.c239 MODULE_PARM_DESC(vce, "vce enable/disable vce support (1 = enable, 0 = disable)");
240 module_param_named(vce, radeon_vce, int, 0444);
H A Dradeon_kms.c540 *value = rdev->vce.fw_version;
543 *value = rdev->vce.fb_version;
H A Dradeon.h1520 /* vce clocks */
1542 /* vce requirements */
2379 struct radeon_vce vce; member in struct:radeon_device
/linux-master/arch/s390/kernel/
H A Dcert_store.c127 struct vce { struct
178 static void pr_dbf_vce(const struct vce *e)
259 static int check_certificate_hash(const struct vce *vce) argument
265 vce_hash = (u8 *)vce + vce->vce_hdr.vc_hash_offset;
266 vc_hash_length = vce->vce_hdr.vc_hash_length;
267 sha256((u8 *)vce + vce->vce_hdr.vc_offset, vce
280 check_certificate_valid(const struct vce *vce) argument
428 get_key_description(struct vcssb *vcssb, const struct vce *vce) argument
453 create_key_from_vce(struct vcssb *vcssb, struct vce *vce, struct key *keyring) argument
523 extract_vce_from_sevcb(struct vcb *vcb, struct vce *vce) argument
575 struct vce *vce; local
[all...]
/linux-master/drivers/gpu/drm/amd/amdgpu/
H A Dvce_v4_0.c37 #include "vce/vce_4_0_offset.h"
38 #include "vce/vce_4_0_default.h"
39 #include "vce/vce_4_0_sh_mask.h"
43 #include "ivsrcid/vce/irqsrcs_vce_4_0.h"
179 WDOORBELL32(adev->vce.ring[0].doorbell_index, 0);
180 *adev->vce.ring[0].wptr_cpu_addr = 0;
181 adev->vce.ring[0].wptr = 0;
182 adev->vce.ring[0].wptr_old = 0;
233 ring = &adev->vce.ring[0];
263 adev->vce
[all...]
H A Damdgpu_vce.c91 * amdgpu_vce_sw_init - allocate memory, load vce firmware
161 r = amdgpu_ucode_request(adev, &adev->vce.fw, fw_name);
165 amdgpu_ucode_release(&adev->vce.fw);
169 hdr = (const struct common_firmware_header *)adev->vce.fw->data;
177 adev->vce.fw_version = ((version_major << 24) | (version_minor << 16) |
183 &adev->vce.vcpu_bo,
184 &adev->vce.gpu_addr, &adev->vce.cpu_addr);
191 atomic_set(&adev->vce.handles[i], 0);
192 adev->vce
[all...]
H A Dvce_v3_0.c33 #include "vce/vce_3_0_d.h"
34 #include "vce/vce_3_0_sh_mask.h"
83 if (adev->vce.harvest_config == 0 ||
84 adev->vce.harvest_config == AMDGPU_VCE_HARVEST_VCE1)
86 else if (adev->vce.harvest_config == AMDGPU_VCE_HARVEST_VCE0)
115 if (adev->vce.harvest_config == 0 ||
116 adev->vce.harvest_config == AMDGPU_VCE_HARVEST_VCE1)
118 else if (adev->vce.harvest_config == AMDGPU_VCE_HARVEST_VCE0)
146 if (adev->vce.harvest_config == 0 ||
147 adev->vce
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H A Dvce_v2_0.c33 #include "vce/vce_2_0_d.h"
34 #include "vce/vce_2_0_sh_mask.h"
183 WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR, (adev->vce.gpu_addr >> 8));
243 ring = &adev->vce.ring[0];
250 ring = &adev->vce.ring[1];
281 DRM_INFO("vce is not idle \n");
405 adev->vce.num_rings = 2;
420 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 167, &adev->vce.irq);
433 for (i = 0; i < adev->vce.num_rings; i++) {
436 ring = &adev->vce
[all...]
H A Damdgpu_kms.c247 fw_info->ver = adev->vce.fw_version;
248 fw_info->feature = adev->vce.fb_version;
455 for (i = 0; i < adev->vce.num_rings; i++)
456 if (adev->vce.ring[i].sched.ready)
900 if (adev->vce.fw_version &&
901 adev->vce.fw_version < AMDGPU_VCE_FW_53_45)
924 dev_info->vce_harvest_config = adev->vce.harvest_config;
H A Damdgpu_virt.c507 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_VCE, adev->vce.fw_version);
H A Damdgpu_ucode.c712 FW_VERSION_ATTR(vce_fw_version, 0444, vce.fw_version);
H A Damdgpu.h1000 /* vce */
1001 struct amdgpu_vce vce; member in struct:amdgpu_device
/linux-master/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dsmu8_hwmgr.h134 uint32_t vce : 1; member in struct:pp_disable_nb_ps_flags::__anon693::__anon694
H A Dsmu10_hwmgr.h111 uint32_t vce : 1; member in struct:pp_disable_nbpslo_flags::__anon485::__anon486
/linux-master/drivers/scsi/qla2xxx/
H A Dqla_isr.c2858 struct vp_ctrl_entry_24xx *vce)
2864 sp = qla2x00_get_sp_from_handle(vha, func, req, vce);
2868 if (vce->entry_status != 0) {
2871 sp->name, vce->entry_status);
2873 } else if (vce->comp_status != cpu_to_le16(CS_COMPLETE)) {
2876 sp->name, le16_to_cpu(vce->comp_status),
2877 le16_to_cpu(vce->vp_idx_failed));
2857 qla_ctrlvp_completed(scsi_qla_host_t *vha, struct req_que *req, struct vp_ctrl_entry_24xx *vce) argument
H A Dqla_iocb.c3815 qla25xx_ctrlvp_iocb(srb_t *sp, struct vp_ctrl_entry_24xx *vce) argument
3819 vce->entry_type = VP_CTRL_IOCB_TYPE;
3820 vce->handle = sp->handle;
3821 vce->entry_count = 1;
3822 vce->command = cpu_to_le16(sp->u.iocb_cmd.u.ctrlvp.cmd);
3823 vce->vp_count = cpu_to_le16(1);
3831 vce->vp_idx_map[map] |= 1 << pos;

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