H A D | amd64_edac.c | 1082 if (!(pvt->umc[i].sdp_ctrl & UMC_SDP_INIT)) 1088 if (pvt->umc[i].umc_cfg & BIT(12)) 1267 static int umc_addr_mask_to_cs_size(struct amd64_pvt *pvt, u8 umc, argument 1311 addr_mask_orig = pvt->csels[umc].csmasks_sec[cs_mask_nr]; 1313 addr_mask_orig = pvt->csels[umc].csmasks[cs_mask_nr]; 1341 struct amd64_umc *umc; local 1346 umc = &pvt->umc[i]; 1348 edac_dbg(1, "UMC%d DIMM cfg: 0x%x\n", i, umc->dimm_cfg); 1349 edac_dbg(1, "UMC%d UMC cfg: 0x%x\n", i, umc 1438 int umc; local 1454 int cs, umc; local 1545 struct amd64_umc *umc; local 2910 struct amd64_umc *umc; local 3070 u8 umc, cs; local 3363 struct amd64_umc *umc; local 3523 gpu_addr_mask_to_cs_size(struct amd64_pvt *pvt, u8 umc, unsigned int cs_mode, int csrow_nr) argument 3547 struct amd64_umc *umc; local 3580 u8 umc, cs; local 3623 gpu_get_umc_base(struct amd64_pvt *pvt, u8 umc, u8 channel) argument 3651 struct amd64_umc *umc; local 3669 int umc, cs; local 3694 int umc; local [all...] |