Searched refs:umc (Results 1 - 20 of 20) sorted by relevance

/linux-master/drivers/ras/amd/atl/
H A DMakefile16 amd_atl-y += umc.o
/linux-master/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_umc.c57 kcalloc(adev->umc.max_ras_err_cnt_per_query,
61 "Failed to alloc memory for umc error record in MCA notifier!\n");
104 if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops &&
105 adev->umc.ras->ras_block.hw_ops->query_ras_error_count)
106 adev->umc.ras->ras_block.hw_ops->query_ras_error_count(adev, ras_error_status);
108 if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops &&
109 adev->umc.ras->ras_block.hw_ops->query_ras_error_address &&
110 adev->umc
[all...]
H A Damdgpu_umc.h45 #define LOOP_UMC_INST(umc_inst) for ((umc_inst) = 0; (umc_inst) < adev->umc.umc_inst_num; (umc_inst)++)
46 #define LOOP_UMC_CH_INST(ch_inst) for ((ch_inst) = 0; (ch_inst) < adev->umc.channel_inst_num; (ch_inst)++)
50 for_each_set_bit((node_inst), &(adev->umc.active_mask), adev->umc.node_inst_num)
80 /* number of umc channel instance with memory map register access */
82 /* number of umc instance with memory map register access */
85 /* Total number of umc node instance including harvest one */
99 /* active mask for umc node instance */
H A Dumc_v8_10.c27 #include "umc/umc_8_10_0_offset.h"
28 #include "umc/umc_8_10_0_sh_mask.h"
75 return adev->umc.channel_offs * ch_inst + UMC_8_INST_DIST * umc_inst +
216 adev->umc.channel_idx_tbl[node_inst * adev->umc.umc_inst_num *
217 adev->umc.channel_inst_num +
218 umc_inst * adev->umc.channel_inst_num +
234 dev_err(adev->dev, "Failed to map pa from umc na.\n");
263 /* clear umc status */
281 /* clear umc statu
[all...]
H A Dumc_v6_7.c28 #include "umc/umc_6_7_0_offset.h"
29 #include "umc/umc_6_7_0_sh_mask.h"
50 uint32_t index = umc_inst * adev->umc.channel_inst_num + ch_inst;
52 /* adjust umc and channel index offset,
53 * the register address is not linear on each umc instace */
57 return adev->umc.channel_offs * ch_inst + UMC_V6_7_INST_DIST * umc_inst;
106 eccinfo_table_idx = umc_inst * adev->umc.channel_inst_num + ch_inst;
119 adev->umc.channel_idx_tbl[umc_inst * adev->umc.channel_inst_num + ch_inst];
123 /* translate umc channe
[all...]
H A Dgmc_v9_0.c46 #include "umc/umc_6_0_sh_mask.h"
1410 adev->umc.funcs = &umc_v6_0_funcs;
1413 adev->umc.max_ras_err_cnt_per_query = UMC_V6_1_TOTAL_CHANNEL_NUM;
1414 adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM;
1415 adev->umc.umc_inst_num = UMC_V6_1_UMC_INSTANCE_NUM;
1416 adev->umc.channel_offs = UMC_V6_1_PER_CHANNEL_OFFSET_VG20;
1417 adev->umc.retire_unit = 1;
1418 adev->umc.channel_idx_tbl = &umc_v6_1_channel_idx_tbl[0][0];
1419 adev->umc.ras = &umc_v6_1_ras;
1422 adev->umc
[all...]
H A Dumc_v8_7.c30 #include "umc/umc_8_7_0_offset.h"
31 #include "umc/umc_8_7_0_sh_mask.h"
47 return adev->umc.channel_offs*ch_inst + UMC_8_INST_DIST*umc_inst;
58 eccinfo_table_idx = umc_inst * adev->umc.channel_inst_num + ch_inst;
77 eccinfo_table_idx = umc_inst * adev->umc.channel_inst_num + ch_inst;
119 adev->umc.channel_idx_tbl[umc_inst * adev->umc.channel_inst_num + ch_inst];
121 /* translate umc channel address to soc pa, 3 parts are included */
139 eccinfo_table_idx = umc_inst * adev->umc.channel_inst_num + ch_inst;
345 /* clear umc statu
[all...]
H A Dgmc_v11_0.c550 adev->umc.channel_inst_num = UMC_V8_10_CHANNEL_INSTANCE_NUM;
551 adev->umc.umc_inst_num = UMC_V8_10_UMC_INSTANCE_NUM;
552 adev->umc.max_ras_err_cnt_per_query = UMC_V8_10_TOTAL_CHANNEL_NUM(adev);
553 adev->umc.channel_offs = UMC_V8_10_PER_CHANNEL_OFFSET;
554 adev->umc.retire_unit = UMC_V8_10_NA_COL_2BITS_POWER_OF_2_NUM;
555 if (adev->umc.node_inst_num == 4)
556 adev->umc.channel_idx_tbl = &umc_v8_10_channel_idx_tbl_ext0[0][0][0];
558 adev->umc.channel_idx_tbl = &umc_v8_10_channel_idx_tbl[0][0][0];
559 adev->umc.ras = &umc_v8_10_ras;
924 if (adev->umc
[all...]
H A Dgmc_v10_0.c586 adev->umc.max_ras_err_cnt_per_query = UMC_V8_7_TOTAL_CHANNEL_NUM;
587 adev->umc.channel_inst_num = UMC_V8_7_CHANNEL_INSTANCE_NUM;
588 adev->umc.umc_inst_num = UMC_V8_7_UMC_INSTANCE_NUM;
589 adev->umc.channel_offs = UMC_V8_7_PER_CHANNEL_OFFSET_SIENNA;
590 adev->umc.retire_unit = 1;
591 adev->umc.channel_idx_tbl = &umc_v8_7_channel_idx_tbl[0][0];
592 adev->umc.ras = &umc_v8_7_ras;
1015 if (adev->umc.funcs && adev->umc.funcs->init_registers)
1016 adev->umc
[all...]
H A Dumc_v12_0.c27 #include "umc/umc_12_0_0_offset.h"
28 #include "umc/umc_12_0_0_sh_mask.h"
58 uint32_t index = umc_inst * adev->umc.channel_inst_num + ch_inst;
64 return adev->umc.channel_offs * ch_inst + UMC_V12_0_INST_DIST * umc_inst +
162 /* NOTE: node_inst is converted by adev->umc.active_mask and the range is [0-3],
251 adev->umc.channel_idx_tbl[node_inst * adev->umc.umc_inst_num *
252 adev->umc.channel_inst_num +
253 umc_inst * adev->umc.channel_inst_num +
255 /* translate umc channe
[all...]
H A Dumc_v6_1.c30 #include "umc/umc_6_1_1_offset.h"
31 #include "umc/umc_6_1_1_sh_mask.h"
32 #include "umc/umc_6_1_2_offset.h"
91 return adev->umc.channel_offs*ch_inst + UMC_6_INST_DIST*umc_inst;
303 uint32_t channel_index = adev->umc.channel_idx_tbl[umc_inst * adev->umc.channel_inst_num + ch_inst];
325 /* clear umc status */
340 /* translate umc channel address to soc pa, 3 parts are included */
349 /* clear umc status */
H A Damdgpu_ras.c60 "umc",
439 * The block is one of: umc, sdma, gfx, etc.
455 * echo inject umc ue 0x0 0x0 0x0 > /sys/kernel/debug/dri/0/ras/ras_ctrl
456 * echo inject umc ce 0 0 0 3 > /sys/kernel/debug/dri/0/ras/ras_ctrl
457 * echo disable umc > /sys/kernel/debug/dri/0/ras/ras_ctrl
465 * /sys/class/drm/card[0/1/2...]/device/ras/[gfx|sdma|umc|...]_err_count
520 /* umc ce/ue error injection for a bad page is not allowed */
1024 if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops &&
1025 adev->umc
[all...]
H A Damdgpu_mca.c27 #include "umc/umc_6_7_0_offset.h"
28 #include "umc/umc_6_7_0_sh_mask.h"
33 if (adev->umc.ras->check_ecc_err_status)
34 return adev->umc.ras->check_ecc_err_status(adev,
H A Damdgpu_ras_eeprom.c426 if (adev->umc.ras &&
427 adev->umc.ras->set_eeprom_table_version)
428 adev->umc.ras->set_eeprom_table_version(hdr);
H A Damdgpu_discovery.c680 adev->umc.active_mask = ((1 << adev->umc.node_inst_num) - 1) &
1334 adev->umc.node_inst_num++;
H A Damdgpu.h1032 struct amdgpu_umc umc; member in struct:amdgpu_device
/linux-master/drivers/edac/
H A Damd64_edac.c1082 if (!(pvt->umc[i].sdp_ctrl & UMC_SDP_INIT))
1088 if (pvt->umc[i].umc_cfg & BIT(12))
1267 static int umc_addr_mask_to_cs_size(struct amd64_pvt *pvt, u8 umc, argument
1311 addr_mask_orig = pvt->csels[umc].csmasks_sec[cs_mask_nr];
1313 addr_mask_orig = pvt->csels[umc].csmasks[cs_mask_nr];
1341 struct amd64_umc *umc; local
1346 umc = &pvt->umc[i];
1348 edac_dbg(1, "UMC%d DIMM cfg: 0x%x\n", i, umc->dimm_cfg);
1349 edac_dbg(1, "UMC%d UMC cfg: 0x%x\n", i, umc
1438 int umc; local
1454 int cs, umc; local
1545 struct amd64_umc *umc; local
2910 struct amd64_umc *umc; local
3070 u8 umc, cs; local
3363 struct amd64_umc *umc; local
3523 gpu_addr_mask_to_cs_size(struct amd64_pvt *pvt, u8 umc, unsigned int cs_mode, int csrow_nr) argument
3547 struct amd64_umc *umc; local
3580 u8 umc, cs; local
3623 gpu_get_umc_base(struct amd64_pvt *pvt, u8 umc, u8 channel) argument
3651 struct amd64_umc *umc; local
3669 int umc, cs; local
3694 int umc; local
[all...]
H A Damd64_edac.h387 struct amd64_umc *umc; /* UMC registers */ member in struct:amd64_pvt
/linux-master/arch/x86/kernel/cpu/
H A DMakefile45 obj-$(CONFIG_CPU_SUP_UMC_32) += umc.o
/linux-master/drivers/scsi/
H A Dmegaraid.c3500 megacmd_t __user *umc; local
3520 umc = MBOX_P(uiocp);
3522 if (get_user(upthru, (mega_passthru __user * __user *)&umc->xferaddr))
3537 umc = (megacmd_t __user *)uioc_mimd->mbox;
3539 if (get_user(upthru, (mega_passthru __user * __user *)&umc->xferaddr))

Completed in 232 milliseconds