Searched refs:timing (Results 1 - 25 of 317) sorted by relevance

1234567891011>>

/linux-master/drivers/gpu/drm/tegra/
H A Dmipi-phy.c16 int mipi_dphy_timing_get_default(struct mipi_dphy_timing *timing, argument
19 timing->clkmiss = 0;
20 timing->clkpost = 70 + 52 * period;
21 timing->clkpre = 8;
22 timing->clkprepare = 65;
23 timing->clksettle = 95;
24 timing->clktermen = 0;
25 timing->clktrail = 80;
26 timing->clkzero = 260;
27 timing
62 mipi_dphy_timing_validate(struct mipi_dphy_timing *timing, unsigned long period) argument
[all...]
H A Dmipi-phy.h10 * D-PHY timing parameters
43 int mipi_dphy_timing_get_default(struct mipi_dphy_timing *timing,
45 int mipi_dphy_timing_validate(struct mipi_dphy_timing *timing,
/linux-master/drivers/gpu/drm/amd/display/dc/link/
H A Dlink_validation.c27 * This file owns timing validation against various link limitations. (ex.
38 static uint32_t get_tmds_output_pixel_clock_100hz(const struct dc_crtc_timing *timing) argument
41 uint32_t pxl_clk = timing->pix_clk_100hz;
43 if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
45 else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
48 if (timing->display_color_depth == COLOR_DEPTH_101010)
50 else if (timing->display_color_depth == COLOR_DEPTH_121212)
57 const struct dc_crtc_timing *timing,
66 if (timing->pixel_encoding == PIXEL_ENCODING_RGB)
77 switch (timing
56 dp_active_dongle_validate_timing( const struct dc_crtc_timing *timing, const struct dpcd_caps *dpcd_caps) argument
258 dp_validate_mode_timing( struct dc_link *link, const struct dc_crtc_timing *timing) argument
309 link_validate_mode_timing( const struct dc_stream_state *stream, struct dc_link *link, const struct dc_crtc_timing *timing) argument
[all...]
H A Dlink_validation.h32 const struct dc_crtc_timing *timing);
/linux-master/drivers/gpu/drm/msm/dsi/phy/
H A Ddsi_phy.c28 static void dsi_dphy_timing_calc_clk_zero(struct msm_dsi_dphy_timing *timing, argument
35 temp = 300 * coeff - ((timing->clk_prepare >> 1) + 1) * 2 * ui;
46 temp = (timing->hs_rqst + timing->clk_prepare + clk_z) & 0x7;
47 timing->clk_zero = clk_z + 8 - temp;
50 int msm_dsi_dphy_timing_calc(struct msm_dsi_dphy_timing *timing, argument
72 timing->clk_prepare = linear_inter(tmax, tmin, pcnt0, 0, true);
76 timing->hs_rqst = temp;
78 timing->hs_rqst = max_t(s32, 0, temp - 2);
81 dsi_dphy_timing_calc_clk_zero(timing, u
145 msm_dsi_dphy_timing_calc_v2(struct msm_dsi_dphy_timing *timing, struct msm_dsi_phy_clk_request *clk_req) argument
261 msm_dsi_dphy_timing_calc_v3(struct msm_dsi_dphy_timing *timing, struct msm_dsi_phy_clk_request *clk_req) argument
371 msm_dsi_dphy_timing_calc_v4(struct msm_dsi_dphy_timing *timing, struct msm_dsi_phy_clk_request *clk_req) argument
469 msm_dsi_cphy_timing_calc_v4(struct msm_dsi_dphy_timing *timing, struct msm_dsi_phy_clk_request *clk_req) argument
[all...]
H A Ddsi_phy_20nm.c11 struct msm_dsi_dphy_timing *timing)
16 DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO(timing->clk_zero));
18 DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL(timing->clk_trail));
20 DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE(timing->clk_prepare));
21 if (timing->clk_zero & BIT(8))
25 DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT(timing->hs_exit));
27 DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO(timing->hs_zero));
29 DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE(timing->hs_prepare));
31 DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL(timing->hs_trail));
33 DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST(timing
10 dsi_20nm_dphy_set_timing(struct msm_dsi_phy *phy, struct msm_dsi_dphy_timing *timing) argument
70 struct msm_dsi_dphy_timing *timing = &phy->timing; local
[all...]
H A Ddsi_phy.h111 struct msm_dsi_dphy_timing timing; member in struct:msm_dsi_phy
130 int msm_dsi_dphy_timing_calc(struct msm_dsi_dphy_timing *timing,
132 int msm_dsi_dphy_timing_calc_v2(struct msm_dsi_dphy_timing *timing,
134 int msm_dsi_dphy_timing_calc_v3(struct msm_dsi_dphy_timing *timing,
136 int msm_dsi_dphy_timing_calc_v4(struct msm_dsi_dphy_timing *timing,
138 int msm_dsi_cphy_timing_calc_v4(struct msm_dsi_dphy_timing *timing,
/linux-master/drivers/gpu/drm/sti/
H A Dsti_awg_utils.c122 struct awg_timing *timing)
127 if (timing->trailing_pixels > 0) {
129 val = timing->blanking_level;
132 val = timing->trailing_pixels - 1 + AWG_DELAY;
137 val = timing->blanking_level;
138 ret |= awg_generate_instr((timing->trailing_pixels > 0) ? SET : RPLSET,
141 if (timing->blanking_pixels > 0) {
143 val = timing->active_pixels - 1;
147 val = timing->blanking_level;
156 struct awg_timing *timing)
120 awg_generate_line_signal( struct awg_code_generation_params *fwparams, struct awg_timing *timing) argument
154 sti_awg_generate_code_data_enable_mode( struct awg_code_generation_params *fwparams, struct awg_timing *timing) argument
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/optc/dcn201/
H A Ddcn201_optc.c42 bool optc201_is_two_pixels_per_containter(const struct dc_crtc_timing *timing) argument
44 return optc1_is_two_pixels_per_containter(timing);
76 const struct dc_crtc_timing *timing)
83 ASSERT(timing != NULL);
85 v_blank = (timing->v_total - timing->v_addressable -
86 timing->v_border_top - timing->v_border_bottom);
88 h_blank = (timing->h_total - timing
74 optc201_validate_timing( struct timing_generator *optc, const struct dc_crtc_timing *timing) argument
[all...]
/linux-master/drivers/clk/tegra/
H A Dclk-tegra124-emc.c48 * When we change the timing to a timing with a parent that has the same
50 * timing that has a different clock source.
120 struct emc_timing *timing = NULL; local
136 timing = tegra->timings + i;
138 if (timing->rate < req->rate && i != t - 1)
141 if (timing->rate > req->max_rate) {
147 if (timing->rate < req->min_rate)
150 req->rate = timing->rate;
154 if (timing) {
209 emc_set_timing(struct tegra_clk_emc *tegra, struct emc_timing *timing) argument
294 struct emc_timing *timing; local
325 struct emc_timing *timing = NULL; local
386 load_one_timing_from_dt(struct tegra_clk_emc *tegra, struct emc_timing *timing, struct device_node *node) argument
462 struct emc_timing *timing = timings_ptr + (i++); local
[all...]
/linux-master/drivers/leds/
H A Dleds-expresswire.c19 usleep_range(props->timing.poweroff_us, props->timing.poweroff_us * 2);
26 udelay(props->timing.detect_delay_us);
28 udelay(props->timing.detect_us);
36 udelay(props->timing.data_start_us);
43 udelay(props->timing.end_of_data_low_us);
45 udelay(props->timing.end_of_data_high_us);
53 udelay(props->timing.short_bitset_us);
55 udelay(props->timing.long_bitset_us);
58 udelay(props->timing
[all...]
/linux-master/drivers/gpu/drm/nouveau/nvkm/subdev/bios/
H A Dtiming.c26 #include <subdev/bios/timing.h>
33 u32 timing = 0; local
37 timing = nvbios_rd32(bios, bit_P.offset + 4);
40 timing = nvbios_rd32(bios, bit_P.offset + 8);
42 if (timing) {
43 *ver = nvbios_rd08(bios, timing + 0);
46 *hdr = nvbios_rd08(bios, timing + 1);
47 *cnt = nvbios_rd08(bios, timing + 2);
48 *len = nvbios_rd08(bios, timing + 3);
51 return timing;
73 u32 timing = nvbios_timingTe(bios, ver, hdr, cnt, len, &snr, &ssz); local
[all...]
/linux-master/drivers/gpu/drm/msm/disp/dpu1/
H A Ddpu_encoder_phys_vid.c45 struct dpu_hw_intf_timing_params *timing)
47 memset(timing, 0, sizeof(*timing));
74 timing->width = mode->hdisplay; /* active width */
75 timing->height = mode->vdisplay; /* active height */
76 timing->xres = timing->width;
77 timing->yres = timing->height;
78 timing
42 drm_mode_to_intf_timing_params( const struct dpu_encoder_phys *phys_enc, const struct drm_display_mode *mode, struct dpu_hw_intf_timing_params *timing) argument
120 get_horizontal_total(const struct dpu_hw_intf_timing_params *timing) argument
129 get_vertical_total(const struct dpu_hw_intf_timing_params *timing) argument
152 programmable_fetch_get_num_lines( struct dpu_encoder_phys *phys_enc, const struct dpu_hw_intf_timing_params *timing) argument
201 programmable_fetch_config(struct dpu_encoder_phys *phys_enc, const struct dpu_hw_intf_timing_params *timing) argument
[all...]
/linux-master/drivers/video/fbdev/
H A Dgbefb.c37 struct gbe_timing_info timing; member in struct:gbefb_par
410 static void gbefb_setup_flatpanel(struct gbe_timing_info *timing) argument
416 (timing->flags & FB_SYNC_HOR_HIGH_ACT) ? 0 : 1);
418 (timing->flags & FB_SYNC_VERT_HIGH_ACT) ? 0 : 1);
426 timing->pll_m = 4;
427 timing->pll_n = 1;
428 timing->pll_p = 0;
455 struct gbe_timing_info *timing)
466 /* Determine valid resolution and timing
502 /* set video timing informatio
454 compute_gbe_timing(struct fb_var_screeninfo *var, struct gbe_timing_info *timing) argument
530 gbe_set_timing_info(struct gbe_timing_info *timing) argument
902 struct gbe_timing_info timing; local
[all...]
/linux-master/drivers/mmc/core/
H A Dhost.h68 return card->host->ios.timing == MMC_TIMING_MMC_HS200;
73 return card->host->ios.timing == MMC_TIMING_MMC_DDR52;
78 return card->host->ios.timing == MMC_TIMING_MMC_HS400;
88 return host->ios.timing == MMC_TIMING_SD_EXP ||
89 host->ios.timing == MMC_TIMING_SD_EXP_1_2V;
/linux-master/drivers/gpu/drm/amd/display/dc/
H A Ddc_dsc.h75 const struct dc_crtc_timing *timing,
84 const struct dc_crtc_timing *timing,
88 uint32_t dc_dsc_stream_bandwidth_in_kbps(const struct dc_crtc_timing *timing,
92 const struct dc_crtc_timing *timing,
101 void dc_dsc_get_policy_for_timing(const struct dc_crtc_timing *timing,
/linux-master/drivers/video/fbdev/via/
H A Dvia_modesetting.c18 void via_set_primary_timing(const struct via_display_timing *timing) argument
22 raw.hor_total = timing->hor_total / 8 - 5;
23 raw.hor_addr = timing->hor_addr / 8 - 1;
24 raw.hor_blank_start = timing->hor_blank_start / 8 - 1;
25 raw.hor_blank_end = timing->hor_blank_end / 8 - 1;
26 raw.hor_sync_start = timing->hor_sync_start / 8;
27 raw.hor_sync_end = timing->hor_sync_end / 8;
28 raw.ver_total = timing->ver_total - 2;
29 raw.ver_addr = timing->ver_addr - 1;
30 raw.ver_blank_start = timing
76 via_set_secondary_timing(const struct via_display_timing *timing) argument
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/dsc/
H A Ddc_dsc.c56 const struct dc_crtc_timing *timing, const uint32_t kbps)
63 if (!timing->flags.DSC) {
68 bpp = dc_fixpt_div_int(bpp, timing->pix_clk_100hz / 10);
73 overhead_factor = dc_fixpt_from_int(timing->h_addressable);
88 const struct dc_crtc_timing *timing,
94 if (timing->flags.DSC)
95 return dc_dsc_stream_bandwidth_in_kbps(timing,
96 timing->dsc_cfg.bits_per_pixel,
97 timing->dsc_cfg.num_slices_h,
98 timing
55 apply_128b_132b_stream_overhead( const struct dc_crtc_timing *timing, const uint32_t kbps) argument
87 dc_bandwidth_in_kbps_from_timing( const struct dc_crtc_timing *timing, const enum dc_link_encoding_format link_encoding) argument
448 dc_dsc_compute_bandwidth_range( const struct display_stream_compressor *dsc, uint32_t dsc_min_slice_height_override, uint32_t min_bpp_x16, uint32_t max_bpp_x16, const struct dsc_dec_dpcd_caps *dsc_sink_caps, const struct dc_crtc_timing *timing, const enum dc_link_encoding_format link_encoding, struct dc_dsc_bw_range *range) argument
585 compute_bpp_x16_from_target_bandwidth( const uint32_t bandwidth_in_kbps, const struct dc_crtc_timing *timing, const uint32_t num_slices_h, const uint32_t bpp_increment_div, const bool is_dp) argument
614 decide_dsc_bandwidth_range( const uint32_t min_bpp_x16, const uint32_t max_bpp_x16, const uint32_t num_slices_h, const struct dsc_enc_caps *dsc_caps, const struct dc_crtc_timing *timing, const enum dc_link_encoding_format link_encoding, struct dc_dsc_bw_range *range) argument
670 decide_dsc_target_bpp_x16( const struct dc_dsc_policy *policy, const struct dsc_enc_caps *dsc_common_caps, const int target_bandwidth_kbps, const struct dc_crtc_timing *timing, const int num_slices_h, const enum dc_link_encoding_format link_encoding, int *target_bpp_x16) argument
861 setup_dsc_config( const struct dsc_dec_dpcd_caps *dsc_sink_caps, const struct dsc_enc_caps *dsc_enc_caps, int target_bandwidth_kbps, const struct dc_crtc_timing *timing, const struct dc_dsc_config_options *options, const enum dc_link_encoding_format link_encoding, struct dc_dsc_config *dsc_cfg) argument
1090 dc_dsc_compute_config( const struct display_stream_compressor *dsc, const struct dsc_dec_dpcd_caps *dsc_sink_caps, const struct dc_dsc_config_options *options, uint32_t target_bandwidth_kbps, const struct dc_crtc_timing *timing, const enum dc_link_encoding_format link_encoding, struct dc_dsc_config *dsc_cfg) argument
1110 dc_dsc_stream_bandwidth_in_kbps(const struct dc_crtc_timing *timing, uint32_t bpp_x16, uint32_t num_slices_h, bool is_dp) argument
1126 dc_dsc_stream_bandwidth_overhead_in_kbps( const struct dc_crtc_timing *timing, const int num_slices_h, const bool is_dp) argument
1152 dc_dsc_get_policy_for_timing(const struct dc_crtc_timing *timing, uint32_t max_target_bpp_limit_override_x16, struct dc_dsc_policy *policy) argument
[all...]
/linux-master/drivers/ata/
H A Dpata_triflex.c62 * triflex_load_timing - timing configuration
76 u32 timing = 0; local
88 timing = 0x0103;break;
90 timing = 0x0203;break;
92 timing = 0x0808;break;
96 timing = 0x0F0F;break;
98 timing = 0x0202;break;
100 timing = 0x0204;break;
102 timing = 0x0404;break;
104 timing
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/dce110/
H A Ddce110_timing_generator_v.c243 const struct dc_crtc_timing *timing)
245 uint32_t vsync_offset = timing->v_border_bottom +
246 timing->v_front_porch;
247 uint32_t v_sync_start = timing->v_addressable + vsync_offset;
249 uint32_t hsync_offset = timing->h_border_right +
250 timing->h_front_porch;
251 uint32_t h_sync_start = timing->h_addressable + hsync_offset;
262 timing->h_total - 1,
271 timing->v_total - 1,
279 tmp = timing
241 dce110_timing_generator_v_program_blanking( struct timing_generator *tg, const struct dc_crtc_timing *timing) argument
383 dce110_timing_generator_v_enable_advanced_request( struct timing_generator *tg, bool enable, const struct dc_crtc_timing *timing) argument
435 dce110_timing_generator_v_program_timing(struct timing_generator *tg, const struct dc_crtc_timing *timing, int vready_offset, int vstartup_start, int vupdate_offset, int vupdate_width, const enum signal_type signal, bool use_vbios) argument
[all...]
/linux-master/drivers/media/i2c/
H A Dbt819.c60 struct timing { struct
70 static struct timing timing_data[] = {
175 struct timing *timing = &timing_data[(decoder->norm & V4L2_STD_525_60) ? 1 : 0]; local
178 (((timing->vdelay >> 8) & 0x03) << 6) |
179 (((timing->vactive >> 8) & 0x03) << 4) |
180 (((timing->hdelay >> 8) & 0x03) << 2) |
181 ((timing->hactive >> 8) & 0x03);
182 init[0x04 * 2 - 1] = timing->vdelay & 0xff;
183 init[0x05 * 2 - 1] = timing
238 struct timing *timing = NULL; local
[all...]
/linux-master/drivers/memory/tegra/
H A Dtegra124-emc.c539 dev_err(emc->dev, "timing update timed out\n");
577 struct emc_timing *timing = NULL; local
582 timing = &emc->timings[i];
587 if (!timing) {
588 dev_err(emc->dev, "no timing for rate %lu\n", rate);
592 return timing;
598 struct emc_timing *timing = tegra_emc_find_timing(emc, rate); local
606 if (!timing)
609 if ((last->emc_mode_1 & 0x1) == (timing->emc_mode_1 & 0x1))
611 else if (timing
826 struct emc_timing *timing = tegra_emc_find_timing(emc, rate); local
880 emc_read_current_timing(struct tegra_emc *emc, struct emc_timing *timing) argument
920 load_one_timing_from_dt(struct tegra_emc *emc, struct emc_timing *timing, struct device_node *node) argument
996 struct emc_timing *timing; local
[all...]
/linux-master/drivers/memory/samsung/
H A Dexynos-srom.c71 u32 timing[6]; local
80 if (of_property_read_u32_array(np, "samsung,srom-timing", timing,
81 ARRAY_SIZE(timing)))
94 writel_relaxed(pmc | (timing[0] << EXYNOS_SROM_BCX__TACP__SHIFT) |
95 (timing[1] << EXYNOS_SROM_BCX__TCAH__SHIFT) |
96 (timing[2] << EXYNOS_SROM_BCX__TCOH__SHIFT) |
97 (timing[3] << EXYNOS_SROM_BCX__TACC__SHIFT) |
98 (timing[4] << EXYNOS_SROM_BCX__TCOS__SHIFT) |
99 (timing[
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/dcn32/
H A Ddcn32_dio_stream_encoder.c235 static bool is_two_pixels_per_containter(const struct dc_crtc_timing *timing) argument
237 bool two_pix = timing->pixel_encoding == PIXEL_ENCODING_YCBCR420;
239 two_pix = two_pix || (timing->flags.DSC && timing->pixel_encoding == PIXEL_ENCODING_YCBCR422
240 && !timing->dsc_cfg.ycbcr422_simple);
244 static bool is_h_timing_divisible_by_2(const struct dc_crtc_timing *timing) argument
254 if (timing) {
255 h_blank_start = timing->h_total - timing->h_front_porch;
256 h_blank_end = h_blank_start - timing
270 is_dp_dig_pixel_rate_div_policy(struct dc *dc, const struct dc_crtc_timing *timing) argument
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/dcn35/
H A Ddcn35_dio_stream_encoder.c267 static bool is_two_pixels_per_containter(const struct dc_crtc_timing *timing) argument
269 bool two_pix = timing->pixel_encoding == PIXEL_ENCODING_YCBCR420;
271 two_pix = two_pix || (timing->flags.DSC && timing->pixel_encoding == PIXEL_ENCODING_YCBCR422
272 && !timing->dsc_cfg.ycbcr422_simple);
276 static bool is_h_timing_divisible_by_2(const struct dc_crtc_timing *timing) argument
286 if (timing) {
287 h_blank_start = timing->h_total - timing->h_front_porch;
288 h_blank_end = h_blank_start - timing
302 is_dp_dig_pixel_rate_div_policy(struct dc *dc, const struct dc_crtc_timing *timing) argument
[all...]

Completed in 350 milliseconds

1234567891011>>