Lines Matching refs:timing
60 struct timing {
70 static struct timing timing_data[] = {
175 struct timing *timing = &timing_data[(decoder->norm & V4L2_STD_525_60) ? 1 : 0];
178 (((timing->vdelay >> 8) & 0x03) << 6) |
179 (((timing->vactive >> 8) & 0x03) << 4) |
180 (((timing->hdelay >> 8) & 0x03) << 2) |
181 ((timing->hactive >> 8) & 0x03);
182 init[0x04 * 2 - 1] = timing->vdelay & 0xff;
183 init[0x05 * 2 - 1] = timing->vactive & 0xff;
184 init[0x06 * 2 - 1] = timing->hdelay & 0xff;
185 init[0x07 * 2 - 1] = timing->hactive & 0xff;
186 init[0x08 * 2 - 1] = timing->hscale >> 8;
187 init[0x09 * 2 - 1] = timing->hscale & 0xff;
238 struct timing *timing = NULL;
253 timing = &timing_data[1];
262 timing = &timing_data[0];
269 (((timing->vdelay >> 8) & 0x03) << 6) |
270 (((timing->vactive >> 8) & 0x03) << 4) |
271 (((timing->hdelay >> 8) & 0x03) << 2) |
272 ((timing->hactive >> 8) & 0x03));
273 bt819_write(decoder, 0x04, timing->vdelay & 0xff);
274 bt819_write(decoder, 0x05, timing->vactive & 0xff);
275 bt819_write(decoder, 0x06, timing->hdelay & 0xff);
276 bt819_write(decoder, 0x07, timing->hactive & 0xff);
277 bt819_write(decoder, 0x08, (timing->hscale >> 8) & 0xff);
278 bt819_write(decoder, 0x09, timing->hscale & 0xff);