clk/tegra/clk-tegra124-emc.c

48  * When we change the timing to a timing with a parent that has the same
50  * timing that has a different clock source.
120 	struct emc_timing *timing = NULL;
136 		timing = tegra->timings + i;
138 		if (timing->rate < req->rate && i != t - 1)
141 		if (timing->rate > req->max_rate) {
147 		if (timing->rate < req->min_rate)
150 		req->rate = timing->rate;
154 	if (timing) {
155 		req->rate = timing->rate;
210 			  struct emc_timing *timing)
221 	pr_debug("going to rate %ld prate %ld p %s\n", timing->rate,
222 		 timing->parent_rate, __clk_get_name(timing->parent));
224 	if (emc_get_parent(&tegra->hw) == timing->parent_index &&
225 	    clk_get_rate(timing->parent) != timing->parent_rate) {
227 			  __clk_get_name(timing->parent),
228 			  clk_get_rate(timing->parent),
229 			  timing->parent_rate);
235 	err = clk_set_rate(timing->parent, timing->parent_rate);
238 		       __clk_get_name(timing->parent), timing->parent_rate,
244 	err = clk_prepare_enable(timing->parent);
250 	div = timing->parent_rate / (timing->rate / 2) - 2;
252 	err = tegra->prepare_timing_change(emc, timing->rate);
254 		clk_disable_unprepare(timing->parent);
263 	car_value |= CLK_SOURCE_EMC_EMC_2X_CLK_SRC(timing->parent_index);
272 	tegra->complete_timing_change(emc, timing->rate);
274 	clk_hw_reparent(&tegra->hw, __clk_get_hw(timing->parent));
277 	tegra->prev_parent = timing->parent;
284  * Get backup timing to use as an intermediate step when a change between
286  * find a timing with a higher clock rate to avoid a rate below any set rate
294 	struct emc_timing *timing;
297 		timing = tegra->timings + i;
298 		if (timing->ram_code != ram_code)
301 		if (emc_parent_clk_sources[timing->parent_index] !=
304 			return timing;
308 		timing = tegra->timings + i;
309 		if (timing->ram_code != ram_code)
312 		if (emc_parent_clk_sources[timing->parent_index] !=
315 			return timing;
325 	struct emc_timing *timing = NULL;
345 			timing = tegra->timings + i;
350 	if (!timing) {
356 	    emc_parent_clk_sources[timing->parent_index] &&
357 	    clk_get_rate(timing->parent) != timing->parent_rate) {
367 			pr_err("cannot find backup timing\n");
376 			pr_err("cannot set backup timing: %d\n", err);
381 	return emc_set_timing(tegra, timing);
387 				   struct emc_timing *timing,
395 		pr_err("timing %pOF: failed to read rate\n", node);
399 	timing->rate = tmp;
403 		pr_err("timing %pOF: failed to read parent rate\n", node);
407 	timing->parent_rate = tmp;
409 	timing->parent = of_clk_get_by_name(node, "emc-parent");
410 	if (IS_ERR(timing->parent)) {
411 		pr_err("timing %pOF: failed to get parent clock\n", node);
412 		return PTR_ERR(timing->parent);
415 	timing->parent_index = 0xff;
417 			 __clk_get_name(timing->parent));
419 		pr_err("timing %pOF: %s is not a valid parent\n",
420 		       node, __clk_get_name(timing->parent));
421 		clk_put(timing->parent);
425 	timing->parent_index = i;
462 		struct emc_timing *timing = timings_ptr + (i++);
464 		err = load_one_timing_from_dt(tegra, timing, child);
471 		timing->ram_code = ram_code;