/linux-master/drivers/gpu/drm/i915/gem/ |
H A D | i915_gem_tiling.h | 16 unsigned int tiling, unsigned int stride); 18 unsigned int tiling, unsigned int stride);
|
H A D | i915_gem_tiling.c | 19 * DOC: buffer object tiling 25 * object, and hence it also doesn't care about tiling or swizzling. There's two 28 * - For X and Y tiling the hardware provides detilers for CPU access, so called 30 * these, and therefore userspace must tell the kernel the object tiling if it 35 * and hence now the tiling. Note that on a subset of platforms with 39 * Since neither of this applies for new tiling layouts on modern platforms like 40 * W, Ys and Yf tiling GEM only allows object tiling to be set to X or Y tiled. 49 * @tiling: tiling mod 55 i915_gem_fence_size(struct drm_i915_private *i915, u32 size, unsigned int tiling, unsigned int stride) argument 95 i915_gem_fence_alignment(struct drm_i915_private *i915, u32 size, unsigned int tiling, unsigned int stride) argument 119 i915_tiling_ok(struct drm_i915_gem_object *obj, unsigned int tiling, unsigned int stride) argument 231 i915_gem_object_set_tiling(struct drm_i915_gem_object *obj, unsigned int tiling, unsigned int stride) argument [all...] |
H A D | i915_gem_object.h | 333 i915_gem_tile_height(unsigned int tiling) argument 335 GEM_BUG_ON(!tiling); 336 return tiling == I915_TILING_Y ? 32 : 8; 353 unsigned int tiling, unsigned int stride);
|
/linux-master/drivers/gpu/drm/i915/display/ |
H A D | intel_fb_bo.c | 24 unsigned int tiling, stride; local 27 tiling = i915_gem_object_get_tiling(obj); 34 * the fb modifier and tiling mode match. 36 if (tiling != I915_TILING_NONE && 37 tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) { 43 if (tiling == I915_TILING_X) { 45 } else if (tiling == I915_TILING_Y) { 47 "No Y tiling for legacy addfb\n"); 54 * so the tiling mode must match the fb modifier exactly. 57 tiling ! [all...] |
H A D | intel_plane_initial.c | 192 switch (plane_config->tiling) { 199 plane_config->tiling; 202 MISSING_CASE(plane_config->tiling); 385 if (plane_config->tiling)
|
H A D | skl_universal_plane.c | 1450 "Y/Yf tiling required for 90/270!\n"); 1482 /* Y-tiling is not supported in IF-ID Interlace mode */ 1488 "Y/Yf tiling not supported in IF-ID mode\n"); 1687 "Unable to find suitable display surface offset due to X-tiling\n"); 2473 u32 val, base, offset, stride_mult, tiling, alpha; local 2521 tiling = val & PLANE_CTL_TILED_MASK; 2522 switch (tiling) { 2527 plane_config->tiling = I915_TILING_X; 2531 plane_config->tiling = I915_TILING_Y; 2568 MISSING_CASE(tiling); [all...] |
/linux-master/drivers/gpu/drm/tegra/ |
H A D | fb.c | 37 struct tegra_bo_tiling *tiling) 43 tiling->sector_layout = TEGRA_BO_SECTOR_LAYOUT_TEGRA; 45 tiling->sector_layout = TEGRA_BO_SECTOR_LAYOUT_GPU; 52 tiling->mode = TEGRA_BO_TILING_MODE_PITCH; 53 tiling->value = 0; 57 tiling->mode = TEGRA_BO_TILING_MODE_TILED; 58 tiling->value = 0; 62 tiling->mode = TEGRA_BO_TILING_MODE_BLOCK; 63 tiling->value = 0; 67 tiling 36 tegra_fb_get_tiling(struct drm_framebuffer *framebuffer, struct tegra_bo_tiling *tiling) argument [all...] |
H A D | gem.h | 49 struct tegra_bo_tiling tiling; member in struct:tegra_bo
|
H A D | plane.h | 49 struct tegra_bo_tiling tiling; member in struct:tegra_plane_state
|
H A D | hub.c | 432 struct tegra_bo_tiling *tiling = &plane_state->tiling; local 446 err = tegra_fb_get_tiling(new_plane_state->fb, tiling); 450 if (tiling->mode == TEGRA_BO_TILING_MODE_BLOCK && 456 if (tiling->sector_layout == TEGRA_BO_SECTOR_LAYOUT_GPU && 637 if (tegra_plane_state->tiling.sector_layout == TEGRA_BO_SECTOR_LAYOUT_GPU) 717 unsigned long height = tegra_plane_state->tiling.value; 720 switch (tegra_plane_state->tiling.mode) {
|
H A D | plane.c | 63 copy->tiling = state->tiling; 285 tegra_state->tiling.mode == TEGRA_BO_TILING_MODE_TILED)
|
H A D | drm.h | 183 struct tegra_bo_tiling *tiling);
|
H A D | dc.c | 428 unsigned long height = window->tiling.value; 430 switch (window->tiling.mode) { 447 switch (window->tiling.mode) { 627 struct tegra_bo_tiling *tiling = &plane_state->tiling; local 659 err = tegra_fb_get_tiling(new_plane_state->fb, tiling); 663 if (tiling->mode == TEGRA_BO_TILING_MODE_BLOCK && 759 window.tiling = tegra_plane_state->tiling;
|
H A D | drm.c | 650 bo->tiling.mode = mode; 651 bo->tiling.value = value; 672 switch (bo->tiling.mode) { 685 args->value = bo->tiling.value;
|
/linux-master/drivers/gpu/drm/i915/gem/selftests/ |
H A D | i915_gem_client_blt.c | 96 enum client_tiling tiling; member in struct:blit_buffer 133 if (buf->tiling == CLIENT_TILING_X && !fastblit_supports_x_tiling(buf->vma->vm->i915)) 167 if (src->tiling == CLIENT_TILING_Y) { 171 } else if (src->tiling == CLIENT_TILING_X) { 178 if (dst->tiling == CLIENT_TILING_Y) { 182 } else if (dst->tiling == CLIENT_TILING_X) { 204 if (src->tiling == CLIENT_TILING_Y) 206 if (dst->tiling == CLIENT_TILING_Y) 224 if (src->tiling) { 230 if (dst->tiling) { 347 tiled_offset(const struct intel_gt *gt, u64 v, unsigned int stride, enum client_tiling tiling, int x_pos, int y_pos) argument 404 repr_tiling(enum client_tiling tiling) argument [all...] |
H A D | i915_gem_mman.c | 35 unsigned int tiling; member in struct:tile 48 if (tile->tiling == I915_TILING_NONE) 54 if (tile->tiling == I915_TILING_X) { 108 err = i915_gem_object_set_tiling(obj, tile->tiling, tile->stride); 110 pr_err("Failed to set tiling mode=%u, stride=%u, err=%d\n", 111 tile->tiling, tile->stride, err); 115 GEM_BUG_ON(i915_gem_object_get_tiling(obj) != tile->tiling); 161 pr_err("Partial view for %lu [%u] (offset=%llu, size=%u [%llu, row size %u], fence=%d, tiling=%d, stride=%d) misalignment, expected write to page (%lu + %u [0x%lx]) of 0x%x, found 0x%x\n", 166 tile->tiling ? tile_row_pages(obj) : 0, 167 vma->fence ? vma->fence->id : -1, tile->tiling, til 321 int tiling; local [all...] |
/linux-master/drivers/gpu/drm/i915/gt/ |
H A D | intel_ggtt_fencing.h | 30 * Whether the tiling parameters for the currently 32 * for the purposes of tracking tiling changes we also 40 u32 tiling; member in struct:i915_fence_reg
|
H A D | intel_ggtt_fencing.c | 31 * have their own tiling state bits and don't need fences. 33 * Also note that fences only support X and Y tiling and hence can't be used for 34 * the fancier new tiling formats like W, Ys and Yf. 77 if (fence->tiling) { 86 if (fence->tiling == I915_TILING_Y) 118 if (fence->tiling) { 120 unsigned int tiling = fence->tiling; local 121 bool is_y_tiled = tiling == I915_TILING_Y; 152 if (fence->tiling) { [all...] |
/linux-master/drivers/gpu/drm/vc4/ |
H A D | vc4_render_cl.c | 440 uint8_t tiling = VC4_GET_FIELD(surf->bits, local 491 if (tiling > VC4_TILING_FORMAT_LT) { 492 DRM_DEBUG("Bad tiling format\n"); 525 if (!vc4_check_tex_size(exec, *obj, surf->offset, tiling, 539 uint8_t tiling = VC4_GET_FIELD(surf->bits, local 568 if (tiling > VC4_TILING_FORMAT_LT) { 569 DRM_DEBUG("Bad tiling format\n"); 586 if (!vc4_check_tex_size(exec, *obj, surf->offset, tiling,
|
H A D | vc4_plane.c | 829 u32 tiling, src_y; local 867 tiling = SCALER_CTL0_TILING_LINEAR; 930 tiling = SCALER_CTL0_TILING_256B_OR_T; 966 tiling = SCALER_CTL0_TILING_128B; 972 tiling = SCALER_CTL0_TILING_64B; 975 tiling = SCALER_CTL0_TILING_128B; 978 tiling = SCALER_CTL0_TILING_256B_OR_T; 1048 DRM_DEBUG_KMS("Unsupported FB tiling flag 0x%16llx", 1069 VC4_SET_FIELD(tiling, SCALER_CTL0_TILING) | 1109 VC4_SET_FIELD(tiling, SCALER_CTL0_TILIN [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn21/ |
H A D | display_rq_dlg_calc_21.c | 330 unsigned int tiling, 336 bool surf_linear = (tiling == dm_sw_linear); 411 (enum dm_swizzle_mode) (tiling), 449 if (tiling != dm_sw_linear) 320 get_meta_and_pte_attr( struct display_mode_lib *mode_lib, display_data_rq_dlg_params_st *rq_dlg_param, display_data_rq_misc_params_st *rq_misc_param, display_data_rq_sizing_params_st *rq_sizing_param, unsigned int vp_width, unsigned int vp_height, unsigned int data_pitch, unsigned int meta_pitch, unsigned int source_format, unsigned int tiling, unsigned int macro_tile_size, unsigned int source_scan, unsigned int hostvm_enable, unsigned int is_chroma) argument
|
/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
H A D | display_rq_dlg_calc_20v2.c | 343 unsigned int tiling, 348 bool surf_linear = (tiling == dm_sw_linear); 419 (enum dm_swizzle_mode)(tiling), 457 if (tiling != dm_sw_linear) 334 get_meta_and_pte_attr(struct display_mode_lib *mode_lib, display_data_rq_dlg_params_st *rq_dlg_param, display_data_rq_misc_params_st *rq_misc_param, display_data_rq_sizing_params_st *rq_sizing_param, unsigned int vp_width, unsigned int vp_height, unsigned int data_pitch, unsigned int meta_pitch, unsigned int source_format, unsigned int tiling, unsigned int macro_tile_size, unsigned int source_scan, unsigned int is_chroma) argument
|
H A D | display_rq_dlg_calc_20.c | 343 unsigned int tiling, 348 bool surf_linear = (tiling == dm_sw_linear); 419 (enum dm_swizzle_mode)(tiling), 457 if (tiling != dm_sw_linear) 334 get_meta_and_pte_attr(struct display_mode_lib *mode_lib, display_data_rq_dlg_params_st *rq_dlg_param, display_data_rq_misc_params_st *rq_misc_param, display_data_rq_sizing_params_st *rq_sizing_param, unsigned int vp_width, unsigned int vp_height, unsigned int data_pitch, unsigned int meta_pitch, unsigned int source_format, unsigned int tiling, unsigned int macro_tile_size, unsigned int source_scan, unsigned int is_chroma) argument
|
/linux-master/drivers/staging/media/ipu3/ |
H A D | ipu3-css-params.c | 313 unsigned int tiling; member in struct:imgu_css_frame_params 426 unsigned int tiling = 0; local 466 &tiling); 472 frame_params[pin].tiling = tiling; 998 fr_pr->tiling = frame_params[pin].tiling; 1081 if (frame_params[pin].tiling) { 1124 * in incorrect tiling (system may hang!) and 1150 param->tiling [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
H A D | display_rq_dlg_calc_31.c | 309 unsigned int tiling, 316 bool surf_linear = (tiling == dm_sw_linear); 385 (enum dm_swizzle_mode) (tiling), 424 if (tiling != dm_sw_linear) 299 get_meta_and_pte_attr( struct display_mode_lib *mode_lib, display_data_rq_dlg_params_st *rq_dlg_param, display_data_rq_misc_params_st *rq_misc_param, display_data_rq_sizing_params_st *rq_sizing_param, unsigned int vp_width, unsigned int vp_height, unsigned int data_pitch, unsigned int meta_pitch, unsigned int source_format, unsigned int tiling, unsigned int macro_tile_size, unsigned int source_scan, unsigned int hostvm_enable, unsigned int is_chroma, unsigned int surface_height) argument
|