Searched refs:taps (Results 1 - 25 of 35) sorted by relevance

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/linux-master/drivers/misc/echo/
H A Dfir.h42 int taps; member in struct:fir16_state_t
54 int taps; member in struct:fir32_state_t
65 int taps; member in struct:fir_float_state_t
72 const int16_t *coeffs, int taps)
74 fir->taps = taps;
75 fir->curr_pos = taps - 1;
77 fir->history = kcalloc(taps, sizeof(int16_t), GFP_KERNEL);
83 memset(fir->history, 0, fir->taps * sizeof(int16_t));
101 offset1 = fir->taps
71 fir16_create(struct fir16_state_t *fir, const int16_t *coeffs, int taps) argument
113 fir32_create(struct fir32_state_t *fir, const int32_t *coeffs, int taps) argument
[all...]
H A Decho.c120 /* Update the FIR taps */
123 offset1 = ec->taps - offset2;
125 for (i = ec->taps - 1; i >= offset1; i--) {
153 ec->taps = len;
155 ec->curr_pos = ec->taps - 1;
158 kcalloc(ec->taps, sizeof(int16_t), GFP_KERNEL);
163 kcalloc(ec->taps, sizeof(int16_t), GFP_KERNEL);
167 history = fir16_create(&ec->fir_state, ec->fir_taps16[0], ec->taps);
170 history = fir16_create(&ec->fir_state_bg, ec->fir_taps16[1], ec->taps);
180 ec->snapshot = kcalloc(ec->taps, sizeo
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H A Decho.h125 int taps; member in struct:oslec_state
/linux-master/drivers/gpu/drm/amd/display/dc/dcn201/
H A Ddcn201_dpp.c210 scl_data->taps.h_taps = 8;
212 scl_data->taps.h_taps = 4;
214 scl_data->taps.h_taps = in_taps->h_taps;
218 scl_data->taps.v_taps = 8;
220 scl_data->taps.v_taps = 4;
222 scl_data->taps.v_taps = in_taps->v_taps;
225 scl_data->taps.v_taps_c = 4;
227 scl_data->taps.v_taps_c = 2;
229 scl_data->taps.v_taps_c = in_taps->v_taps_c;
232 scl_data->taps
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/linux-master/drivers/gpu/drm/amd/display/dc/dcn10/
H A Ddcn10_dpp_dscl.c215 static const uint16_t *dpp1_dscl_get_filter_coeffs_64p(int taps, struct fixed31_32 ratio) argument
217 if (taps == 8)
219 else if (taps == 7)
221 else if (taps == 6)
223 else if (taps == 5)
225 else if (taps == 4)
227 else if (taps == 3)
229 else if (taps == 2)
231 else if (taps == 1)
242 uint32_t taps,
240 dpp1_dscl_set_scaler_filter( struct dcn10_dpp *dpp, uint32_t taps, enum dcn10_coef_filter_type_sel filter_type, const uint16_t *filter) argument
[all...]
H A Ddcn10_dpp.c153 /* Set default taps if none are provided */
155 scl_data->taps.h_taps = 4;
157 scl_data->taps.h_taps = in_taps->h_taps;
159 scl_data->taps.v_taps = 4;
161 scl_data->taps.v_taps = in_taps->v_taps;
163 scl_data->taps.v_taps_c = 2;
165 scl_data->taps.v_taps_c = in_taps->v_taps_c;
167 scl_data->taps.h_taps_c = 2;
170 scl_data->taps.h_taps_c = in_taps->h_taps_c - 1;
172 scl_data->taps
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/linux-master/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_dwb_scl.c649 static const uint16_t *wbscl_get_filter_coeffs_16p(int taps, struct fixed31_32 ratio) argument
651 if (taps == 12)
653 else if (taps == 11)
655 else if (taps == 10)
657 else if (taps == 9)
659 else if (taps == 8)
661 else if (taps == 7)
663 else if (taps == 6)
665 else if (taps == 5)
667 else if (taps
682 wbscl_set_scaler_filter( struct dcn20_dwbc *dwbc20, uint32_t taps, enum wbscl_coef_filter_type_sel filter_type, const uint16_t *filter) argument
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_transform.c122 if (data->taps.h_taps + data->taps.v_taps <= 2) {
132 SCL_H_NUM_OF_TAPS, data->taps.h_taps - 1,
133 SCL_V_NUM_OF_TAPS, data->taps.v_taps - 1);
156 if (data->taps.h_taps + data->taps.v_taps <= 2) {
165 SCL_H_NUM_OF_TAPS, data->taps.h_taps - 1,
166 SCL_V_NUM_OF_TAPS, data->taps.v_taps - 1);
209 int taps,
215 int taps_pairs = (taps
207 program_multi_taps_filter( struct dce_transform *xfm_dce, int taps, const uint16_t *coeffs, enum ram_filter_type filter_type) argument
391 get_filter_coeffs_16p(int taps, struct fixed31_32 ratio) argument
1143 uint32_t taps; local
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/dce110/
H A Ddce110_transform_v.c151 * Purpose: setup scaling mode : bypass, RGb, YCbCr and nummber of taps
165 set_reg_field_value(value, data->taps.h_taps - 1,
167 set_reg_field_value(value, data->taps.v_taps - 1,
169 set_reg_field_value(value, data->taps.h_taps_c - 1,
171 set_reg_field_value(value, data->taps.v_taps_c - 1,
176 if (data->taps.h_taps + data->taps.v_taps > 2) {
185 if (data->taps.h_taps_c + data->taps.v_taps_c > 2) {
284 int taps,
282 program_multi_taps_filter( struct dce_transform *xfm_dce, int taps, const uint16_t *coeffs, enum ram_filter_type filter_type) argument
488 get_filter_coeffs_64p(int taps, struct fixed31_32 ratio) argument
[all...]
/linux-master/drivers/mmc/host/
H A Drenesas_sdhi.h33 struct renesas_sdhi_scc *taps; member in struct:renesas_sdhi_of_data
89 DECLARE_BITMAP(taps, BITS_PER_LONG);
H A Dsdhci-of-aspeed.c144 const struct aspeed_sdhci_tap_param *taps)
151 reg = aspeed_sdc_set_phase_tap(&desc->in, taps->in, taps->valid, reg);
152 reg = aspeed_sdc_set_phase_tap(&desc->out, taps->out, taps->valid, reg);
201 struct aspeed_sdhci_tap_param *taps)
203 taps->valid = phases->valid;
208 taps->in = aspeed_sdhci_phase_to_tap(dev, rate, phases->in_deg);
209 taps->out = aspeed_sdhci_phase_to_tap(dev, rate, phases->out_deg);
215 struct aspeed_sdhci_tap_param _taps = {0}, *taps local
142 aspeed_sdc_set_phase_taps(struct aspeed_sdc *sdc, const struct aspeed_sdhci_phase_desc *desc, const struct aspeed_sdhci_tap_param *taps) argument
199 aspeed_sdhci_phases_to_taps(struct device *dev, unsigned long rate, const struct mmc_clk_phase *phases, struct aspeed_sdhci_tap_param *taps) argument
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H A Drenesas_sdhi_core.c632 if (!test_bit(i, priv->taps))
633 clear_bit(i + offset, priv->taps);
643 if (bitmap_full(priv->taps, taps_size)) {
647 bitmap = priv->taps;
690 if (priv->tap_num * 2 >= sizeof(priv->taps) * BITS_PER_BYTE) {
692 "Too many taps, please update 'taps' in tmio_mmc_host!\n");
696 bitmap_zero(priv->taps, priv->tap_num * 2);
707 set_bit(i, priv->taps);
803 * Skip checking SCC errors when running on 4 taps i
1079 const struct renesas_sdhi_scc *taps = of_data->taps; local
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H A Drenesas_sdhi_internal_dmac.c100 .taps = rcar_gen3_scc_taps,
115 .taps = rcar_gen3_scc_taps,
131 .taps = rcar_gen3_scc_taps,
H A Drenesas_sdhi_sys_dmac.c69 .taps = rcar_gen2_scc_taps,
/linux-master/include/linux/
H A Dif_tap.h38 /* This array tracks active taps. */
39 struct tap_queue __rcu *taps[MAX_TAP_QUEUES]; member in struct:tap_dev
40 /* This list tracks all taps (both enabled and disabled) */
/linux-master/sound/soc/ti/
H A Domap-mcbsp-st.c58 s16 taps[128]; /* Sidetone filter coefficients */ member in struct:omap_mcbsp_st_data
247 st_data->taps[i]);
264 memset(st_data->taps, 0, sizeof(st_data->taps));
277 st_data->taps[i++] = val;
308 omap_mcbsp_st_fir_write(mcbsp, st_data->taps);
/linux-master/drivers/gpu/drm/amd/display/dc/dcn30/
H A Ddcn30_dpp.c434 * Set default taps if none are provided
435 * From programming guide: taps = min{ ceil(2*H_RATIO,1), 8} for downscaling
436 * taps = 4 for upscaling
440 scl_data->taps.h_taps = min(2 * dc_fixpt_ceil(scl_data->ratios.horz), 8);
442 scl_data->taps.h_taps = 4;
444 scl_data->taps.h_taps = in_taps->h_taps;
447 scl_data->taps.v_taps = min(dc_fixpt_ceil(dc_fixpt_mul_int(scl_data->ratios.vert, 2)), 8);
449 scl_data->taps.v_taps = 4;
451 scl_data->taps.v_taps = in_taps->v_taps;
454 scl_data->taps
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/linux-master/drivers/gpu/drm/amd/display/dc/inc/hw/
H A Dtransform.h171 struct scaling_taps taps; member in struct:scaler_data
/linux-master/drivers/net/
H A Dtap.c157 rcu_assign_pointer(tap->taps[tap->numvtaps], q);
174 rcu_assign_pointer(tap->taps[tap->numvtaps], q);
203 nq = rtnl_dereference(tap->taps[tap->numvtaps - 1]);
206 rcu_assign_pointer(tap->taps[index], nq);
207 RCU_INIT_POINTER(tap->taps[tap->numvtaps - 1], NULL);
258 /* Access to taps array is protected by rcu, but access to numvtaps
275 queue = rcu_dereference(tap->taps[rxq % numvtaps]);
285 queue = rcu_dereference(tap->taps[rxq]);
290 queue = rcu_dereference(tap->taps[0]);
/linux-master/drivers/gpu/drm/amd/display/dc/dml/calcs/
H A Ddcn_calcs.c398 input->scale_taps.htaps = pipe->plane_res.scl_data.taps.h_taps;
404 input->scale_taps.vtaps = pipe->plane_res.scl_data.taps.v_taps;
405 input->scale_taps.vtaps_c = pipe->plane_res.scl_data.taps.v_taps_c;
406 input->scale_taps.htaps_c = pipe->plane_res.scl_data.taps.h_taps_c;
1012 v->override_hta_ps[input_idx] = pipe->plane_res.scl_data.taps.h_taps;
1013 v->override_vta_ps[input_idx] = pipe->plane_res.scl_data.taps.v_taps;
1014 v->override_hta_pschroma[input_idx] = pipe->plane_res.scl_data.taps.h_taps_c;
1015 v->override_vta_pschroma[input_idx] = pipe->plane_res.scl_data.taps.v_taps_c;
/linux-master/drivers/gpu/drm/amd/display/dc/dml2/
H A Ddml2_translation_helper.c810 temp_pipe->plane_res.scl_data.taps = pipe->plane_res.scl_data.taps;
919 if (!scaler_data.taps.h_taps) {
923 out->HTaps[location] = scaler_data.taps.h_taps;
924 out->HTapsChroma[location] = scaler_data.taps.h_taps_c;
926 if (!scaler_data.taps.v_taps) {
930 out->VTaps[location] = scaler_data.taps.v_taps;
931 out->VTapsChroma[location] = scaler_data.taps.v_taps_c;
/linux-master/drivers/gpu/drm/imx/dcss/
H A Ddcss-scaler.c168 * @use_5_taps: indicates whether to use 5 taps or 7 taps
180 int taps; local
189 taps = use_5_taps ? PSC_NUM_TAPS_RGBA : PSC_NUM_TAPS;
190 mid = (PSC_NUM_PHASES * taps) / 2 - 1;
264 * @use_5_taps: 0 for 7 taps per phase, 1 for 5 taps
/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn21/
H A Ddisplay_rq_dlg_calc_21.c846 const scaler_taps_st *taps = &e2e_pipe_param[pipe_idx].pipe.scale_taps; local
1036 htaps_l = taps->htaps;
1037 htaps_c = taps->htaps_c;
/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn20/
H A Ddisplay_rq_dlg_calc_20v2.c800 const scaler_taps_st *taps = &e2e_pipe_param[pipe_idx].pipe.scale_taps; local
985 htaps_l = taps->htaps;
986 htaps_c = taps->htaps_c;
H A Ddisplay_rq_dlg_calc_20.c800 const scaler_taps_st *taps = &e2e_pipe_param[pipe_idx].pipe.scale_taps; local
984 htaps_l = taps->htaps;
985 htaps_c = taps->htaps_c;

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