/broadcom-cfe-1.4.2/cfe/arch/mips/chipset/sibyte/include/ |
H A D | sb1250_wid.h | 210 #define WID_UNCONVOLUTE(wid,t1,t2,t3) \ 214 li t2,(M_WID_SWAPBITS << 1); \ 215 and t2,t2,wid ; \ 216 srl t2,t2,1 ; \ 220 or wid,wid,t2
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H A D | sbmips.h | 192 #define t2 $10 macro
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/broadcom-cfe-1.4.2/cfe/arch/mips/board/bcm91480ht/src/ |
H A D | bcm91480ht_init.S | 487 * t0,t1,t2,t3 525 move t2,a0 530 move a0,t2 547 move a0,t2
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H A D | cpu1test.S | 82 * t0,t1,t2,t3 164 addi t2,t0,'1' /* cpu number */
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/broadcom-cfe-1.4.2/cfe/arch/mips/board/bcm91125e/src/ |
H A D | bcm91125e_init.S | 329 li t2,0x07 /*JEDEC SDRAM memory type*/ 330 bne spd_byte,t2,man 334 li t2,0x0D /*There should be 13 rows*/ 335 bne spd_byte,t2,man 339 li t2,0x09 /*There should be 9 columns*/ 340 bne spd_byte,t2,man 344 li t2,0x82 /*Refresh rate should be set for 128 KHZ*/ 345 bne spd_byte,t2,man 453 * t0,t1,t2,t3 465 move t2,a [all...] |
/broadcom-cfe-1.4.2/cfe/arch/mips/board/bcm91125f/src/ |
H A D | bcm91125f_init.S | 317 li t2,0x07 /*JEDEC SDRAM memory type*/ 318 bne spd_byte,t2,man 322 li t2,0x0D /*There should be 13 rows*/ 323 bne spd_byte,t2,man 327 li t2,0x09 /*There should be 9 columns*/ 328 bne spd_byte,t2,man 332 li t2,0x82 /*Refresh rate should be set for 128 KHZ*/ 333 bne spd_byte,t2,man 441 * t0,t1,t2,t3 453 move t2,a [all...] |
/broadcom-cfe-1.4.2/cfe/arch/mips/board/sentosa/src/ |
H A D | sentosa_init.S | 381 * t0,t1,t2,t3 389 move t2,a0 394 move a0,t2
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/broadcom-cfe-1.4.2/cfe/arch/mips/board/bcm91480b/src/ |
H A D | bcm91480b_init.S | 146 li t2,(~M_PCMCIA_MODE) 147 and t1,t1,t2 148 li t2,V_PCMCIA_MODE(BCM91480_PCMCIA_MODE) 149 or t1,t1,t2 647 * t0,t1,t2,t3 685 move t2,a0 690 move a0,t2 707 move a0,t2
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H A D | cpu1test.S | 82 * t0,t1,t2,t3 165 addi t2,t0,'1' /* cpu number */
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/broadcom-cfe-1.4.2/cfe/arch/mips/cpu/bcm1480/src/ |
H A D | bcm1480_altcpu.S | 340 dli t2,BCM1480_IMR_REGISTER_SPACING 342 multu v0,t2 343 mflo t2 344 daddu t1,t1,t2 403 JAL(bcm1480_l1cache_flush_d) # uses t0, t2, t3 415 li t2,PHYS_TO_K1(A_SCD_SYSTEM_CFG) 416 ld t0,0(t2) 420 BCM1480_WRITE_SYSTEM_CFG(t2, t0) 441 la t2,PHYS_TO_K1(A_BCM1480_IMR_REGISTER(0,R_BCM1480_IMR_MAILBOX_0_CLR_CPU)) 444 sd t0,(t2) # d [all...] |
H A D | bcm1480_ircpoll.S | 308 li t2,~(M_SR_IMMASK|M_SR_IE) 310 and t0,t0,t2 344 li t2,~(M_SR_IMMASK|M_SR_IE) 346 and t0,t0,t2
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H A D | bcm1480_l1cache.S | 97 * t0,t1,t2,t3 107 li t2,K1BASE 114 add t0,t2,t3 116 1: cache L1CACHEOP(L1C_I,L1C_OP_IDXSTORETAG),0(t2) 117 addu t2,L1CACHE_LINESIZE 118 bne t0,t2,1b 123 li t2,K1BASE 124 add t0,t2,t3 126 1: cache L1CACHEOP(L1C_D,L1C_OP_IDXSTORETAG),0(t2) 127 addu t2,L1CACHE_LINESIZ [all...] |
H A D | bcm1480_l2cache.S | 80 * t0,t1,t2 105 mfc0 t2,C0_SR 106 or t1,t2,M_SR_KX 154 mtc0 t2,C0_SR 289 * t0,t1,t2,t3,t4: scratch 329 ld t2, 0(t0) 330 or t3, t1, t2 331 beq t2, t3, 1f 343 ld t2, (R_BCM1480_MC_DRAMMODE)(t0) 344 or t3, t1, t2 [all...] |
H A D | bcm1480_cpu.S | 137 dli t2,~M_BCM1480_SYS_SB_SOFTRES 138 and t1,t1,t2
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/broadcom-cfe-1.4.2/cfe/arch/mips/cpu/sb1250/src/ |
H A D | sb1250_ircpoll.S | 310 li t2,~(M_SR_IMMASK|M_SR_IE) 312 and t0,t0,t2 346 li t2,~(M_SR_IMMASK|M_SR_IE) 348 and t0,t0,t2
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H A D | sb1250_l1cache.S | 104 * t0,t1,t2,t3 115 li t2,K1BASE 122 add t0,t2,t3 124 1: cache L1CACHEOP(L1C_I,L1C_OP_IDXSTORETAG),0(t2) 125 addu t2,L1CACHE_LINESIZE 126 bne t0,t2,1b 131 li t2,K1BASE 132 add t0,t2,t3 134 1: cache L1CACHEOP(L1C_D,L1C_OP_IDXSTORETAG),0(t2) 135 addu t2,L1CACHE_LINESIZ [all...] |
H A D | sb1250_altcpu.S | 348 JAL(sb1250_l1cache_flush_d) # uses t0, t2, t3 579 ld t2,R_CPUSTART_GPVAL(a1) 580 sd t2,0(t1) 584 ld t2,R_CPUSTART_SPVAL(a1) 585 sd t2,0(t1) 589 ld t2,R_CPUSTART_A1VAL(a1) 590 sd t2,0(t1) 594 ld t2,R_CPUSTART_PCVAL(a1) 595 sd t2,0(t1) 782 ld t2,cpu_start_gpval [all...] |
H A D | sb1250_l2cache.S | 87 * t0,t1,t2 106 mfc0 t2,C0_SR 107 or t1,t2,M_SR_KX 144 mtc0 t2,C0_SR 268 * t0, t1, t2, t3: scratch 339 li t2, (L2C_ENTRIES_PER_WAY * L2C_NUM_WAYS \ 343 daddiu t2, -CACHE_LINE_SIZE 347 or t3, t0, t2 353 or t3, t1, t2 357 bnez t2, [all...] |
/broadcom-cfe-1.4.2/cfe/arch/mips/common/src/ |
H A D | exception.S | 198 LR t2,R_EXC_CERR_TEMPLATE_END(t1) 205 blt t1,t2,1b # till done 225 LR t2,R_EXC_CERR_TEMPLATE_END(t1) 232 blt t1,t2,1b # till done 373 SREG t2,XGR_T2(k1) 399 MFC0 t2,C0_BADVADDR 406 SREG t2,XCP0_VADDR(k1) 447 LREG t2,XGR_T2(k1)
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H A D | init_mips.S | 617 lw t2,8(v0) 625 sw t2,8(s0) 748 andi t2,t1,M_REL_TYPE # Ignore R_MIPS_NONE 749 bne t2,K_REL_TYPE_REL32,2f # only take R_MIPS_R32 769 lw t2,R_ELF32SYM_ST_VALUE(t1) # Symbol value 770 addu t2,RELOCOFFSET # Relocation base 773 addu t1,t2 # Add in offset 840 LR t2,R_SEG_FDATA(a0) 842 ADD t2,RELOCOFFSET # Relocate to actual data segment 849 SR t4,0(t2) # writ [all...] |
H A D | dev_flashop_engine.S | 425 1: lbu t2,0(reg_dest) # t2 = byte from flash 427 and t1,t2,0x80 # done if bit7 of flash 431 and t1,t2,0x20 # not done if bit5 465 1: lh t2,0(reg_dest) # t2 = word from flash 467 and t1,t2,0x80 # done if bit7 of flash 471 and t1,t2,0x20 # not done if bit5 504 1: lb t2,0(reg_dest) # t2 [all...] |
H A D | zipstart_init.S | 416 LR t2,R_SEG_FDATA(a0) 423 SR t4,0(t2) # write one cache line 424 SR t5,(REGSIZE*1)(t2) 425 SR t6,(REGSIZE*2)(t2) 426 SR t7,(REGSIZE*3)(t2) 428 add t2,(REGSIZE*4) 429 bltu t2,t3,1b
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/broadcom-cfe-1.4.2/cfe/arch/mips/board/bcm91280e/src/ |
H A D | cpu1test.S | 82 * t0,t1,t2,t3 165 addi t2,t0,'1' /* cpu number */
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/broadcom-cfe-1.4.2/cfe/verif/ |
H A D | vapi.S | 134 sd t2,SAVE_T2(k0) ; \ 151 ld t2,SAVE_T2(k0) ; \ 168 li t2,(VAPI_CFESEAL | (x)) ; \ 173 or t2,t2,t0 ; \ 174 dsll t2,t2,32 ; \ 175 or t2,id ; \ 176 sd t2,VAPI_REC_SIGNATURE(RECPTR) ; \ 177 mfc0 t2,C0_COUN [all...] |
/broadcom-cfe-1.4.2/cfe/arch/mips/cpu/bcmcore/src/ |
H A D | bcmcore_l1cache.S | 95 * t0,t1,t2 110 li t2,M_CFG_IS 111 and t2,t0 112 srl t2,S_CFG_IS 114 sll t1,t2 120 li t2,M_CFG_IA 121 and t2,t0 122 srl t2,S_CFG_IA 123 addiu t2,1 129 multu t1,t2 [all...] |