1/*  *********************************************************************
2    *  SB1250 Board Support Package
3    *
4    *  Wafer ID bit definitions			File: sb1250_wid.h
5    *
6    *  Some preproduction BCM1250 samples use the wafer ID (WID) bits
7    *  in the system_revision register in the SCD to determine which
8    *  portions of the L1 and L2 caches are usable.
9    *
10    *  This file describes the WID register layout.
11    *
12    *********************************************************************
13    *
14    *  Copyright 2000,2001,2002,2003
15    *  Broadcom Corporation. All rights reserved.
16    *
17    *  This software is furnished under license and may be used and
18    *  copied only in accordance with the following terms and
19    *  conditions.  Subject to these conditions, you may download,
20    *  copy, install, use, modify and distribute modified or unmodified
21    *  copies of this software in source and/or binary form.  No title
22    *  or ownership is transferred hereby.
23    *
24    *  1) Any source code used, modified or distributed must reproduce
25    *     and retain this copyright notice and list of conditions
26    *     as they appear in the source file.
27    *
28    *  2) No right is granted to use any trade name, trademark, or
29    *     logo of Broadcom Corporation.  The "Broadcom Corporation"
30    *     name may not be used to endorse or promote products derived
31    *     from this software without the prior written permission of
32    *     Broadcom Corporation.
33    *
34    *  3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR
35    *     IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED
36    *     WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
37    *     PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT
38    *     SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN
39    *     PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT,
40    *     INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
41    *     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
42    *     GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
43    *     BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
44    *     OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
45    *     TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF
46    *     THE POSSIBILITY OF SUCH DAMAGE.
47    ********************************************************************* */
48
49
50#ifndef _SB1250_WID_H
51#define _SB1250_WID_H
52
53#include "sb1250_defs.h"
54
55/*
56 * To make things easier to work with, we'll assume that the
57 * WID bits have been shifted from their normal home
58 * in scd_system_revision[63:32] to bits [31..0].
59 *
60 * That is, we've already shifted right by S_SYS_WID
61 */
62
63#define S_WID_BIN             0
64#define M_WID_BIN             _SB_MAKEMASK(3,S_WID_BIN)
65#define V_WID_BIN(x)          _SB_MAKEVALUE(x,S_WID_BIN)
66#define G_WID_BIN(x)          _SB_GETVALUE(x,S_WID_BIN,M_WID_BIN)
67
68                                        /* CPUs  L1I    L1D    L2   */
69#define K_WID_BIN_2CPU_FI_1D_H2	0	/*  2    full   1/4    1/2  */
70#define K_WID_BIN_2CPU_FI_FD_F2	1	/*  2    full   full   full */
71#define K_WID_BIN_2CPU_FI_FD_H2 2 	/*  2    full   full   1/2  */
72#define K_WID_BIN_2CPU_3I_3D_F2 3       /*  2    3/4    3/4    full */
73#define K_WID_BIN_2CPU_3I_3D_H2 4	/*  2    3/4    3/4    1/2  */
74#define K_WID_BIN_1CPU_FI_FD_F2 5	/*  1    full   full   full */
75#define K_WID_BIN_1CPU_FI_FD_H2 6       /*  1    full   full   1/2  */
76#define K_WID_BIN_2CPU_1I_1D_Q2 7       /*  2    1/4    1/4    1/4  */
77
78/*
79 * '1' bits in this mask represent bins with only one CPU
80 */
81
82#define M_WID_BIN_1CPU (_SB_MAKEMASK1(K_WID_BIN_1CPU_FI_FD_F2) | \
83                        _SB_MAKEMASK1(K_WID_BIN_1CPU_FI_FD_H2))
84
85
86/*
87 * '1' bits in this mask represent bins with a good L2
88 */
89
90#define M_WID_BIN_F2 (_SB_MAKEMASK1(K_WID_BIN_2CPU_FI_FD_F2) | \
91                      _SB_MAKEMASK1(K_WID_BIN_2CPU_3I_3D_F2) | \
92                      _SB_MAKEMASK1(K_WID_BIN_1CPU_FI_FD_F2))
93
94/*
95 * '1' bits in this mask represent bins with 1/2 L2
96 */
97
98#define M_WID_BIN_H2   (_SB_MAKEMASK1(K_WID_BIN_2CPU_FI_1D_H2) | \
99                        _SB_MAKEMASK1(K_WID_BIN_2CPU_FI_FD_H2) | \
100                        _SB_MAKEMASK1(K_WID_BIN_2CPU_3I_3D_H2) | \
101                        _SB_MAKEMASK1(K_WID_BIN_1CPU_FI_FD_H2) )
102
103/*
104 * '1' bits in this mask represent bins with 1/4 L2
105 */
106
107#define M_WID_BIN_Q2   (_SB_MAKEMASK1(K_WID_BIN_2CPU_1I_1D_Q2))
108
109/*
110 * '1' bits in this mask represent bins with 3/4 L1
111 */
112
113#define M_WID_BIN_3ID  (_SB_MAKEMASK1(K_WID_BIN_2CPU_3I_3D_F2) | \
114			_SB_MAKEMASK1(K_WID_BIN_2CPU_3I_3D_H2))
115
116/*
117 * '1' bits in this mask represent bins with a full L1I
118 */
119
120#define M_WID_BIN_FI   (_SB_MAKEMASK1(K_WID_BIN_2CPU_FI_1D_H2) | \
121			_SB_MAKEMASK1(K_WID_BIN_2CPU_FI_FD_F2) | \
122			_SB_MAKEMASK1(K_WID_BIN_2CPU_FI_FD_H2) | \
123			_SB_MAKEMASK1(K_WID_BIN_1CPU_FI_FD_F2) | \
124			_SB_MAKEMASK1(K_WID_BIN_1CPU_FI_FD_H2))
125
126/*
127 * '1' bits in this mask represent bins with a full L1D
128 */
129
130#define M_WID_BIN_FD   (_SB_MAKEMASK1(K_WID_BIN_2CPU_FI_FD_F2) | \
131			_SB_MAKEMASK1(K_WID_BIN_2CPU_FI_FD_H2) | \
132			_SB_MAKEMASK1(K_WID_BIN_1CPU_FI_FD_F2) | \
133			_SB_MAKEMASK1(K_WID_BIN_1CPU_FI_FD_H2))
134
135/*
136 * '1' bits in this mask represent bins with a full L1 (both I and D)
137 */
138
139#define M_WID_BIN_FID  (_SB_MAKEMASK1(K_WID_BIN_2CPU_FI_FD_F2) | \
140			_SB_MAKEMASK1(K_WID_BIN_2CPU_FI_FD_H2) | \
141			_SB_MAKEMASK1(K_WID_BIN_1CPU_FI_FD_F2) | \
142			_SB_MAKEMASK1(K_WID_BIN_1CPU_FI_FD_H2))
143
144#define S_WID_L2QTR           3
145#define M_WID_L2QTR           _SB_MAKEMASK(2,S_WID_L2QTR)
146#define V_WID_L2QTR(x)        _SB_MAKEVALUE(x,S_WID_L2QTR)
147#define G_WID_L2QTR(x)        _SB_GETVALUE(x,S_WID_L2QTR,M_WID_L2QTR)
148
149#define M_WID_L2HALF	      _SB_MAKEMASK1(4)
150
151#define S_WID_CPU0_L1I        5
152#define M_WID_CPU0_L1I        _SB_MAKEMASK(2,S_WID_CPU0_L1I)
153#define V_WID_CPU0_L1I(x)     _SB_MAKEVALUE(x,S_WID_CPU0_L1I)
154#define G_WID_CPU0_L1I(x)     _SB_GETVALUE(x,S_WID_CPU0_L1I,M_WID_CPU0_L1I)
155
156#define S_WID_CPU0_L1D        7
157#define M_WID_CPU0_L1D        _SB_MAKEMASK(2,S_WID_CPU0_L1D)
158#define V_WID_CPU0_L1D(x)     _SB_MAKEVALUE(x,S_WID_CPU0_L1D)
159#define G_WID_CPU0_L1D(x)     _SB_GETVALUE(x,S_WID_CPU0_L1D,M_WID_CPU0_L1D)
160
161#define S_WID_CPU1_L1I        9
162#define M_WID_CPU1_L1I        _SB_MAKEMASK(2,S_WID_CPU1_L1I)
163#define V_WID_CPU1_L1I(x)     _SB_MAKEVALUE(x,S_WID_CPU1_L1I)
164#define G_WID_CPU1_L1I(x)     _SB_GETVALUE(x,S_WID_CPU1_L1I,M_WID_CPU1_L1I)
165
166#define S_WID_CPU1_L1D        11
167#define M_WID_CPU1_L1D        _SB_MAKEMASK(2,S_WID_CPU1_L1D)
168#define V_WID_CPU1_L1D(x)     _SB_MAKEVALUE(x,S_WID_CPU1_L1D)
169#define G_WID_CPU1_L1D(x)     _SB_GETVALUE(x,S_WID_CPU1_L1D,M_WID_CPU1_L1D)
170
171/*
172 * The macros below assume that the CPU bits have been shifted into the
173 * low-order 4 bits.
174 */
175
176#define S_WID_CPUX_L1I        0
177#define M_WID_CPUX_L1I        _SB_MAKEMASK(2,S_WID_CPUX_L1I)
178#define V_WID_CPUX_L1I(x)     _SB_MAKEVALUE(x,S_WID_CPUX_L1I)
179#define G_WID_CPUX_L1I(x)     _SB_GETVALUE(x,S_WID_CPUX_L1I,M_WID_CPUX_L1I)
180
181#define S_WID_CPUX_L1D        2
182#define M_WID_CPUX_L1D        _SB_MAKEMASK(2,S_WID_CPUX_L1D)
183#define V_WID_CPUX_L1D(x)     _SB_MAKEVALUE(x,S_WID_CPUX_L1D)
184#define G_WID_CPUX_L1D(x)     _SB_GETVALUE(x,S_WID_CPUX_L1D,M_WID_CPUX_L1D)
185
186#define S_WID_CPU0	      5
187#define S_WID_CPU1	      9
188
189#define S_WID_WAFERID        13
190#define M_WID_WAFERID        _SB_MAKEMASK(5,S_WID_WAFERID)
191#define V_WID_WAFERID(x)     _SB_MAKEVALUE(x,S_WID_WAFERID)
192#define G_WID_WAFERID(x)     _SB_GETVALUE(x,S_WID_WAFERID,M_WID_WAFERID)
193
194#define S_WID_LOTID        18
195#define M_WID_LOTID        _SB_MAKEMASK(14,S_WID_LOTID)
196#define V_WID_LOTID(x)     _SB_MAKEVALUE(x,S_WID_LOTID)
197#define G_WID_LOTID(x)     _SB_GETVALUE(x,S_WID_LOTID,M_WID_LOTID)
198
199/*
200 * Now, to make things even more confusing, the fuses on the chip
201 * don't exactly correspond to the bits in the register. The mask
202 * below represents bits that need to be swapped with the ones to
203 * their left.  So, if bit 10 is set, swap bits 10 and 11
204 */
205
206#define M_WID_SWAPBITS	(_SB_MAKEMASK1(2) | _SB_MAKEMASK1(4) | _SB_MAKEMASK1(10) | \
207                         _SB_MAKEMASK1(20) | _SB_MAKEMASK1(18) | _SB_MAKEMASK1(26) )
208
209#ifdef __ASSEMBLER__
210#define WID_UNCONVOLUTE(wid,t1,t2,t3) \
211       li    t1,M_WID_SWAPBITS ; \
212       and   t1,t1,wid ; \
213       sll   t1,t1,1 ; \
214       li    t2,(M_WID_SWAPBITS << 1); \
215       and   t2,t2,wid ; \
216       srl   t2,t2,1 ; \
217       li    t3, ~((M_WID_SWAPBITS | (M_WID_SWAPBITS << 1))) ; \
218       and   wid,wid,t3 ; \
219       or    wid,wid,t1 ; \
220       or    wid,wid,t2
221#else
222#define WID_UNCONVOLUTE(wid) \
223     (((wid) & ~((M_WID_SWAPBITS | (M_WID_SWAPBITS << 1)))) | \
224      (((wid) & M_WID_SWAPBITS) << 1) |  \
225      (((wid) & (M_WID_SWAPBITS<<1)) >> 1))
226#endif
227
228
229
230#endif
231