Searched refs:sseu (Results 1 - 25 of 25) sorted by relevance

/linux-master/drivers/gpu/drm/i915/gt/
H A Dintel_sseu.c14 void intel_sseu_set_info(struct sseu_dev_info *sseu, u8 max_slices, argument
17 sseu->max_slices = max_slices;
18 sseu->max_subslices = max_subslices;
19 sseu->max_eus_per_subslice = max_eus_per_subslice;
23 intel_sseu_subslice_total(const struct sseu_dev_info *sseu) argument
27 if (sseu->has_xehp_dss)
28 return bitmap_weight(sseu->subslice_mask.xehp,
29 XEHP_BITMAP_BITS(sseu->subslice_mask));
31 for (i = 0; i < ARRAY_SIZE(sseu->subslice_mask.hsw); i++)
32 total += hweight8(sseu
38 intel_sseu_get_hsw_subslices(const struct sseu_dev_info *sseu, u8 slice) argument
47 sseu_get_eus(const struct sseu_dev_info *sseu, int slice, int subslice) argument
58 sseu_set_eus(struct sseu_dev_info *sseu, int slice, int subslice, u16 eu_mask) argument
70 compute_eu_total(const struct sseu_dev_info *sseu) argument
94 intel_sseu_copy_eumask_to_user(void __user *to, const struct sseu_dev_info *sseu) argument
128 intel_sseu_copy_ssmask_to_user(void __user *to, const struct sseu_dev_info *sseu) argument
150 gen11_compute_sseu_info(struct sseu_dev_info *sseu, u32 ss_en, u16 eu_en) argument
167 xehp_compute_sseu_info(struct sseu_dev_info *sseu, u16 eu_en) argument
210 struct sseu_dev_info *sseu = &gt->info.sseu; local
258 struct sseu_dev_info *sseu = &gt->info.sseu; local
299 struct sseu_dev_info *sseu = &gt->info.sseu; local
333 struct sseu_dev_info *sseu = &gt->info.sseu; local
386 struct sseu_dev_info *sseu = &gt->info.sseu; local
491 struct sseu_dev_info *sseu = &gt->info.sseu; local
577 struct sseu_dev_info *sseu = &gt->info.sseu; local
665 const struct sseu_dev_info *sseu = &gt->info.sseu; local
776 intel_sseu_dump(const struct sseu_dev_info *sseu, struct drm_printer *p) argument
813 sseu_print_hsw_topology(const struct sseu_dev_info *sseu, struct drm_printer *p) argument
833 sseu_print_xehp_topology(const struct sseu_dev_info *sseu, struct drm_printer *p) argument
848 intel_sseu_print_topology(struct drm_i915_private *i915, const struct sseu_dev_info *sseu, struct drm_printer *p) argument
860 intel_sseu_print_ss_info(const char *type, const struct sseu_dev_info *sseu, struct seq_file *m) argument
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H A Dintel_sseu_debugfs.c16 struct sseu_dev_info *sseu)
36 sseu->slice_mask = BIT(0);
37 sseu->subslice_mask.hsw[0] |= BIT(ss);
42 sseu->eu_total += eu_cnt;
43 sseu->eu_per_subslice = max_t(unsigned int,
44 sseu->eu_per_subslice, eu_cnt);
50 struct sseu_dev_info *sseu)
58 for (s = 0; s < info->sseu.max_slices; s++) {
82 for (s = 0; s < info->sseu.max_slices; s++) {
87 sseu
15 cherryview_sseu_device_status(struct intel_gt *gt, struct sseu_dev_info *sseu) argument
49 gen11_sseu_device_status(struct intel_gt *gt, struct sseu_dev_info *sseu) argument
109 gen9_sseu_device_status(struct intel_gt *gt, struct sseu_dev_info *sseu) argument
168 bdw_sseu_device_status(struct intel_gt *gt, struct sseu_dev_info *sseu) argument
193 i915_print_sseu_info(struct seq_file *m, bool is_available_info, bool has_pooled_eu, const struct sseu_dev_info *sseu) argument
235 struct sseu_dev_info *sseu; local
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H A Dintel_context_sseu.c18 const struct intel_sseu sseu)
33 *cs++ = intel_sseu_make_rpcs(rq->engine->gt, &sseu);
41 gen8_modify_rpcs(struct intel_context *ce, const struct intel_sseu sseu) argument
66 ret = gen8_emit_rpcs_config(rq, ce, sseu);
76 const struct intel_sseu sseu)
87 if (!memcmp(&ce->sseu, &sseu, sizeof(sseu)))
90 ret = gen8_modify_rpcs(ce, sseu);
92 ce->sseu
16 gen8_emit_rpcs_config(struct i915_request *rq, const struct intel_context *ce, const struct intel_sseu sseu) argument
75 intel_context_reconfigure_sseu(struct intel_context *ce, const struct intel_sseu sseu) argument
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H A Dintel_sseu.h109 intel_sseu_from_device_info(const struct sseu_dev_info *sseu) argument
112 .slice_mask = sseu->slice_mask,
113 .subslice_mask = sseu->subslice_mask.hsw[0],
114 .min_eus_per_subslice = sseu->max_eus_per_subslice,
115 .max_eus_per_subslice = sseu->max_eus_per_subslice,
122 intel_sseu_has_subslice(const struct sseu_dev_info *sseu, int slice, argument
125 if (slice >= sseu->max_slices ||
126 subslice >= sseu->max_subslices)
129 if (sseu->has_xehp_dss)
130 return test_bit(subslice, sseu
141 intel_sseu_find_first_xehp_dss(const struct sseu_dev_info *sseu, int groupsize, int groupnum) argument
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H A Dintel_gt_mcr.h58 intel_sseu_has_subslice(&(gt_)->info.sseu, 0, ss_) : \
59 intel_sseu_has_subslice(&(gt_)->info.sseu, group_, instance_))
H A Dintel_gt_types.h267 struct sseu_dev_info sseu; member in struct:intel_gt::intel_gt_info
H A Dintel_context_types.h175 /** sseu: Control eu/slice partitioning */
176 struct intel_sseu sseu; member in struct:intel_context
H A Dintel_workarounds.c551 if (!is_power_of_2(gt->info.sseu.subslice_7eu[i]))
560 ss = ffs(gt->info.sseu.subslice_7eu[i]) - 1;
1105 const struct sseu_dev_info *sseu = &to_gt(i915)->info.sseu; local
1122 slice = ffs(sseu->slice_mask) - 1;
1123 GEM_BUG_ON(slice >= ARRAY_SIZE(sseu->subslice_mask.hsw));
1124 subslice = ffs(intel_sseu_get_hsw_subslices(sseu, slice));
1267 const struct sseu_dev_info *sseu = &gt->info.sseu; local
1271 GEM_BUG_ON(hweight8(sseu
1298 const struct sseu_dev_info *sseu = &gt->info.sseu; local
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H A Dintel_context.h48 const struct intel_sseu sseu);
H A Dintel_context.c399 ce->sseu = engine->sseu;
H A Dintel_gt_mcr.c155 intel_slicemask_from_xehp_dssmask(gt->info.sseu.subslice_mask,
662 dss = intel_sseu_find_first_xehp_dss(&gt->info.sseu, 0, 0);
H A Dintel_engine_types.h415 struct intel_sseu sseu; member in struct:intel_engine_cs
H A Dintel_engine_cs.c820 int ss_per_ccs = info->sseu.max_subslices / I915_MAX_CCS;
830 ccs_mask = intel_slicemask_from_xehp_dssmask(info->sseu.compute_subslice_mask,
1309 engine->sseu =
1310 intel_sseu_from_device_info(&engine->gt->info.sseu);
H A Dintel_gt.c1008 intel_sseu_dump(&info->sseu, p);
H A Dintel_lrc.c1592 intel_sseu_make_rpcs(engine->gt, &ce->sseu);
H A Dintel_rps.c1274 switch (gt->info.sseu.eu_total) {
/linux-master/drivers/gpu/drm/i915/
H A Di915_getparam.c20 const struct sseu_dev_info *sseu = &to_gt(i915)->info.sseu; local
78 value = intel_sseu_subslice_total(sseu);
83 value = sseu->eu_total;
100 value = sseu->min_eu_in_pool;
166 value = sseu->slice_mask;
176 value = intel_sseu_get_hsw_subslices(sseu, 0);
H A Di915_query.c32 static int fill_topology_info(const struct sseu_dev_info *sseu, argument
38 int ss_stride = GEN_SSEU_STRIDE(sseu->max_subslices);
39 int eu_stride = GEN_SSEU_STRIDE(sseu->max_eus_per_subslice);
42 BUILD_BUG_ON(sizeof(u8) != sizeof(sseu->slice_mask));
44 if (sseu->max_slices == 0)
47 slice_length = sizeof(sseu->slice_mask);
48 subslice_length = sseu->max_slices * ss_stride;
49 eu_length = sseu->max_slices * sseu->max_subslices * eu_stride;
59 topo.max_slices = sseu
93 const struct sseu_dev_info *sseu = &to_gt(dev_priv)->info.sseu; local
104 const struct sseu_dev_info *sseu; local
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H A Di915_perf_types.h442 * @sseu: sseu configuration selected to run while perf is active,
445 struct intel_sseu sseu; member in struct:i915_perf_gt
H A Di915_perf.c354 * @has_sseu: Whether @sseu was specified by userspace
355 * @sseu: internal SSEU configuration computed either from the userspace
381 struct intel_sseu sseu; member in struct:perf_open_properties
2594 flex->value = intel_sseu_make_rpcs(ce->engine->gt, &ce->sseu);
2741 regs[0].value = intel_sseu_make_rpcs(engine->gt, &ce->sseu);
3190 const struct sseu_dev_info *devinfo_sseu = &engine->gt->info.sseu;
3382 stream->engine->gt->perf.sseu = props->sseu;
3892 get_default_sseu_config(&props->sseu, props->engine);
4137 "Unable to copy global sseu paramete
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H A Di915_gpu_error.c729 intel_sseu_print_topology(gt->_gt->i915, &gt->info.sseu, &p);
/linux-master/drivers/gpu/drm/i915/gem/
H A Di915_gem_context_types.h124 /** @sseu: Client-set SSEU parameters */
125 struct intel_sseu sseu; member in struct:i915_gem_proto_engine
H A Di915_gem_context.c820 struct intel_sseu *sseu; local
856 sseu = &pe->sseu;
866 sseu = &pc->legacy_rcs_sseu;
869 ret = i915_gem_user_to_context_sseu(to_gt(i915), &user_sseu, sseu);
962 struct intel_sseu sseu)
992 if (sseu.slice_mask && !WARN_ON(ce->engine->class != RENDER_CLASS))
993 ret = intel_context_reconfigure_sseu(ce, sseu);
1116 struct intel_sseu sseu = {}; local
1135 sseu
960 intel_context_set_gem(struct intel_context *ce, struct i915_gem_context *ctx, struct intel_sseu sseu) argument
1999 struct intel_sseu sseu; local
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/linux-master/drivers/gpu/drm/i915/gem/selftests/
H A Di915_gem_context.c1169 unsigned int slices = hweight32(ce->engine->sseu.slice_mask);
1174 ret = intel_engine_reset(ce->engine, "sseu");
1210 struct intel_sseu sseu)
1221 ret = intel_context_reconfigure_sseu(ce, sseu);
1226 hweight32(sseu.slice_mask), spin);
1271 if (hweight32(engine->sseu.slice_mask) < 2)
1274 if (!engine->gt->info.sseu.has_slice_pg)
1281 pg_sseu = engine->sseu;
1284 ~(~0 << (hweight32(engine->sseu.subslice_mask) / 2));
1288 hweight32(engine->sseu
1206 __sseu_test(const char *name, unsigned int flags, struct intel_context *ce, struct drm_i915_gem_object *obj, struct intel_sseu sseu) argument
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/linux-master/drivers/gpu/drm/i915/gt/uc/
H A Dintel_guc_ads.c814 hweight8(gt->info.sseu.slice_mask));

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