Searched refs:spll_func_cntl (Results 1 - 12 of 12) sorted by relevance
/linux-master/drivers/gpu/drm/radeon/ |
H A D | rv730_dpm.c | 43 u32 spll_func_cntl = pi->clk_regs.rv730.cg_spll_func_cntl; local 73 spll_func_cntl |= SPLL_DIVEN; 75 spll_func_cntl &= ~SPLL_DIVEN; 76 spll_func_cntl &= ~(SPLL_HILEN_MASK | SPLL_LOLEN_MASK | SPLL_REF_DIV_MASK); 77 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div); 78 spll_func_cntl |= SPLL_HILEN((dividers.post_div >> 4) & 0xf); 79 spll_func_cntl |= SPLL_LOLEN(dividers.post_div & 0xf); 107 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl); 235 u32 spll_func_cntl; local 284 spll_func_cntl [all...] |
H A D | rv740_dpm.c | 124 u32 spll_func_cntl = pi->clk_regs.rv770.cg_spll_func_cntl; local 146 spll_func_cntl &= ~(SPLL_PDIV_A_MASK | SPLL_REF_DIV_MASK); 147 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div); 148 spll_func_cntl |= SPLL_PDIV_A(dividers.post_div); 176 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl); 325 u32 spll_func_cntl = pi->clk_regs.rv770.cg_spll_func_cntl; local 371 spll_func_cntl |= SPLL_RESET | SPLL_SLEEP | SPLL_BYPASS_EN; 385 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl);
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H A D | rv770_dpm.c | 491 u32 spll_func_cntl = local 524 spll_func_cntl |= SPLL_DIVEN; 526 spll_func_cntl &= ~SPLL_DIVEN; 527 spll_func_cntl &= ~(SPLL_HILEN_MASK | SPLL_LOLEN_MASK | SPLL_REF_DIV_MASK); 528 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div); 529 spll_func_cntl |= SPLL_HILEN((dividers.post_div >> 4) & 0xf); 530 spll_func_cntl |= SPLL_LOLEN(dividers.post_div & 0xf); 558 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl); 929 u32 spll_func_cntl = local 978 spll_func_cntl | [all...] |
H A D | ni_dpm.c | 1800 u32 spll_func_cntl = ni_pi->clock_registers.cg_spll_func_cntl; local 1912 table->ACPIState.level.sclk.vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl); 2005 u32 spll_func_cntl = ni_pi->clock_registers.cg_spll_func_cntl; local 2029 spll_func_cntl &= ~(SPLL_PDIV_A_MASK | SPLL_REF_DIV_MASK); 2030 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div); 2031 spll_func_cntl |= SPLL_PDIV_A(dividers.post_div); 2059 sclk->vCG_SPLL_FUNC_CNTL = spll_func_cntl;
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H A D | cypress_dpm.c | 1346 u32 spll_func_cntl = local 1431 spll_func_cntl |= SPLL_RESET | SPLL_SLEEP | SPLL_BYPASS_EN; 1451 cpu_to_be32(spll_func_cntl);
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H A D | si_dpm.c | 4430 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl; local 4534 cpu_to_be32(spll_func_cntl); 4726 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl; local 4749 spll_func_cntl &= ~(SPLL_PDIV_A_MASK | SPLL_REF_DIV_MASK); 4750 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div); 4751 spll_func_cntl |= SPLL_PDIV_A(dividers.post_div); 4779 sclk->vCG_SPLL_FUNC_CNTL = spll_func_cntl;
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H A D | ci_dpm.c | 2951 u32 spll_func_cntl = pi->clock_registers.cg_spll_func_cntl; local 2978 spll_func_cntl &= ~SPLL_PWRON; 2979 spll_func_cntl |= SPLL_RESET; 2984 table->ACPILevel.CgSpllFuncCntl = spll_func_cntl;
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/linux-master/drivers/gpu/drm/amd/pm/powerplay/smumgr/ |
H A D | fiji_smumgr.c | 860 uint32_t spll_func_cntl = data->clock_registers.vCG_SPLL_FUNC_CNTL; local 885 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL, 887 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL, 1307 uint32_t spll_func_cntl = data->clock_registers.vCG_SPLL_FUNC_CNTL; local 1343 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL, 1345 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNT [all...] |
H A D | iceland_smumgr.c | 800 uint32_t spll_func_cntl = data->clock_registers.vCG_SPLL_FUNC_CNTL; local 825 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, 827 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, 1431 uint32_t spll_func_cntl = data->clock_registers.vCG_SPLL_FUNC_CNTL; local 1461 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, 1463 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, [all...] |
H A D | tonga_smumgr.c | 543 uint32_t spll_func_cntl = data->clock_registers.vCG_SPLL_FUNC_CNTL; local 568 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, 570 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, 1183 uint32_t spll_func_cntl = data->clock_registers.vCG_SPLL_FUNC_CNTL; local 1210 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL, 1212 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNT [all...] |
H A D | ci_smumgr.c | 302 uint32_t spll_func_cntl = data->clock_registers.vCG_SPLL_FUNC_CNTL; local 327 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL, 329 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL, 1385 uint32_t spll_func_cntl = data->clock_registers.vCG_SPLL_FUNC_CNTL; local 1415 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, 1417 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, [all...] |
/linux-master/drivers/gpu/drm/amd/pm/legacy-dpm/ |
H A D | si_dpm.c | 4976 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl; local 5081 cpu_to_be32(spll_func_cntl); 5272 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl; local 5295 spll_func_cntl &= ~(SPLL_PDIV_A_MASK | SPLL_REF_DIV_MASK); 5296 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div); 5297 spll_func_cntl |= SPLL_PDIV_A(dividers.post_div); 5325 sclk->vCG_SPLL_FUNC_CNTL = spll_func_cntl;
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