Searched refs:smu_wm_set (Results 1 - 12 of 12) sorted by path

/linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/
H A Dvg_clk_mgr.c446 struct watermarks *table = clk_mgr_vgh->smu_wm_set.wm_set;
451 if (!table || clk_mgr_vgh->smu_wm_set.mc_address.quad_part == 0)
459 clk_mgr_vgh->smu_wm_set.mc_address.high_part);
461 clk_mgr_vgh->smu_wm_set.mc_address.low_part);
683 clk_mgr->smu_wm_set.wm_set = (struct watermarks *)dm_helpers_allocate_gpu_mem(
687 &clk_mgr->smu_wm_set.mc_address.quad_part);
689 if (!clk_mgr->smu_wm_set.wm_set) {
690 clk_mgr->smu_wm_set.wm_set = &dummy_wms;
691 clk_mgr->smu_wm_set.mc_address.quad_part = 0;
693 ASSERT(clk_mgr->smu_wm_set
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H A Dvg_clk_mgr.h42 struct smu_watermark_set smu_wm_set; member in struct:clk_mgr_vgh
/linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/
H A Ddcn31_clk_mgr.c480 struct dcn31_watermarks *table = clk_mgr_dcn31->smu_wm_set.wm_set;
485 if (!table || clk_mgr_dcn31->smu_wm_set.mc_address.quad_part == 0)
493 clk_mgr_dcn31->smu_wm_set.mc_address.high_part);
495 clk_mgr_dcn31->smu_wm_set.mc_address.low_part);
694 clk_mgr->smu_wm_set.wm_set = (struct dcn31_watermarks *)dm_helpers_allocate_gpu_mem(
698 &clk_mgr->smu_wm_set.mc_address.quad_part);
700 if (!clk_mgr->smu_wm_set.wm_set) {
701 clk_mgr->smu_wm_set.wm_set = &dummy_wms;
702 clk_mgr->smu_wm_set.mc_address.quad_part = 0;
704 ASSERT(clk_mgr->smu_wm_set
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H A Ddcn31_clk_mgr.h39 struct dcn31_smu_watermark_set smu_wm_set; member in struct:clk_mgr_dcn31
/linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/
H A Ddcn314_clk_mgr.c545 struct dcn314_watermarks *table = clk_mgr_dcn314->smu_wm_set.wm_set;
550 if (!table || clk_mgr_dcn314->smu_wm_set.mc_address.quad_part == 0)
558 clk_mgr_dcn314->smu_wm_set.mc_address.high_part);
560 clk_mgr_dcn314->smu_wm_set.mc_address.low_part);
805 clk_mgr->smu_wm_set.wm_set = (struct dcn314_watermarks *)dm_helpers_allocate_gpu_mem(
809 &clk_mgr->smu_wm_set.mc_address.quad_part);
811 if (!clk_mgr->smu_wm_set.wm_set) {
812 clk_mgr->smu_wm_set.wm_set = &dummy_wms;
813 clk_mgr->smu_wm_set.mc_address.quad_part = 0;
815 ASSERT(clk_mgr->smu_wm_set
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H A Ddcn314_clk_mgr.h42 struct dcn314_smu_watermark_set smu_wm_set; member in struct:clk_mgr_dcn314
/linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/
H A Ddcn315_clk_mgr.c440 struct dcn315_watermarks *table = clk_mgr_dcn315->smu_wm_set.wm_set;
445 if (!table || clk_mgr_dcn315->smu_wm_set.mc_address.quad_part == 0)
453 clk_mgr_dcn315->smu_wm_set.mc_address.high_part);
455 clk_mgr_dcn315->smu_wm_set.mc_address.low_part);
624 clk_mgr->smu_wm_set.wm_set = (struct dcn315_watermarks *)dm_helpers_allocate_gpu_mem(
628 &clk_mgr->smu_wm_set.mc_address.quad_part);
630 if (!clk_mgr->smu_wm_set.wm_set) {
631 clk_mgr->smu_wm_set.wm_set = &dummy_wms;
632 clk_mgr->smu_wm_set.mc_address.quad_part = 0;
634 ASSERT(clk_mgr->smu_wm_set
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H A Ddcn315_clk_mgr.h39 struct dcn315_smu_watermark_set smu_wm_set; member in struct:clk_mgr_dcn315
/linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/
H A Ddcn316_clk_mgr.c402 struct dcn316_watermarks *table = clk_mgr_dcn316->smu_wm_set.wm_set;
407 if (!table || clk_mgr_dcn316->smu_wm_set.mc_address.quad_part == 0)
415 clk_mgr_dcn316->smu_wm_set.mc_address.high_part);
417 clk_mgr_dcn316->smu_wm_set.mc_address.low_part);
595 clk_mgr->smu_wm_set.wm_set = (struct dcn316_watermarks *)dm_helpers_allocate_gpu_mem(
599 &clk_mgr->smu_wm_set.mc_address.quad_part);
601 if (!clk_mgr->smu_wm_set.wm_set) {
602 clk_mgr->smu_wm_set.wm_set = &dummy_wms;
603 clk_mgr->smu_wm_set.mc_address.quad_part = 0;
605 ASSERT(clk_mgr->smu_wm_set
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H A Ddcn316_clk_mgr.h39 struct dcn316_smu_watermark_set smu_wm_set; member in struct:clk_mgr_dcn316
/linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/
H A Ddcn35_clk_mgr.c628 struct dcn35_watermarks *table = clk_mgr_dcn35->smu_wm_set.wm_set;
633 if (!table || clk_mgr_dcn35->smu_wm_set.mc_address.quad_part == 0)
641 clk_mgr_dcn35->smu_wm_set.mc_address.high_part);
643 clk_mgr_dcn35->smu_wm_set.mc_address.low_part);
1028 clk_mgr->smu_wm_set.wm_set = (struct dcn35_watermarks *)dm_helpers_allocate_gpu_mem(
1032 &clk_mgr->smu_wm_set.mc_address.quad_part);
1034 if (!clk_mgr->smu_wm_set.wm_set) {
1035 clk_mgr->smu_wm_set.wm_set = &dummy_wms;
1036 clk_mgr->smu_wm_set.mc_address.quad_part = 0;
1038 ASSERT(clk_mgr->smu_wm_set
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H A Ddcn35_clk_mgr.h46 struct dcn35_smu_watermark_set smu_wm_set; member in struct:clk_mgr_dcn35

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