Searched refs:sclk_table (Results 1 - 15 of 15) sorted by relevance

/linux-master/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dsmu7_hwmgr.c746 &data->dpm_table.sclk_table,
804 data->dpm_table.sclk_table.count = 0;
807 if (i == 0 || data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count-1].value !=
809 data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].value =
811 data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].enabled = (i == 0) ? 1 : 0;
812 data->dpm_table.sclk_table.count++;
898 data->dpm_table.sclk_table
2055 struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table = NULL; local
2207 struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table = local
2288 phm_ppt_v1_clock_voltage_dependency_table *sclk_table = pptable_info->vdd_dep_on_sclk; local
4084 struct smu7_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table); local
4962 struct smu7_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table); local
5084 struct smu7_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table); local
5171 struct phm_clock_voltage_dependency_table *sclk_table; local
5411 struct smu7_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table); local
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H A Dprocess_pptables_v1_0.c407 phm_ppt_v1_clock_voltage_dependency_table *sclk_table; local
418 sclk_table = kzalloc(struct_size(sclk_table, entries, tonga_table->ucNumEntries),
420 if (!sclk_table)
423 sclk_table->count = (uint32_t)tonga_table->ucNumEntries;
431 entries, sclk_table, i);
447 sclk_table = kzalloc(struct_size(sclk_table, entries, polaris_table->ucNumEntries),
449 if (!sclk_table)
452 sclk_table
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H A Dsmu7_hwmgr.h104 struct smu7_single_dpm_table sclk_table; member in struct:smu7_dpm_table
H A Dvega10_hwmgr.c3417 struct vega10_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table); local
3425 for (i = 0; i < sclk_table->count; i++) {
3426 if (sclk == sclk_table->dpm_levels[i].value)
3430 if (i >= sclk_table->count) {
3431 if (sclk > sclk_table->dpm_levels[i-1].value) {
3433 sclk_table->dpm_levels[i-1].value = sclk;
4649 struct vega10_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table); local
4673 count = sclk_table->count;
4676 i, sclk_table->dpm_levels[i].value / 100,
4795 struct vega10_single_dpm_table *sclk_table local
5104 struct vega10_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table); local
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H A Dsmu8_hwmgr.c1560 struct phm_clock_voltage_dependency_table *sclk_table = local
1573 for (i = 0; i < sclk_table->count; i++)
1575 i, sclk_table->entries[i].clk / 100,
H A Dvega12_hwmgr.c2691 struct vega12_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table);
2694 int value = sclk_table->dpm_levels[sclk_table->count - 1].value;
H A Dvega20_hwmgr.c1469 struct vega20_single_dpm_table *sclk_table = local
1473 int value = sclk_table->dpm_levels[sclk_table->count - 1].value;
/linux-master/drivers/gpu/drm/amd/pm/powerplay/smumgr/
H A Dvegam_smumgr.c888 for (i = 0; i < dpm_table->sclk_table.count; i++) {
891 dpm_table->sclk_table.dpm_levels[i].value,
909 (uint8_t)dpm_table->sclk_table.count;
911 phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
913 for (i = 0; i < dpm_table->sclk_table.count; i++)
922 for (i = 0; i < dpm_table->sclk_table.count; i++)
947 for (i = 2; i < dpm_table->sclk_table.count; i++)
1287 for (i = 0; i < hw_data->dpm_table.sclk_table.count; i++) {
1290 hw_data->dpm_table.sclk_table.dpm_levels[i].value,
1374 result = phm_find_boot_level(&(data->dpm_table.sclk_table),
1495 struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table = local
1575 struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table = local
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H A Dfiji_smumgr.c1022 for (i = 0; i < dpm_table->sclk_table.count; i++) {
1024 dpm_table->sclk_table.dpm_levels[i].value,
1038 levels[dpm_table->sclk_table.count - 1].DisplayWatermark =
1042 (uint8_t)dpm_table->sclk_table.count;
1044 phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
1051 for (i = 0; i < dpm_table->sclk_table.count; i++)
1076 for (i = 2; i < dpm_table->sclk_table.count; i++)
1316 data->dpm_table.sclk_table.dpm_levels[0].value;
1532 for (i = 0; i < data->dpm_table.sclk_table.count; i++) {
1535 data->dpm_table.sclk_table
1670 struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table = local
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H A Dpolaris10_smumgr.c1067 for (i = 0; i < dpm_table->sclk_table.count; i++) {
1070 dpm_table->sclk_table.dpm_levels[i].value,
1084 dpm_table->sclk_table.dpm_levels[0].value,
1091 dividers.real_clock < dpm_table->sclk_table.dpm_levels[0].value ?
1098 (uint8_t)dpm_table->sclk_table.count;
1100 phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
1111 for (i = 0; i < dpm_table->sclk_table.count; i++)
1136 for (i = 2; i < dpm_table->sclk_table.count; i++)
1498 for (i = 0; i < hw_data->dpm_table.sclk_table.count; i++) {
1501 hw_data->dpm_table.sclk_table
1656 struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table = local
1784 struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table = local
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H A Dtonga_smumgr.c710 for (i = 0; i < dpm_table->sclk_table.count; i++) {
712 dpm_table->sclk_table.dpm_levels[i].value,
726 if (dpm_table->sclk_table.count > 1)
727 smu_data->smc_state_table.GraphicsLevel[dpm_table->sclk_table.count-1].DisplayWatermark =
731 (uint8_t)dpm_table->sclk_table.count;
733 phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
740 for (i = 0; i < dpm_table->sclk_table.count; i++) {
770 for (i = 2; i < dpm_table->sclk_table.count; i++)
1497 for (i = 0; i < data->dpm_table.sclk_table.count; i++) {
1500 (hwmgr, data->dpm_table.sclk_table
1584 struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table = local
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H A Diceland_smumgr.c980 for (i = 0; i < dpm_table->sclk_table.count; i++) {
982 dpm_table->sclk_table.dpm_levels[i].value,
996 if (dpm_table->sclk_table.count > 1)
997 smu_data->smc_state_table.GraphicsLevel[dpm_table->sclk_table.count-1].DisplayWatermark =
1001 (uint8_t)dpm_table->sclk_table.count;
1003 phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
1026 for (i = 2; i < dpm_table->sclk_table.count; i++) {
1621 for (i = 0; i < data->dpm_table.sclk_table.count; i++) {
1624 (hwmgr, data->dpm_table.sclk_table.dpm_levels[i].value,
1657 result = phm_find_boot_level(&(data->dpm_table.sclk_table),
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H A Dci_smumgr.c486 for (i = 0; i < dpm_table->sclk_table.count; i++) {
488 dpm_table->sclk_table.dpm_levels[i].value,
494 if (i == (dpm_table->sclk_table.count - 1))
501 smu_data->smc_state_table.GraphicsDpmLevelCount = (u8)dpm_table->sclk_table.count;
503 phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
1660 for (i = 0; i < data->dpm_table.sclk_table.count; i++) {
1663 (hwmgr, data->dpm_table.sclk_table.dpm_levels[i].value,
1696 result = phm_find_boot_level(&(data->dpm_table.sclk_table),
/linux-master/drivers/gpu/drm/radeon/
H A Dci_dpm.h69 struct ci_single_dpm_table sclk_table; member in struct:ci_dpm_table
H A Dci_dpm.c2511 for (i = 0; i < pi->dpm_table.sclk_table.count; i++) {
2514 pi->dpm_table.sclk_table.dpm_levels[i].value,
3245 for (i = 0; i < dpm_table->sclk_table.count; i++) {
3247 dpm_table->sclk_table.dpm_levels[i].value,
3254 if (i == (dpm_table->sclk_table.count - 1))
3260 pi->smc_state_table.GraphicsDpmLevelCount = (u8)dpm_table->sclk_table.count;
3262 ci_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
3420 &pi->dpm_table.sclk_table,
3435 pi->dpm_table.sclk_table.count = 0;
3438 (pi->dpm_table.sclk_table
3816 struct ci_single_dpm_table *sclk_table = &pi->dpm_table.sclk_table; local
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