/linux-master/arch/arm/mach-pxa/ |
H A D | reset.h | 12 extern void pxa_register_wdt(unsigned int reset_status);
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H A D | devices.c | 716 void __init pxa_register_wdt(unsigned int reset_status) argument 720 reset_status &= RESET_STATUS_WATCHDOG; 722 &reset_status, sizeof(reset_status));
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/linux-master/drivers/input/misc/ |
H A D | atc260x-onkey.c | 75 enum atc260x_onkey_reset_status reset_status, 89 if (reset_status == KEY_RESET_DISABLED) { 91 } else if (reset_status == KEY_RESET_USER_SEL) { 195 enum atc260x_onkey_reset_status reset_status; local 206 reset_status = KEY_RESET_HW_DEFAULT; 213 reset_status = KEY_RESET_USER_SEL; 216 reset_status = KEY_RESET_DISABLED; 284 error = atc2603x_onkey_hw_init(onkey, reset_status, 74 atc2603x_onkey_hw_init(struct atc260x_onkey *onkey, enum atc260x_onkey_reset_status reset_status, u32 reset_time, u32 press_time) argument
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/linux-master/drivers/s390/crypto/ |
H A D | vfio_ap_private.h | 138 * @reset_status: the status from the last reset of the queue 149 struct ap_queue_status reset_status; member in struct:vfio_ap_queue
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H A D | vfio_ap_ops.c | 667 switch (q->reset_status.response_code) { 1740 memcpy(&status, &q->reset_status, sizeof(status)); 1756 if (q->reset_status.response_code == AP_RESPONSE_RESET_IN_PROGRESS || 1757 q->reset_status.response_code == AP_RESPONSE_BUSY || 1758 q->reset_status.response_code == AP_RESPONSE_STATE_CHANGE_IN_PROGRESS || 1761 memcpy(&q->reset_status, &status, sizeof(status)); 1778 memcpy(&q->reset_status, &status, sizeof(status)); 1812 if (q->reset_status.response_code) 1830 if (q->reset_status.response_code) 2174 memset(&q->reset_status, [all...] |
/linux-master/drivers/gpu/drm/xe/ |
H A D | xe_exec_queue_types.h | 194 /** @reset_status: check exec queue reset status */ 195 bool (*reset_status)(struct xe_exec_queue *q); member in struct:xe_exec_queue_ops
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H A D | xe_wait_user_fence.c | 150 if (q->ops->reset_status(q)) {
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H A D | xe_execlist.c | 452 .reset_status = execlist_exec_queue_reset_status,
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H A D | xe_guc_submit.c | 1408 .reset_status = guc_exec_queue_reset_status,
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/linux-master/drivers/gpu/drm/amd/display/modules/hdcp/ |
H A D | hdcp.c | 538 enum mod_hdcp_status exec_status, trans_status, reset_status, status; local 563 reset_status = reset_authentication(hdcp, output); 564 if (reset_status != MOD_HDCP_STATUS_SUCCESS) 565 push_error_status(hdcp, reset_status);
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/linux-master/include/soc/tegra/ |
H A D | mc.h | 138 int (*reset_status)(struct tegra_mc *mc, member in struct:tegra_mc_reset_ops
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/linux-master/drivers/memory/tegra/ |
H A D | mc.c | 184 .reset_status = tegra_mc_reset_status_common, 222 if (rst_ops->reset_status) { 224 if (rst_ops->reset_status(mc, rst)) 318 return rst_ops->reset_status(mc, rst);
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H A D | tegra20.c | 361 .reset_status = tegra20_mc_reset_status,
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/linux-master/drivers/sbus/char/ |
H A D | uctrl.c | 97 u8 reset_status; /* 0x0b */ member in struct:uctrl_status
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/linux-master/drivers/gpu/drm/amd/amdgpu/ |
H A D | amdgpu_ctx.c | 564 out->state.reset_status = AMDGPU_CTX_NO_RESET; 566 out->state.reset_status = AMDGPU_CTX_UNKNOWN_RESET;
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/linux-master/drivers/message/fusion/ |
H A D | mptbase.h | 756 u8 reset_status; member in struct:_MPT_ADAPTER
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H A D | mptbase.c | 7169 return ioc->reset_status; 7212 ioc->reset_status = rc;
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/linux-master/include/uapi/drm/ |
H A D | amdgpu_drm.h | 306 __u32 reset_status; member in struct:drm_amdgpu_ctx_out::__anon1268
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/linux-master/drivers/scsi/smartpqi/ |
H A D | smartpqi_init.c | 3607 enum pqi_soft_reset_status reset_status; local 3610 reset_status = pqi_poll_for_soft_reset_status(ctrl_info); 3612 reset_status = RESET_INITIATE_FIRMWARE; 3616 switch (reset_status) { 3649 reset_status);
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/linux-master/drivers/net/ethernet/hisilicon/hns3/hns3pf/ |
H A D | hclge_main.c | 10686 u8 *reset_status) 10704 *reset_status = hnae3_get_bit(req->ready_to_reset, HCLGE_TQP_RESET_B); 10725 u8 reset_status; local 10742 &reset_status); 10746 if (reset_status) 10685 hclge_get_reset_status(struct hclge_dev *hdev, u16 queue_id, u8 *reset_status) argument
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