1// SPDX-License-Identifier: GPL-2.0-only
2/* uctrl.c: TS102 Microcontroller interface on Tadpole Sparcbook 3
3 *
4 * Copyright 1999 Derrick J Brashear (shadow@dementia.org)
5 * Copyright 2008 David S. Miller (davem@davemloft.net)
6 */
7
8#include <linux/module.h>
9#include <linux/errno.h>
10#include <linux/delay.h>
11#include <linux/interrupt.h>
12#include <linux/slab.h>
13#include <linux/mutex.h>
14#include <linux/ioport.h>
15#include <linux/miscdevice.h>
16#include <linux/mm.h>
17#include <linux/of.h>
18#include <linux/platform_device.h>
19
20#include <asm/openprom.h>
21#include <asm/oplib.h>
22#include <asm/irq.h>
23#include <asm/io.h>
24
25#define DEBUG 1
26#ifdef DEBUG
27#define dprintk(x) printk x
28#else
29#define dprintk(x)
30#endif
31
32struct uctrl_regs {
33	u32 uctrl_intr;
34	u32 uctrl_data;
35	u32 uctrl_stat;
36	u32 uctrl_xxx[5];
37};
38
39struct ts102_regs {
40	u32 card_a_intr;
41	u32 card_a_stat;
42	u32 card_a_ctrl;
43	u32 card_a_xxx;
44	u32 card_b_intr;
45	u32 card_b_stat;
46	u32 card_b_ctrl;
47	u32 card_b_xxx;
48	u32 uctrl_intr;
49	u32 uctrl_data;
50	u32 uctrl_stat;
51	u32 uctrl_xxx;
52	u32 ts102_xxx[4];
53};
54
55/* Bits for uctrl_intr register */
56#define UCTRL_INTR_TXE_REQ         0x01    /* transmit FIFO empty int req */
57#define UCTRL_INTR_TXNF_REQ        0x02    /* transmit FIFO not full int req */
58#define UCTRL_INTR_RXNE_REQ        0x04    /* receive FIFO not empty int req */
59#define UCTRL_INTR_RXO_REQ         0x08    /* receive FIFO overflow int req */
60#define UCTRL_INTR_TXE_MSK         0x10    /* transmit FIFO empty mask */
61#define UCTRL_INTR_TXNF_MSK        0x20    /* transmit FIFO not full mask */
62#define UCTRL_INTR_RXNE_MSK        0x40    /* receive FIFO not empty mask */
63#define UCTRL_INTR_RXO_MSK         0x80    /* receive FIFO overflow mask */
64
65/* Bits for uctrl_stat register */
66#define UCTRL_STAT_TXE_STA         0x01    /* transmit FIFO empty status */
67#define UCTRL_STAT_TXNF_STA        0x02    /* transmit FIFO not full status */
68#define UCTRL_STAT_RXNE_STA        0x04    /* receive FIFO not empty status */
69#define UCTRL_STAT_RXO_STA         0x08    /* receive FIFO overflow status */
70
71static DEFINE_MUTEX(uctrl_mutex);
72static const char *uctrl_extstatus[16] = {
73        "main power available",
74        "internal battery attached",
75        "external battery attached",
76        "external VGA attached",
77        "external keyboard attached",
78        "external mouse attached",
79        "lid down",
80        "internal battery currently charging",
81        "external battery currently charging",
82        "internal battery currently discharging",
83        "external battery currently discharging",
84};
85
86/* Everything required for one transaction with the uctrl */
87struct uctrl_txn {
88	u8 opcode;
89	u8 inbits;
90	u8 outbits;
91	u8 *inbuf;
92	u8 *outbuf;
93};
94
95struct uctrl_status {
96	u8 current_temp; /* 0x07 */
97	u8 reset_status; /* 0x0b */
98	u16 event_status; /* 0x0c */
99	u16 error_status; /* 0x10 */
100	u16 external_status; /* 0x11, 0x1b */
101	u8 internal_charge; /* 0x18 */
102	u8 external_charge; /* 0x19 */
103	u16 control_lcd; /* 0x20 */
104	u8 control_bitport; /* 0x21 */
105	u8 speaker_volume; /* 0x23 */
106	u8 control_tft_brightness; /* 0x24 */
107	u8 control_kbd_repeat_delay; /* 0x28 */
108	u8 control_kbd_repeat_period; /* 0x29 */
109	u8 control_screen_contrast; /* 0x2F */
110};
111
112enum uctrl_opcode {
113  READ_SERIAL_NUMBER=0x1,
114  READ_ETHERNET_ADDRESS=0x2,
115  READ_HARDWARE_VERSION=0x3,
116  READ_MICROCONTROLLER_VERSION=0x4,
117  READ_MAX_TEMPERATURE=0x5,
118  READ_MIN_TEMPERATURE=0x6,
119  READ_CURRENT_TEMPERATURE=0x7,
120  READ_SYSTEM_VARIANT=0x8,
121  READ_POWERON_CYCLES=0x9,
122  READ_POWERON_SECONDS=0xA,
123  READ_RESET_STATUS=0xB,
124  READ_EVENT_STATUS=0xC,
125  READ_REAL_TIME_CLOCK=0xD,
126  READ_EXTERNAL_VGA_PORT=0xE,
127  READ_MICROCONTROLLER_ROM_CHECKSUM=0xF,
128  READ_ERROR_STATUS=0x10,
129  READ_EXTERNAL_STATUS=0x11,
130  READ_USER_CONFIGURATION_AREA=0x12,
131  READ_MICROCONTROLLER_VOLTAGE=0x13,
132  READ_INTERNAL_BATTERY_VOLTAGE=0x14,
133  READ_DCIN_VOLTAGE=0x15,
134  READ_HORIZONTAL_POINTER_VOLTAGE=0x16,
135  READ_VERTICAL_POINTER_VOLTAGE=0x17,
136  READ_INTERNAL_BATTERY_CHARGE_LEVEL=0x18,
137  READ_EXTERNAL_BATTERY_CHARGE_LEVEL=0x19,
138  READ_REAL_TIME_CLOCK_ALARM=0x1A,
139  READ_EVENT_STATUS_NO_RESET=0x1B,
140  READ_INTERNAL_KEYBOARD_LAYOUT=0x1C,
141  READ_EXTERNAL_KEYBOARD_LAYOUT=0x1D,
142  READ_EEPROM_STATUS=0x1E,
143  CONTROL_LCD=0x20,
144  CONTROL_BITPORT=0x21,
145  SPEAKER_VOLUME=0x23,
146  CONTROL_TFT_BRIGHTNESS=0x24,
147  CONTROL_WATCHDOG=0x25,
148  CONTROL_FACTORY_EEPROM_AREA=0x26,
149  CONTROL_KBD_TIME_UNTIL_REPEAT=0x28,
150  CONTROL_KBD_TIME_BETWEEN_REPEATS=0x29,
151  CONTROL_TIMEZONE=0x2A,
152  CONTROL_MARK_SPACE_RATIO=0x2B,
153  CONTROL_DIAGNOSTIC_MODE=0x2E,
154  CONTROL_SCREEN_CONTRAST=0x2F,
155  RING_BELL=0x30,
156  SET_DIAGNOSTIC_STATUS=0x32,
157  CLEAR_KEY_COMBINATION_TABLE=0x33,
158  PERFORM_SOFTWARE_RESET=0x34,
159  SET_REAL_TIME_CLOCK=0x35,
160  RECALIBRATE_POINTING_STICK=0x36,
161  SET_BELL_FREQUENCY=0x37,
162  SET_INTERNAL_BATTERY_CHARGE_RATE=0x39,
163  SET_EXTERNAL_BATTERY_CHARGE_RATE=0x3A,
164  SET_REAL_TIME_CLOCK_ALARM=0x3B,
165  READ_EEPROM=0x40,
166  WRITE_EEPROM=0x41,
167  WRITE_TO_STATUS_DISPLAY=0x42,
168  DEFINE_SPECIAL_CHARACTER=0x43,
169  DEFINE_KEY_COMBINATION_ENTRY=0x50,
170  DEFINE_STRING_TABLE_ENTRY=0x51,
171  DEFINE_STATUS_SCREEN_DISPLAY=0x52,
172  PERFORM_EMU_COMMANDS=0x64,
173  READ_EMU_REGISTER=0x65,
174  WRITE_EMU_REGISTER=0x66,
175  READ_EMU_RAM=0x67,
176  WRITE_EMU_RAM=0x68,
177  READ_BQ_REGISTER=0x69,
178  WRITE_BQ_REGISTER=0x6A,
179  SET_USER_PASSWORD=0x70,
180  VERIFY_USER_PASSWORD=0x71,
181  GET_SYSTEM_PASSWORD_KEY=0x72,
182  VERIFY_SYSTEM_PASSWORD=0x73,
183  POWER_OFF=0x82,
184  POWER_RESTART=0x83,
185};
186
187static struct uctrl_driver {
188	struct uctrl_regs __iomem *regs;
189	int irq;
190	int pending;
191	struct uctrl_status status;
192} *global_driver;
193
194static void uctrl_get_event_status(struct uctrl_driver *);
195static void uctrl_get_external_status(struct uctrl_driver *);
196
197static long
198uctrl_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
199{
200	switch (cmd) {
201		default:
202			return -EINVAL;
203	}
204	return 0;
205}
206
207static int
208uctrl_open(struct inode *inode, struct file *file)
209{
210	mutex_lock(&uctrl_mutex);
211	uctrl_get_event_status(global_driver);
212	uctrl_get_external_status(global_driver);
213	mutex_unlock(&uctrl_mutex);
214	return 0;
215}
216
217static irqreturn_t uctrl_interrupt(int irq, void *dev_id)
218{
219	return IRQ_HANDLED;
220}
221
222static const struct file_operations uctrl_fops = {
223	.owner =	THIS_MODULE,
224	.llseek =	no_llseek,
225	.unlocked_ioctl =	uctrl_ioctl,
226	.open =		uctrl_open,
227};
228
229static struct miscdevice uctrl_dev = {
230	UCTRL_MINOR,
231	"uctrl",
232	&uctrl_fops
233};
234
235/* Wait for space to write, then write to it */
236#define WRITEUCTLDATA(value) \
237{ \
238  unsigned int i; \
239  for (i = 0; i < 10000; i++) { \
240      if (UCTRL_STAT_TXNF_STA & sbus_readl(&driver->regs->uctrl_stat)) \
241      break; \
242  } \
243  dprintk(("write data 0x%02x\n", value)); \
244  sbus_writel(value, &driver->regs->uctrl_data); \
245}
246
247/* Wait for something to read, read it, then clear the bit */
248#define READUCTLDATA(value) \
249{ \
250  unsigned int i; \
251  value = 0; \
252  for (i = 0; i < 10000; i++) { \
253      if ((UCTRL_STAT_RXNE_STA & sbus_readl(&driver->regs->uctrl_stat)) == 0) \
254      break; \
255    udelay(1); \
256  } \
257  value = sbus_readl(&driver->regs->uctrl_data); \
258  dprintk(("read data 0x%02x\n", value)); \
259  sbus_writel(UCTRL_STAT_RXNE_STA, &driver->regs->uctrl_stat); \
260}
261
262static void uctrl_do_txn(struct uctrl_driver *driver, struct uctrl_txn *txn)
263{
264	int stat, incnt, outcnt, bytecnt, intr;
265	u32 byte;
266
267	stat = sbus_readl(&driver->regs->uctrl_stat);
268	intr = sbus_readl(&driver->regs->uctrl_intr);
269	sbus_writel(stat, &driver->regs->uctrl_stat);
270
271	dprintk(("interrupt stat 0x%x int 0x%x\n", stat, intr));
272
273	incnt = txn->inbits;
274	outcnt = txn->outbits;
275	byte = (txn->opcode << 8);
276	WRITEUCTLDATA(byte);
277
278	bytecnt = 0;
279	while (incnt > 0) {
280		byte = (txn->inbuf[bytecnt] << 8);
281		WRITEUCTLDATA(byte);
282		incnt--;
283		bytecnt++;
284	}
285
286	/* Get the ack */
287	READUCTLDATA(byte);
288	dprintk(("ack was %x\n", (byte >> 8)));
289
290	bytecnt = 0;
291	while (outcnt > 0) {
292		READUCTLDATA(byte);
293		txn->outbuf[bytecnt] = (byte >> 8);
294		dprintk(("set byte to %02x\n", byte));
295		outcnt--;
296		bytecnt++;
297	}
298}
299
300static void uctrl_get_event_status(struct uctrl_driver *driver)
301{
302	struct uctrl_txn txn;
303	u8 outbits[2];
304
305	txn.opcode = READ_EVENT_STATUS;
306	txn.inbits = 0;
307	txn.outbits = 2;
308	txn.inbuf = NULL;
309	txn.outbuf = outbits;
310
311	uctrl_do_txn(driver, &txn);
312
313	dprintk(("bytes %x %x\n", (outbits[0] & 0xff), (outbits[1] & 0xff)));
314	driver->status.event_status =
315		((outbits[0] & 0xff) << 8) | (outbits[1] & 0xff);
316	dprintk(("ev is %x\n", driver->status.event_status));
317}
318
319static void uctrl_get_external_status(struct uctrl_driver *driver)
320{
321	struct uctrl_txn txn;
322	u8 outbits[2];
323	int i, v;
324
325	txn.opcode = READ_EXTERNAL_STATUS;
326	txn.inbits = 0;
327	txn.outbits = 2;
328	txn.inbuf = NULL;
329	txn.outbuf = outbits;
330
331	uctrl_do_txn(driver, &txn);
332
333	dprintk(("bytes %x %x\n", (outbits[0] & 0xff), (outbits[1] & 0xff)));
334	driver->status.external_status =
335		((outbits[0] * 256) + (outbits[1]));
336	dprintk(("ex is %x\n", driver->status.external_status));
337	v = driver->status.external_status;
338	for (i = 0; v != 0; i++, v >>= 1) {
339		if (v & 1) {
340			dprintk(("%s%s", " ", uctrl_extstatus[i]));
341		}
342	}
343	dprintk(("\n"));
344
345}
346
347static int uctrl_probe(struct platform_device *op)
348{
349	struct uctrl_driver *p;
350	int err = -ENOMEM;
351
352	p = kzalloc(sizeof(*p), GFP_KERNEL);
353	if (!p) {
354		printk(KERN_ERR "uctrl: Unable to allocate device struct.\n");
355		goto out;
356	}
357
358	p->regs = of_ioremap(&op->resource[0], 0,
359			     resource_size(&op->resource[0]),
360			     "uctrl");
361	if (!p->regs) {
362		printk(KERN_ERR "uctrl: Unable to map registers.\n");
363		goto out_free;
364	}
365
366	p->irq = op->archdata.irqs[0];
367	err = request_irq(p->irq, uctrl_interrupt, 0, "uctrl", p);
368	if (err) {
369		printk(KERN_ERR "uctrl: Unable to register irq.\n");
370		goto out_iounmap;
371	}
372
373	err = misc_register(&uctrl_dev);
374	if (err) {
375		printk(KERN_ERR "uctrl: Unable to register misc device.\n");
376		goto out_free_irq;
377	}
378
379	sbus_writel(UCTRL_INTR_RXNE_REQ|UCTRL_INTR_RXNE_MSK, &p->regs->uctrl_intr);
380	printk(KERN_INFO "%pOF: uctrl regs[0x%p] (irq %d)\n",
381	       op->dev.of_node, p->regs, p->irq);
382	uctrl_get_event_status(p);
383	uctrl_get_external_status(p);
384
385	dev_set_drvdata(&op->dev, p);
386	global_driver = p;
387
388out:
389	return err;
390
391out_free_irq:
392	free_irq(p->irq, p);
393
394out_iounmap:
395	of_iounmap(&op->resource[0], p->regs, resource_size(&op->resource[0]));
396
397out_free:
398	kfree(p);
399	goto out;
400}
401
402static void uctrl_remove(struct platform_device *op)
403{
404	struct uctrl_driver *p = dev_get_drvdata(&op->dev);
405
406	if (p) {
407		misc_deregister(&uctrl_dev);
408		free_irq(p->irq, p);
409		of_iounmap(&op->resource[0], p->regs, resource_size(&op->resource[0]));
410		kfree(p);
411	}
412}
413
414static const struct of_device_id uctrl_match[] = {
415	{
416		.name = "uctrl",
417	},
418	{},
419};
420MODULE_DEVICE_TABLE(of, uctrl_match);
421
422static struct platform_driver uctrl_driver = {
423	.driver = {
424		.name = "uctrl",
425		.of_match_table = uctrl_match,
426	},
427	.probe		= uctrl_probe,
428	.remove_new	= uctrl_remove,
429};
430
431
432module_platform_driver(uctrl_driver);
433
434MODULE_LICENSE("GPL");
435