Searched refs:reset_domain (Results 1 - 19 of 19) sorted by relevance

/linux-master/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_reset.c114 struct amdgpu_reset_domain *reset_domain = container_of(ref, local
117 if (reset_domain->wq)
118 destroy_workqueue(reset_domain->wq);
120 kvfree(reset_domain);
126 struct amdgpu_reset_domain *reset_domain; local
128 reset_domain = kvzalloc(sizeof(struct amdgpu_reset_domain), GFP_KERNEL);
129 if (!reset_domain) {
134 reset_domain->type = type;
135 kref_init(&reset_domain->refcount);
137 reset_domain
152 amdgpu_device_lock_reset_domain(struct amdgpu_reset_domain *reset_domain) argument
159 amdgpu_device_unlock_reset_domain(struct amdgpu_reset_domain *reset_domain) argument
[all...]
H A Damdgpu_reset.h140 void amdgpu_device_lock_reset_domain(struct amdgpu_reset_domain *reset_domain);
142 void amdgpu_device_unlock_reset_domain(struct amdgpu_reset_domain *reset_domain);
H A Damdgpu_xgmi.h45 struct amdgpu_reset_domain *reset_domain; member in struct:amdgpu_hive_info
H A Dmxgpu_ai.c262 if (atomic_cmpxchg(&adev->reset_domain->in_gpu_reset, 0, 1) != 0)
265 down_write(&adev->reset_domain->sem);
280 atomic_set(&adev->reset_domain->in_gpu_reset, 0);
281 up_write(&adev->reset_domain->sem);
321 WARN_ONCE(!amdgpu_reset_domain_schedule(adev->reset_domain,
H A Dmxgpu_nv.c295 if (atomic_cmpxchg(&adev->reset_domain->in_gpu_reset, 0, 1) != 0)
298 down_write(&adev->reset_domain->sem);
313 atomic_set(&adev->reset_domain->in_gpu_reset, 0);
314 up_write(&adev->reset_domain->sem);
360 WARN_ONCE(!amdgpu_reset_domain_schedule(adev->reset_domain,
H A Damdgpu_ras_eeprom.c268 down_read(&adev->reset_domain->sem);
273 up_read(&adev->reset_domain->sem);
329 down_read(&adev->reset_domain->sem);
334 up_read(&adev->reset_domain->sem);
581 down_read(&adev->reset_domain->sem);
587 up_read(&adev->reset_domain->sem);
761 down_read(&adev->reset_domain->sem);
766 up_read(&adev->reset_domain->sem);
871 down_read(&adev->reset_domain->sem);
877 up_read(&adev->reset_domain
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H A Damdgpu_amdkfd_arcturus.c321 if (!down_read_trylock(&adev->reset_domain->sem))
339 up_read(&adev->reset_domain->sem);
H A Damdgpu_xgmi.c347 amdgpu_reset_put_reset_domain(hive->reset_domain);
348 hive->reset_domain = NULL;
632 * Only init hive->reset_domain for none SRIOV configuration. For SRIOV,
643 if (adev->reset_domain->type != XGMI_HIVE) {
644 hive->reset_domain =
646 if (!hive->reset_domain) {
654 amdgpu_reset_get_reset_domain(adev->reset_domain);
655 hive->reset_domain = adev->reset_domain;
H A Damdgpu_debugfs.c1673 r = down_write_killable(&adev->reset_domain->sem);
1702 up_write(&adev->reset_domain->sem);
1938 r = down_read_killable(&adev->reset_domain->sem);
1979 up_read(&adev->reset_domain->sem);
2040 ret = down_read_killable(&adev->reset_domain->sem);
2046 up_read(&adev->reset_domain->sem);
2051 ret = down_read_killable(&adev->reset_domain->sem);
2056 up_read(&adev->reset_domain->sem);
2098 ret = down_write_killable(&adev->reset_domain->sem);
2105 up_write(&adev->reset_domain
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H A Damdgpu_device.c508 if (down_read_trylock(&adev->reset_domain->sem))
509 up_read(&adev->reset_domain->sem);
511 lockdep_assert_held(&adev->reset_domain->sem);
537 down_read_trylock(&adev->reset_domain->sem)) {
539 up_read(&adev->reset_domain->sem);
605 down_read_trylock(&adev->reset_domain->sem)) {
607 up_read(&adev->reset_domain->sem);
664 down_read_trylock(&adev->reset_domain->sem)) {
666 up_read(&adev->reset_domain->sem);
736 down_read_trylock(&adev->reset_domain
[all...]
H A Damdgpu_gmc.c631 if (!down_read_trylock(&adev->reset_domain->sem))
644 up_read(&adev->reset_domain->sem);
691 !down_read_trylock(&adev->reset_domain->sem)) {
745 up_read(&adev->reset_domain->sem);
H A Damdgpu_fence.c957 if (amdgpu_reset_domain_schedule(adev->reset_domain, &adev->reset_work))
960 *val = atomic_read(&adev->reset_domain->reset_res);
H A Dmxgpu_vi.c564 WARN_ONCE(!amdgpu_reset_domain_schedule(adev->reset_domain,
H A Damdgpu_amdkfd.c287 amdgpu_reset_domain_schedule(adev->reset_domain,
H A Damdgpu.h1134 struct amdgpu_reset_domain *reset_domain; member in struct:amdgpu_device
H A Damdgpu_ras.c3668 amdgpu_reset_domain_schedule(ras->adev->reset_domain, &ras->recovery_work);
/linux-master/drivers/gpu/drm/i915/gt/
H A Dintel_engine_types.h372 u32 reset_domain; member in struct:intel_engine_cs
H A Dintel_engine_cs.c398 u32 reset_domain; local
432 reset_domain = engine_reset_domains[id];
443 reset_domain = engine_reset_domains[id];
446 return reset_domain;
484 engine->reset_domain = get_reset_domain(GRAPHICS_VER(gt->i915),
H A Dintel_reset.c335 hw_mask |= engine->reset_domain;
536 reset_mask |= engine->reset_domain;

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