Searched refs:regmap_write (Results 1 - 25 of 1163) sorted by relevance

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/linux-master/drivers/phy/qualcomm/
H A Dphy-qcom-sgmii-eth.c36 regmap_write(regmap, QSERDES_PCS + QPHY_PCS_SW_RESET, 0x01);
37 regmap_write(regmap, QSERDES_PCS + QPHY_PCS_POWER_DOWN_CONTROL, 0x01);
39 regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_PLL_IVCO, 0x0F);
40 regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_CP_CTRL_MODE0, 0x06);
41 regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16);
42 regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36);
43 regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_SYSCLK_EN_SEL, 0x1A);
44 regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0A);
45 regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1A);
46 regmap_write(regma
[all...]
H A Dphy-qcom-eusb2-repeater.c135 regmap_write(regmap, base + EUSB2_EN_CTL1, EUSB2_RPTR_EN);
137 regmap_write(regmap, base + EUSB2_TUNE_EUSB_HS_COMP_CUR, init_tbl[TUNE_EUSB_HS_COMP_CUR]);
138 regmap_write(regmap, base + EUSB2_TUNE_EUSB_EQU, init_tbl[TUNE_EUSB_EQU]);
139 regmap_write(regmap, base + EUSB2_TUNE_EUSB_SLEW, init_tbl[TUNE_EUSB_SLEW]);
140 regmap_write(regmap, base + EUSB2_TUNE_USB2_HS_COMP_CUR, init_tbl[TUNE_USB2_HS_COMP_CUR]);
141 regmap_write(regmap, base + EUSB2_TUNE_USB2_EQU, init_tbl[TUNE_USB2_EQU]);
142 regmap_write(regmap, base + EUSB2_TUNE_USB2_SLEW, init_tbl[TUNE_USB2_SLEW]);
143 regmap_write(regmap, base + EUSB2_TUNE_SQUELCH_U, init_tbl[TUNE_SQUELCH_U]);
144 regmap_write(regmap, base + EUSB2_TUNE_RES_FSDIF, init_tbl[TUNE_RES_FSDIF]);
145 regmap_write(regma
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/linux-master/drivers/iio/imu/inv_mpu6050/
H A Dinv_mpu_aux.c29 ret = regmap_write(st->map, st->reg->sample_rate_div, d);
35 ret = regmap_write(st->map, st->reg->user_ctrl, user_ctrl);
44 ret = regmap_write(st->map, st->reg->user_ctrl, user_ctrl);
50 ret = regmap_write(st->map, st->reg->sample_rate_div, d);
57 regmap_write(st->map, st->reg->user_ctrl, st->chip_config.user_ctrl);
59 regmap_write(st->map, st->reg->sample_rate_div, st->chip_config.divider);
90 ret = regmap_write(st->map, INV_MPU6050_REG_I2C_MST_CTRL, val);
95 ret = regmap_write(st->map, INV_MPU6050_REG_I2C_SLV4_CTRL, 0);
104 return regmap_write(st->map, INV_MPU6050_REG_I2C_MST_DELAY_CTRL, val);
127 ret = regmap_write(s
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/linux-master/drivers/gpu/drm/sprd/
H A Dmegacores_pll.c102 regmap_write(regmap, reg_addr[i], reg_val[i]);
131 regmap_write(regmap, 0x31, val[CLK]);
132 regmap_write(regmap, 0x41, val[DATA]);
133 regmap_write(regmap, 0x51, val[DATA]);
134 regmap_write(regmap, 0x61, val[DATA]);
135 regmap_write(regmap, 0x71, val[DATA]);
137 regmap_write(regmap, 0x90, val[CLK]);
138 regmap_write(regmap, 0xa0, val[DATA]);
139 regmap_write(regmap, 0xb0, val[DATA]);
140 regmap_write(regma
[all...]
/linux-master/drivers/power/reset/
H A Darm-versatile-reboot.c79 regmap_write(syscon_regmap, INTEGRATOR_HDR_LOCK_OFFSET,
87 regmap_write(syscon_regmap, VERSATILE_SYS_LOCK_OFFSET,
93 regmap_write(syscon_regmap, VERSATILE_SYS_LOCK_OFFSET,
97 regmap_write(syscon_regmap, VERSATILE_SYS_LOCK_OFFSET,
99 regmap_write(syscon_regmap,
103 regmap_write(syscon_regmap, VERSATILE_SYS_LOCK_OFFSET,
105 regmap_write(syscon_regmap,
110 regmap_write(syscon_regmap, VERSATILE_SYS_LOCK_OFFSET,
112 regmap_write(syscon_regmap, VERSATILE_SYS_RESETCTL_OFFSET,
114 regmap_write(syscon_regma
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/linux-master/drivers/gpu/drm/bridge/adv7511/
H A Dadv7533.c42 regmap_write(adv->regmap_cec, 0x16,
46 regmap_write(adv->regmap_cec, 0x28, mode->htotal >> 4);
47 regmap_write(adv->regmap_cec, 0x29, (mode->htotal << 4) & 0xff);
48 regmap_write(adv->regmap_cec, 0x2a, hsw >> 4);
49 regmap_write(adv->regmap_cec, 0x2b, (hsw << 4) & 0xff);
50 regmap_write(adv->regmap_cec, 0x2c, hfp >> 4);
51 regmap_write(adv->regmap_cec, 0x2d, (hfp << 4) & 0xff);
52 regmap_write(adv->regmap_cec, 0x2e, hbp >> 4);
53 regmap_write(adv->regmap_cec, 0x2f, (hbp << 4) & 0xff);
56 regmap_write(ad
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/linux-master/drivers/gpu/drm/bridge/
H A Dlontium-lt9611.c147 regmap_write(lt9611->regmap, 0x830d, (u8)(v_total / 256));
148 regmap_write(lt9611->regmap, 0x830e, (u8)(v_total % 256));
150 regmap_write(lt9611->regmap, 0x830f, (u8)(vactive / 256));
151 regmap_write(lt9611->regmap, 0x8310, (u8)(vactive % 256));
153 regmap_write(lt9611->regmap, 0x8311, (u8)(h_total / 256));
154 regmap_write(lt9611->regmap, 0x8312, (u8)(h_total % 256));
156 regmap_write(lt9611->regmap, 0x8313, (u8)(hactive / 256));
157 regmap_write(lt9611->regmap, 0x8314, (u8)(hactive % 256));
159 regmap_write(lt9611->regmap, 0x8315, (u8)(vsync_len % 256));
160 regmap_write(lt961
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H A Dchrontel-ch7033.c337 regmap_write(priv->regmap, 0x03, 0x04);
345 regmap_write(priv->regmap, 0x03, 0x04);
362 regmap_write(priv->regmap, 0x03, 0x04);
365 regmap_write(priv->regmap, 0x52, 0x00);
367 regmap_write(priv->regmap, 0x52, RESETIB);
372 regmap_write(priv->regmap, 0x03, 0x00);
382 regmap_write(priv->regmap, 0x0b, (mode->htotal >> 8) << 3 |
384 regmap_write(priv->regmap, 0x0c, mode->hdisplay);
385 regmap_write(priv->regmap, 0x0d, mode->htotal);
386 regmap_write(pri
[all...]
/linux-master/drivers/media/platform/nxp/imx8-isi/
H A Dimx8-isi-gasket.c34 regmap_write(isi->gasket, GASKET_BASE(port) + GASKET_HSIZE, fmt->width);
35 regmap_write(isi->gasket, GASKET_BASE(port) + GASKET_VSIZE, fmt->height);
42 regmap_write(isi->gasket, GASKET_BASE(port) + GASKET_CTRL, val);
48 regmap_write(isi->gasket, GASKET_BASE(port) + GASKET_CTRL, 0);
73 regmap_write(isi->gasket, DISP_MIX_CAMERA_MUX, val);
79 regmap_write(isi->gasket, DISP_MIX_CAMERA_MUX, 0);
/linux-master/sound/soc/codecs/
H A Dmt6358.c333 regmap_write(priv->regmap, MT6358_ZCD_CON0, 0x0000);
894 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0006);
896 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON0, 0xCBA1);
898 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0003);
900 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x000B);
911 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0000);
912 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON0, 0xcba0);
936 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0006);
938 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON0, 0xCBA1);
940 regmap_write(pri
[all...]
H A Drt700.c38 ret = regmap_write(regmap, addr, value);
280 regmap_write(rt700->regmap,
285 regmap_write(rt700->regmap,
287 regmap_write(rt700->regmap,
289 regmap_write(rt700->regmap,
299 regmap_write(rt700->regmap,
301 regmap_write(rt700->regmap,
303 regmap_write(rt700->regmap,
311 regmap_write(rt700->regmap,
403 regmap_write(rt70
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H A Drt715.c41 ret = regmap_write(regmap, addr, value);
56 ret = regmap_write(regmap, addr, value);
97 regmap_write(regmap, RT715_FUNC_RESET, 0);
156 regmap_write(rt715->regmap,
182 regmap_write(rt715->regmap, addr_h,
184 regmap_write(rt715->regmap, addr_l,
189 regmap_write(rt715->regmap, addr_h,
193 regmap_write(rt715->regmap, addr_l,
210 regmap_write(rt715->regmap,
278 regmap_write(rt71
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H A Drt1305.c393 regmap_write(regmap, RT1305_RESET, 0);
999 regmap_write(rt1305->regmap, RT1305_ADC_SET_3, 0x0219);
1000 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xcf, 0x5548);
1001 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xc1, 0x0320);
1002 regmap_write(rt1305->regmap, RT1305_CLOCK_DETECT, 0x1000);
1003 regmap_write(rt1305->regmap, RT1305_CLK_1, 0x0600);
1004 regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xffd0);
1005 regmap_write(rt1305->regmap, RT1305_EFUSE_1, 0x0080);
1006 regmap_write(rt1305->regmap, RT1305_EFUSE_1, 0x0880);
1007 regmap_write(rt130
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H A Drt1308-sdw.c115 regmap_write(rt1308->regmap, 0xe0, value);
116 regmap_write(rt1308->regmap, 0xf0, value);
173 regmap_write(rt1308->regmap, 0xc7f0, 0x04);
174 regmap_write(rt1308->regmap, 0xc7f1, 0xfe);
176 regmap_write(rt1308->regmap, 0xc7f0, 0x44);
178 regmap_write(rt1308->regmap, 0xc240, 0x10);
209 regmap_write(rt1308->regmap, reg, data);
240 regmap_write(rt1308->regmap, RT1308_SDW_RESET, 0);
247 regmap_write(rt1308->regmap, 0xc103, 0xc0);
248 regmap_write(rt130
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H A Des8326.c81 regmap_write(es8326->regmap, ES8326_DAC_CROSSTALK, crosstalk_l);
119 regmap_write(es8326->regmap, ES8326_DAC_CROSSTALK, crosstalk_l);
568 regmap_write(es8326->regmap, ES8326_CLK_DIV1,
570 regmap_write(es8326->regmap, ES8326_CLK_DIV2,
572 regmap_write(es8326->regmap, ES8326_CLK_DLL,
574 regmap_write(es8326->regmap, ES8326_CLK_MUX,
576 regmap_write(es8326->regmap, ES8326_CLK_ADC_SEL,
578 regmap_write(es8326->regmap, ES8326_CLK_DAC_SEL,
580 regmap_write(es8326->regmap, ES8326_CLK_ADC_OSR,
582 regmap_write(es832
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/linux-master/drivers/regulator/
H A Draa215300.c87 regmap_write(regmap, RAA215300_REG_BLOCK_EN, val);
91 regmap_write(regmap, RAA215300_FAULT_LATCHED_STATUS_1, val);
93 regmap_write(regmap, RAA215300_FAULT_LATCHED_STATUS_2, val);
95 regmap_write(regmap, RAA215300_FAULT_LATCHED_STATUS_3, val);
97 regmap_write(regmap, RAA215300_FAULT_LATCHED_STATUS_4, val);
99 regmap_write(regmap, RAA215300_FAULT_LATCHED_STATUS_6, val);
102 regmap_write(regmap, RAA215300_INT_MASK_1, RAA215300_INT_MASK_1_ALL);
103 regmap_write(regmap, RAA215300_INT_MASK_2, RAA215300_INT_MASK_2_ALL);
104 regmap_write(regmap, RAA215300_INT_MASK_3, RAA215300_INT_MASK_3_ALL);
105 regmap_write(regma
[all...]
/linux-master/drivers/clocksource/
H A Dtimer-atmel-st.c100 regmap_write(regmap_st, AT91_ST_IDR, AT91_ST_PITS | AT91_ST_ALMS);
109 regmap_write(regmap_st, AT91_ST_IER, irqmask);
122 regmap_write(regmap_st, AT91_ST_RTAR, last_crtr);
123 regmap_write(regmap_st, AT91_ST_IER, irqmask);
133 regmap_write(regmap_st, AT91_ST_PIMR, timer_latch);
134 regmap_write(regmap_st, AT91_ST_IER, irqmask);
158 regmap_write(regmap_st, AT91_ST_RTAR, alm);
163 regmap_write(regmap_st, AT91_ST_RTAR, alm);
196 regmap_write(regmap_st, AT91_ST_IDR,
239 regmap_write(regmap_s
[all...]
/linux-master/drivers/media/dvb-frontends/
H A Drtl2832_sdr.c550 ret = regmap_write(dev->regmap, 0x1b1, u8tmp1);
554 ret = regmap_write(dev->regmap, 0x008, u8tmp2);
558 ret = regmap_write(dev->regmap, 0x006, 0x80);
585 ret = regmap_write(dev->regmap, 0x019, 0x05);
600 ret = regmap_write(dev->regmap, 0x061, 0x60);
607 ret = regmap_write(dev->regmap, 0x112, 0x5a);
608 ret = regmap_write(dev->regmap, 0x102, 0x40);
609 ret = regmap_write(dev->regmap, 0x103, 0x5a);
610 ret = regmap_write(dev->regmap, 0x1c7, 0x30);
611 ret = regmap_write(de
[all...]
H A Dts2020.c68 ret = regmap_write(priv->regmap, u8tmp, 0x00);
86 regmap_write(priv->regmap, 0x42, 0x73);
87 regmap_write(priv->regmap, 0x05, priv->clk_out_div);
88 regmap_write(priv->regmap, 0x20, 0x27);
89 regmap_write(priv->regmap, 0x07, 0x02);
90 regmap_write(priv->regmap, 0x11, 0xff);
91 regmap_write(priv->regmap, 0x60, 0xf9);
92 regmap_write(priv->regmap, 0x08, 0x01);
93 regmap_write(priv->regmap, 0x00, 0x41);
109 regmap_write(pri
[all...]
/linux-master/drivers/phy/amlogic/
H A Dphy-meson-axg-mipi-dphy.c229 regmap_write(priv->regmap, MIPI_DSI_PHY_CTRL, 0x1);
230 regmap_write(priv->regmap, MIPI_DSI_PHY_CTRL,
247 regmap_write(priv->regmap, MIPI_DSI_CLK_TIM,
253 regmap_write(priv->regmap, MIPI_DSI_CLK_TIM1,
256 regmap_write(priv->regmap, MIPI_DSI_HS_TIM,
262 regmap_write(priv->regmap, MIPI_DSI_LP_TIM,
268 regmap_write(priv->regmap, MIPI_DSI_ANA_UP_TIM, 0x0100);
269 regmap_write(priv->regmap, MIPI_DSI_INIT_TIM,
271 regmap_write(priv->regmap, MIPI_DSI_WAKEUP_TIM,
273 regmap_write(pri
[all...]
/linux-master/drivers/media/tuners/
H A Dm88rs6000t.c108 ret = regmap_write(dev->regmap, 0x05, 0x40);
111 ret = regmap_write(dev->regmap, 0x11, 0x08);
114 ret = regmap_write(dev->regmap, 0x15, reg15);
117 ret = regmap_write(dev->regmap, 0x16, reg16);
120 ret = regmap_write(dev->regmap, 0x1D, reg1D);
123 ret = regmap_write(dev->regmap, 0x1E, reg1E);
126 ret = regmap_write(dev->regmap, 0x1F, reg1F);
129 ret = regmap_write(dev->regmap, 0x17, 0xc1);
132 ret = regmap_write(dev->regmap, 0x17, 0x81);
136 ret = regmap_write(de
[all...]
/linux-master/drivers/phy/lantiq/
H A Dphy-lantiq-vrx200-pcie.c103 regmap_write(priv->phy_regmap, PCIE_PHY_PLL_A_CTRL1, 0x120e);
106 regmap_write(priv->phy_regmap, PCIE_PHY_PLL_A_CTRL2, 0x39d7);
107 regmap_write(priv->phy_regmap, PCIE_PHY_PLL_A_CTRL3, 0x0900);
110 regmap_write(priv->phy_regmap, PCIE_PHY_RX1_EI, 0x0004);
111 regmap_write(priv->phy_regmap, PCIE_PHY_RX1_A_CTRL, 0x6803);
118 regmap_write(priv->phy_regmap, PCIE_PHY_TX1_A_CTRL2, 0x0706);
121 regmap_write(priv->phy_regmap, PCIE_PHY_TX1_CTRL3, 0x1fff);
124 regmap_write(priv->phy_regmap, PCIE_PHY_TX1_A_CTRL1, 0x0810);
131 regmap_write(priv->phy_regmap, PCIE_PHY_TX1_CTRL2, 0x2e00);
134 regmap_write(pri
[all...]
/linux-master/drivers/phy/allwinner/
H A Dphy-sun6i-mipi-dphy.c229 regmap_write(dphy->regs, SUN6I_DPHY_ANA0_REG,
236 regmap_write(dphy->regs, SUN6I_DPHY_ANA1_REG,
240 regmap_write(dphy->regs, SUN6I_DPHY_ANA4_REG,
251 regmap_write(dphy->regs, SUN6I_DPHY_ANA2_REG,
255 regmap_write(dphy->regs, SUN6I_DPHY_ANA3_REG,
267 regmap_write(dphy->regs, SUN6I_DPHY_ANA4_REG,
287 regmap_write(dphy->regs, SUN6I_DPHY_ANA3_REG,
292 regmap_write(dphy->regs, SUN6I_DPHY_ANA0_REG,
296 regmap_write(dphy->regs, SUN50I_COMBO_PHY_REG0,
303 regmap_write(dph
[all...]
/linux-master/arch/arm/mach-rockchip/
H A Dpm.c102 regmap_write(sgrf_regmap, RK3288_SGRF_SOC_CON0,
111 regmap_write(sgrf_regmap, RK3288_SGRF_CPU_CON0, SGRF_DAPDEVICEEN_WRITE);
114 regmap_write(sgrf_regmap, RK3288_SGRF_FAST_BOOT_ADDR,
137 regmap_write(pmu_regmap, RK3288_PMU_WAKEUP_CFG1,
147 regmap_write(pmu_regmap, RK3288_PMU_STABL_CNT, 32 * 30);
150 regmap_write(pmu_regmap, RK3288_PMU_OSC_CNT,
160 regmap_write(pmu_regmap, RK3288_PMU_WAKEUP_CFG1,
164 regmap_write(pmu_regmap, RK3288_PMU_STABL_CNT, 24000 * 30);
167 regmap_write(pmu_regmap, RK3288_PMU_OSC_CNT, 0);
170 regmap_write(pmu_regma
[all...]
/linux-master/drivers/clk/bcm/
H A Dclk-bcm53573-ilp.c29 regmap_write(ilp->regmap, PMU_SLOW_CLK_PERIOD, 0x10199);
30 regmap_write(ilp->regmap, 0x674, 0x10000);
39 regmap_write(ilp->regmap, PMU_SLOW_CLK_PERIOD, 0);
40 regmap_write(ilp->regmap, 0x674, 0);
53 regmap_write(regmap, PMU_XTAL_FREQ_RATIO, XTAL_CTL_EN);
85 regmap_write(regmap, PMU_XTAL_FREQ_RATIO, 0x0);

Completed in 201 milliseconds

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