Searched refs:ref_div (Results 1 - 25 of 40) sorted by relevance

12

/linux-master/arch/mips/ath79/
H A Dclock.c148 u32 ref_div; local
167 ref_div = 1;
182 ref_div = t;
205 ref_div * out_div * cpu_div);
207 ref_div * out_div * ddr_div);
209 ref_div * out_div * ahb_div);
212 static u32 __init ar934x_get_pll_freq(u32 ref, u32 ref_div, u32 nint, u32 nfrac, argument
220 do_div(t, ref_div);
225 do_div(t, ref_div * frac);
238 u32 pll, out_div, ref_div, nin local
356 u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv; local
439 u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv; local
522 u32 pll, out_div, ref_div, nint, hfrac, lfrac, clk_ctrl, postdiv; local
[all...]
/linux-master/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_pll.c79 * @ref_div: resulting reference divider
87 unsigned int *fb_div, unsigned int *ref_div)
97 *ref_div = min(max(DIV_ROUND_CLOSEST(den, post_div), 1u), ref_div_max);
98 *fb_div = DIV_ROUND_CLOSEST(nom * *ref_div * post_div, den);
102 *ref_div = DIV_ROUND_CLOSEST(*ref_div * fb_div_max, *fb_div);
120 * dot_clock = (ref_freq * feedback_div) / (ref_div * post_div)
136 unsigned ref_div_min, ref_div_max, ref_div; local
211 ref_div_max, &fb_div, &ref_div);
213 (ref_div * post_di
84 amdgpu_pll_get_fb_ref_div(struct amdgpu_device *adev, unsigned int nom, unsigned int den, unsigned int post_div, unsigned int fb_div_max, unsigned int ref_div_max, unsigned int *fb_div, unsigned int *ref_div) argument
[all...]
H A Datombios_crtc.h48 u32 ref_div,
H A Datombios_crtc.c336 /* use recommended ref_div for ss */
581 u32 ref_div,
608 args.v1.usRefDiv = cpu_to_le16(ref_div);
618 args.v2.usRefDiv = cpu_to_le16(ref_div);
628 args.v3.usRefDiv = cpu_to_le16(ref_div);
645 args.v5.ucRefDiv = ref_div;
675 args.v6.ucRefDiv = ref_div;
825 u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0; local
854 &fb_div, &frac_fb_div, &ref_div, &post_div);
861 ref_div, fb_di
575 amdgpu_atombios_crtc_program_pll(struct drm_crtc *crtc, u32 crtc_id, int pll_id, u32 encoder_mode, u32 encoder_id, u32 clock, u32 ref_div, u32 fb_div, u32 frac_fb_div, u32 post_div, int bpc, bool ss_enabled, struct amdgpu_atom_ss *ss) argument
[all...]
H A Damdgpu_atombios.h43 u32 ref_div; member in struct:atom_clock_dividers
/linux-master/drivers/gpu/drm/radeon/
H A Dradeon_display.c925 * @ref_div: resulting reference divider
932 unsigned *fb_div, unsigned *ref_div)
938 *ref_div = min(max(den/post_div, 1u), ref_div_max);
939 *fb_div = DIV_ROUND_CLOSEST(nom * *ref_div * post_div, den);
943 *ref_div = (*ref_div * fb_div_max)/(*fb_div);
960 * dot_clock = (ref_freq * feedback_div) / (ref_div * post_div)
975 unsigned ref_div_min, ref_div_max, ref_div; local
1053 ref_div_max, &fb_div, &ref_div);
1055 (ref_div * post_di
930 avivo_get_fb_ref_div(unsigned nom, unsigned den, unsigned post_div, unsigned fb_div_max, unsigned ref_div_max, unsigned *fb_div, unsigned *ref_div) argument
1176 uint32_t ref_div; local
[all...]
H A Dradeon_clocks.c43 uint32_t fb_div, ref_div, post_div, sclk; local
50 ref_div =
53 if (ref_div == 0)
56 sclk = fb_div / ref_div;
73 uint32_t fb_div, ref_div, post_div, mclk; local
80 ref_div =
83 if (ref_div == 0)
86 mclk = fb_div / ref_div;
356 int ref_div = spll->reference_div; local
358 if (!ref_div)
[all...]
H A Drv740_dpm.c140 reference_divider = 1 + dividers.ref_div;
147 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div);
215 mpll_ad_func_cntl |= CLKR(dividers.ref_div);
232 mpll_dq_func_cntl |= CLKR(dividers.ref_div);
251 u32 decoded_ref = rv740_get_decoded_reference_divider(dividers.ref_div);
H A Drs780_dpm.c87 r600_engine_clock_entry_set_reference_divider(rdev, 0, dividers.ref_div);
453 if ((min_dividers.ref_div != max_dividers.ref_div) ||
455 (max_dividers.ref_div != current_max_dividers.ref_div) ||
988 u32 ref_div = ((func_cntl & SPLL_REF_DIV_MASK) >> SPLL_REF_DIV_SHIFT) + 1; local
992 (post_div * ref_div);
1010 u32 ref_div = ((func_cntl & SPLL_REF_DIV_MASK) >> SPLL_REF_DIV_SHIFT) + 1; local
1014 (post_div * ref_div);
H A Drv730_dpm.c59 reference_divider = 1 + dividers.ref_div;
77 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div);
137 reference_divider = dividers.ref_div + 1;
152 mpll_func_cntl |= MPLL_REF_DIV(dividers.ref_div);
H A Datombios_crtc.c619 /* use recommended ref_div for ss */
821 u32 ref_div,
848 args.v1.usRefDiv = cpu_to_le16(ref_div);
858 args.v2.usRefDiv = cpu_to_le16(ref_div);
868 args.v3.usRefDiv = cpu_to_le16(ref_div);
885 args.v5.ucRefDiv = ref_div;
914 args.v6.ucRefDiv = ref_div;
1062 u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0; local
1094 &fb_div, &frac_fb_div, &ref_div, &post_div);
1097 &fb_div, &frac_fb_div, &ref_div,
815 atombios_crtc_program_pll(struct drm_crtc *crtc, u32 crtc_id, int pll_id, u32 encoder_mode, u32 encoder_id, u32 clock, u32 ref_div, u32 fb_div, u32 frac_fb_div, u32 post_div, int bpc, bool ss_enabled, struct radeon_atom_ss *ss) argument
[all...]
H A Drv770_dpm.c335 reference_divider = dividers->ref_div;
416 if ((dividers.ref_div < 1) || (dividers.ref_div > 5))
434 mpll_ad_func_cntl |= CLKR(encoded_reference_dividers[dividers.ref_div - 1]);
462 mpll_dq_func_cntl |= CLKR(encoded_reference_dividers[dividers.ref_div - 1]);
512 reference_divider = 1 + dividers.ref_div;
528 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div);
812 (MPLL_LOCK_TIME(R600_MPLLLOCKTIME_DFLT * pi->ref_div) |
2378 pi->ref_div = dividers.ref_div
[all...]
H A Drv770_dpm.h115 u32 ref_div; member in struct:rv7xx_power_info
H A Drv6xx_dpm.c530 (dividers->ref_div + 1);
567 (ref_clk / (dividers.ref_div + 1)),
573 (ref_clk / (dividers.ref_div + 1)));
606 rv6xx_memory_clock_entry_set_reference_divider(rdev, entry, dividers.ref_div);
685 (ref_clk / (dividers.ref_div + 1)),
691 (ref_clk / (dividers.ref_div + 1)));
1960 pi->spll_ref_div = dividers.ref_div + 1;
1967 pi->mpll_ref_div = dividers.ref_div + 1;
H A Dradeon_legacy_crtc.c266 static uint8_t radeon_compute_pll_gain(uint16_t ref_freq, uint16_t ref_div, argument
271 if (!ref_div)
274 vcoFreq = ((unsigned)ref_freq * fb_div) / ref_div;
H A Dcypress_dpm.c518 mpll_ad_func_cntl |= CLKR(dividers.ref_div);
535 mpll_dq_func_cntl |= CLKR(dividers.ref_div);
559 u32 decoded_ref = rv740_get_decoded_reference_divider(dividers.ref_div);
2061 pi->ref_div = dividers.ref_div + 1;
2063 pi->ref_div = R600_REFERENCEDIVIDER_DFLT;
/linux-master/drivers/media/dvb-frontends/
H A Dtda8261.c72 static const u8 ref_div[] = { 0x00, 0x01, 0x02, 0x05, 0x07 }; variable
109 buf[2] = (0x01 << 7) | ((ref_div[config->step_size] & 0x07) << 1);
/linux-master/drivers/clk/microchip/
H A Dclk-mpfs-ccc.c78 u32 mult, ref_div; local
82 ref_div = readl_relaxed(ref_div_addr) >> MPFS_CCC_REFDIV_SHIFT;
83 ref_div &= clk_div_mask(MPFS_CCC_REFDIV_WIDTH);
85 return prate * mult / (ref_div * MPFS_CCC_FIXED_DIV);
H A Dclk-mpfs.c124 u32 mult, ref_div; local
128 ref_div = readl_relaxed(ref_div_addr) >> MSSPLL_REFDIV_SHIFT;
129 ref_div &= clk_div_mask(MSSPLL_REFDIV_WIDTH);
131 return prate * mult / (ref_div * MSSPLL_FIXED_DIV);
/linux-master/drivers/net/wireless/ath/ath9k/
H A Dar9002_phy.c307 int ref_div = 5; local
313 ref_div = 10;
320 pll = SM(ref_div, AR_RTC_9160_PLL_REFDIV);
/linux-master/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_hubbub.c544 uint32_t ref_div = 0; local
547 REG_GET_2(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, &ref_div,
551 if (ref_div == 2)
/linux-master/drivers/gpu/drm/amd/display/dc/dcn35/
H A Ddcn35_hubbub.c263 uint32_t ref_div = 0; local
267 REG_GET_2(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, &ref_div,
271 if (ref_div == 2)
/linux-master/drivers/video/fbdev/aty/
H A Dradeon_base.c579 unsigned sclk, mclk, tmp, ref_div; local
689 ref_div = INPLL(PPLL_REF_DIV) & 0x3ff;
699 rinfo->pll.ref_div = ref_div;
768 rinfo->pll.ref_div = INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK;
791 rinfo->pll.ref_div = BIOS_IN16(pll_info_block + 0x10);
826 rinfo->pll.ref_div,
1614 pr_debug("ref_div = %d, ref_clk = %d, output_freq = %d\n",
1615 rinfo->pll.ref_div, rinfo->pll.ref_clk,
1624 pr_debug("ref_div
[all...]
H A Datyfb.h53 int ref_div; member in struct:pll_info
/linux-master/drivers/gpu/drm/bridge/
H A Dchipone-icn6211.c261 u8 ref_div; local
332 ref_div = PLL_REF_DIV_P(best_p >> best_p_pot) | PLL_REF_DIV_S(best_s);
334 ref_div |= PLL_REF_DIV_Pe;
339 chipone_writeb(icn, PLL_REF_DIV, ref_div);

Completed in 256 milliseconds

12