Searched refs:qos_level_high_wm (Results 1 - 20 of 20) sorted by relevance

/linux-master/drivers/gpu/drm/amd/display/dc/dcn10/
H A Ddcn10_hw_sequencer_debug.c159 (s->qos_level_high_wm * frac) / ref_clk_mhz / frac, (s->qos_level_high_wm * frac) / ref_clk_mhz % frac);
179 (s->qos_level_high_wm * frac) / ref_clk_mhz / frac, (s->qos_level_high_wm * frac) / ref_clk_mhz % frac);
312 pool->hubps[i]->inst, ttu_regs->qos_level_low_wm, ttu_regs->qos_level_high_wm, ttu_regs->min_ttu_vblank,
H A Ddcn10_hubp.c653 QoS_LEVEL_HIGH_WM, ttu_attr->qos_level_high_wm);
992 QoS_LEVEL_HIGH_WM, &ttu_attr->qos_level_high_wm);
1056 QoS_LEVEL_HIGH_WM, &s->qos_level_high_wm);
H A Ddcn10_hubp.h688 uint32_t qos_level_high_wm; member in struct:dcn_hubp_state
/linux-master/drivers/gpu/drm/amd/display/dc/dcn21/
H A Ddcn21_hubp.c480 QoS_LEVEL_HIGH_WM, &ttu_attr.qos_level_high_wm);
485 if (ttu_attr.qos_level_high_wm != dml_ttu_attr->qos_level_high_wm)
487 dml_ttu_attr->qos_level_high_wm, ttu_attr.qos_level_high_wm);
/linux-master/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_hubp.c148 QoS_LEVEL_HIGH_WM, ttu_attr->qos_level_high_wm);
1227 QoS_LEVEL_HIGH_WM, &ttu_attr->qos_level_high_wm);
1291 QoS_LEVEL_HIGH_WM, &s->qos_level_high_wm);
1572 QoS_LEVEL_HIGH_WM, &ttu_attr.qos_level_high_wm);
1577 if (ttu_attr.qos_level_high_wm != dml_ttu_attr->qos_level_high_wm)
1579 dml_ttu_attr->qos_level_high_wm, ttu_attr.qos_level_high_wm);
/linux-master/drivers/gpu/drm/amd/display/dc/dml/
H A Ddisplay_rq_dlg_helpers.c336 "DML_RQ_DLG_CALC: qos_level_high_wm = 0x%0x\n",
337 ttu_regs->qos_level_high_wm);
H A Ddisplay_mode_structs.h675 unsigned int qos_level_high_wm; member in struct:_vcs_dpi_display_ttu_regs_st
H A Ddml1_display_rq_dlg_calc.c1911 disp_ttu_regs->qos_level_high_wm = (unsigned int) (4.0 * (double) htotal
1913 ASSERT(disp_ttu_regs->qos_level_high_wm < dml_pow(2, 14));
/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn32/
H A Ddisplay_rq_dlg_calc_32.c543 ttu_regs->qos_level_high_wm = (unsigned int) (4.0 * (double) htotal * ref_freq_to_pix_freq);
608 ASSERT(ttu_regs->qos_level_high_wm < dml_pow(2, 14));
/linux-master/drivers/gpu/drm/amd/display/dc/dml2/
H A Ddml_display_rq_dlg_calc.c504 disp_ttu_regs->qos_level_high_wm = (dml_uint_t)(4.0 * (dml_float_t)htotal * ref_freq_to_pix_freq);
568 ASSERT(disp_ttu_regs->qos_level_high_wm < (dml_uint_t) dml_pow(2, 14));
H A Ddisplay_mode_util.c305 dml_print("DML: qos_level_high_wm = 0x%x\n", ttu_regs->qos_level_high_wm);
H A Ddml2_translation_helper.c1318 out->ttu_regs.qos_level_high_wm = disp_ttu_regs->qos_level_high_wm;
H A Ddisplay_mode_core_structs.h1921 dml_uint_t qos_level_high_wm; member in struct:_vcs_dpi_dml_display_ttu_regs_st
/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn21/
H A Ddisplay_rq_dlg_calc_21.c1638 disp_ttu_regs->qos_level_high_wm = (unsigned int) (4.0 * (double) htotal
1640 ASSERT(disp_ttu_regs->qos_level_high_wm < dml_pow(2, 14));
/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn31/
H A Ddisplay_rq_dlg_calc_31.c1542 disp_ttu_regs->qos_level_high_wm = (unsigned int) (4.0 * (double) htotal * ref_freq_to_pix_freq);
1543 ASSERT(disp_ttu_regs->qos_level_high_wm < dml_pow(2, 14));
/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn30/
H A Ddisplay_rq_dlg_calc_30.c1723 disp_ttu_regs->qos_level_high_wm = (unsigned int)(4.0 * (double)htotal
1725 ASSERT(disp_ttu_regs->qos_level_high_wm < dml_pow(2, 14));
/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn314/
H A Ddisplay_rq_dlg_calc_314.c1630 disp_ttu_regs->qos_level_high_wm = (unsigned int) (4.0 * (double) htotal * ref_freq_to_pix_freq);
1631 ASSERT(disp_ttu_regs->qos_level_high_wm < dml_pow(2, 14));
/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn20/
H A Ddisplay_rq_dlg_calc_20v2.c1531 disp_ttu_regs->qos_level_high_wm = (unsigned int) (4.0 * (double) htotal
1533 /*ASSERT(disp_ttu_regs->qos_level_high_wm < dml_pow(2, 14));*/
H A Ddisplay_rq_dlg_calc_20.c1530 disp_ttu_regs->qos_level_high_wm = (unsigned int) (4.0 * (double) htotal
1532 /*ASSERT(disp_ttu_regs->qos_level_high_wm < dml_pow(2, 14));*/
/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn10/
H A Ddcn10_hwseq.c203 DTN_INFO_MICRO_SEC(s->qos_level_high_wm);
275 pool->hubps[i]->inst, ttu_regs->qos_level_low_wm, ttu_regs->qos_level_high_wm, ttu_regs->min_ttu_vblank,

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