| /linux-master/drivers/clk/actions/ |
| H A D | owl-pll.c | 18 static u32 owl_pll_calculate_mul(struct owl_pll_hw *pll_hw, unsigned long rate) argument
22 mul = DIV_ROUND_CLOSEST(rate, pll_hw->bfreq);
23 if (mul < pll_hw->min_mul)
24 mul = pll_hw->min_mul;
25 else if (mul > pll_hw->max_mul)
26 mul = pll_hw->max_mul;
28 return mul & mul_mask(pll_hw);
63 struct owl_pll_hw *pll_hw = &pll->pll_hw; local
67 if (pll_hw
85 struct owl_pll_hw *pll_hw = &pll->pll_hw; local
113 struct owl_pll_hw *pll_hw = &pll->pll_hw; local
122 owl_pll_set(const struct owl_clk_common *common, const struct owl_pll_hw *pll_hw, bool enable) argument
159 struct owl_pll_hw *pll_hw = &pll->pll_hw; local
[all...] |
| H A D | owl-pll.h | 37 struct owl_pll_hw pll_hw; member in struct:owl_pll
58 .pll_hw = OWL_PLL_HW(_reg, _bfreq, _bit_idx, _shift, \
73 .pll_hw = OWL_PLL_HW(_reg, _bfreq, _bit_idx, _shift, \
88 .pll_hw = OWL_PLL_HW(_reg, _bfreq, _bit_idx, _shift, \
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| /linux-master/drivers/phy/mediatek/ |
| H A D | phy-mtk-mipi-dsi.c | 10 return container_of(hw, struct mtk_mipi_tx, pll_hw);
39 ret = clk_prepare_enable(mipi_tx->pll_hw.clk);
56 clk_disable_unprepare(mipi_tx->pll_hw.clk);
160 mipi_tx->pll_hw.init = &clk_init;
161 ret = devm_clk_hw_register(dev, &mipi_tx->pll_hw);
179 return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, &mipi_tx->pll_hw);
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| H A D | phy-mtk-hdmi.h | 34 struct clk_hw pll_hw; member in struct:mtk_hdmi_phy
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| H A D | phy-mtk-mipi-dsi.h | 33 struct clk_hw pll_hw; member in struct:mtk_mipi_tx
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| H A D | phy-mtk-hdmi.c | 22 return container_of(hw, struct mtk_hdmi_phy, pll_hw);
117 hdmi_phy->pll_hw.init = &clk_init;
118 hdmi_phy->pll = devm_clk_register(dev, &hdmi_phy->pll_hw);
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| /linux-master/drivers/clk/microchip/ |
| H A D | clk-mpfs-ccc.c | 202 struct mpfs_ccc_pll_hw_clock *pll_hw = &pll_hws[i]; local
204 pll_hw->name = devm_kasprintf(dev, GFP_KERNEL, "ccc%s_pll%u",
206 if (!pll_hw->name)
209 pll_hw->base = data->pll_base[i];
210 pll_hw->hw.init = CLK_HW_INIT_PARENTS_DATA_FIXED_SIZE(pll_hw->name,
211 pll_hw->parents,
214 ret = devm_clk_hw_register(dev, &pll_hw->hw);
217 pll_hw->id);
219 data->hw_data.hws[pll_hw
[all...] |
| /linux-master/drivers/gpu/drm/msm/disp/mdp4/ |
| H A D | mdp4_lvds_pll.c | 13 struct clk_hw pll_hw; member in struct:mdp4_lvds_pll
17 #define to_mdp4_lvds_pll(x) container_of(x, struct mdp4_lvds_pll, pll_hw)
150 lvds_pll->pll_hw.init = &pll_init;
151 clk = devm_clk_register(dev->dev, &lvds_pll->pll_hw);
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| /linux-master/drivers/clk/ |
| H A D | clk-asm9260.c | 258 struct clk_hw *pll_hw; local
278 pll_hw = clk_hw_register_fixed_rate_parent_accuracy(NULL, pll_clk, &pll_parent_data,
280 if (IS_ERR(pll_hw))
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| H A D | clk-stm32f4.c | 745 struct clk_hw *pll_hw, spinlock_t *lock)
772 pll_div->hw_pll = pll_hw;
791 struct clk_hw *pll_hw; local
821 pll_hw = &pll->gate.hw;
822 ret = clk_hw_register(NULL, pll_hw);
838 pll_hw,
840 return pll_hw;
741 clk_register_pll_div(const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags, const struct clk_div_table *table, struct clk_hw *pll_hw, spinlock_t *lock) argument
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| H A D | clk-bm1880.c | 495 struct bm1880_pll_hw_clock *pll_hw = to_bm1880_pll_clk(hw); local
499 regval = readl(pll_hw->base + pll_hw->pll.reg);
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| /linux-master/drivers/gpu/drm/omapdrm/dss/ |
| H A D | dsi.h | 332 const struct dss_pll_hw *pll_hw; member in struct:dsi_of_data
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| H A D | dsi.c | 4544 pll->hw = dsi->data->pll_hw;
4811 .pll_hw = &dss_omap3_dsi_pll_hw,
4823 .pll_hw = &dss_omap3_dsi_pll_hw,
4835 .pll_hw = &dss_omap4_dsi_pll_hw,
4849 .pll_hw = &dss_omap5_dsi_pll_hw,
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