Searched refs:phy_ctrl (Results 1 - 6 of 6) sorted by relevance

/freebsd-11-stable/sys/dev/e1000/
H A De1000_phy.c1628 u16 phy_ctrl; local
1654 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
1658 phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
1659 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
2005 * @phy_ctrl: pointer to current value of PHY_CONTROL
2014 void e1000_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl) argument
2033 *phy_ctrl &= ~MII_CR_AUTO_NEG_EN;
2038 *phy_ctrl &= ~MII_CR_FULL_DUPLEX;
2042 *phy_ctrl |= MII_CR_FULL_DUPLEX;
2049 *phy_ctrl |
2821 u16 phy_ctrl; local
[all...]
H A De1000_ich8lan.c3225 u32 phy_ctrl; local
3234 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
3237 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
3238 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3262 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
3263 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3321 u32 phy_ctrl; local
3327 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
3330 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
3331 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
5457 u32 phy_ctrl; local
5640 u32 phy_ctrl; local
[all...]
H A De1000_phy.h70 void e1000_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl);
/freebsd-11-stable/sys/dev/bwi/
H A Dif_bwi.c2926 uint16_t phy_ctrl; local
3018 phy_ctrl = __SHIFTIN(mac->mac_rf.rf_ant_mode,
3021 phy_ctrl |= BWI_TXH_PHY_C_OFDM;
3023 phy_ctrl |= BWI_TXH_PHY_C_SHPREAMBLE;
3032 hdr->txh_phy_ctrl = htole16(phy_ctrl);
3117 uint16_t phy_ctrl; local
3200 phy_ctrl = __SHIFTIN(mac->mac_rf.rf_ant_mode,
3203 phy_ctrl |= BWI_TXH_PHY_C_OFDM;
3206 phy_ctrl |= BWI_TXH_PHY_C_SHPREAMBLE;
3209 hdr->txh_phy_ctrl = htole16(phy_ctrl);
[all...]
/freebsd-11-stable/sys/contrib/octeon-sdk/
H A Dcvmx-pcieepx-defs.h6065 uint32_t phy_ctrl : 32; /**< PHY Control */ member in struct:cvmx_pcieepx_cfg517::cvmx_pcieepx_cfg517_s
6067 uint32_t phy_ctrl : 32;
H A Dcvmx-pciercx-defs.h5763 uint32_t phy_ctrl : 32; /**< PHY Control */ member in struct:cvmx_pciercx_cfg517::cvmx_pciercx_cfg517_s
5765 uint32_t phy_ctrl : 32;

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