1/***********************license start*************** 2 * Copyright (c) 2003-2012 Cavium Inc. (support@cavium.com). All rights 3 * reserved. 4 * 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: 9 * 10 * * Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 13 * * Redistributions in binary form must reproduce the above 14 * copyright notice, this list of conditions and the following 15 * disclaimer in the documentation and/or other materials provided 16 * with the distribution. 17 18 * * Neither the name of Cavium Inc. nor the names of 19 * its contributors may be used to endorse or promote products 20 * derived from this software without specific prior written 21 * permission. 22 23 * This Software, including technical data, may be subject to U.S. export control 24 * laws, including the U.S. Export Administration Act and its associated 25 * regulations, and may be subject to export or import regulations in other 26 * countries. 27 28 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29 * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR 30 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32 * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34 * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35 * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38 ***********************license end**************************************/ 39 40 41/** 42 * cvmx-pcieepx-defs.h 43 * 44 * Configuration and status register (CSR) type definitions for 45 * Octeon pcieepx. 46 * 47 * This file is auto generated. Do not edit. 48 * 49 * <hr>$Revision$<hr> 50 * 51 */ 52#ifndef __CVMX_PCIEEPX_DEFS_H__ 53#define __CVMX_PCIEEPX_DEFS_H__ 54 55#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 56static inline uint64_t CVMX_PCIEEPX_CFG000(unsigned long block_id) 57{ 58 if (!( 59 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 60 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 61 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 62 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 63 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 64 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 65 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 66 cvmx_warn("CVMX_PCIEEPX_CFG000(%lu) is invalid on this chip\n", block_id); 67 return 0x0000000000000000ull; 68} 69#else 70#define CVMX_PCIEEPX_CFG000(block_id) (0x0000000000000000ull) 71#endif 72#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 73static inline uint64_t CVMX_PCIEEPX_CFG001(unsigned long block_id) 74{ 75 if (!( 76 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 77 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 78 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 79 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 80 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 81 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 82 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 83 cvmx_warn("CVMX_PCIEEPX_CFG001(%lu) is invalid on this chip\n", block_id); 84 return 0x0000000000000004ull; 85} 86#else 87#define CVMX_PCIEEPX_CFG001(block_id) (0x0000000000000004ull) 88#endif 89#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 90static inline uint64_t CVMX_PCIEEPX_CFG002(unsigned long block_id) 91{ 92 if (!( 93 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 94 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 95 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 96 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 97 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 98 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 99 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 100 cvmx_warn("CVMX_PCIEEPX_CFG002(%lu) is invalid on this chip\n", block_id); 101 return 0x0000000000000008ull; 102} 103#else 104#define CVMX_PCIEEPX_CFG002(block_id) (0x0000000000000008ull) 105#endif 106#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 107static inline uint64_t CVMX_PCIEEPX_CFG003(unsigned long block_id) 108{ 109 if (!( 110 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 111 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 112 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 113 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 114 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 115 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 116 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 117 cvmx_warn("CVMX_PCIEEPX_CFG003(%lu) is invalid on this chip\n", block_id); 118 return 0x000000000000000Cull; 119} 120#else 121#define CVMX_PCIEEPX_CFG003(block_id) (0x000000000000000Cull) 122#endif 123#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 124static inline uint64_t CVMX_PCIEEPX_CFG004(unsigned long block_id) 125{ 126 if (!( 127 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 128 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 129 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 130 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 131 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 132 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 133 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 134 cvmx_warn("CVMX_PCIEEPX_CFG004(%lu) is invalid on this chip\n", block_id); 135 return 0x0000000000000010ull; 136} 137#else 138#define CVMX_PCIEEPX_CFG004(block_id) (0x0000000000000010ull) 139#endif 140#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 141static inline uint64_t CVMX_PCIEEPX_CFG004_MASK(unsigned long block_id) 142{ 143 if (!( 144 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 145 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 146 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 147 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 148 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 149 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 150 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 151 cvmx_warn("CVMX_PCIEEPX_CFG004_MASK(%lu) is invalid on this chip\n", block_id); 152 return 0x0000000080000010ull; 153} 154#else 155#define CVMX_PCIEEPX_CFG004_MASK(block_id) (0x0000000080000010ull) 156#endif 157#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 158static inline uint64_t CVMX_PCIEEPX_CFG005(unsigned long block_id) 159{ 160 if (!( 161 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 162 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 163 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 164 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 165 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 166 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 167 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 168 cvmx_warn("CVMX_PCIEEPX_CFG005(%lu) is invalid on this chip\n", block_id); 169 return 0x0000000000000014ull; 170} 171#else 172#define CVMX_PCIEEPX_CFG005(block_id) (0x0000000000000014ull) 173#endif 174#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 175static inline uint64_t CVMX_PCIEEPX_CFG005_MASK(unsigned long block_id) 176{ 177 if (!( 178 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 179 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 180 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 181 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 182 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 183 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 184 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 185 cvmx_warn("CVMX_PCIEEPX_CFG005_MASK(%lu) is invalid on this chip\n", block_id); 186 return 0x0000000080000014ull; 187} 188#else 189#define CVMX_PCIEEPX_CFG005_MASK(block_id) (0x0000000080000014ull) 190#endif 191#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 192static inline uint64_t CVMX_PCIEEPX_CFG006(unsigned long block_id) 193{ 194 if (!( 195 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 196 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 197 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 198 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 199 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 200 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 201 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 202 cvmx_warn("CVMX_PCIEEPX_CFG006(%lu) is invalid on this chip\n", block_id); 203 return 0x0000000000000018ull; 204} 205#else 206#define CVMX_PCIEEPX_CFG006(block_id) (0x0000000000000018ull) 207#endif 208#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 209static inline uint64_t CVMX_PCIEEPX_CFG006_MASK(unsigned long block_id) 210{ 211 if (!( 212 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 213 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 214 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 215 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 216 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 217 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 218 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 219 cvmx_warn("CVMX_PCIEEPX_CFG006_MASK(%lu) is invalid on this chip\n", block_id); 220 return 0x0000000080000018ull; 221} 222#else 223#define CVMX_PCIEEPX_CFG006_MASK(block_id) (0x0000000080000018ull) 224#endif 225#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 226static inline uint64_t CVMX_PCIEEPX_CFG007(unsigned long block_id) 227{ 228 if (!( 229 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 230 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 231 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 232 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 233 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 234 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 235 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 236 cvmx_warn("CVMX_PCIEEPX_CFG007(%lu) is invalid on this chip\n", block_id); 237 return 0x000000000000001Cull; 238} 239#else 240#define CVMX_PCIEEPX_CFG007(block_id) (0x000000000000001Cull) 241#endif 242#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 243static inline uint64_t CVMX_PCIEEPX_CFG007_MASK(unsigned long block_id) 244{ 245 if (!( 246 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 247 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 248 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 249 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 250 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 251 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 252 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 253 cvmx_warn("CVMX_PCIEEPX_CFG007_MASK(%lu) is invalid on this chip\n", block_id); 254 return 0x000000008000001Cull; 255} 256#else 257#define CVMX_PCIEEPX_CFG007_MASK(block_id) (0x000000008000001Cull) 258#endif 259#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 260static inline uint64_t CVMX_PCIEEPX_CFG008(unsigned long block_id) 261{ 262 if (!( 263 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 264 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 265 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 266 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 267 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 268 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 269 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 270 cvmx_warn("CVMX_PCIEEPX_CFG008(%lu) is invalid on this chip\n", block_id); 271 return 0x0000000000000020ull; 272} 273#else 274#define CVMX_PCIEEPX_CFG008(block_id) (0x0000000000000020ull) 275#endif 276#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 277static inline uint64_t CVMX_PCIEEPX_CFG008_MASK(unsigned long block_id) 278{ 279 if (!( 280 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 281 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 282 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 283 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 284 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 285 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 286 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 287 cvmx_warn("CVMX_PCIEEPX_CFG008_MASK(%lu) is invalid on this chip\n", block_id); 288 return 0x0000000080000020ull; 289} 290#else 291#define CVMX_PCIEEPX_CFG008_MASK(block_id) (0x0000000080000020ull) 292#endif 293#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 294static inline uint64_t CVMX_PCIEEPX_CFG009(unsigned long block_id) 295{ 296 if (!( 297 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 298 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 299 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 300 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 301 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 302 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 303 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 304 cvmx_warn("CVMX_PCIEEPX_CFG009(%lu) is invalid on this chip\n", block_id); 305 return 0x0000000000000024ull; 306} 307#else 308#define CVMX_PCIEEPX_CFG009(block_id) (0x0000000000000024ull) 309#endif 310#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 311static inline uint64_t CVMX_PCIEEPX_CFG009_MASK(unsigned long block_id) 312{ 313 if (!( 314 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 315 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 316 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 317 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 318 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 319 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 320 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 321 cvmx_warn("CVMX_PCIEEPX_CFG009_MASK(%lu) is invalid on this chip\n", block_id); 322 return 0x0000000080000024ull; 323} 324#else 325#define CVMX_PCIEEPX_CFG009_MASK(block_id) (0x0000000080000024ull) 326#endif 327#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 328static inline uint64_t CVMX_PCIEEPX_CFG010(unsigned long block_id) 329{ 330 if (!( 331 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 332 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 333 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 334 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 335 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 336 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 337 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 338 cvmx_warn("CVMX_PCIEEPX_CFG010(%lu) is invalid on this chip\n", block_id); 339 return 0x0000000000000028ull; 340} 341#else 342#define CVMX_PCIEEPX_CFG010(block_id) (0x0000000000000028ull) 343#endif 344#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 345static inline uint64_t CVMX_PCIEEPX_CFG011(unsigned long block_id) 346{ 347 if (!( 348 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 349 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 350 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 351 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 352 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 353 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 354 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 355 cvmx_warn("CVMX_PCIEEPX_CFG011(%lu) is invalid on this chip\n", block_id); 356 return 0x000000000000002Cull; 357} 358#else 359#define CVMX_PCIEEPX_CFG011(block_id) (0x000000000000002Cull) 360#endif 361#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 362static inline uint64_t CVMX_PCIEEPX_CFG012(unsigned long block_id) 363{ 364 if (!( 365 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 366 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 367 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 368 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 369 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 370 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 371 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 372 cvmx_warn("CVMX_PCIEEPX_CFG012(%lu) is invalid on this chip\n", block_id); 373 return 0x0000000000000030ull; 374} 375#else 376#define CVMX_PCIEEPX_CFG012(block_id) (0x0000000000000030ull) 377#endif 378#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 379static inline uint64_t CVMX_PCIEEPX_CFG012_MASK(unsigned long block_id) 380{ 381 if (!( 382 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 383 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 384 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 385 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 386 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 387 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 388 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 389 cvmx_warn("CVMX_PCIEEPX_CFG012_MASK(%lu) is invalid on this chip\n", block_id); 390 return 0x0000000080000030ull; 391} 392#else 393#define CVMX_PCIEEPX_CFG012_MASK(block_id) (0x0000000080000030ull) 394#endif 395#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 396static inline uint64_t CVMX_PCIEEPX_CFG013(unsigned long block_id) 397{ 398 if (!( 399 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 400 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 401 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 402 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 403 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 404 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 405 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 406 cvmx_warn("CVMX_PCIEEPX_CFG013(%lu) is invalid on this chip\n", block_id); 407 return 0x0000000000000034ull; 408} 409#else 410#define CVMX_PCIEEPX_CFG013(block_id) (0x0000000000000034ull) 411#endif 412#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 413static inline uint64_t CVMX_PCIEEPX_CFG015(unsigned long block_id) 414{ 415 if (!( 416 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 417 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 418 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 419 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 420 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 421 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 422 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 423 cvmx_warn("CVMX_PCIEEPX_CFG015(%lu) is invalid on this chip\n", block_id); 424 return 0x000000000000003Cull; 425} 426#else 427#define CVMX_PCIEEPX_CFG015(block_id) (0x000000000000003Cull) 428#endif 429#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 430static inline uint64_t CVMX_PCIEEPX_CFG016(unsigned long block_id) 431{ 432 if (!( 433 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 434 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 435 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 436 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 437 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 438 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 439 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 440 cvmx_warn("CVMX_PCIEEPX_CFG016(%lu) is invalid on this chip\n", block_id); 441 return 0x0000000000000040ull; 442} 443#else 444#define CVMX_PCIEEPX_CFG016(block_id) (0x0000000000000040ull) 445#endif 446#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 447static inline uint64_t CVMX_PCIEEPX_CFG017(unsigned long block_id) 448{ 449 if (!( 450 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 451 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 452 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 453 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 454 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 455 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 456 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 457 cvmx_warn("CVMX_PCIEEPX_CFG017(%lu) is invalid on this chip\n", block_id); 458 return 0x0000000000000044ull; 459} 460#else 461#define CVMX_PCIEEPX_CFG017(block_id) (0x0000000000000044ull) 462#endif 463#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 464static inline uint64_t CVMX_PCIEEPX_CFG020(unsigned long block_id) 465{ 466 if (!( 467 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 468 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 469 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 470 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 471 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 472 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 473 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 474 cvmx_warn("CVMX_PCIEEPX_CFG020(%lu) is invalid on this chip\n", block_id); 475 return 0x0000000000000050ull; 476} 477#else 478#define CVMX_PCIEEPX_CFG020(block_id) (0x0000000000000050ull) 479#endif 480#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 481static inline uint64_t CVMX_PCIEEPX_CFG021(unsigned long block_id) 482{ 483 if (!( 484 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 485 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 486 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 487 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 488 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 489 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 490 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 491 cvmx_warn("CVMX_PCIEEPX_CFG021(%lu) is invalid on this chip\n", block_id); 492 return 0x0000000000000054ull; 493} 494#else 495#define CVMX_PCIEEPX_CFG021(block_id) (0x0000000000000054ull) 496#endif 497#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 498static inline uint64_t CVMX_PCIEEPX_CFG022(unsigned long block_id) 499{ 500 if (!( 501 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 502 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 503 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 504 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 505 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 506 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 507 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 508 cvmx_warn("CVMX_PCIEEPX_CFG022(%lu) is invalid on this chip\n", block_id); 509 return 0x0000000000000058ull; 510} 511#else 512#define CVMX_PCIEEPX_CFG022(block_id) (0x0000000000000058ull) 513#endif 514#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 515static inline uint64_t CVMX_PCIEEPX_CFG023(unsigned long block_id) 516{ 517 if (!( 518 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 519 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 520 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 521 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 522 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 523 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 524 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 525 cvmx_warn("CVMX_PCIEEPX_CFG023(%lu) is invalid on this chip\n", block_id); 526 return 0x000000000000005Cull; 527} 528#else 529#define CVMX_PCIEEPX_CFG023(block_id) (0x000000000000005Cull) 530#endif 531#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 532static inline uint64_t CVMX_PCIEEPX_CFG028(unsigned long block_id) 533{ 534 if (!( 535 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 536 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 537 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 538 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 539 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 540 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 541 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 542 cvmx_warn("CVMX_PCIEEPX_CFG028(%lu) is invalid on this chip\n", block_id); 543 return 0x0000000000000070ull; 544} 545#else 546#define CVMX_PCIEEPX_CFG028(block_id) (0x0000000000000070ull) 547#endif 548#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 549static inline uint64_t CVMX_PCIEEPX_CFG029(unsigned long block_id) 550{ 551 if (!( 552 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 553 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 554 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 555 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 556 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 557 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 558 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 559 cvmx_warn("CVMX_PCIEEPX_CFG029(%lu) is invalid on this chip\n", block_id); 560 return 0x0000000000000074ull; 561} 562#else 563#define CVMX_PCIEEPX_CFG029(block_id) (0x0000000000000074ull) 564#endif 565#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 566static inline uint64_t CVMX_PCIEEPX_CFG030(unsigned long block_id) 567{ 568 if (!( 569 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 570 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 571 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 572 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 573 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 574 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 575 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 576 cvmx_warn("CVMX_PCIEEPX_CFG030(%lu) is invalid on this chip\n", block_id); 577 return 0x0000000000000078ull; 578} 579#else 580#define CVMX_PCIEEPX_CFG030(block_id) (0x0000000000000078ull) 581#endif 582#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 583static inline uint64_t CVMX_PCIEEPX_CFG031(unsigned long block_id) 584{ 585 if (!( 586 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 587 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 588 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 589 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 590 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 591 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 592 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 593 cvmx_warn("CVMX_PCIEEPX_CFG031(%lu) is invalid on this chip\n", block_id); 594 return 0x000000000000007Cull; 595} 596#else 597#define CVMX_PCIEEPX_CFG031(block_id) (0x000000000000007Cull) 598#endif 599#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 600static inline uint64_t CVMX_PCIEEPX_CFG032(unsigned long block_id) 601{ 602 if (!( 603 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 604 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 605 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 606 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 607 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 608 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 609 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 610 cvmx_warn("CVMX_PCIEEPX_CFG032(%lu) is invalid on this chip\n", block_id); 611 return 0x0000000000000080ull; 612} 613#else 614#define CVMX_PCIEEPX_CFG032(block_id) (0x0000000000000080ull) 615#endif 616#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 617static inline uint64_t CVMX_PCIEEPX_CFG033(unsigned long block_id) 618{ 619 if (!( 620 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 621 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 622 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 623 cvmx_warn("CVMX_PCIEEPX_CFG033(%lu) is invalid on this chip\n", block_id); 624 return 0x0000000000000084ull; 625} 626#else 627#define CVMX_PCIEEPX_CFG033(block_id) (0x0000000000000084ull) 628#endif 629#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 630static inline uint64_t CVMX_PCIEEPX_CFG034(unsigned long block_id) 631{ 632 if (!( 633 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 634 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 635 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 636 cvmx_warn("CVMX_PCIEEPX_CFG034(%lu) is invalid on this chip\n", block_id); 637 return 0x0000000000000088ull; 638} 639#else 640#define CVMX_PCIEEPX_CFG034(block_id) (0x0000000000000088ull) 641#endif 642#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 643static inline uint64_t CVMX_PCIEEPX_CFG037(unsigned long block_id) 644{ 645 if (!( 646 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 647 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 648 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 649 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 650 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 651 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 652 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 653 cvmx_warn("CVMX_PCIEEPX_CFG037(%lu) is invalid on this chip\n", block_id); 654 return 0x0000000000000094ull; 655} 656#else 657#define CVMX_PCIEEPX_CFG037(block_id) (0x0000000000000094ull) 658#endif 659#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 660static inline uint64_t CVMX_PCIEEPX_CFG038(unsigned long block_id) 661{ 662 if (!( 663 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 664 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 665 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 666 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 667 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 668 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 669 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 670 cvmx_warn("CVMX_PCIEEPX_CFG038(%lu) is invalid on this chip\n", block_id); 671 return 0x0000000000000098ull; 672} 673#else 674#define CVMX_PCIEEPX_CFG038(block_id) (0x0000000000000098ull) 675#endif 676#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 677static inline uint64_t CVMX_PCIEEPX_CFG039(unsigned long block_id) 678{ 679 if (!( 680 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 681 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 682 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 683 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 684 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 685 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 686 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 687 cvmx_warn("CVMX_PCIEEPX_CFG039(%lu) is invalid on this chip\n", block_id); 688 return 0x000000000000009Cull; 689} 690#else 691#define CVMX_PCIEEPX_CFG039(block_id) (0x000000000000009Cull) 692#endif 693#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 694static inline uint64_t CVMX_PCIEEPX_CFG040(unsigned long block_id) 695{ 696 if (!( 697 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 698 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 699 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 700 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 701 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 702 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 703 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 704 cvmx_warn("CVMX_PCIEEPX_CFG040(%lu) is invalid on this chip\n", block_id); 705 return 0x00000000000000A0ull; 706} 707#else 708#define CVMX_PCIEEPX_CFG040(block_id) (0x00000000000000A0ull) 709#endif 710#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 711static inline uint64_t CVMX_PCIEEPX_CFG041(unsigned long block_id) 712{ 713 if (!( 714 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 715 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 716 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 717 cvmx_warn("CVMX_PCIEEPX_CFG041(%lu) is invalid on this chip\n", block_id); 718 return 0x00000000000000A4ull; 719} 720#else 721#define CVMX_PCIEEPX_CFG041(block_id) (0x00000000000000A4ull) 722#endif 723#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 724static inline uint64_t CVMX_PCIEEPX_CFG042(unsigned long block_id) 725{ 726 if (!( 727 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 728 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 729 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 730 cvmx_warn("CVMX_PCIEEPX_CFG042(%lu) is invalid on this chip\n", block_id); 731 return 0x00000000000000A8ull; 732} 733#else 734#define CVMX_PCIEEPX_CFG042(block_id) (0x00000000000000A8ull) 735#endif 736#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 737static inline uint64_t CVMX_PCIEEPX_CFG064(unsigned long block_id) 738{ 739 if (!( 740 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 741 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 742 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 743 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 744 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 745 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 746 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 747 cvmx_warn("CVMX_PCIEEPX_CFG064(%lu) is invalid on this chip\n", block_id); 748 return 0x0000000000000100ull; 749} 750#else 751#define CVMX_PCIEEPX_CFG064(block_id) (0x0000000000000100ull) 752#endif 753#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 754static inline uint64_t CVMX_PCIEEPX_CFG065(unsigned long block_id) 755{ 756 if (!( 757 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 758 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 759 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 760 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 761 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 762 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 763 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 764 cvmx_warn("CVMX_PCIEEPX_CFG065(%lu) is invalid on this chip\n", block_id); 765 return 0x0000000000000104ull; 766} 767#else 768#define CVMX_PCIEEPX_CFG065(block_id) (0x0000000000000104ull) 769#endif 770#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 771static inline uint64_t CVMX_PCIEEPX_CFG066(unsigned long block_id) 772{ 773 if (!( 774 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 775 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 776 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 777 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 778 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 779 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 780 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 781 cvmx_warn("CVMX_PCIEEPX_CFG066(%lu) is invalid on this chip\n", block_id); 782 return 0x0000000000000108ull; 783} 784#else 785#define CVMX_PCIEEPX_CFG066(block_id) (0x0000000000000108ull) 786#endif 787#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 788static inline uint64_t CVMX_PCIEEPX_CFG067(unsigned long block_id) 789{ 790 if (!( 791 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 792 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 793 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 794 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 795 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 796 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 797 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 798 cvmx_warn("CVMX_PCIEEPX_CFG067(%lu) is invalid on this chip\n", block_id); 799 return 0x000000000000010Cull; 800} 801#else 802#define CVMX_PCIEEPX_CFG067(block_id) (0x000000000000010Cull) 803#endif 804#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 805static inline uint64_t CVMX_PCIEEPX_CFG068(unsigned long block_id) 806{ 807 if (!( 808 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 809 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 810 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 811 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 812 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 813 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 814 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 815 cvmx_warn("CVMX_PCIEEPX_CFG068(%lu) is invalid on this chip\n", block_id); 816 return 0x0000000000000110ull; 817} 818#else 819#define CVMX_PCIEEPX_CFG068(block_id) (0x0000000000000110ull) 820#endif 821#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 822static inline uint64_t CVMX_PCIEEPX_CFG069(unsigned long block_id) 823{ 824 if (!( 825 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 826 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 827 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 828 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 829 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 830 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 831 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 832 cvmx_warn("CVMX_PCIEEPX_CFG069(%lu) is invalid on this chip\n", block_id); 833 return 0x0000000000000114ull; 834} 835#else 836#define CVMX_PCIEEPX_CFG069(block_id) (0x0000000000000114ull) 837#endif 838#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 839static inline uint64_t CVMX_PCIEEPX_CFG070(unsigned long block_id) 840{ 841 if (!( 842 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 843 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 844 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 845 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 846 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 847 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 848 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 849 cvmx_warn("CVMX_PCIEEPX_CFG070(%lu) is invalid on this chip\n", block_id); 850 return 0x0000000000000118ull; 851} 852#else 853#define CVMX_PCIEEPX_CFG070(block_id) (0x0000000000000118ull) 854#endif 855#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 856static inline uint64_t CVMX_PCIEEPX_CFG071(unsigned long block_id) 857{ 858 if (!( 859 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 860 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 861 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 862 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 863 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 864 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 865 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 866 cvmx_warn("CVMX_PCIEEPX_CFG071(%lu) is invalid on this chip\n", block_id); 867 return 0x000000000000011Cull; 868} 869#else 870#define CVMX_PCIEEPX_CFG071(block_id) (0x000000000000011Cull) 871#endif 872#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 873static inline uint64_t CVMX_PCIEEPX_CFG072(unsigned long block_id) 874{ 875 if (!( 876 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 877 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 878 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 879 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 880 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 881 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 882 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 883 cvmx_warn("CVMX_PCIEEPX_CFG072(%lu) is invalid on this chip\n", block_id); 884 return 0x0000000000000120ull; 885} 886#else 887#define CVMX_PCIEEPX_CFG072(block_id) (0x0000000000000120ull) 888#endif 889#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 890static inline uint64_t CVMX_PCIEEPX_CFG073(unsigned long block_id) 891{ 892 if (!( 893 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 894 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 895 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 896 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 897 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 898 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 899 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 900 cvmx_warn("CVMX_PCIEEPX_CFG073(%lu) is invalid on this chip\n", block_id); 901 return 0x0000000000000124ull; 902} 903#else 904#define CVMX_PCIEEPX_CFG073(block_id) (0x0000000000000124ull) 905#endif 906#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 907static inline uint64_t CVMX_PCIEEPX_CFG074(unsigned long block_id) 908{ 909 if (!( 910 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 911 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 912 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 913 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 914 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 915 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 916 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 917 cvmx_warn("CVMX_PCIEEPX_CFG074(%lu) is invalid on this chip\n", block_id); 918 return 0x0000000000000128ull; 919} 920#else 921#define CVMX_PCIEEPX_CFG074(block_id) (0x0000000000000128ull) 922#endif 923#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 924static inline uint64_t CVMX_PCIEEPX_CFG448(unsigned long block_id) 925{ 926 if (!( 927 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 928 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 929 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 930 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 931 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 932 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 933 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 934 cvmx_warn("CVMX_PCIEEPX_CFG448(%lu) is invalid on this chip\n", block_id); 935 return 0x0000000000000700ull; 936} 937#else 938#define CVMX_PCIEEPX_CFG448(block_id) (0x0000000000000700ull) 939#endif 940#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 941static inline uint64_t CVMX_PCIEEPX_CFG449(unsigned long block_id) 942{ 943 if (!( 944 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 945 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 946 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 947 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 948 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 949 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 950 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 951 cvmx_warn("CVMX_PCIEEPX_CFG449(%lu) is invalid on this chip\n", block_id); 952 return 0x0000000000000704ull; 953} 954#else 955#define CVMX_PCIEEPX_CFG449(block_id) (0x0000000000000704ull) 956#endif 957#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 958static inline uint64_t CVMX_PCIEEPX_CFG450(unsigned long block_id) 959{ 960 if (!( 961 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 962 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 963 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 964 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 965 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 966 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 967 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 968 cvmx_warn("CVMX_PCIEEPX_CFG450(%lu) is invalid on this chip\n", block_id); 969 return 0x0000000000000708ull; 970} 971#else 972#define CVMX_PCIEEPX_CFG450(block_id) (0x0000000000000708ull) 973#endif 974#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 975static inline uint64_t CVMX_PCIEEPX_CFG451(unsigned long block_id) 976{ 977 if (!( 978 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 979 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 980 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 981 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 982 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 983 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 984 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 985 cvmx_warn("CVMX_PCIEEPX_CFG451(%lu) is invalid on this chip\n", block_id); 986 return 0x000000000000070Cull; 987} 988#else 989#define CVMX_PCIEEPX_CFG451(block_id) (0x000000000000070Cull) 990#endif 991#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 992static inline uint64_t CVMX_PCIEEPX_CFG452(unsigned long block_id) 993{ 994 if (!( 995 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 996 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 997 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 998 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 999 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 1000 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 1001 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 1002 cvmx_warn("CVMX_PCIEEPX_CFG452(%lu) is invalid on this chip\n", block_id); 1003 return 0x0000000000000710ull; 1004} 1005#else 1006#define CVMX_PCIEEPX_CFG452(block_id) (0x0000000000000710ull) 1007#endif 1008#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1009static inline uint64_t CVMX_PCIEEPX_CFG453(unsigned long block_id) 1010{ 1011 if (!( 1012 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 1013 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 1014 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 1015 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 1016 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 1017 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 1018 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 1019 cvmx_warn("CVMX_PCIEEPX_CFG453(%lu) is invalid on this chip\n", block_id); 1020 return 0x0000000000000714ull; 1021} 1022#else 1023#define CVMX_PCIEEPX_CFG453(block_id) (0x0000000000000714ull) 1024#endif 1025#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1026static inline uint64_t CVMX_PCIEEPX_CFG454(unsigned long block_id) 1027{ 1028 if (!( 1029 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 1030 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 1031 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 1032 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 1033 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 1034 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 1035 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 1036 cvmx_warn("CVMX_PCIEEPX_CFG454(%lu) is invalid on this chip\n", block_id); 1037 return 0x0000000000000718ull; 1038} 1039#else 1040#define CVMX_PCIEEPX_CFG454(block_id) (0x0000000000000718ull) 1041#endif 1042#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1043static inline uint64_t CVMX_PCIEEPX_CFG455(unsigned long block_id) 1044{ 1045 if (!( 1046 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 1047 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 1048 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 1049 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 1050 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 1051 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 1052 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 1053 cvmx_warn("CVMX_PCIEEPX_CFG455(%lu) is invalid on this chip\n", block_id); 1054 return 0x000000000000071Cull; 1055} 1056#else 1057#define CVMX_PCIEEPX_CFG455(block_id) (0x000000000000071Cull) 1058#endif 1059#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1060static inline uint64_t CVMX_PCIEEPX_CFG456(unsigned long block_id) 1061{ 1062 if (!( 1063 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 1064 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 1065 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 1066 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 1067 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 1068 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 1069 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 1070 cvmx_warn("CVMX_PCIEEPX_CFG456(%lu) is invalid on this chip\n", block_id); 1071 return 0x0000000000000720ull; 1072} 1073#else 1074#define CVMX_PCIEEPX_CFG456(block_id) (0x0000000000000720ull) 1075#endif 1076#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1077static inline uint64_t CVMX_PCIEEPX_CFG458(unsigned long block_id) 1078{ 1079 if (!( 1080 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 1081 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 1082 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 1083 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 1084 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 1085 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 1086 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 1087 cvmx_warn("CVMX_PCIEEPX_CFG458(%lu) is invalid on this chip\n", block_id); 1088 return 0x0000000000000728ull; 1089} 1090#else 1091#define CVMX_PCIEEPX_CFG458(block_id) (0x0000000000000728ull) 1092#endif 1093#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1094static inline uint64_t CVMX_PCIEEPX_CFG459(unsigned long block_id) 1095{ 1096 if (!( 1097 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 1098 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 1099 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 1100 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 1101 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 1102 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 1103 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 1104 cvmx_warn("CVMX_PCIEEPX_CFG459(%lu) is invalid on this chip\n", block_id); 1105 return 0x000000000000072Cull; 1106} 1107#else 1108#define CVMX_PCIEEPX_CFG459(block_id) (0x000000000000072Cull) 1109#endif 1110#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1111static inline uint64_t CVMX_PCIEEPX_CFG460(unsigned long block_id) 1112{ 1113 if (!( 1114 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 1115 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 1116 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 1117 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 1118 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 1119 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 1120 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 1121 cvmx_warn("CVMX_PCIEEPX_CFG460(%lu) is invalid on this chip\n", block_id); 1122 return 0x0000000000000730ull; 1123} 1124#else 1125#define CVMX_PCIEEPX_CFG460(block_id) (0x0000000000000730ull) 1126#endif 1127#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1128static inline uint64_t CVMX_PCIEEPX_CFG461(unsigned long block_id) 1129{ 1130 if (!( 1131 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 1132 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 1133 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 1134 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 1135 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 1136 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 1137 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 1138 cvmx_warn("CVMX_PCIEEPX_CFG461(%lu) is invalid on this chip\n", block_id); 1139 return 0x0000000000000734ull; 1140} 1141#else 1142#define CVMX_PCIEEPX_CFG461(block_id) (0x0000000000000734ull) 1143#endif 1144#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1145static inline uint64_t CVMX_PCIEEPX_CFG462(unsigned long block_id) 1146{ 1147 if (!( 1148 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 1149 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 1150 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 1151 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 1152 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 1153 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 1154 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 1155 cvmx_warn("CVMX_PCIEEPX_CFG462(%lu) is invalid on this chip\n", block_id); 1156 return 0x0000000000000738ull; 1157} 1158#else 1159#define CVMX_PCIEEPX_CFG462(block_id) (0x0000000000000738ull) 1160#endif 1161#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1162static inline uint64_t CVMX_PCIEEPX_CFG463(unsigned long block_id) 1163{ 1164 if (!( 1165 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 1166 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 1167 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 1168 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 1169 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 1170 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 1171 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 1172 cvmx_warn("CVMX_PCIEEPX_CFG463(%lu) is invalid on this chip\n", block_id); 1173 return 0x000000000000073Cull; 1174} 1175#else 1176#define CVMX_PCIEEPX_CFG463(block_id) (0x000000000000073Cull) 1177#endif 1178#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1179static inline uint64_t CVMX_PCIEEPX_CFG464(unsigned long block_id) 1180{ 1181 if (!( 1182 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 1183 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 1184 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 1185 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 1186 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 1187 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 1188 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 1189 cvmx_warn("CVMX_PCIEEPX_CFG464(%lu) is invalid on this chip\n", block_id); 1190 return 0x0000000000000740ull; 1191} 1192#else 1193#define CVMX_PCIEEPX_CFG464(block_id) (0x0000000000000740ull) 1194#endif 1195#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1196static inline uint64_t CVMX_PCIEEPX_CFG465(unsigned long block_id) 1197{ 1198 if (!( 1199 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 1200 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 1201 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 1202 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 1203 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 1204 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 1205 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 1206 cvmx_warn("CVMX_PCIEEPX_CFG465(%lu) is invalid on this chip\n", block_id); 1207 return 0x0000000000000744ull; 1208} 1209#else 1210#define CVMX_PCIEEPX_CFG465(block_id) (0x0000000000000744ull) 1211#endif 1212#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1213static inline uint64_t CVMX_PCIEEPX_CFG466(unsigned long block_id) 1214{ 1215 if (!( 1216 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 1217 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 1218 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 1219 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 1220 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 1221 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 1222 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 1223 cvmx_warn("CVMX_PCIEEPX_CFG466(%lu) is invalid on this chip\n", block_id); 1224 return 0x0000000000000748ull; 1225} 1226#else 1227#define CVMX_PCIEEPX_CFG466(block_id) (0x0000000000000748ull) 1228#endif 1229#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1230static inline uint64_t CVMX_PCIEEPX_CFG467(unsigned long block_id) 1231{ 1232 if (!( 1233 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 1234 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 1235 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 1236 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 1237 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 1238 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 1239 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 1240 cvmx_warn("CVMX_PCIEEPX_CFG467(%lu) is invalid on this chip\n", block_id); 1241 return 0x000000000000074Cull; 1242} 1243#else 1244#define CVMX_PCIEEPX_CFG467(block_id) (0x000000000000074Cull) 1245#endif 1246#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1247static inline uint64_t CVMX_PCIEEPX_CFG468(unsigned long block_id) 1248{ 1249 if (!( 1250 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 1251 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 1252 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 1253 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 1254 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 1255 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 1256 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 1257 cvmx_warn("CVMX_PCIEEPX_CFG468(%lu) is invalid on this chip\n", block_id); 1258 return 0x0000000000000750ull; 1259} 1260#else 1261#define CVMX_PCIEEPX_CFG468(block_id) (0x0000000000000750ull) 1262#endif 1263#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1264static inline uint64_t CVMX_PCIEEPX_CFG490(unsigned long block_id) 1265{ 1266 if (!( 1267 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 1268 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 1269 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 1270 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 1271 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 1272 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 1273 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 1274 cvmx_warn("CVMX_PCIEEPX_CFG490(%lu) is invalid on this chip\n", block_id); 1275 return 0x00000000000007A8ull; 1276} 1277#else 1278#define CVMX_PCIEEPX_CFG490(block_id) (0x00000000000007A8ull) 1279#endif 1280#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1281static inline uint64_t CVMX_PCIEEPX_CFG491(unsigned long block_id) 1282{ 1283 if (!( 1284 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 1285 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 1286 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 1287 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 1288 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 1289 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 1290 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 1291 cvmx_warn("CVMX_PCIEEPX_CFG491(%lu) is invalid on this chip\n", block_id); 1292 return 0x00000000000007ACull; 1293} 1294#else 1295#define CVMX_PCIEEPX_CFG491(block_id) (0x00000000000007ACull) 1296#endif 1297#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1298static inline uint64_t CVMX_PCIEEPX_CFG492(unsigned long block_id) 1299{ 1300 if (!( 1301 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 1302 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 1303 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 1304 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 1305 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 1306 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 1307 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 1308 cvmx_warn("CVMX_PCIEEPX_CFG492(%lu) is invalid on this chip\n", block_id); 1309 return 0x00000000000007B0ull; 1310} 1311#else 1312#define CVMX_PCIEEPX_CFG492(block_id) (0x00000000000007B0ull) 1313#endif 1314#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1315static inline uint64_t CVMX_PCIEEPX_CFG515(unsigned long block_id) 1316{ 1317 if (!( 1318 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 1319 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 1320 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 1321 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 1322 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 1323 cvmx_warn("CVMX_PCIEEPX_CFG515(%lu) is invalid on this chip\n", block_id); 1324 return 0x000000000000080Cull; 1325} 1326#else 1327#define CVMX_PCIEEPX_CFG515(block_id) (0x000000000000080Cull) 1328#endif 1329#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1330static inline uint64_t CVMX_PCIEEPX_CFG516(unsigned long block_id) 1331{ 1332 if (!( 1333 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 1334 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 1335 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 1336 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 1337 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 1338 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 1339 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 1340 cvmx_warn("CVMX_PCIEEPX_CFG516(%lu) is invalid on this chip\n", block_id); 1341 return 0x0000000000000810ull; 1342} 1343#else 1344#define CVMX_PCIEEPX_CFG516(block_id) (0x0000000000000810ull) 1345#endif 1346#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1347static inline uint64_t CVMX_PCIEEPX_CFG517(unsigned long block_id) 1348{ 1349 if (!( 1350 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 1351 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 1352 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 1353 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 1354 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 1355 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 1356 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 1357 cvmx_warn("CVMX_PCIEEPX_CFG517(%lu) is invalid on this chip\n", block_id); 1358 return 0x0000000000000814ull; 1359} 1360#else 1361#define CVMX_PCIEEPX_CFG517(block_id) (0x0000000000000814ull) 1362#endif 1363 1364/** 1365 * cvmx_pcieep#_cfg000 1366 * 1367 * PCIE_CFG000 = First 32-bits of PCIE type 0 config space (Device ID and Vendor ID Register) 1368 * 1369 */ 1370union cvmx_pcieepx_cfg000 { 1371 uint32_t u32; 1372 struct cvmx_pcieepx_cfg000_s { 1373#ifdef __BIG_ENDIAN_BITFIELD 1374 uint32_t devid : 16; /**< Device ID, writable through PEM(0..1)_CFG_WR 1375 However, the application must not change this field. 1376 For EEPROM loads also see VENDID of this register. */ 1377 uint32_t vendid : 16; /**< Vendor ID, writable through PEM(0..1)_CFG_WR 1378 However, the application must not change this field. 1379 During and EPROM Load is a value of 0xFFFF is loaded to this 1380 field and a value of 0xFFFF is loaded to the DEVID field of 1381 this register, the value will not be loaded, EEPROM load will 1382 stop, and the FastLinkEnable bit will be set in the 1383 PCIE_CFG452 register. */ 1384#else 1385 uint32_t vendid : 16; 1386 uint32_t devid : 16; 1387#endif 1388 } s; 1389 struct cvmx_pcieepx_cfg000_s cn52xx; 1390 struct cvmx_pcieepx_cfg000_s cn52xxp1; 1391 struct cvmx_pcieepx_cfg000_s cn56xx; 1392 struct cvmx_pcieepx_cfg000_s cn56xxp1; 1393 struct cvmx_pcieepx_cfg000_s cn61xx; 1394 struct cvmx_pcieepx_cfg000_s cn63xx; 1395 struct cvmx_pcieepx_cfg000_s cn63xxp1; 1396 struct cvmx_pcieepx_cfg000_s cn66xx; 1397 struct cvmx_pcieepx_cfg000_s cn68xx; 1398 struct cvmx_pcieepx_cfg000_s cn68xxp1; 1399 struct cvmx_pcieepx_cfg000_s cnf71xx; 1400}; 1401typedef union cvmx_pcieepx_cfg000 cvmx_pcieepx_cfg000_t; 1402 1403/** 1404 * cvmx_pcieep#_cfg001 1405 * 1406 * PCIE_CFG001 = Second 32-bits of PCIE type 0 config space (Command/Status Register) 1407 * 1408 */ 1409union cvmx_pcieepx_cfg001 { 1410 uint32_t u32; 1411 struct cvmx_pcieepx_cfg001_s { 1412#ifdef __BIG_ENDIAN_BITFIELD 1413 uint32_t dpe : 1; /**< Detected Parity Error */ 1414 uint32_t sse : 1; /**< Signaled System Error */ 1415 uint32_t rma : 1; /**< Received Master Abort */ 1416 uint32_t rta : 1; /**< Received Target Abort */ 1417 uint32_t sta : 1; /**< Signaled Target Abort */ 1418 uint32_t devt : 2; /**< DEVSEL Timing 1419 Not applicable for PCI Express. Hardwired to 0. */ 1420 uint32_t mdpe : 1; /**< Master Data Parity Error */ 1421 uint32_t fbb : 1; /**< Fast Back-to-Back Capable 1422 Not applicable for PCI Express. Hardwired to 0. */ 1423 uint32_t reserved_22_22 : 1; 1424 uint32_t m66 : 1; /**< 66 MHz Capable 1425 Not applicable for PCI Express. Hardwired to 0. */ 1426 uint32_t cl : 1; /**< Capabilities List 1427 Indicates presence of an extended capability item. 1428 Hardwired to 1. */ 1429 uint32_t i_stat : 1; /**< INTx Status */ 1430 uint32_t reserved_11_18 : 8; 1431 uint32_t i_dis : 1; /**< INTx Assertion Disable */ 1432 uint32_t fbbe : 1; /**< Fast Back-to-Back Enable 1433 Not applicable for PCI Express. Must be hardwired to 0. */ 1434 uint32_t see : 1; /**< SERR# Enable */ 1435 uint32_t ids_wcc : 1; /**< IDSEL Stepping/Wait Cycle Control 1436 Not applicable for PCI Express. Must be hardwired to 0 */ 1437 uint32_t per : 1; /**< Parity Error Response */ 1438 uint32_t vps : 1; /**< VGA Palette Snoop 1439 Not applicable for PCI Express. Must be hardwired to 0. */ 1440 uint32_t mwice : 1; /**< Memory Write and Invalidate 1441 Not applicable for PCI Express. Must be hardwired to 0. */ 1442 uint32_t scse : 1; /**< Special Cycle Enable 1443 Not applicable for PCI Express. Must be hardwired to 0. */ 1444 uint32_t me : 1; /**< Bus Master Enable */ 1445 uint32_t msae : 1; /**< Memory Space Enable */ 1446 uint32_t isae : 1; /**< I/O Space Enable */ 1447#else 1448 uint32_t isae : 1; 1449 uint32_t msae : 1; 1450 uint32_t me : 1; 1451 uint32_t scse : 1; 1452 uint32_t mwice : 1; 1453 uint32_t vps : 1; 1454 uint32_t per : 1; 1455 uint32_t ids_wcc : 1; 1456 uint32_t see : 1; 1457 uint32_t fbbe : 1; 1458 uint32_t i_dis : 1; 1459 uint32_t reserved_11_18 : 8; 1460 uint32_t i_stat : 1; 1461 uint32_t cl : 1; 1462 uint32_t m66 : 1; 1463 uint32_t reserved_22_22 : 1; 1464 uint32_t fbb : 1; 1465 uint32_t mdpe : 1; 1466 uint32_t devt : 2; 1467 uint32_t sta : 1; 1468 uint32_t rta : 1; 1469 uint32_t rma : 1; 1470 uint32_t sse : 1; 1471 uint32_t dpe : 1; 1472#endif 1473 } s; 1474 struct cvmx_pcieepx_cfg001_s cn52xx; 1475 struct cvmx_pcieepx_cfg001_s cn52xxp1; 1476 struct cvmx_pcieepx_cfg001_s cn56xx; 1477 struct cvmx_pcieepx_cfg001_s cn56xxp1; 1478 struct cvmx_pcieepx_cfg001_s cn61xx; 1479 struct cvmx_pcieepx_cfg001_s cn63xx; 1480 struct cvmx_pcieepx_cfg001_s cn63xxp1; 1481 struct cvmx_pcieepx_cfg001_s cn66xx; 1482 struct cvmx_pcieepx_cfg001_s cn68xx; 1483 struct cvmx_pcieepx_cfg001_s cn68xxp1; 1484 struct cvmx_pcieepx_cfg001_s cnf71xx; 1485}; 1486typedef union cvmx_pcieepx_cfg001 cvmx_pcieepx_cfg001_t; 1487 1488/** 1489 * cvmx_pcieep#_cfg002 1490 * 1491 * PCIE_CFG002 = Third 32-bits of PCIE type 0 config space (Revision ID/Class Code Register) 1492 * 1493 */ 1494union cvmx_pcieepx_cfg002 { 1495 uint32_t u32; 1496 struct cvmx_pcieepx_cfg002_s { 1497#ifdef __BIG_ENDIAN_BITFIELD 1498 uint32_t bcc : 8; /**< Base Class Code, writable through PEM(0..1)_CFG_WR 1499 However, the application must not change this field. */ 1500 uint32_t sc : 8; /**< Subclass Code, writable through PEM(0..1)_CFG_WR 1501 However, the application must not change this field. */ 1502 uint32_t pi : 8; /**< Programming Interface, writable through PEM(0..1)_CFG_WR 1503 However, the application must not change this field. */ 1504 uint32_t rid : 8; /**< Revision ID, writable through PEM(0..1)_CFG_WR 1505 However, the application must not change this field. */ 1506#else 1507 uint32_t rid : 8; 1508 uint32_t pi : 8; 1509 uint32_t sc : 8; 1510 uint32_t bcc : 8; 1511#endif 1512 } s; 1513 struct cvmx_pcieepx_cfg002_s cn52xx; 1514 struct cvmx_pcieepx_cfg002_s cn52xxp1; 1515 struct cvmx_pcieepx_cfg002_s cn56xx; 1516 struct cvmx_pcieepx_cfg002_s cn56xxp1; 1517 struct cvmx_pcieepx_cfg002_s cn61xx; 1518 struct cvmx_pcieepx_cfg002_s cn63xx; 1519 struct cvmx_pcieepx_cfg002_s cn63xxp1; 1520 struct cvmx_pcieepx_cfg002_s cn66xx; 1521 struct cvmx_pcieepx_cfg002_s cn68xx; 1522 struct cvmx_pcieepx_cfg002_s cn68xxp1; 1523 struct cvmx_pcieepx_cfg002_s cnf71xx; 1524}; 1525typedef union cvmx_pcieepx_cfg002 cvmx_pcieepx_cfg002_t; 1526 1527/** 1528 * cvmx_pcieep#_cfg003 1529 * 1530 * PCIE_CFG003 = Fourth 32-bits of PCIE type 0 config space (Cache Line Size/Master Latency Timer/Header Type Register/BIST Register) 1531 * 1532 */ 1533union cvmx_pcieepx_cfg003 { 1534 uint32_t u32; 1535 struct cvmx_pcieepx_cfg003_s { 1536#ifdef __BIG_ENDIAN_BITFIELD 1537 uint32_t bist : 8; /**< The BIST register functions are not supported. 1538 All 8 bits of the BIST register are hardwired to 0. */ 1539 uint32_t mfd : 1; /**< Multi Function Device 1540 The Multi Function Device bit is writable through PEM(0..1)_CFG_WR. 1541 However, this is a single function device. Therefore, the 1542 application must not write a 1 to this bit. */ 1543 uint32_t chf : 7; /**< Configuration Header Format 1544 Hardwired to 0 for type 0. */ 1545 uint32_t lt : 8; /**< Master Latency Timer 1546 Not applicable for PCI Express, hardwired to 0. */ 1547 uint32_t cls : 8; /**< Cache Line Size 1548 The Cache Line Size register is RW for legacy compatibility 1549 purposes and is not applicable to PCI Express device 1550 functionality. 1551 Writing to the Cache Line Size register does not impact 1552 functionality. */ 1553#else 1554 uint32_t cls : 8; 1555 uint32_t lt : 8; 1556 uint32_t chf : 7; 1557 uint32_t mfd : 1; 1558 uint32_t bist : 8; 1559#endif 1560 } s; 1561 struct cvmx_pcieepx_cfg003_s cn52xx; 1562 struct cvmx_pcieepx_cfg003_s cn52xxp1; 1563 struct cvmx_pcieepx_cfg003_s cn56xx; 1564 struct cvmx_pcieepx_cfg003_s cn56xxp1; 1565 struct cvmx_pcieepx_cfg003_s cn61xx; 1566 struct cvmx_pcieepx_cfg003_s cn63xx; 1567 struct cvmx_pcieepx_cfg003_s cn63xxp1; 1568 struct cvmx_pcieepx_cfg003_s cn66xx; 1569 struct cvmx_pcieepx_cfg003_s cn68xx; 1570 struct cvmx_pcieepx_cfg003_s cn68xxp1; 1571 struct cvmx_pcieepx_cfg003_s cnf71xx; 1572}; 1573typedef union cvmx_pcieepx_cfg003 cvmx_pcieepx_cfg003_t; 1574 1575/** 1576 * cvmx_pcieep#_cfg004 1577 * 1578 * PCIE_CFG004 = Fifth 32-bits of PCIE type 0 config space (Base Address Register 0 - Low) 1579 * 1580 */ 1581union cvmx_pcieepx_cfg004 { 1582 uint32_t u32; 1583 struct cvmx_pcieepx_cfg004_s { 1584#ifdef __BIG_ENDIAN_BITFIELD 1585 uint32_t lbab : 18; /**< Lower bits of the BAR 0 base address */ 1586 uint32_t reserved_4_13 : 10; 1587 uint32_t pf : 1; /**< Prefetchable 1588 This field is writable through PEM(0..1)_CFG_WR. 1589 However, the application must not change this field. */ 1590 uint32_t typ : 2; /**< BAR type 1591 o 00 = 32-bit BAR 1592 o 10 = 64-bit BAR 1593 This field is writable through PEM(0..1)_CFG_WR. 1594 However, the application must not change this field. */ 1595 uint32_t mspc : 1; /**< Memory Space Indicator 1596 o 0 = BAR 0 is a memory BAR 1597 o 1 = BAR 0 is an I/O BAR 1598 This field is writable through PEM(0..1)_CFG_WR. 1599 However, the application must not change this field. */ 1600#else 1601 uint32_t mspc : 1; 1602 uint32_t typ : 2; 1603 uint32_t pf : 1; 1604 uint32_t reserved_4_13 : 10; 1605 uint32_t lbab : 18; 1606#endif 1607 } s; 1608 struct cvmx_pcieepx_cfg004_s cn52xx; 1609 struct cvmx_pcieepx_cfg004_s cn52xxp1; 1610 struct cvmx_pcieepx_cfg004_s cn56xx; 1611 struct cvmx_pcieepx_cfg004_s cn56xxp1; 1612 struct cvmx_pcieepx_cfg004_s cn61xx; 1613 struct cvmx_pcieepx_cfg004_s cn63xx; 1614 struct cvmx_pcieepx_cfg004_s cn63xxp1; 1615 struct cvmx_pcieepx_cfg004_s cn66xx; 1616 struct cvmx_pcieepx_cfg004_s cn68xx; 1617 struct cvmx_pcieepx_cfg004_s cn68xxp1; 1618 struct cvmx_pcieepx_cfg004_s cnf71xx; 1619}; 1620typedef union cvmx_pcieepx_cfg004 cvmx_pcieepx_cfg004_t; 1621 1622/** 1623 * cvmx_pcieep#_cfg004_mask 1624 * 1625 * PCIE_CFG004_MASK (BAR Mask 0 - Low) 1626 * The BAR 0 Mask register is invisible to host software and not readable from the application. 1627 * The BAR 0 Mask register is only writable through PEM(0..1)_CFG_WR. 1628 */ 1629union cvmx_pcieepx_cfg004_mask { 1630 uint32_t u32; 1631 struct cvmx_pcieepx_cfg004_mask_s { 1632#ifdef __BIG_ENDIAN_BITFIELD 1633 uint32_t lmask : 31; /**< Bar Mask Low */ 1634 uint32_t enb : 1; /**< Bar Enable 1635 o 0: BAR 0 is disabled 1636 o 1: BAR 0 is enabled 1637 Bit 0 is interpreted as BAR Enable when writing to the BAR Mask 1638 register rather than as a mask bit because bit 0 of a BAR is 1639 always masked from writing by host software. Bit 0 must be 1640 written prior to writing the other mask bits. */ 1641#else 1642 uint32_t enb : 1; 1643 uint32_t lmask : 31; 1644#endif 1645 } s; 1646 struct cvmx_pcieepx_cfg004_mask_s cn52xx; 1647 struct cvmx_pcieepx_cfg004_mask_s cn52xxp1; 1648 struct cvmx_pcieepx_cfg004_mask_s cn56xx; 1649 struct cvmx_pcieepx_cfg004_mask_s cn56xxp1; 1650 struct cvmx_pcieepx_cfg004_mask_s cn61xx; 1651 struct cvmx_pcieepx_cfg004_mask_s cn63xx; 1652 struct cvmx_pcieepx_cfg004_mask_s cn63xxp1; 1653 struct cvmx_pcieepx_cfg004_mask_s cn66xx; 1654 struct cvmx_pcieepx_cfg004_mask_s cn68xx; 1655 struct cvmx_pcieepx_cfg004_mask_s cn68xxp1; 1656 struct cvmx_pcieepx_cfg004_mask_s cnf71xx; 1657}; 1658typedef union cvmx_pcieepx_cfg004_mask cvmx_pcieepx_cfg004_mask_t; 1659 1660/** 1661 * cvmx_pcieep#_cfg005 1662 * 1663 * PCIE_CFG005 = Sixth 32-bits of PCIE type 0 config space (Base Address Register 0 - High) 1664 * 1665 */ 1666union cvmx_pcieepx_cfg005 { 1667 uint32_t u32; 1668 struct cvmx_pcieepx_cfg005_s { 1669#ifdef __BIG_ENDIAN_BITFIELD 1670 uint32_t ubab : 32; /**< Contains the upper 32 bits of the BAR 0 base address. */ 1671#else 1672 uint32_t ubab : 32; 1673#endif 1674 } s; 1675 struct cvmx_pcieepx_cfg005_s cn52xx; 1676 struct cvmx_pcieepx_cfg005_s cn52xxp1; 1677 struct cvmx_pcieepx_cfg005_s cn56xx; 1678 struct cvmx_pcieepx_cfg005_s cn56xxp1; 1679 struct cvmx_pcieepx_cfg005_s cn61xx; 1680 struct cvmx_pcieepx_cfg005_s cn63xx; 1681 struct cvmx_pcieepx_cfg005_s cn63xxp1; 1682 struct cvmx_pcieepx_cfg005_s cn66xx; 1683 struct cvmx_pcieepx_cfg005_s cn68xx; 1684 struct cvmx_pcieepx_cfg005_s cn68xxp1; 1685 struct cvmx_pcieepx_cfg005_s cnf71xx; 1686}; 1687typedef union cvmx_pcieepx_cfg005 cvmx_pcieepx_cfg005_t; 1688 1689/** 1690 * cvmx_pcieep#_cfg005_mask 1691 * 1692 * PCIE_CFG005_MASK = (BAR Mask 0 - High) 1693 * The BAR 0 Mask register is invisible to host software and not readable from the application. 1694 * The BAR 0 Mask register is only writable through PEM(0..1)_CFG_WR. 1695 */ 1696union cvmx_pcieepx_cfg005_mask { 1697 uint32_t u32; 1698 struct cvmx_pcieepx_cfg005_mask_s { 1699#ifdef __BIG_ENDIAN_BITFIELD 1700 uint32_t umask : 32; /**< Bar Mask High */ 1701#else 1702 uint32_t umask : 32; 1703#endif 1704 } s; 1705 struct cvmx_pcieepx_cfg005_mask_s cn52xx; 1706 struct cvmx_pcieepx_cfg005_mask_s cn52xxp1; 1707 struct cvmx_pcieepx_cfg005_mask_s cn56xx; 1708 struct cvmx_pcieepx_cfg005_mask_s cn56xxp1; 1709 struct cvmx_pcieepx_cfg005_mask_s cn61xx; 1710 struct cvmx_pcieepx_cfg005_mask_s cn63xx; 1711 struct cvmx_pcieepx_cfg005_mask_s cn63xxp1; 1712 struct cvmx_pcieepx_cfg005_mask_s cn66xx; 1713 struct cvmx_pcieepx_cfg005_mask_s cn68xx; 1714 struct cvmx_pcieepx_cfg005_mask_s cn68xxp1; 1715 struct cvmx_pcieepx_cfg005_mask_s cnf71xx; 1716}; 1717typedef union cvmx_pcieepx_cfg005_mask cvmx_pcieepx_cfg005_mask_t; 1718 1719/** 1720 * cvmx_pcieep#_cfg006 1721 * 1722 * PCIE_CFG006 = Seventh 32-bits of PCIE type 0 config space (Base Address Register 1 - Low) 1723 * 1724 */ 1725union cvmx_pcieepx_cfg006 { 1726 uint32_t u32; 1727 struct cvmx_pcieepx_cfg006_s { 1728#ifdef __BIG_ENDIAN_BITFIELD 1729 uint32_t lbab : 6; /**< Lower bits of the BAR 1 base address */ 1730 uint32_t reserved_4_25 : 22; 1731 uint32_t pf : 1; /**< Prefetchable 1732 This field is writable through PEM(0..1)_CFG_WR. 1733 However, the application must not change this field. */ 1734 uint32_t typ : 2; /**< BAR type 1735 o 00 = 32-bit BAR 1736 o 10 = 64-bit BAR 1737 This field is writable through PEM(0..1)_CFG_WR. 1738 However, the application must not change this field. */ 1739 uint32_t mspc : 1; /**< Memory Space Indicator 1740 o 0 = BAR 0 is a memory BAR 1741 o 1 = BAR 0 is an I/O BAR 1742 This field is writable through PEM(0..1)_CFG_WR. 1743 However, the application must not change this field. */ 1744#else 1745 uint32_t mspc : 1; 1746 uint32_t typ : 2; 1747 uint32_t pf : 1; 1748 uint32_t reserved_4_25 : 22; 1749 uint32_t lbab : 6; 1750#endif 1751 } s; 1752 struct cvmx_pcieepx_cfg006_s cn52xx; 1753 struct cvmx_pcieepx_cfg006_s cn52xxp1; 1754 struct cvmx_pcieepx_cfg006_s cn56xx; 1755 struct cvmx_pcieepx_cfg006_s cn56xxp1; 1756 struct cvmx_pcieepx_cfg006_s cn61xx; 1757 struct cvmx_pcieepx_cfg006_s cn63xx; 1758 struct cvmx_pcieepx_cfg006_s cn63xxp1; 1759 struct cvmx_pcieepx_cfg006_s cn66xx; 1760 struct cvmx_pcieepx_cfg006_s cn68xx; 1761 struct cvmx_pcieepx_cfg006_s cn68xxp1; 1762 struct cvmx_pcieepx_cfg006_s cnf71xx; 1763}; 1764typedef union cvmx_pcieepx_cfg006 cvmx_pcieepx_cfg006_t; 1765 1766/** 1767 * cvmx_pcieep#_cfg006_mask 1768 * 1769 * PCIE_CFG006_MASK (BAR Mask 1 - Low) 1770 * The BAR 1 Mask register is invisible to host software and not readable from the application. 1771 * The BAR 1 Mask register is only writable through PEM(0..1)_CFG_WR. 1772 */ 1773union cvmx_pcieepx_cfg006_mask { 1774 uint32_t u32; 1775 struct cvmx_pcieepx_cfg006_mask_s { 1776#ifdef __BIG_ENDIAN_BITFIELD 1777 uint32_t lmask : 31; /**< Bar Mask Low */ 1778 uint32_t enb : 1; /**< Bar Enable 1779 o 0: BAR 1 is disabled 1780 o 1: BAR 1 is enabled 1781 Bit 0 is interpreted as BAR Enable when writing to the BAR Mask 1782 register rather than as a mask bit because bit 0 of a BAR is 1783 always masked from writing by host software. Bit 0 must be 1784 written prior to writing the other mask bits. */ 1785#else 1786 uint32_t enb : 1; 1787 uint32_t lmask : 31; 1788#endif 1789 } s; 1790 struct cvmx_pcieepx_cfg006_mask_s cn52xx; 1791 struct cvmx_pcieepx_cfg006_mask_s cn52xxp1; 1792 struct cvmx_pcieepx_cfg006_mask_s cn56xx; 1793 struct cvmx_pcieepx_cfg006_mask_s cn56xxp1; 1794 struct cvmx_pcieepx_cfg006_mask_s cn61xx; 1795 struct cvmx_pcieepx_cfg006_mask_s cn63xx; 1796 struct cvmx_pcieepx_cfg006_mask_s cn63xxp1; 1797 struct cvmx_pcieepx_cfg006_mask_s cn66xx; 1798 struct cvmx_pcieepx_cfg006_mask_s cn68xx; 1799 struct cvmx_pcieepx_cfg006_mask_s cn68xxp1; 1800 struct cvmx_pcieepx_cfg006_mask_s cnf71xx; 1801}; 1802typedef union cvmx_pcieepx_cfg006_mask cvmx_pcieepx_cfg006_mask_t; 1803 1804/** 1805 * cvmx_pcieep#_cfg007 1806 * 1807 * PCIE_CFG007 = Eighth 32-bits of PCIE type 0 config space (Base Address Register 1 - High) 1808 * 1809 */ 1810union cvmx_pcieepx_cfg007 { 1811 uint32_t u32; 1812 struct cvmx_pcieepx_cfg007_s { 1813#ifdef __BIG_ENDIAN_BITFIELD 1814 uint32_t ubab : 32; /**< Contains the upper 32 bits of the BAR 1 base address. */ 1815#else 1816 uint32_t ubab : 32; 1817#endif 1818 } s; 1819 struct cvmx_pcieepx_cfg007_s cn52xx; 1820 struct cvmx_pcieepx_cfg007_s cn52xxp1; 1821 struct cvmx_pcieepx_cfg007_s cn56xx; 1822 struct cvmx_pcieepx_cfg007_s cn56xxp1; 1823 struct cvmx_pcieepx_cfg007_s cn61xx; 1824 struct cvmx_pcieepx_cfg007_s cn63xx; 1825 struct cvmx_pcieepx_cfg007_s cn63xxp1; 1826 struct cvmx_pcieepx_cfg007_s cn66xx; 1827 struct cvmx_pcieepx_cfg007_s cn68xx; 1828 struct cvmx_pcieepx_cfg007_s cn68xxp1; 1829 struct cvmx_pcieepx_cfg007_s cnf71xx; 1830}; 1831typedef union cvmx_pcieepx_cfg007 cvmx_pcieepx_cfg007_t; 1832 1833/** 1834 * cvmx_pcieep#_cfg007_mask 1835 * 1836 * PCIE_CFG007_MASK (BAR Mask 1 - High) 1837 * The BAR 1 Mask register is invisible to host software and not readable from the application. 1838 * The BAR 1 Mask register is only writable through PEM(0..1)_CFG_WR. 1839 */ 1840union cvmx_pcieepx_cfg007_mask { 1841 uint32_t u32; 1842 struct cvmx_pcieepx_cfg007_mask_s { 1843#ifdef __BIG_ENDIAN_BITFIELD 1844 uint32_t umask : 32; /**< Bar Mask High */ 1845#else 1846 uint32_t umask : 32; 1847#endif 1848 } s; 1849 struct cvmx_pcieepx_cfg007_mask_s cn52xx; 1850 struct cvmx_pcieepx_cfg007_mask_s cn52xxp1; 1851 struct cvmx_pcieepx_cfg007_mask_s cn56xx; 1852 struct cvmx_pcieepx_cfg007_mask_s cn56xxp1; 1853 struct cvmx_pcieepx_cfg007_mask_s cn61xx; 1854 struct cvmx_pcieepx_cfg007_mask_s cn63xx; 1855 struct cvmx_pcieepx_cfg007_mask_s cn63xxp1; 1856 struct cvmx_pcieepx_cfg007_mask_s cn66xx; 1857 struct cvmx_pcieepx_cfg007_mask_s cn68xx; 1858 struct cvmx_pcieepx_cfg007_mask_s cn68xxp1; 1859 struct cvmx_pcieepx_cfg007_mask_s cnf71xx; 1860}; 1861typedef union cvmx_pcieepx_cfg007_mask cvmx_pcieepx_cfg007_mask_t; 1862 1863/** 1864 * cvmx_pcieep#_cfg008 1865 * 1866 * PCIE_CFG008 = Ninth 32-bits of PCIE type 0 config space (Base Address Register 2 - Low) 1867 * 1868 */ 1869union cvmx_pcieepx_cfg008 { 1870 uint32_t u32; 1871 struct cvmx_pcieepx_cfg008_s { 1872#ifdef __BIG_ENDIAN_BITFIELD 1873 uint32_t reserved_4_31 : 28; 1874 uint32_t pf : 1; /**< Prefetchable 1875 This field is writable through PEM(0..1)_CFG_WR. 1876 However, the application must not change this field. */ 1877 uint32_t typ : 2; /**< BAR type 1878 o 00 = 32-bit BAR 1879 o 10 = 64-bit BAR 1880 This field is writable through PEM(0..1)_CFG_WR. 1881 However, the application must not change this field. */ 1882 uint32_t mspc : 1; /**< Memory Space Indicator 1883 o 0 = BAR 0 is a memory BAR 1884 o 1 = BAR 0 is an I/O BAR 1885 This field is writable through PEM(0..1)_CFG_WR. 1886 However, the application must not change this field. */ 1887#else 1888 uint32_t mspc : 1; 1889 uint32_t typ : 2; 1890 uint32_t pf : 1; 1891 uint32_t reserved_4_31 : 28; 1892#endif 1893 } s; 1894 struct cvmx_pcieepx_cfg008_s cn52xx; 1895 struct cvmx_pcieepx_cfg008_s cn52xxp1; 1896 struct cvmx_pcieepx_cfg008_s cn56xx; 1897 struct cvmx_pcieepx_cfg008_s cn56xxp1; 1898 struct cvmx_pcieepx_cfg008_s cn61xx; 1899 struct cvmx_pcieepx_cfg008_s cn63xx; 1900 struct cvmx_pcieepx_cfg008_s cn63xxp1; 1901 struct cvmx_pcieepx_cfg008_s cn66xx; 1902 struct cvmx_pcieepx_cfg008_s cn68xx; 1903 struct cvmx_pcieepx_cfg008_s cn68xxp1; 1904 struct cvmx_pcieepx_cfg008_s cnf71xx; 1905}; 1906typedef union cvmx_pcieepx_cfg008 cvmx_pcieepx_cfg008_t; 1907 1908/** 1909 * cvmx_pcieep#_cfg008_mask 1910 * 1911 * PCIE_CFG008_MASK (BAR Mask 2 - Low) 1912 * The BAR 2 Mask register is invisible to host software and not readable from the application. 1913 * The BAR 2 Mask register is only writable through PEM(0..1)_CFG_WR. 1914 */ 1915union cvmx_pcieepx_cfg008_mask { 1916 uint32_t u32; 1917 struct cvmx_pcieepx_cfg008_mask_s { 1918#ifdef __BIG_ENDIAN_BITFIELD 1919 uint32_t lmask : 31; /**< Bar Mask Low */ 1920 uint32_t enb : 1; /**< Bar Enable 1921 o 0: BAR 2 is disabled 1922 o 1: BAR 2 is enabled 1923 Bit 0 is interpreted as BAR Enable when writing to the BAR Mask 1924 register rather than as a mask bit because bit 0 of a BAR is 1925 always masked from writing by host software. Bit 0 must be 1926 written prior to writing the other mask bits. */ 1927#else 1928 uint32_t enb : 1; 1929 uint32_t lmask : 31; 1930#endif 1931 } s; 1932 struct cvmx_pcieepx_cfg008_mask_s cn52xx; 1933 struct cvmx_pcieepx_cfg008_mask_s cn52xxp1; 1934 struct cvmx_pcieepx_cfg008_mask_s cn56xx; 1935 struct cvmx_pcieepx_cfg008_mask_s cn56xxp1; 1936 struct cvmx_pcieepx_cfg008_mask_s cn61xx; 1937 struct cvmx_pcieepx_cfg008_mask_s cn63xx; 1938 struct cvmx_pcieepx_cfg008_mask_s cn63xxp1; 1939 struct cvmx_pcieepx_cfg008_mask_s cn66xx; 1940 struct cvmx_pcieepx_cfg008_mask_s cn68xx; 1941 struct cvmx_pcieepx_cfg008_mask_s cn68xxp1; 1942 struct cvmx_pcieepx_cfg008_mask_s cnf71xx; 1943}; 1944typedef union cvmx_pcieepx_cfg008_mask cvmx_pcieepx_cfg008_mask_t; 1945 1946/** 1947 * cvmx_pcieep#_cfg009 1948 * 1949 * PCIE_CFG009 = Tenth 32-bits of PCIE type 0 config space (Base Address Register 2 - High) 1950 * 1951 */ 1952union cvmx_pcieepx_cfg009 { 1953 uint32_t u32; 1954 struct cvmx_pcieepx_cfg009_s { 1955#ifdef __BIG_ENDIAN_BITFIELD 1956 uint32_t reserved_0_31 : 32; 1957#else 1958 uint32_t reserved_0_31 : 32; 1959#endif 1960 } s; 1961 struct cvmx_pcieepx_cfg009_cn52xx { 1962#ifdef __BIG_ENDIAN_BITFIELD 1963 uint32_t ubab : 25; /**< Contains the upper 32 bits of the BAR 2 base address. */ 1964 uint32_t reserved_0_6 : 7; 1965#else 1966 uint32_t reserved_0_6 : 7; 1967 uint32_t ubab : 25; 1968#endif 1969 } cn52xx; 1970 struct cvmx_pcieepx_cfg009_cn52xx cn52xxp1; 1971 struct cvmx_pcieepx_cfg009_cn52xx cn56xx; 1972 struct cvmx_pcieepx_cfg009_cn52xx cn56xxp1; 1973 struct cvmx_pcieepx_cfg009_cn61xx { 1974#ifdef __BIG_ENDIAN_BITFIELD 1975 uint32_t ubab : 23; /**< Contains the upper 32 bits of the BAR 2 base address. */ 1976 uint32_t reserved_0_8 : 9; 1977#else 1978 uint32_t reserved_0_8 : 9; 1979 uint32_t ubab : 23; 1980#endif 1981 } cn61xx; 1982 struct cvmx_pcieepx_cfg009_cn61xx cn63xx; 1983 struct cvmx_pcieepx_cfg009_cn61xx cn63xxp1; 1984 struct cvmx_pcieepx_cfg009_cn61xx cn66xx; 1985 struct cvmx_pcieepx_cfg009_cn61xx cn68xx; 1986 struct cvmx_pcieepx_cfg009_cn61xx cn68xxp1; 1987 struct cvmx_pcieepx_cfg009_cn61xx cnf71xx; 1988}; 1989typedef union cvmx_pcieepx_cfg009 cvmx_pcieepx_cfg009_t; 1990 1991/** 1992 * cvmx_pcieep#_cfg009_mask 1993 * 1994 * PCIE_CFG009_MASK (BAR Mask 2 - High) 1995 * The BAR 2 Mask register is invisible to host software and not readable from the application. 1996 * The BAR 2 Mask register is only writable through PEM(0..1)_CFG_WR. 1997 */ 1998union cvmx_pcieepx_cfg009_mask { 1999 uint32_t u32; 2000 struct cvmx_pcieepx_cfg009_mask_s { 2001#ifdef __BIG_ENDIAN_BITFIELD 2002 uint32_t umask : 32; /**< Bar Mask High */ 2003#else 2004 uint32_t umask : 32; 2005#endif 2006 } s; 2007 struct cvmx_pcieepx_cfg009_mask_s cn52xx; 2008 struct cvmx_pcieepx_cfg009_mask_s cn52xxp1; 2009 struct cvmx_pcieepx_cfg009_mask_s cn56xx; 2010 struct cvmx_pcieepx_cfg009_mask_s cn56xxp1; 2011 struct cvmx_pcieepx_cfg009_mask_s cn61xx; 2012 struct cvmx_pcieepx_cfg009_mask_s cn63xx; 2013 struct cvmx_pcieepx_cfg009_mask_s cn63xxp1; 2014 struct cvmx_pcieepx_cfg009_mask_s cn66xx; 2015 struct cvmx_pcieepx_cfg009_mask_s cn68xx; 2016 struct cvmx_pcieepx_cfg009_mask_s cn68xxp1; 2017 struct cvmx_pcieepx_cfg009_mask_s cnf71xx; 2018}; 2019typedef union cvmx_pcieepx_cfg009_mask cvmx_pcieepx_cfg009_mask_t; 2020 2021/** 2022 * cvmx_pcieep#_cfg010 2023 * 2024 * PCIE_CFG010 = Eleventh 32-bits of PCIE type 0 config space (CardBus CIS Pointer Register) 2025 * 2026 */ 2027union cvmx_pcieepx_cfg010 { 2028 uint32_t u32; 2029 struct cvmx_pcieepx_cfg010_s { 2030#ifdef __BIG_ENDIAN_BITFIELD 2031 uint32_t cisp : 32; /**< CardBus CIS Pointer 2032 Optional, writable through PEM(0..1)_CFG_WR. */ 2033#else 2034 uint32_t cisp : 32; 2035#endif 2036 } s; 2037 struct cvmx_pcieepx_cfg010_s cn52xx; 2038 struct cvmx_pcieepx_cfg010_s cn52xxp1; 2039 struct cvmx_pcieepx_cfg010_s cn56xx; 2040 struct cvmx_pcieepx_cfg010_s cn56xxp1; 2041 struct cvmx_pcieepx_cfg010_s cn61xx; 2042 struct cvmx_pcieepx_cfg010_s cn63xx; 2043 struct cvmx_pcieepx_cfg010_s cn63xxp1; 2044 struct cvmx_pcieepx_cfg010_s cn66xx; 2045 struct cvmx_pcieepx_cfg010_s cn68xx; 2046 struct cvmx_pcieepx_cfg010_s cn68xxp1; 2047 struct cvmx_pcieepx_cfg010_s cnf71xx; 2048}; 2049typedef union cvmx_pcieepx_cfg010 cvmx_pcieepx_cfg010_t; 2050 2051/** 2052 * cvmx_pcieep#_cfg011 2053 * 2054 * PCIE_CFG011 = Twelfth 32-bits of PCIE type 0 config space (Subsystem ID and Subsystem Vendor ID Register) 2055 * 2056 */ 2057union cvmx_pcieepx_cfg011 { 2058 uint32_t u32; 2059 struct cvmx_pcieepx_cfg011_s { 2060#ifdef __BIG_ENDIAN_BITFIELD 2061 uint32_t ssid : 16; /**< Subsystem ID 2062 Assigned by PCI-SIG, writable through PEM(0..1)_CFG_WR. However, the application must not change this field. */ 2063 uint32_t ssvid : 16; /**< Subsystem Vendor ID 2064 Assigned by PCI-SIG, writable through PEM(0..1)_CFG_WR. 2065 However, the application must not change this field. */ 2066#else 2067 uint32_t ssvid : 16; 2068 uint32_t ssid : 16; 2069#endif 2070 } s; 2071 struct cvmx_pcieepx_cfg011_s cn52xx; 2072 struct cvmx_pcieepx_cfg011_s cn52xxp1; 2073 struct cvmx_pcieepx_cfg011_s cn56xx; 2074 struct cvmx_pcieepx_cfg011_s cn56xxp1; 2075 struct cvmx_pcieepx_cfg011_s cn61xx; 2076 struct cvmx_pcieepx_cfg011_s cn63xx; 2077 struct cvmx_pcieepx_cfg011_s cn63xxp1; 2078 struct cvmx_pcieepx_cfg011_s cn66xx; 2079 struct cvmx_pcieepx_cfg011_s cn68xx; 2080 struct cvmx_pcieepx_cfg011_s cn68xxp1; 2081 struct cvmx_pcieepx_cfg011_s cnf71xx; 2082}; 2083typedef union cvmx_pcieepx_cfg011 cvmx_pcieepx_cfg011_t; 2084 2085/** 2086 * cvmx_pcieep#_cfg012 2087 * 2088 * PCIE_CFG012 = Thirteenth 32-bits of PCIE type 0 config space (Expansion ROM Base Address Register) 2089 * 2090 */ 2091union cvmx_pcieepx_cfg012 { 2092 uint32_t u32; 2093 struct cvmx_pcieepx_cfg012_s { 2094#ifdef __BIG_ENDIAN_BITFIELD 2095 uint32_t eraddr : 16; /**< Expansion ROM Address */ 2096 uint32_t reserved_1_15 : 15; 2097 uint32_t er_en : 1; /**< Expansion ROM Enable */ 2098#else 2099 uint32_t er_en : 1; 2100 uint32_t reserved_1_15 : 15; 2101 uint32_t eraddr : 16; 2102#endif 2103 } s; 2104 struct cvmx_pcieepx_cfg012_s cn52xx; 2105 struct cvmx_pcieepx_cfg012_s cn52xxp1; 2106 struct cvmx_pcieepx_cfg012_s cn56xx; 2107 struct cvmx_pcieepx_cfg012_s cn56xxp1; 2108 struct cvmx_pcieepx_cfg012_s cn61xx; 2109 struct cvmx_pcieepx_cfg012_s cn63xx; 2110 struct cvmx_pcieepx_cfg012_s cn63xxp1; 2111 struct cvmx_pcieepx_cfg012_s cn66xx; 2112 struct cvmx_pcieepx_cfg012_s cn68xx; 2113 struct cvmx_pcieepx_cfg012_s cn68xxp1; 2114 struct cvmx_pcieepx_cfg012_s cnf71xx; 2115}; 2116typedef union cvmx_pcieepx_cfg012 cvmx_pcieepx_cfg012_t; 2117 2118/** 2119 * cvmx_pcieep#_cfg012_mask 2120 * 2121 * PCIE_CFG012_MASK (Exapansion ROM BAR Mask) 2122 * The ROM Mask register is invisible to host software and not readable from the application. 2123 * The ROM Mask register is only writable through PEM(0..1)_CFG_WR. 2124 */ 2125union cvmx_pcieepx_cfg012_mask { 2126 uint32_t u32; 2127 struct cvmx_pcieepx_cfg012_mask_s { 2128#ifdef __BIG_ENDIAN_BITFIELD 2129 uint32_t mask : 31; /**< Bar Mask Low NS */ 2130 uint32_t enb : 1; /**< Bar Enable NS 2131 o 0: BAR ROM is disabled 2132 o 1: BAR ROM is enabled 2133 Bit 0 is interpreted as BAR Enable when writing to the BAR Mask 2134 register rather than as a mask bit because bit 0 of a BAR is 2135 always masked from writing by host software. Bit 0 must be 2136 written prior to writing the other mask bits. */ 2137#else 2138 uint32_t enb : 1; 2139 uint32_t mask : 31; 2140#endif 2141 } s; 2142 struct cvmx_pcieepx_cfg012_mask_s cn52xx; 2143 struct cvmx_pcieepx_cfg012_mask_s cn52xxp1; 2144 struct cvmx_pcieepx_cfg012_mask_s cn56xx; 2145 struct cvmx_pcieepx_cfg012_mask_s cn56xxp1; 2146 struct cvmx_pcieepx_cfg012_mask_s cn61xx; 2147 struct cvmx_pcieepx_cfg012_mask_s cn63xx; 2148 struct cvmx_pcieepx_cfg012_mask_s cn63xxp1; 2149 struct cvmx_pcieepx_cfg012_mask_s cn66xx; 2150 struct cvmx_pcieepx_cfg012_mask_s cn68xx; 2151 struct cvmx_pcieepx_cfg012_mask_s cn68xxp1; 2152 struct cvmx_pcieepx_cfg012_mask_s cnf71xx; 2153}; 2154typedef union cvmx_pcieepx_cfg012_mask cvmx_pcieepx_cfg012_mask_t; 2155 2156/** 2157 * cvmx_pcieep#_cfg013 2158 * 2159 * PCIE_CFG013 = Fourteenth 32-bits of PCIE type 0 config space (Capability Pointer Register) 2160 * 2161 */ 2162union cvmx_pcieepx_cfg013 { 2163 uint32_t u32; 2164 struct cvmx_pcieepx_cfg013_s { 2165#ifdef __BIG_ENDIAN_BITFIELD 2166 uint32_t reserved_8_31 : 24; 2167 uint32_t cp : 8; /**< First Capability Pointer. 2168 Points to Power Management Capability structure by 2169 default, writable through PEM(0..1)_CFG_WR. 2170 However, the application must not change this field. */ 2171#else 2172 uint32_t cp : 8; 2173 uint32_t reserved_8_31 : 24; 2174#endif 2175 } s; 2176 struct cvmx_pcieepx_cfg013_s cn52xx; 2177 struct cvmx_pcieepx_cfg013_s cn52xxp1; 2178 struct cvmx_pcieepx_cfg013_s cn56xx; 2179 struct cvmx_pcieepx_cfg013_s cn56xxp1; 2180 struct cvmx_pcieepx_cfg013_s cn61xx; 2181 struct cvmx_pcieepx_cfg013_s cn63xx; 2182 struct cvmx_pcieepx_cfg013_s cn63xxp1; 2183 struct cvmx_pcieepx_cfg013_s cn66xx; 2184 struct cvmx_pcieepx_cfg013_s cn68xx; 2185 struct cvmx_pcieepx_cfg013_s cn68xxp1; 2186 struct cvmx_pcieepx_cfg013_s cnf71xx; 2187}; 2188typedef union cvmx_pcieepx_cfg013 cvmx_pcieepx_cfg013_t; 2189 2190/** 2191 * cvmx_pcieep#_cfg015 2192 * 2193 * PCIE_CFG015 = Sixteenth 32-bits of PCIE type 0 config space (Interrupt Line Register/Interrupt Pin/Bridge Control Register) 2194 * 2195 */ 2196union cvmx_pcieepx_cfg015 { 2197 uint32_t u32; 2198 struct cvmx_pcieepx_cfg015_s { 2199#ifdef __BIG_ENDIAN_BITFIELD 2200 uint32_t ml : 8; /**< Maximum Latency (Hardwired to 0) */ 2201 uint32_t mg : 8; /**< Minimum Grant (Hardwired to 0) */ 2202 uint32_t inta : 8; /**< Interrupt Pin 2203 Identifies the legacy interrupt Message that the device 2204 (or device function) uses. 2205 The Interrupt Pin register is writable through PEM(0..1)_CFG_WR. 2206 In a single-function configuration, only INTA is used. 2207 Therefore, the application must not change this field. */ 2208 uint32_t il : 8; /**< Interrupt Line */ 2209#else 2210 uint32_t il : 8; 2211 uint32_t inta : 8; 2212 uint32_t mg : 8; 2213 uint32_t ml : 8; 2214#endif 2215 } s; 2216 struct cvmx_pcieepx_cfg015_s cn52xx; 2217 struct cvmx_pcieepx_cfg015_s cn52xxp1; 2218 struct cvmx_pcieepx_cfg015_s cn56xx; 2219 struct cvmx_pcieepx_cfg015_s cn56xxp1; 2220 struct cvmx_pcieepx_cfg015_s cn61xx; 2221 struct cvmx_pcieepx_cfg015_s cn63xx; 2222 struct cvmx_pcieepx_cfg015_s cn63xxp1; 2223 struct cvmx_pcieepx_cfg015_s cn66xx; 2224 struct cvmx_pcieepx_cfg015_s cn68xx; 2225 struct cvmx_pcieepx_cfg015_s cn68xxp1; 2226 struct cvmx_pcieepx_cfg015_s cnf71xx; 2227}; 2228typedef union cvmx_pcieepx_cfg015 cvmx_pcieepx_cfg015_t; 2229 2230/** 2231 * cvmx_pcieep#_cfg016 2232 * 2233 * PCIE_CFG016 = Seventeenth 32-bits of PCIE type 0 config space 2234 * (Power Management Capability ID/ 2235 * Power Management Next Item Pointer/ 2236 * Power Management Capabilities Register) 2237 */ 2238union cvmx_pcieepx_cfg016 { 2239 uint32_t u32; 2240 struct cvmx_pcieepx_cfg016_s { 2241#ifdef __BIG_ENDIAN_BITFIELD 2242 uint32_t pmes : 5; /**< PME_Support 2243 o Bit 11: If set, PME Messages can be generated from D0 2244 o Bit 12: If set, PME Messages can be generated from D1 2245 o Bit 13: If set, PME Messages can be generated from D2 2246 o Bit 14: If set, PME Messages can be generated from D3hot 2247 o Bit 15: If set, PME Messages can be generated from D3cold 2248 The PME_Support field is writable through PEM(0..1)_CFG_WR. 2249 However, the application must not change this field. */ 2250 uint32_t d2s : 1; /**< D2 Support, writable through PEM(0..1)_CFG_WR 2251 However, the application must not change this field. */ 2252 uint32_t d1s : 1; /**< D1 Support, writable through PEM(0..1)_CFG_WR 2253 However, the application must not change this field. */ 2254 uint32_t auxc : 3; /**< AUX Current, writable through PEM(0..1)_CFG_WR 2255 However, the application must not change this field. */ 2256 uint32_t dsi : 1; /**< Device Specific Initialization (DSI), writable through PEM(0..1)_CFG_WR 2257 However, the application must not change this field. */ 2258 uint32_t reserved_20_20 : 1; 2259 uint32_t pme_clock : 1; /**< PME Clock, hardwired to 0 */ 2260 uint32_t pmsv : 3; /**< Power Management Specification Version, writable through PEM(0..1)_CFG_WR 2261 However, the application must not change this field. */ 2262 uint32_t ncp : 8; /**< Next Capability Pointer 2263 Points to the MSI capabilities by default, writable 2264 through PEM(0..1)_CFG_WR. 2265 However, the application must not change this field. */ 2266 uint32_t pmcid : 8; /**< Power Management Capability ID */ 2267#else 2268 uint32_t pmcid : 8; 2269 uint32_t ncp : 8; 2270 uint32_t pmsv : 3; 2271 uint32_t pme_clock : 1; 2272 uint32_t reserved_20_20 : 1; 2273 uint32_t dsi : 1; 2274 uint32_t auxc : 3; 2275 uint32_t d1s : 1; 2276 uint32_t d2s : 1; 2277 uint32_t pmes : 5; 2278#endif 2279 } s; 2280 struct cvmx_pcieepx_cfg016_s cn52xx; 2281 struct cvmx_pcieepx_cfg016_s cn52xxp1; 2282 struct cvmx_pcieepx_cfg016_s cn56xx; 2283 struct cvmx_pcieepx_cfg016_s cn56xxp1; 2284 struct cvmx_pcieepx_cfg016_s cn61xx; 2285 struct cvmx_pcieepx_cfg016_s cn63xx; 2286 struct cvmx_pcieepx_cfg016_s cn63xxp1; 2287 struct cvmx_pcieepx_cfg016_s cn66xx; 2288 struct cvmx_pcieepx_cfg016_s cn68xx; 2289 struct cvmx_pcieepx_cfg016_s cn68xxp1; 2290 struct cvmx_pcieepx_cfg016_s cnf71xx; 2291}; 2292typedef union cvmx_pcieepx_cfg016 cvmx_pcieepx_cfg016_t; 2293 2294/** 2295 * cvmx_pcieep#_cfg017 2296 * 2297 * PCIE_CFG017 = Eighteenth 32-bits of PCIE type 0 config space (Power Management Control and Status Register) 2298 * 2299 */ 2300union cvmx_pcieepx_cfg017 { 2301 uint32_t u32; 2302 struct cvmx_pcieepx_cfg017_s { 2303#ifdef __BIG_ENDIAN_BITFIELD 2304 uint32_t pmdia : 8; /**< Data register for additional information (not supported) */ 2305 uint32_t bpccee : 1; /**< Bus Power/Clock Control Enable, hardwired to 0 */ 2306 uint32_t bd3h : 1; /**< B2/B3 Support, hardwired to 0 */ 2307 uint32_t reserved_16_21 : 6; 2308 uint32_t pmess : 1; /**< PME Status 2309 Indicates if a previously enabled PME event occurred or not. */ 2310 uint32_t pmedsia : 2; /**< Data Scale (not supported) */ 2311 uint32_t pmds : 4; /**< Data Select (not supported) */ 2312 uint32_t pmeens : 1; /**< PME Enable 2313 A value of 1 indicates that the device is enabled to 2314 generate PME. */ 2315 uint32_t reserved_4_7 : 4; 2316 uint32_t nsr : 1; /**< No Soft Reset, writable through PEM(0..1)_CFG_WR 2317 However, the application must not change this field. */ 2318 uint32_t reserved_2_2 : 1; 2319 uint32_t ps : 2; /**< Power State 2320 Controls the device power state: 2321 o 00b: D0 2322 o 01b: D1 2323 o 10b: D2 2324 o 11b: D3 2325 The written value is ignored if the specific state is 2326 not supported. */ 2327#else 2328 uint32_t ps : 2; 2329 uint32_t reserved_2_2 : 1; 2330 uint32_t nsr : 1; 2331 uint32_t reserved_4_7 : 4; 2332 uint32_t pmeens : 1; 2333 uint32_t pmds : 4; 2334 uint32_t pmedsia : 2; 2335 uint32_t pmess : 1; 2336 uint32_t reserved_16_21 : 6; 2337 uint32_t bd3h : 1; 2338 uint32_t bpccee : 1; 2339 uint32_t pmdia : 8; 2340#endif 2341 } s; 2342 struct cvmx_pcieepx_cfg017_s cn52xx; 2343 struct cvmx_pcieepx_cfg017_s cn52xxp1; 2344 struct cvmx_pcieepx_cfg017_s cn56xx; 2345 struct cvmx_pcieepx_cfg017_s cn56xxp1; 2346 struct cvmx_pcieepx_cfg017_s cn61xx; 2347 struct cvmx_pcieepx_cfg017_s cn63xx; 2348 struct cvmx_pcieepx_cfg017_s cn63xxp1; 2349 struct cvmx_pcieepx_cfg017_s cn66xx; 2350 struct cvmx_pcieepx_cfg017_s cn68xx; 2351 struct cvmx_pcieepx_cfg017_s cn68xxp1; 2352 struct cvmx_pcieepx_cfg017_s cnf71xx; 2353}; 2354typedef union cvmx_pcieepx_cfg017 cvmx_pcieepx_cfg017_t; 2355 2356/** 2357 * cvmx_pcieep#_cfg020 2358 * 2359 * PCIE_CFG020 = Twenty-first 32-bits of PCIE type 0 config space 2360 * (MSI Capability ID/ 2361 * MSI Next Item Pointer/ 2362 * MSI Control Register) 2363 */ 2364union cvmx_pcieepx_cfg020 { 2365 uint32_t u32; 2366 struct cvmx_pcieepx_cfg020_s { 2367#ifdef __BIG_ENDIAN_BITFIELD 2368 uint32_t reserved_25_31 : 7; 2369 uint32_t pvm : 1; /**< Per-vector masking capable */ 2370 uint32_t m64 : 1; /**< 64-bit Address Capable, writable through PEM(0..1)_CFG_WR 2371 However, the application must not change this field. */ 2372 uint32_t mme : 3; /**< Multiple Message Enabled 2373 Indicates that multiple Message mode is enabled by system 2374 software. The number of Messages enabled must be less than 2375 or equal to the Multiple Message Capable value. */ 2376 uint32_t mmc : 3; /**< Multiple Message Capable, writable through PEM(0..1)_CFG_WR 2377 However, the application must not change this field. */ 2378 uint32_t msien : 1; /**< MSI Enabled 2379 When set, INTx must be disabled. */ 2380 uint32_t ncp : 8; /**< Next Capability Pointer 2381 Points to PCI Express Capabilities by default, 2382 writable through PEM(0..1)_CFG_WR. 2383 However, the application must not change this field. */ 2384 uint32_t msicid : 8; /**< MSI Capability ID */ 2385#else 2386 uint32_t msicid : 8; 2387 uint32_t ncp : 8; 2388 uint32_t msien : 1; 2389 uint32_t mmc : 3; 2390 uint32_t mme : 3; 2391 uint32_t m64 : 1; 2392 uint32_t pvm : 1; 2393 uint32_t reserved_25_31 : 7; 2394#endif 2395 } s; 2396 struct cvmx_pcieepx_cfg020_cn52xx { 2397#ifdef __BIG_ENDIAN_BITFIELD 2398 uint32_t reserved_24_31 : 8; 2399 uint32_t m64 : 1; /**< 64-bit Address Capable, writable through PESC(0..1)_CFG_WR 2400 However, the application must not change this field. */ 2401 uint32_t mme : 3; /**< Multiple Message Enabled 2402 Indicates that multiple Message mode is enabled by system 2403 software. The number of Messages enabled must be less than 2404 or equal to the Multiple Message Capable value. */ 2405 uint32_t mmc : 3; /**< Multiple Message Capable, writable through PESC(0..1)_CFG_WR 2406 However, the application must not change this field. */ 2407 uint32_t msien : 1; /**< MSI Enabled 2408 When set, INTx must be disabled. */ 2409 uint32_t ncp : 8; /**< Next Capability Pointer 2410 Points to PCI Express Capabilities by default, 2411 writable through PESC(0..1)_CFG_WR. 2412 However, the application must not change this field. */ 2413 uint32_t msicid : 8; /**< MSI Capability ID */ 2414#else 2415 uint32_t msicid : 8; 2416 uint32_t ncp : 8; 2417 uint32_t msien : 1; 2418 uint32_t mmc : 3; 2419 uint32_t mme : 3; 2420 uint32_t m64 : 1; 2421 uint32_t reserved_24_31 : 8; 2422#endif 2423 } cn52xx; 2424 struct cvmx_pcieepx_cfg020_cn52xx cn52xxp1; 2425 struct cvmx_pcieepx_cfg020_cn52xx cn56xx; 2426 struct cvmx_pcieepx_cfg020_cn52xx cn56xxp1; 2427 struct cvmx_pcieepx_cfg020_s cn61xx; 2428 struct cvmx_pcieepx_cfg020_cn52xx cn63xx; 2429 struct cvmx_pcieepx_cfg020_cn52xx cn63xxp1; 2430 struct cvmx_pcieepx_cfg020_s cn66xx; 2431 struct cvmx_pcieepx_cfg020_s cn68xx; 2432 struct cvmx_pcieepx_cfg020_s cn68xxp1; 2433 struct cvmx_pcieepx_cfg020_s cnf71xx; 2434}; 2435typedef union cvmx_pcieepx_cfg020 cvmx_pcieepx_cfg020_t; 2436 2437/** 2438 * cvmx_pcieep#_cfg021 2439 * 2440 * PCIE_CFG021 = Twenty-second 32-bits of PCIE type 0 config space (MSI Lower 32 Bits Address Register) 2441 * 2442 */ 2443union cvmx_pcieepx_cfg021 { 2444 uint32_t u32; 2445 struct cvmx_pcieepx_cfg021_s { 2446#ifdef __BIG_ENDIAN_BITFIELD 2447 uint32_t lmsi : 30; /**< Lower 32-bit Address */ 2448 uint32_t reserved_0_1 : 2; 2449#else 2450 uint32_t reserved_0_1 : 2; 2451 uint32_t lmsi : 30; 2452#endif 2453 } s; 2454 struct cvmx_pcieepx_cfg021_s cn52xx; 2455 struct cvmx_pcieepx_cfg021_s cn52xxp1; 2456 struct cvmx_pcieepx_cfg021_s cn56xx; 2457 struct cvmx_pcieepx_cfg021_s cn56xxp1; 2458 struct cvmx_pcieepx_cfg021_s cn61xx; 2459 struct cvmx_pcieepx_cfg021_s cn63xx; 2460 struct cvmx_pcieepx_cfg021_s cn63xxp1; 2461 struct cvmx_pcieepx_cfg021_s cn66xx; 2462 struct cvmx_pcieepx_cfg021_s cn68xx; 2463 struct cvmx_pcieepx_cfg021_s cn68xxp1; 2464 struct cvmx_pcieepx_cfg021_s cnf71xx; 2465}; 2466typedef union cvmx_pcieepx_cfg021 cvmx_pcieepx_cfg021_t; 2467 2468/** 2469 * cvmx_pcieep#_cfg022 2470 * 2471 * PCIE_CFG022 = Twenty-third 32-bits of PCIE type 0 config space (MSI Upper 32 bits Address Register) 2472 * 2473 */ 2474union cvmx_pcieepx_cfg022 { 2475 uint32_t u32; 2476 struct cvmx_pcieepx_cfg022_s { 2477#ifdef __BIG_ENDIAN_BITFIELD 2478 uint32_t umsi : 32; /**< Upper 32-bit Address */ 2479#else 2480 uint32_t umsi : 32; 2481#endif 2482 } s; 2483 struct cvmx_pcieepx_cfg022_s cn52xx; 2484 struct cvmx_pcieepx_cfg022_s cn52xxp1; 2485 struct cvmx_pcieepx_cfg022_s cn56xx; 2486 struct cvmx_pcieepx_cfg022_s cn56xxp1; 2487 struct cvmx_pcieepx_cfg022_s cn61xx; 2488 struct cvmx_pcieepx_cfg022_s cn63xx; 2489 struct cvmx_pcieepx_cfg022_s cn63xxp1; 2490 struct cvmx_pcieepx_cfg022_s cn66xx; 2491 struct cvmx_pcieepx_cfg022_s cn68xx; 2492 struct cvmx_pcieepx_cfg022_s cn68xxp1; 2493 struct cvmx_pcieepx_cfg022_s cnf71xx; 2494}; 2495typedef union cvmx_pcieepx_cfg022 cvmx_pcieepx_cfg022_t; 2496 2497/** 2498 * cvmx_pcieep#_cfg023 2499 * 2500 * PCIE_CFG023 = Twenty-fourth 32-bits of PCIE type 0 config space (MSI Data Register) 2501 * 2502 */ 2503union cvmx_pcieepx_cfg023 { 2504 uint32_t u32; 2505 struct cvmx_pcieepx_cfg023_s { 2506#ifdef __BIG_ENDIAN_BITFIELD 2507 uint32_t reserved_16_31 : 16; 2508 uint32_t msimd : 16; /**< MSI Data 2509 Pattern assigned by system software, bits [4:0] are Or-ed with 2510 MSI_VECTOR to generate 32 MSI Messages per function. */ 2511#else 2512 uint32_t msimd : 16; 2513 uint32_t reserved_16_31 : 16; 2514#endif 2515 } s; 2516 struct cvmx_pcieepx_cfg023_s cn52xx; 2517 struct cvmx_pcieepx_cfg023_s cn52xxp1; 2518 struct cvmx_pcieepx_cfg023_s cn56xx; 2519 struct cvmx_pcieepx_cfg023_s cn56xxp1; 2520 struct cvmx_pcieepx_cfg023_s cn61xx; 2521 struct cvmx_pcieepx_cfg023_s cn63xx; 2522 struct cvmx_pcieepx_cfg023_s cn63xxp1; 2523 struct cvmx_pcieepx_cfg023_s cn66xx; 2524 struct cvmx_pcieepx_cfg023_s cn68xx; 2525 struct cvmx_pcieepx_cfg023_s cn68xxp1; 2526 struct cvmx_pcieepx_cfg023_s cnf71xx; 2527}; 2528typedef union cvmx_pcieepx_cfg023 cvmx_pcieepx_cfg023_t; 2529 2530/** 2531 * cvmx_pcieep#_cfg028 2532 * 2533 * PCIE_CFG028 = Twenty-ninth 32-bits of PCIE type 0 config space 2534 * (PCI Express Capabilities List Register/ 2535 * PCI Express Capabilities Register) 2536 */ 2537union cvmx_pcieepx_cfg028 { 2538 uint32_t u32; 2539 struct cvmx_pcieepx_cfg028_s { 2540#ifdef __BIG_ENDIAN_BITFIELD 2541 uint32_t reserved_30_31 : 2; 2542 uint32_t imn : 5; /**< Interrupt Message Number 2543 Updated by hardware, writable through PEM(0..1)_CFG_WR. 2544 However, the application must not change this field. */ 2545 uint32_t si : 1; /**< Slot Implemented 2546 This bit is writable through PEM(0..1)_CFG_WR. 2547 However, it must be 0 for 2548 an Endpoint device. Therefore, the application must not write a 2549 1 to this bit. */ 2550 uint32_t dpt : 4; /**< Device Port Type */ 2551 uint32_t pciecv : 4; /**< PCI Express Capability Version */ 2552 uint32_t ncp : 8; /**< Next Capability Pointer 2553 writable through PEM(0..1)_CFG_WR. 2554 However, the application must not change this field. */ 2555 uint32_t pcieid : 8; /**< PCIE Capability ID */ 2556#else 2557 uint32_t pcieid : 8; 2558 uint32_t ncp : 8; 2559 uint32_t pciecv : 4; 2560 uint32_t dpt : 4; 2561 uint32_t si : 1; 2562 uint32_t imn : 5; 2563 uint32_t reserved_30_31 : 2; 2564#endif 2565 } s; 2566 struct cvmx_pcieepx_cfg028_s cn52xx; 2567 struct cvmx_pcieepx_cfg028_s cn52xxp1; 2568 struct cvmx_pcieepx_cfg028_s cn56xx; 2569 struct cvmx_pcieepx_cfg028_s cn56xxp1; 2570 struct cvmx_pcieepx_cfg028_s cn61xx; 2571 struct cvmx_pcieepx_cfg028_s cn63xx; 2572 struct cvmx_pcieepx_cfg028_s cn63xxp1; 2573 struct cvmx_pcieepx_cfg028_s cn66xx; 2574 struct cvmx_pcieepx_cfg028_s cn68xx; 2575 struct cvmx_pcieepx_cfg028_s cn68xxp1; 2576 struct cvmx_pcieepx_cfg028_s cnf71xx; 2577}; 2578typedef union cvmx_pcieepx_cfg028 cvmx_pcieepx_cfg028_t; 2579 2580/** 2581 * cvmx_pcieep#_cfg029 2582 * 2583 * PCIE_CFG029 = Thirtieth 32-bits of PCIE type 0 config space (Device Capabilities Register) 2584 * 2585 */ 2586union cvmx_pcieepx_cfg029 { 2587 uint32_t u32; 2588 struct cvmx_pcieepx_cfg029_s { 2589#ifdef __BIG_ENDIAN_BITFIELD 2590 uint32_t reserved_28_31 : 4; 2591 uint32_t cspls : 2; /**< Captured Slot Power Limit Scale 2592 From Message from RC, upstream port only. */ 2593 uint32_t csplv : 8; /**< Captured Slot Power Limit Value 2594 From Message from RC, upstream port only. */ 2595 uint32_t reserved_16_17 : 2; 2596 uint32_t rber : 1; /**< Role-Based Error Reporting, writable through PEM(0..1)_CFG_WR 2597 However, the application must not change this field. */ 2598 uint32_t reserved_12_14 : 3; 2599 uint32_t el1al : 3; /**< Endpoint L1 Acceptable Latency, writable through PEM(0..1)_CFG_WR 2600 However, the application must not change this field. */ 2601 uint32_t el0al : 3; /**< Endpoint L0s Acceptable Latency, writable through PEM(0..1)_CFG_WR 2602 However, the application must not change this field. */ 2603 uint32_t etfs : 1; /**< Extended Tag Field Supported 2604 This bit is writable through PEM(0..1)_CFG_WR. 2605 However, the application 2606 must not write a 1 to this bit. */ 2607 uint32_t pfs : 2; /**< Phantom Function Supported 2608 This field is writable through PEM(0..1)_CFG_WR. 2609 However, Phantom 2610 Function is not supported. Therefore, the application must not 2611 write any value other than 0x0 to this field. */ 2612 uint32_t mpss : 3; /**< Max_Payload_Size Supported, writable through PEM(0..1)_CFG_WR 2613 However, the application must not change this field. */ 2614#else 2615 uint32_t mpss : 3; 2616 uint32_t pfs : 2; 2617 uint32_t etfs : 1; 2618 uint32_t el0al : 3; 2619 uint32_t el1al : 3; 2620 uint32_t reserved_12_14 : 3; 2621 uint32_t rber : 1; 2622 uint32_t reserved_16_17 : 2; 2623 uint32_t csplv : 8; 2624 uint32_t cspls : 2; 2625 uint32_t reserved_28_31 : 4; 2626#endif 2627 } s; 2628 struct cvmx_pcieepx_cfg029_s cn52xx; 2629 struct cvmx_pcieepx_cfg029_s cn52xxp1; 2630 struct cvmx_pcieepx_cfg029_s cn56xx; 2631 struct cvmx_pcieepx_cfg029_s cn56xxp1; 2632 struct cvmx_pcieepx_cfg029_cn61xx { 2633#ifdef __BIG_ENDIAN_BITFIELD 2634 uint32_t reserved_29_31 : 3; 2635 uint32_t flr_cap : 1; /**< Function Level Reset Capable 2636 not supported */ 2637 uint32_t cspls : 2; /**< Captured Slot Power Limit Scale 2638 From Message from RC, upstream port only. */ 2639 uint32_t csplv : 8; /**< Captured Slot Power Limit Value 2640 From Message from RC, upstream port only. */ 2641 uint32_t reserved_16_17 : 2; 2642 uint32_t rber : 1; /**< Role-Based Error Reporting, writable through PEM(0..1)_CFG_WR 2643 However, the application must not change this field. */ 2644 uint32_t reserved_12_14 : 3; 2645 uint32_t el1al : 3; /**< Endpoint L1 Acceptable Latency, writable through PEM(0..1)_CFG_WR 2646 However, the application must not change this field. */ 2647 uint32_t el0al : 3; /**< Endpoint L0s Acceptable Latency, writable through PEM(0..1)_CFG_WR 2648 However, the application must not change this field. */ 2649 uint32_t etfs : 1; /**< Extended Tag Field Supported 2650 This bit is writable through PEM(0..1)_CFG_WR. 2651 However, the application 2652 must not write a 1 to this bit. */ 2653 uint32_t pfs : 2; /**< Phantom Function Supported 2654 This field is writable through PEM(0..1)_CFG_WR. 2655 However, Phantom 2656 Function is not supported. Therefore, the application must not 2657 write any value other than 0x0 to this field. */ 2658 uint32_t mpss : 3; /**< Max_Payload_Size Supported, writable through PEM(0..1)_CFG_WR 2659 However, the application must not change this field. */ 2660#else 2661 uint32_t mpss : 3; 2662 uint32_t pfs : 2; 2663 uint32_t etfs : 1; 2664 uint32_t el0al : 3; 2665 uint32_t el1al : 3; 2666 uint32_t reserved_12_14 : 3; 2667 uint32_t rber : 1; 2668 uint32_t reserved_16_17 : 2; 2669 uint32_t csplv : 8; 2670 uint32_t cspls : 2; 2671 uint32_t flr_cap : 1; 2672 uint32_t reserved_29_31 : 3; 2673#endif 2674 } cn61xx; 2675 struct cvmx_pcieepx_cfg029_s cn63xx; 2676 struct cvmx_pcieepx_cfg029_s cn63xxp1; 2677 struct cvmx_pcieepx_cfg029_cn66xx { 2678#ifdef __BIG_ENDIAN_BITFIELD 2679 uint32_t reserved_29_31 : 3; 2680 uint32_t flr : 1; /**< Function Level Reset Capability 2681 When set, core support of SR-IOV */ 2682 uint32_t cspls : 2; /**< Captured Slot Power Limit Scale 2683 From Message from RC, upstream port only. */ 2684 uint32_t csplv : 8; /**< Captured Slot Power Limit Value 2685 From Message from RC, upstream port only. */ 2686 uint32_t reserved_16_17 : 2; 2687 uint32_t rber : 1; /**< Role-Based Error Reporting, writable through PEM(0..1)_CFG_WR 2688 However, the application must not change this field. */ 2689 uint32_t reserved_12_14 : 3; 2690 uint32_t el1al : 3; /**< Endpoint L1 Acceptable Latency, writable through PEM(0..1)_CFG_WR 2691 However, the application must not change this field. */ 2692 uint32_t el0al : 3; /**< Endpoint L0s Acceptable Latency, writable through PEM(0..1)_CFG_WR 2693 However, the application must not change this field. */ 2694 uint32_t etfs : 1; /**< Extended Tag Field Supported 2695 This bit is writable through PEM(0..1)_CFG_WR. 2696 However, the application 2697 must not write a 1 to this bit. */ 2698 uint32_t pfs : 2; /**< Phantom Function Supported 2699 This field is writable through PEM(0..1)_CFG_WR. 2700 However, Phantom 2701 Function is not supported. Therefore, the application must not 2702 write any value other than 0x0 to this field. */ 2703 uint32_t mpss : 3; /**< Max_Payload_Size Supported, writable through PEM(0..1)_CFG_WR 2704 However, the application must not change this field. */ 2705#else 2706 uint32_t mpss : 3; 2707 uint32_t pfs : 2; 2708 uint32_t etfs : 1; 2709 uint32_t el0al : 3; 2710 uint32_t el1al : 3; 2711 uint32_t reserved_12_14 : 3; 2712 uint32_t rber : 1; 2713 uint32_t reserved_16_17 : 2; 2714 uint32_t csplv : 8; 2715 uint32_t cspls : 2; 2716 uint32_t flr : 1; 2717 uint32_t reserved_29_31 : 3; 2718#endif 2719 } cn66xx; 2720 struct cvmx_pcieepx_cfg029_cn66xx cn68xx; 2721 struct cvmx_pcieepx_cfg029_cn66xx cn68xxp1; 2722 struct cvmx_pcieepx_cfg029_cn61xx cnf71xx; 2723}; 2724typedef union cvmx_pcieepx_cfg029 cvmx_pcieepx_cfg029_t; 2725 2726/** 2727 * cvmx_pcieep#_cfg030 2728 * 2729 * PCIE_CFG030 = Thirty-first 32-bits of PCIE type 0 config space 2730 * (Device Control Register/Device Status Register) 2731 */ 2732union cvmx_pcieepx_cfg030 { 2733 uint32_t u32; 2734 struct cvmx_pcieepx_cfg030_s { 2735#ifdef __BIG_ENDIAN_BITFIELD 2736 uint32_t reserved_22_31 : 10; 2737 uint32_t tp : 1; /**< Transaction Pending 2738 Set to 1 when Non-Posted Requests are not yet completed 2739 and clear when they are completed. */ 2740 uint32_t ap_d : 1; /**< Aux Power Detected 2741 Set to 1 if Aux power detected. */ 2742 uint32_t ur_d : 1; /**< Unsupported Request Detected 2743 Errors are logged in this register regardless of whether 2744 error reporting is enabled in the Device Control register. 2745 UR_D occurs when we receive something we don't support. 2746 Unsupported requests are Nonfatal errors, so UR_D should 2747 cause NFE_D. Receiving a vendor defined message should 2748 cause an unsupported request. */ 2749 uint32_t fe_d : 1; /**< Fatal Error Detected 2750 Errors are logged in this register regardless of whether 2751 error reporting is enabled in the Device Control register. 2752 FE_D is set if receive any of the errors in PCIE_CFG066 that 2753 has a severity set to Fatal. Malformed TLP's generally fit 2754 into this category. */ 2755 uint32_t nfe_d : 1; /**< Non-Fatal Error detected 2756 Errors are logged in this register regardless of whether 2757 error reporting is enabled in the Device Control register. 2758 NFE_D is set if we receive any of the errors in PCIE_CFG066 2759 that has a severity set to Nonfatal and does NOT meet Advisory 2760 Nonfatal criteria , which 2761 most poisoned TLP's should be. */ 2762 uint32_t ce_d : 1; /**< Correctable Error Detected 2763 Errors are logged in this register regardless of whether 2764 error reporting is enabled in the Device Control register. 2765 CE_D is set if we receive any of the errors in PCIE_CFG068 2766 for example a Replay Timer Timeout. Also, it can be set if 2767 we get any of the errors in PCIE_CFG066 that has a severity 2768 set to Nonfatal and meets the Advisory Nonfatal criteria, 2769 which most ECRC errors 2770 should be. */ 2771 uint32_t i_flr : 1; /**< Initiate Function Level Reset 2772 (Not Supported) */ 2773 uint32_t mrrs : 3; /**< Max Read Request Size 2774 0 = 128B 2775 1 = 256B 2776 2 = 512B 2777 3 = 1024B 2778 4 = 2048B 2779 5 = 4096B 2780 Note: SLI_S2M_PORT#_CTL[MRRS] and DPI_SLI_PRT#_CFG[MRRS] and 2781 also must be set properly. 2782 SLI_S2M_PORT#_CTL[MRRS] and DPI_SLI_PRT#_CFG[MRRS] must 2783 not exceed the desired max read request size. */ 2784 uint32_t ns_en : 1; /**< Enable No Snoop */ 2785 uint32_t ap_en : 1; /**< AUX Power PM Enable */ 2786 uint32_t pf_en : 1; /**< Phantom Function Enable 2787 This bit should never be set - OCTEON requests never use 2788 phantom functions. */ 2789 uint32_t etf_en : 1; /**< Extended Tag Field Enable 2790 This bit should never be set - OCTEON requests never use 2791 extended tags. */ 2792 uint32_t mps : 3; /**< Max Payload Size 2793 Legal values: 2794 0 = 128B 2795 1 = 256B 2796 Larger sizes not supported by OCTEON. 2797 Note: DPI_SLI_PRT#_CFG[MPS] must be set to the same 2798 value for proper functionality. */ 2799 uint32_t ro_en : 1; /**< Enable Relaxed Ordering 2800 This bit is not used. */ 2801 uint32_t ur_en : 1; /**< Unsupported Request Reporting Enable */ 2802 uint32_t fe_en : 1; /**< Fatal Error Reporting Enable */ 2803 uint32_t nfe_en : 1; /**< Non-Fatal Error Reporting Enable */ 2804 uint32_t ce_en : 1; /**< Correctable Error Reporting Enable */ 2805#else 2806 uint32_t ce_en : 1; 2807 uint32_t nfe_en : 1; 2808 uint32_t fe_en : 1; 2809 uint32_t ur_en : 1; 2810 uint32_t ro_en : 1; 2811 uint32_t mps : 3; 2812 uint32_t etf_en : 1; 2813 uint32_t pf_en : 1; 2814 uint32_t ap_en : 1; 2815 uint32_t ns_en : 1; 2816 uint32_t mrrs : 3; 2817 uint32_t i_flr : 1; 2818 uint32_t ce_d : 1; 2819 uint32_t nfe_d : 1; 2820 uint32_t fe_d : 1; 2821 uint32_t ur_d : 1; 2822 uint32_t ap_d : 1; 2823 uint32_t tp : 1; 2824 uint32_t reserved_22_31 : 10; 2825#endif 2826 } s; 2827 struct cvmx_pcieepx_cfg030_cn52xx { 2828#ifdef __BIG_ENDIAN_BITFIELD 2829 uint32_t reserved_22_31 : 10; 2830 uint32_t tp : 1; /**< Transaction Pending 2831 Set to 1 when Non-Posted Requests are not yet completed 2832 and clear when they are completed. */ 2833 uint32_t ap_d : 1; /**< Aux Power Detected 2834 Set to 1 if Aux power detected. */ 2835 uint32_t ur_d : 1; /**< Unsupported Request Detected 2836 Errors are logged in this register regardless of whether 2837 error reporting is enabled in the Device Control register. 2838 UR_D occurs when we receive something we don't support. 2839 Unsupported requests are Nonfatal errors, so UR_D should 2840 cause NFE_D. Receiving a vendor defined message should 2841 cause an unsupported request. */ 2842 uint32_t fe_d : 1; /**< Fatal Error Detected 2843 Errors are logged in this register regardless of whether 2844 error reporting is enabled in the Device Control register. 2845 FE_D is set if receive any of the errors in PCIE_CFG066 that 2846 has a severity set to Fatal. Malformed TLP's generally fit 2847 into this category. */ 2848 uint32_t nfe_d : 1; /**< Non-Fatal Error detected 2849 Errors are logged in this register regardless of whether 2850 error reporting is enabled in the Device Control register. 2851 NFE_D is set if we receive any of the errors in PCIE_CFG066 2852 that has a severity set to Nonfatal and does NOT meet Advisory 2853 Nonfatal criteria (PCIe 1.1 spec, Section 6.2.3.2.4), which 2854 most poisoned TLP's should be. */ 2855 uint32_t ce_d : 1; /**< Correctable Error Detected 2856 Errors are logged in this register regardless of whether 2857 error reporting is enabled in the Device Control register. 2858 CE_D is set if we receive any of the errors in PCIE_CFG068 2859 for example a Replay Timer Timeout. Also, it can be set if 2860 we get any of the errors in PCIE_CFG066 that has a severity 2861 set to Nonfatal and meets the Advisory Nonfatal criteria 2862 (PCIe 1.1 spec, Section 6.2.3.2.4), which most ECRC errors 2863 should be. */ 2864 uint32_t reserved_15_15 : 1; 2865 uint32_t mrrs : 3; /**< Max Read Request Size 2866 0 = 128B 2867 1 = 256B 2868 2 = 512B 2869 3 = 1024B 2870 4 = 2048B 2871 5 = 4096B 2872 Note: NPEI_CTL_STATUS2[MRRS] also must be set properly. 2873 NPEI_CTL_STATUS2[MRRS] must not exceed the 2874 desired max read request size. */ 2875 uint32_t ns_en : 1; /**< Enable No Snoop */ 2876 uint32_t ap_en : 1; /**< AUX Power PM Enable */ 2877 uint32_t pf_en : 1; /**< Phantom Function Enable 2878 This bit should never be set - OCTEON requests never use 2879 phantom functions. */ 2880 uint32_t etf_en : 1; /**< Extended Tag Field Enable 2881 This bit should never be set - OCTEON requests never use 2882 extended tags. */ 2883 uint32_t mps : 3; /**< Max Payload Size 2884 Legal values: 2885 0 = 128B 2886 1 = 256B 2887 Larger sizes not supported by OCTEON. 2888 Note: NPEI_CTL_STATUS2[MPS] must be set to the same 2889 value for proper functionality. */ 2890 uint32_t ro_en : 1; /**< Enable Relaxed Ordering */ 2891 uint32_t ur_en : 1; /**< Unsupported Request Reporting Enable */ 2892 uint32_t fe_en : 1; /**< Fatal Error Reporting Enable */ 2893 uint32_t nfe_en : 1; /**< Non-Fatal Error Reporting Enable */ 2894 uint32_t ce_en : 1; /**< Correctable Error Reporting Enable */ 2895#else 2896 uint32_t ce_en : 1; 2897 uint32_t nfe_en : 1; 2898 uint32_t fe_en : 1; 2899 uint32_t ur_en : 1; 2900 uint32_t ro_en : 1; 2901 uint32_t mps : 3; 2902 uint32_t etf_en : 1; 2903 uint32_t pf_en : 1; 2904 uint32_t ap_en : 1; 2905 uint32_t ns_en : 1; 2906 uint32_t mrrs : 3; 2907 uint32_t reserved_15_15 : 1; 2908 uint32_t ce_d : 1; 2909 uint32_t nfe_d : 1; 2910 uint32_t fe_d : 1; 2911 uint32_t ur_d : 1; 2912 uint32_t ap_d : 1; 2913 uint32_t tp : 1; 2914 uint32_t reserved_22_31 : 10; 2915#endif 2916 } cn52xx; 2917 struct cvmx_pcieepx_cfg030_cn52xx cn52xxp1; 2918 struct cvmx_pcieepx_cfg030_cn52xx cn56xx; 2919 struct cvmx_pcieepx_cfg030_cn52xx cn56xxp1; 2920 struct cvmx_pcieepx_cfg030_s cn61xx; 2921 struct cvmx_pcieepx_cfg030_cn52xx cn63xx; 2922 struct cvmx_pcieepx_cfg030_cn52xx cn63xxp1; 2923 struct cvmx_pcieepx_cfg030_s cn66xx; 2924 struct cvmx_pcieepx_cfg030_s cn68xx; 2925 struct cvmx_pcieepx_cfg030_s cn68xxp1; 2926 struct cvmx_pcieepx_cfg030_s cnf71xx; 2927}; 2928typedef union cvmx_pcieepx_cfg030 cvmx_pcieepx_cfg030_t; 2929 2930/** 2931 * cvmx_pcieep#_cfg031 2932 * 2933 * PCIE_CFG031 = Thirty-second 32-bits of PCIE type 0 config space 2934 * (Link Capabilities Register) 2935 */ 2936union cvmx_pcieepx_cfg031 { 2937 uint32_t u32; 2938 struct cvmx_pcieepx_cfg031_s { 2939#ifdef __BIG_ENDIAN_BITFIELD 2940 uint32_t pnum : 8; /**< Port Number 2941 writable through PEM(0..1)_CFG_WR, however the application 2942 must not change this field. */ 2943 uint32_t reserved_23_23 : 1; 2944 uint32_t aspm : 1; /**< ASPM Optionality Compliance */ 2945 uint32_t lbnc : 1; /**< Link Bandwidth Notification Capability 2946 Set 0 for Endpoint devices. */ 2947 uint32_t dllarc : 1; /**< Data Link Layer Active Reporting Capable */ 2948 uint32_t sderc : 1; /**< Surprise Down Error Reporting Capable 2949 Not supported, hardwired to 0x0. */ 2950 uint32_t cpm : 1; /**< Clock Power Management 2951 The default value is the value you specify during hardware 2952 configuration, writable through PEM(0..1)_CFG_WR. 2953 However, the application must not change this field. */ 2954 uint32_t l1el : 3; /**< L1 Exit Latency 2955 The default value is the value you specify during hardware 2956 configuration, writable through PEM(0..1)_CFG_WR. 2957 However, the application must not change this field. */ 2958 uint32_t l0el : 3; /**< L0s Exit Latency 2959 The default value is the value you specify during hardware 2960 configuration, writable through PEM(0..1)_CFG_WR. 2961 However, the application must not change this field. */ 2962 uint32_t aslpms : 2; /**< Active State Link PM Support 2963 The default value is the value you specify during hardware 2964 configuration, writable through PEM(0..1)_CFG_WR. 2965 However, the application must not change this field. */ 2966 uint32_t mlw : 6; /**< Maximum Link Width 2967 The default value is the value you specify during hardware 2968 configuration (x1), writable through PEM(0..1)_CFG_WR 2969 however wider cofigurations are not supported. */ 2970 uint32_t mls : 4; /**< Maximum Link Speed 2971 The reset value of this field is controlled by a value sent from 2972 the lsb of the MIO_QLM#_SPD register. 2973 qlm#_spd[1] RST_VALUE NOTE 2974 1 0001b 2.5 GHz supported 2975 0 0010b 5.0 GHz and 2.5 GHz supported 2976 This field is writable through PEM(0..1)_CFG_WR. 2977 However, the application must not change this field. */ 2978#else 2979 uint32_t mls : 4; 2980 uint32_t mlw : 6; 2981 uint32_t aslpms : 2; 2982 uint32_t l0el : 3; 2983 uint32_t l1el : 3; 2984 uint32_t cpm : 1; 2985 uint32_t sderc : 1; 2986 uint32_t dllarc : 1; 2987 uint32_t lbnc : 1; 2988 uint32_t aspm : 1; 2989 uint32_t reserved_23_23 : 1; 2990 uint32_t pnum : 8; 2991#endif 2992 } s; 2993 struct cvmx_pcieepx_cfg031_cn52xx { 2994#ifdef __BIG_ENDIAN_BITFIELD 2995 uint32_t pnum : 8; /**< Port Number, writable through PESC(0..1)_CFG_WR 2996 However, the application must not change this field. */ 2997 uint32_t reserved_22_23 : 2; 2998 uint32_t lbnc : 1; /**< Link Bandwith Notification Capability */ 2999 uint32_t dllarc : 1; /**< Data Link Layer Active Reporting Capable */ 3000 uint32_t sderc : 1; /**< Surprise Down Error Reporting Capable 3001 Not supported, hardwired to 0x0. */ 3002 uint32_t cpm : 1; /**< Clock Power Management 3003 The default value is the value you specify during hardware 3004 configuration, writable through PESC(0..1)_CFG_WR. 3005 However, the application must not change this field. */ 3006 uint32_t l1el : 3; /**< L1 Exit Latency 3007 The default value is the value you specify during hardware 3008 configuration, writable through PESC(0..1)_CFG_WR. 3009 However, the application must not change this field. */ 3010 uint32_t l0el : 3; /**< L0s Exit Latency 3011 The default value is the value you specify during hardware 3012 configuration, writable through PESC(0..1)_CFG_WR. 3013 However, the application must not change this field. */ 3014 uint32_t aslpms : 2; /**< Active State Link PM Support 3015 The default value is the value you specify during hardware 3016 configuration, writable through PESC(0..1)_CFG_WR. 3017 However, the application must not change this field. */ 3018 uint32_t mlw : 6; /**< Maximum Link Width 3019 The default value is the value you specify during hardware 3020 configuration (x1, x2, x4, x8, or x16), writable through PESC(0..1)_CFG_WR. 3021 This value will be set to 0x4 or 0x2 depending on the max 3022 number of lanes (QLM_CFG == 0 set to 0x2 else 0x4). */ 3023 uint32_t mls : 4; /**< Maximum Link Speed 3024 Default value is 0x1 for 2.5 Gbps Link. 3025 This field is writable through PESC(0..1)_CFG_WR. 3026 However, 0x1 is the 3027 only supported value. Therefore, the application must not write 3028 any value other than 0x1 to this field. */ 3029#else 3030 uint32_t mls : 4; 3031 uint32_t mlw : 6; 3032 uint32_t aslpms : 2; 3033 uint32_t l0el : 3; 3034 uint32_t l1el : 3; 3035 uint32_t cpm : 1; 3036 uint32_t sderc : 1; 3037 uint32_t dllarc : 1; 3038 uint32_t lbnc : 1; 3039 uint32_t reserved_22_23 : 2; 3040 uint32_t pnum : 8; 3041#endif 3042 } cn52xx; 3043 struct cvmx_pcieepx_cfg031_cn52xx cn52xxp1; 3044 struct cvmx_pcieepx_cfg031_cn52xx cn56xx; 3045 struct cvmx_pcieepx_cfg031_cn52xx cn56xxp1; 3046 struct cvmx_pcieepx_cfg031_s cn61xx; 3047 struct cvmx_pcieepx_cfg031_cn52xx cn63xx; 3048 struct cvmx_pcieepx_cfg031_cn52xx cn63xxp1; 3049 struct cvmx_pcieepx_cfg031_s cn66xx; 3050 struct cvmx_pcieepx_cfg031_s cn68xx; 3051 struct cvmx_pcieepx_cfg031_cn52xx cn68xxp1; 3052 struct cvmx_pcieepx_cfg031_s cnf71xx; 3053}; 3054typedef union cvmx_pcieepx_cfg031 cvmx_pcieepx_cfg031_t; 3055 3056/** 3057 * cvmx_pcieep#_cfg032 3058 * 3059 * PCIE_CFG032 = Thirty-third 32-bits of PCIE type 0 config space 3060 * (Link Control Register/Link Status Register) 3061 */ 3062union cvmx_pcieepx_cfg032 { 3063 uint32_t u32; 3064 struct cvmx_pcieepx_cfg032_s { 3065#ifdef __BIG_ENDIAN_BITFIELD 3066 uint32_t lab : 1; /**< Link Autonomous Bandwidth Status */ 3067 uint32_t lbm : 1; /**< Link Bandwidth Management Status */ 3068 uint32_t dlla : 1; /**< Data Link Layer Active 3069 Not applicable for an upstream Port or Endpoint device, 3070 hardwired to 0. */ 3071 uint32_t scc : 1; /**< Slot Clock Configuration 3072 Indicates that the component uses the same physical reference 3073 clock that the platform provides on the connector. 3074 Writable through PEM(0..1)_CFG_WR. 3075 However, the application must not change this field. */ 3076 uint32_t lt : 1; /**< Link Training 3077 Not applicable for an upstream Port or Endpoint device, 3078 hardwired to 0. */ 3079 uint32_t reserved_26_26 : 1; 3080 uint32_t nlw : 6; /**< Negotiated Link Width 3081 Set automatically by hardware after Link initialization. 3082 Value is undefined when link is not up. */ 3083 uint32_t ls : 4; /**< Link Speed 3084 1 == The negotiated Link speed: 2.5 Gbps 3085 2 == The negotiated Link speed: 5.0 Gbps 3086 4 == The negotiated Link speed: 8.0 Gbps (Not Supported) */ 3087 uint32_t reserved_12_15 : 4; 3088 uint32_t lab_int_enb : 1; /**< Link Autonomous Bandwidth Interrupt Enable 3089 This bit is not applicable and is reserved for endpoints */ 3090 uint32_t lbm_int_enb : 1; /**< Link Bandwidth Management Interrupt Enable 3091 This bit is not applicable and is reserved for endpoints */ 3092 uint32_t hawd : 1; /**< Hardware Autonomous Width Disable 3093 (Not Supported) */ 3094 uint32_t ecpm : 1; /**< Enable Clock Power Management 3095 Hardwired to 0 if Clock Power Management is disabled in 3096 the Link Capabilities register. */ 3097 uint32_t es : 1; /**< Extended Synch */ 3098 uint32_t ccc : 1; /**< Common Clock Configuration */ 3099 uint32_t rl : 1; /**< Retrain Link 3100 Not applicable for an upstream Port or Endpoint device, 3101 hardwired to 0. */ 3102 uint32_t ld : 1; /**< Link Disable 3103 Not applicable for an upstream Port or Endpoint device, 3104 hardwired to 0. */ 3105 uint32_t rcb : 1; /**< Read Completion Boundary (RCB) */ 3106 uint32_t reserved_2_2 : 1; 3107 uint32_t aslpc : 2; /**< Active State Link PM Control */ 3108#else 3109 uint32_t aslpc : 2; 3110 uint32_t reserved_2_2 : 1; 3111 uint32_t rcb : 1; 3112 uint32_t ld : 1; 3113 uint32_t rl : 1; 3114 uint32_t ccc : 1; 3115 uint32_t es : 1; 3116 uint32_t ecpm : 1; 3117 uint32_t hawd : 1; 3118 uint32_t lbm_int_enb : 1; 3119 uint32_t lab_int_enb : 1; 3120 uint32_t reserved_12_15 : 4; 3121 uint32_t ls : 4; 3122 uint32_t nlw : 6; 3123 uint32_t reserved_26_26 : 1; 3124 uint32_t lt : 1; 3125 uint32_t scc : 1; 3126 uint32_t dlla : 1; 3127 uint32_t lbm : 1; 3128 uint32_t lab : 1; 3129#endif 3130 } s; 3131 struct cvmx_pcieepx_cfg032_cn52xx { 3132#ifdef __BIG_ENDIAN_BITFIELD 3133 uint32_t reserved_30_31 : 2; 3134 uint32_t dlla : 1; /**< Data Link Layer Active 3135 Not applicable for an upstream Port or Endpoint device, 3136 hardwired to 0. */ 3137 uint32_t scc : 1; /**< Slot Clock Configuration 3138 Indicates that the component uses the same physical reference 3139 clock that the platform provides on the connector. 3140 Writable through PESC(0..1)_CFG_WR. 3141 However, the application must not change this field. */ 3142 uint32_t lt : 1; /**< Link Training 3143 Not applicable for an upstream Port or Endpoint device, 3144 hardwired to 0. */ 3145 uint32_t reserved_26_26 : 1; 3146 uint32_t nlw : 6; /**< Negotiated Link Width 3147 Set automatically by hardware after Link initialization. */ 3148 uint32_t ls : 4; /**< Link Speed 3149 The negotiated Link speed: 2.5 Gbps */ 3150 uint32_t reserved_10_15 : 6; 3151 uint32_t hawd : 1; /**< Hardware Autonomous Width Disable 3152 (Not Supported) */ 3153 uint32_t ecpm : 1; /**< Enable Clock Power Management 3154 Hardwired to 0 if Clock Power Management is disabled in 3155 the Link Capabilities register. */ 3156 uint32_t es : 1; /**< Extended Synch */ 3157 uint32_t ccc : 1; /**< Common Clock Configuration */ 3158 uint32_t rl : 1; /**< Retrain Link 3159 Not applicable for an upstream Port or Endpoint device, 3160 hardwired to 0. */ 3161 uint32_t ld : 1; /**< Link Disable 3162 Not applicable for an upstream Port or Endpoint device, 3163 hardwired to 0. */ 3164 uint32_t rcb : 1; /**< Read Completion Boundary (RCB) */ 3165 uint32_t reserved_2_2 : 1; 3166 uint32_t aslpc : 2; /**< Active State Link PM Control */ 3167#else 3168 uint32_t aslpc : 2; 3169 uint32_t reserved_2_2 : 1; 3170 uint32_t rcb : 1; 3171 uint32_t ld : 1; 3172 uint32_t rl : 1; 3173 uint32_t ccc : 1; 3174 uint32_t es : 1; 3175 uint32_t ecpm : 1; 3176 uint32_t hawd : 1; 3177 uint32_t reserved_10_15 : 6; 3178 uint32_t ls : 4; 3179 uint32_t nlw : 6; 3180 uint32_t reserved_26_26 : 1; 3181 uint32_t lt : 1; 3182 uint32_t scc : 1; 3183 uint32_t dlla : 1; 3184 uint32_t reserved_30_31 : 2; 3185#endif 3186 } cn52xx; 3187 struct cvmx_pcieepx_cfg032_cn52xx cn52xxp1; 3188 struct cvmx_pcieepx_cfg032_cn52xx cn56xx; 3189 struct cvmx_pcieepx_cfg032_cn52xx cn56xxp1; 3190 struct cvmx_pcieepx_cfg032_s cn61xx; 3191 struct cvmx_pcieepx_cfg032_cn52xx cn63xx; 3192 struct cvmx_pcieepx_cfg032_cn52xx cn63xxp1; 3193 struct cvmx_pcieepx_cfg032_s cn66xx; 3194 struct cvmx_pcieepx_cfg032_s cn68xx; 3195 struct cvmx_pcieepx_cfg032_cn68xxp1 { 3196#ifdef __BIG_ENDIAN_BITFIELD 3197 uint32_t reserved_30_31 : 2; 3198 uint32_t dlla : 1; /**< Data Link Layer Active 3199 Not applicable for an upstream Port or Endpoint device, 3200 hardwired to 0. */ 3201 uint32_t scc : 1; /**< Slot Clock Configuration 3202 Indicates that the component uses the same physical reference 3203 clock that the platform provides on the connector. 3204 Writable through PEM(0..1)_CFG_WR. 3205 However, the application must not change this field. */ 3206 uint32_t lt : 1; /**< Link Training 3207 Not applicable for an upstream Port or Endpoint device, 3208 hardwired to 0. */ 3209 uint32_t reserved_26_26 : 1; 3210 uint32_t nlw : 6; /**< Negotiated Link Width 3211 Set automatically by hardware after Link initialization. */ 3212 uint32_t ls : 4; /**< Link Speed 3213 1 == The negotiated Link speed: 2.5 Gbps 3214 2 == The negotiated Link speed: 5.0 Gbps 3215 4 == The negotiated Link speed: 8.0 Gbps (Not Supported) */ 3216 uint32_t reserved_12_15 : 4; 3217 uint32_t lab_int_enb : 1; /**< Link Autonomous Bandwidth Interrupt Enable 3218 This bit is not applicable and is reserved for endpoints */ 3219 uint32_t lbm_int_enb : 1; /**< Link Bandwidth Management Interrupt Enable 3220 This bit is not applicable and is reserved for endpoints */ 3221 uint32_t hawd : 1; /**< Hardware Autonomous Width Disable 3222 (Not Supported) */ 3223 uint32_t ecpm : 1; /**< Enable Clock Power Management 3224 Hardwired to 0 if Clock Power Management is disabled in 3225 the Link Capabilities register. */ 3226 uint32_t es : 1; /**< Extended Synch */ 3227 uint32_t ccc : 1; /**< Common Clock Configuration */ 3228 uint32_t rl : 1; /**< Retrain Link 3229 Not applicable for an upstream Port or Endpoint device, 3230 hardwired to 0. */ 3231 uint32_t ld : 1; /**< Link Disable 3232 Not applicable for an upstream Port or Endpoint device, 3233 hardwired to 0. */ 3234 uint32_t rcb : 1; /**< Read Completion Boundary (RCB) */ 3235 uint32_t reserved_2_2 : 1; 3236 uint32_t aslpc : 2; /**< Active State Link PM Control */ 3237#else 3238 uint32_t aslpc : 2; 3239 uint32_t reserved_2_2 : 1; 3240 uint32_t rcb : 1; 3241 uint32_t ld : 1; 3242 uint32_t rl : 1; 3243 uint32_t ccc : 1; 3244 uint32_t es : 1; 3245 uint32_t ecpm : 1; 3246 uint32_t hawd : 1; 3247 uint32_t lbm_int_enb : 1; 3248 uint32_t lab_int_enb : 1; 3249 uint32_t reserved_12_15 : 4; 3250 uint32_t ls : 4; 3251 uint32_t nlw : 6; 3252 uint32_t reserved_26_26 : 1; 3253 uint32_t lt : 1; 3254 uint32_t scc : 1; 3255 uint32_t dlla : 1; 3256 uint32_t reserved_30_31 : 2; 3257#endif 3258 } cn68xxp1; 3259 struct cvmx_pcieepx_cfg032_s cnf71xx; 3260}; 3261typedef union cvmx_pcieepx_cfg032 cvmx_pcieepx_cfg032_t; 3262 3263/** 3264 * cvmx_pcieep#_cfg033 3265 * 3266 * PCIE_CFG033 = Thirty-fourth 32-bits of PCIE type 0 config space 3267 * (Slot Capabilities Register) 3268 */ 3269union cvmx_pcieepx_cfg033 { 3270 uint32_t u32; 3271 struct cvmx_pcieepx_cfg033_s { 3272#ifdef __BIG_ENDIAN_BITFIELD 3273 uint32_t ps_num : 13; /**< Physical Slot Number, writable through PEM(0..1)_CFG_WR 3274 However, the application must not change this field. */ 3275 uint32_t nccs : 1; /**< No Command Complete Support, writable through PEM(0..1)_CFG_WR 3276 However, the application must not change this field. */ 3277 uint32_t emip : 1; /**< Electromechanical Interlock Present, writable through PEM(0..1)_CFG_WR 3278 However, the application must not change this field. */ 3279 uint32_t sp_ls : 2; /**< Slot Power Limit Scale, writable through PEM(0..1)_CFG_WR 3280 However, the application must not change this field. */ 3281 uint32_t sp_lv : 8; /**< Slot Power Limit Value, writable through PEM(0..1)_CFG_WR 3282 However, the application must not change this field. */ 3283 uint32_t hp_c : 1; /**< Hot-Plug Capable, writable through PEM(0..1)_CFG_WR 3284 However, the application must not change this field. */ 3285 uint32_t hp_s : 1; /**< Hot-Plug Surprise, writable through PEM(0..1)_CFG_WR 3286 However, the application must not change this field. */ 3287 uint32_t pip : 1; /**< Power Indicator Present, writable through PEM(0..1)_CFG_WR 3288 However, the application must not change this field. */ 3289 uint32_t aip : 1; /**< Attention Indicator Present, writable through PEM(0..1)_CFG_WR 3290 However, the application must not change this field. */ 3291 uint32_t mrlsp : 1; /**< MRL Sensor Present, writable through PEM(0..1)_CFG_WR 3292 However, the application must not change this field. */ 3293 uint32_t pcp : 1; /**< Power Controller Present, writable through PEM(0..1)_CFG_WR 3294 However, the application must not change this field. */ 3295 uint32_t abp : 1; /**< Attention Button Present, writable through PEM(0..1)_CFG_WR 3296 However, the application must not change this field. */ 3297#else 3298 uint32_t abp : 1; 3299 uint32_t pcp : 1; 3300 uint32_t mrlsp : 1; 3301 uint32_t aip : 1; 3302 uint32_t pip : 1; 3303 uint32_t hp_s : 1; 3304 uint32_t hp_c : 1; 3305 uint32_t sp_lv : 8; 3306 uint32_t sp_ls : 2; 3307 uint32_t emip : 1; 3308 uint32_t nccs : 1; 3309 uint32_t ps_num : 13; 3310#endif 3311 } s; 3312 struct cvmx_pcieepx_cfg033_s cn52xx; 3313 struct cvmx_pcieepx_cfg033_s cn52xxp1; 3314 struct cvmx_pcieepx_cfg033_s cn56xx; 3315 struct cvmx_pcieepx_cfg033_s cn56xxp1; 3316 struct cvmx_pcieepx_cfg033_s cn63xx; 3317 struct cvmx_pcieepx_cfg033_s cn63xxp1; 3318}; 3319typedef union cvmx_pcieepx_cfg033 cvmx_pcieepx_cfg033_t; 3320 3321/** 3322 * cvmx_pcieep#_cfg034 3323 * 3324 * PCIE_CFG034 = Thirty-fifth 32-bits of PCIE type 0 config space 3325 * (Slot Control Register/Slot Status Register) 3326 */ 3327union cvmx_pcieepx_cfg034 { 3328 uint32_t u32; 3329 struct cvmx_pcieepx_cfg034_s { 3330#ifdef __BIG_ENDIAN_BITFIELD 3331 uint32_t reserved_25_31 : 7; 3332 uint32_t dlls_c : 1; /**< Data Link Layer State Changed 3333 Not applicable for an upstream Port or Endpoint device, 3334 hardwired to 0. */ 3335 uint32_t emis : 1; /**< Electromechanical Interlock Status */ 3336 uint32_t pds : 1; /**< Presence Detect State */ 3337 uint32_t mrlss : 1; /**< MRL Sensor State */ 3338 uint32_t ccint_d : 1; /**< Command Completed */ 3339 uint32_t pd_c : 1; /**< Presence Detect Changed */ 3340 uint32_t mrls_c : 1; /**< MRL Sensor Changed */ 3341 uint32_t pf_d : 1; /**< Power Fault Detected */ 3342 uint32_t abp_d : 1; /**< Attention Button Pressed */ 3343 uint32_t reserved_13_15 : 3; 3344 uint32_t dlls_en : 1; /**< Data Link Layer State Changed Enable 3345 Not applicable for an upstream Port or Endpoint device, 3346 hardwired to 0. */ 3347 uint32_t emic : 1; /**< Electromechanical Interlock Control */ 3348 uint32_t pcc : 1; /**< Power Controller Control */ 3349 uint32_t pic : 2; /**< Power Indicator Control */ 3350 uint32_t aic : 2; /**< Attention Indicator Control */ 3351 uint32_t hpint_en : 1; /**< Hot-Plug Interrupt Enable */ 3352 uint32_t ccint_en : 1; /**< Command Completed Interrupt Enable */ 3353 uint32_t pd_en : 1; /**< Presence Detect Changed Enable */ 3354 uint32_t mrls_en : 1; /**< MRL Sensor Changed Enable */ 3355 uint32_t pf_en : 1; /**< Power Fault Detected Enable */ 3356 uint32_t abp_en : 1; /**< Attention Button Pressed Enable */ 3357#else 3358 uint32_t abp_en : 1; 3359 uint32_t pf_en : 1; 3360 uint32_t mrls_en : 1; 3361 uint32_t pd_en : 1; 3362 uint32_t ccint_en : 1; 3363 uint32_t hpint_en : 1; 3364 uint32_t aic : 2; 3365 uint32_t pic : 2; 3366 uint32_t pcc : 1; 3367 uint32_t emic : 1; 3368 uint32_t dlls_en : 1; 3369 uint32_t reserved_13_15 : 3; 3370 uint32_t abp_d : 1; 3371 uint32_t pf_d : 1; 3372 uint32_t mrls_c : 1; 3373 uint32_t pd_c : 1; 3374 uint32_t ccint_d : 1; 3375 uint32_t mrlss : 1; 3376 uint32_t pds : 1; 3377 uint32_t emis : 1; 3378 uint32_t dlls_c : 1; 3379 uint32_t reserved_25_31 : 7; 3380#endif 3381 } s; 3382 struct cvmx_pcieepx_cfg034_s cn52xx; 3383 struct cvmx_pcieepx_cfg034_s cn52xxp1; 3384 struct cvmx_pcieepx_cfg034_s cn56xx; 3385 struct cvmx_pcieepx_cfg034_s cn56xxp1; 3386 struct cvmx_pcieepx_cfg034_s cn63xx; 3387 struct cvmx_pcieepx_cfg034_s cn63xxp1; 3388}; 3389typedef union cvmx_pcieepx_cfg034 cvmx_pcieepx_cfg034_t; 3390 3391/** 3392 * cvmx_pcieep#_cfg037 3393 * 3394 * PCIE_CFG037 = Thirty-eighth 32-bits of PCIE type 0 config space 3395 * (Device Capabilities 2 Register) 3396 */ 3397union cvmx_pcieepx_cfg037 { 3398 uint32_t u32; 3399 struct cvmx_pcieepx_cfg037_s { 3400#ifdef __BIG_ENDIAN_BITFIELD 3401 uint32_t reserved_20_31 : 12; 3402 uint32_t obffs : 2; /**< Optimized Buffer Flush Fill (OBFF) Supported 3403 (Not Supported) */ 3404 uint32_t reserved_12_17 : 6; 3405 uint32_t ltrs : 1; /**< Latency Tolerance Reporting (LTR) Mechanism Supported 3406 (Not Supported) */ 3407 uint32_t noroprpr : 1; /**< No RO-enabled PR-PR Passing 3408 (This bit applies to RCs) */ 3409 uint32_t atom128s : 1; /**< 128-bit AtomicOp Supported 3410 (Not Supported) */ 3411 uint32_t atom64s : 1; /**< 64-bit AtomicOp Supported 3412 (Not Supported) */ 3413 uint32_t atom32s : 1; /**< 32-bit AtomicOp Supported 3414 (Not Supported) */ 3415 uint32_t atom_ops : 1; /**< AtomicOp Routing Supported 3416 (Not Applicable for EP) */ 3417 uint32_t ari : 1; /**< Alternate Routing ID Forwarding Supported 3418 (Not Supported) */ 3419 uint32_t ctds : 1; /**< Completion Timeout Disable Supported */ 3420 uint32_t ctrs : 4; /**< Completion Timeout Ranges Supported */ 3421#else 3422 uint32_t ctrs : 4; 3423 uint32_t ctds : 1; 3424 uint32_t ari : 1; 3425 uint32_t atom_ops : 1; 3426 uint32_t atom32s : 1; 3427 uint32_t atom64s : 1; 3428 uint32_t atom128s : 1; 3429 uint32_t noroprpr : 1; 3430 uint32_t ltrs : 1; 3431 uint32_t reserved_12_17 : 6; 3432 uint32_t obffs : 2; 3433 uint32_t reserved_20_31 : 12; 3434#endif 3435 } s; 3436 struct cvmx_pcieepx_cfg037_cn52xx { 3437#ifdef __BIG_ENDIAN_BITFIELD 3438 uint32_t reserved_5_31 : 27; 3439 uint32_t ctds : 1; /**< Completion Timeout Disable Supported */ 3440 uint32_t ctrs : 4; /**< Completion Timeout Ranges Supported 3441 Value of 0 indicates that Completion Timeout Programming 3442 is not supported 3443 Completion timeout is 16.7ms. */ 3444#else 3445 uint32_t ctrs : 4; 3446 uint32_t ctds : 1; 3447 uint32_t reserved_5_31 : 27; 3448#endif 3449 } cn52xx; 3450 struct cvmx_pcieepx_cfg037_cn52xx cn52xxp1; 3451 struct cvmx_pcieepx_cfg037_cn52xx cn56xx; 3452 struct cvmx_pcieepx_cfg037_cn52xx cn56xxp1; 3453 struct cvmx_pcieepx_cfg037_cn61xx { 3454#ifdef __BIG_ENDIAN_BITFIELD 3455 uint32_t reserved_14_31 : 18; 3456 uint32_t tph : 2; /**< TPH Completer Supported 3457 (Not Supported) */ 3458 uint32_t reserved_11_11 : 1; 3459 uint32_t noroprpr : 1; /**< No RO-enabled PR-PR Passing 3460 (This bit applies to RCs) */ 3461 uint32_t atom128s : 1; /**< 128-bit AtomicOp Supported 3462 (Not Supported) */ 3463 uint32_t atom64s : 1; /**< 64-bit AtomicOp Supported 3464 (Not Supported) */ 3465 uint32_t atom32s : 1; /**< 32-bit AtomicOp Supported 3466 (Not Supported) */ 3467 uint32_t atom_ops : 1; /**< AtomicOp Routing Supported 3468 (Not Applicable for EP) */ 3469 uint32_t ari : 1; /**< Alternate Routing ID Forwarding Supported 3470 (Not Supported) */ 3471 uint32_t ctds : 1; /**< Completion Timeout Disable Supported */ 3472 uint32_t ctrs : 4; /**< Completion Timeout Ranges Supported */ 3473#else 3474 uint32_t ctrs : 4; 3475 uint32_t ctds : 1; 3476 uint32_t ari : 1; 3477 uint32_t atom_ops : 1; 3478 uint32_t atom32s : 1; 3479 uint32_t atom64s : 1; 3480 uint32_t atom128s : 1; 3481 uint32_t noroprpr : 1; 3482 uint32_t reserved_11_11 : 1; 3483 uint32_t tph : 2; 3484 uint32_t reserved_14_31 : 18; 3485#endif 3486 } cn61xx; 3487 struct cvmx_pcieepx_cfg037_cn52xx cn63xx; 3488 struct cvmx_pcieepx_cfg037_cn52xx cn63xxp1; 3489 struct cvmx_pcieepx_cfg037_cn61xx cn66xx; 3490 struct cvmx_pcieepx_cfg037_cn61xx cn68xx; 3491 struct cvmx_pcieepx_cfg037_cn61xx cn68xxp1; 3492 struct cvmx_pcieepx_cfg037_cnf71xx { 3493#ifdef __BIG_ENDIAN_BITFIELD 3494 uint32_t reserved_20_31 : 12; 3495 uint32_t obffs : 2; /**< Optimized Buffer Flush Fill (OBFF) Supported 3496 (Not Supported) */ 3497 uint32_t reserved_14_17 : 4; 3498 uint32_t tphs : 2; /**< TPH Completer Supported 3499 (Not Supported) */ 3500 uint32_t ltrs : 1; /**< Latency Tolerance Reporting (LTR) Mechanism Supported 3501 (Not Supported) */ 3502 uint32_t noroprpr : 1; /**< No RO-enabled PR-PR Passing 3503 (This bit applies to RCs) */ 3504 uint32_t atom128s : 1; /**< 128-bit AtomicOp Supported 3505 (Not Supported) */ 3506 uint32_t atom64s : 1; /**< 64-bit AtomicOp Supported 3507 (Not Supported) */ 3508 uint32_t atom32s : 1; /**< 32-bit AtomicOp Supported 3509 (Not Supported) */ 3510 uint32_t atom_ops : 1; /**< AtomicOp Routing Supported 3511 (Not Applicable for EP) */ 3512 uint32_t ari : 1; /**< Alternate Routing ID Forwarding Supported 3513 (Not Supported) */ 3514 uint32_t ctds : 1; /**< Completion Timeout Disable Supported */ 3515 uint32_t ctrs : 4; /**< Completion Timeout Ranges Supported */ 3516#else 3517 uint32_t ctrs : 4; 3518 uint32_t ctds : 1; 3519 uint32_t ari : 1; 3520 uint32_t atom_ops : 1; 3521 uint32_t atom32s : 1; 3522 uint32_t atom64s : 1; 3523 uint32_t atom128s : 1; 3524 uint32_t noroprpr : 1; 3525 uint32_t ltrs : 1; 3526 uint32_t tphs : 2; 3527 uint32_t reserved_14_17 : 4; 3528 uint32_t obffs : 2; 3529 uint32_t reserved_20_31 : 12; 3530#endif 3531 } cnf71xx; 3532}; 3533typedef union cvmx_pcieepx_cfg037 cvmx_pcieepx_cfg037_t; 3534 3535/** 3536 * cvmx_pcieep#_cfg038 3537 * 3538 * PCIE_CFG038 = Thirty-ninth 32-bits of PCIE type 0 config space 3539 * (Device Control 2 Register/Device Status 2 Register) 3540 */ 3541union cvmx_pcieepx_cfg038 { 3542 uint32_t u32; 3543 struct cvmx_pcieepx_cfg038_s { 3544#ifdef __BIG_ENDIAN_BITFIELD 3545 uint32_t reserved_15_31 : 17; 3546 uint32_t obffe : 2; /**< Optimized Buffer Flush Fill (OBFF) Enable 3547 (Not Supported) */ 3548 uint32_t reserved_11_12 : 2; 3549 uint32_t ltre : 1; /**< Latency Tolerance Reporting (LTR) Mechanism Enable 3550 (Not Supported) */ 3551 uint32_t id0_cp : 1; /**< ID Based Ordering Completion Enable 3552 (Not Supported) */ 3553 uint32_t id0_rq : 1; /**< ID Based Ordering Request Enable 3554 (Not Supported) */ 3555 uint32_t atom_op_eb : 1; /**< AtomicOp Egress Blocking 3556 (Not Supported)m */ 3557 uint32_t atom_op : 1; /**< AtomicOp Requester Enable 3558 (Not Supported) */ 3559 uint32_t ari : 1; /**< Alternate Routing ID Forwarding Supported 3560 (Not Supported) */ 3561 uint32_t ctd : 1; /**< Completion Timeout Disable */ 3562 uint32_t ctv : 4; /**< Completion Timeout Value 3563 Completion Timeout Programming is not supported 3564 Completion timeout is the range of 16 ms to 55 ms. */ 3565#else 3566 uint32_t ctv : 4; 3567 uint32_t ctd : 1; 3568 uint32_t ari : 1; 3569 uint32_t atom_op : 1; 3570 uint32_t atom_op_eb : 1; 3571 uint32_t id0_rq : 1; 3572 uint32_t id0_cp : 1; 3573 uint32_t ltre : 1; 3574 uint32_t reserved_11_12 : 2; 3575 uint32_t obffe : 2; 3576 uint32_t reserved_15_31 : 17; 3577#endif 3578 } s; 3579 struct cvmx_pcieepx_cfg038_cn52xx { 3580#ifdef __BIG_ENDIAN_BITFIELD 3581 uint32_t reserved_5_31 : 27; 3582 uint32_t ctd : 1; /**< Completion Timeout Disable */ 3583 uint32_t ctv : 4; /**< Completion Timeout Value 3584 Completion Timeout Programming is not supported 3585 Completion timeout is 16.7ms. */ 3586#else 3587 uint32_t ctv : 4; 3588 uint32_t ctd : 1; 3589 uint32_t reserved_5_31 : 27; 3590#endif 3591 } cn52xx; 3592 struct cvmx_pcieepx_cfg038_cn52xx cn52xxp1; 3593 struct cvmx_pcieepx_cfg038_cn52xx cn56xx; 3594 struct cvmx_pcieepx_cfg038_cn52xx cn56xxp1; 3595 struct cvmx_pcieepx_cfg038_cn61xx { 3596#ifdef __BIG_ENDIAN_BITFIELD 3597 uint32_t reserved_10_31 : 22; 3598 uint32_t id0_cp : 1; /**< ID Based Ordering Completion Enable 3599 (Not Supported) */ 3600 uint32_t id0_rq : 1; /**< ID Based Ordering Request Enable 3601 (Not Supported) */ 3602 uint32_t atom_op_eb : 1; /**< AtomicOp Egress Blocking 3603 (Not Supported)m */ 3604 uint32_t atom_op : 1; /**< AtomicOp Requester Enable 3605 (Not Supported) */ 3606 uint32_t ari : 1; /**< Alternate Routing ID Forwarding Supported 3607 (Not Supported) */ 3608 uint32_t ctd : 1; /**< Completion Timeout Disable */ 3609 uint32_t ctv : 4; /**< Completion Timeout Value 3610 Completion Timeout Programming is not supported 3611 Completion timeout is the range of 16 ms to 55 ms. */ 3612#else 3613 uint32_t ctv : 4; 3614 uint32_t ctd : 1; 3615 uint32_t ari : 1; 3616 uint32_t atom_op : 1; 3617 uint32_t atom_op_eb : 1; 3618 uint32_t id0_rq : 1; 3619 uint32_t id0_cp : 1; 3620 uint32_t reserved_10_31 : 22; 3621#endif 3622 } cn61xx; 3623 struct cvmx_pcieepx_cfg038_cn52xx cn63xx; 3624 struct cvmx_pcieepx_cfg038_cn52xx cn63xxp1; 3625 struct cvmx_pcieepx_cfg038_cn61xx cn66xx; 3626 struct cvmx_pcieepx_cfg038_cn61xx cn68xx; 3627 struct cvmx_pcieepx_cfg038_cn61xx cn68xxp1; 3628 struct cvmx_pcieepx_cfg038_s cnf71xx; 3629}; 3630typedef union cvmx_pcieepx_cfg038 cvmx_pcieepx_cfg038_t; 3631 3632/** 3633 * cvmx_pcieep#_cfg039 3634 * 3635 * PCIE_CFG039 = Fourtieth 32-bits of PCIE type 0 config space 3636 * (Link Capabilities 2 Register) 3637 */ 3638union cvmx_pcieepx_cfg039 { 3639 uint32_t u32; 3640 struct cvmx_pcieepx_cfg039_s { 3641#ifdef __BIG_ENDIAN_BITFIELD 3642 uint32_t reserved_9_31 : 23; 3643 uint32_t cls : 1; /**< Crosslink Supported */ 3644 uint32_t slsv : 7; /**< Supported Link Speeds Vector 3645 Indicates the supported Link speeds of the associated Port. 3646 For each bit, a value of 1b indicates that the cooresponding 3647 Link speed is supported; otherwise, the Link speed is not 3648 supported. 3649 Bit definitions are: 3650 Bit 1 2.5 GT/s 3651 Bit 2 5.0 GT/s 3652 Bit 3 8.0 GT/s (Not Supported) 3653 Bits 7:4 reserved 3654 The reset value of this field is controlled by a value sent from 3655 the lsb of the MIO_QLM#_SPD register 3656 qlm#_spd[0] RST_VALUE NOTE 3657 1 0001b 2.5 GHz supported 3658 0 0011b 5.0 GHz and 2.5 GHz supported */ 3659 uint32_t reserved_0_0 : 1; 3660#else 3661 uint32_t reserved_0_0 : 1; 3662 uint32_t slsv : 7; 3663 uint32_t cls : 1; 3664 uint32_t reserved_9_31 : 23; 3665#endif 3666 } s; 3667 struct cvmx_pcieepx_cfg039_cn52xx { 3668#ifdef __BIG_ENDIAN_BITFIELD 3669 uint32_t reserved_0_31 : 32; 3670#else 3671 uint32_t reserved_0_31 : 32; 3672#endif 3673 } cn52xx; 3674 struct cvmx_pcieepx_cfg039_cn52xx cn52xxp1; 3675 struct cvmx_pcieepx_cfg039_cn52xx cn56xx; 3676 struct cvmx_pcieepx_cfg039_cn52xx cn56xxp1; 3677 struct cvmx_pcieepx_cfg039_s cn61xx; 3678 struct cvmx_pcieepx_cfg039_s cn63xx; 3679 struct cvmx_pcieepx_cfg039_cn52xx cn63xxp1; 3680 struct cvmx_pcieepx_cfg039_s cn66xx; 3681 struct cvmx_pcieepx_cfg039_s cn68xx; 3682 struct cvmx_pcieepx_cfg039_s cn68xxp1; 3683 struct cvmx_pcieepx_cfg039_s cnf71xx; 3684}; 3685typedef union cvmx_pcieepx_cfg039 cvmx_pcieepx_cfg039_t; 3686 3687/** 3688 * cvmx_pcieep#_cfg040 3689 * 3690 * PCIE_CFG040 = Fourty-first 32-bits of PCIE type 0 config space 3691 * (Link Control 2 Register/Link Status 2 Register) 3692 */ 3693union cvmx_pcieepx_cfg040 { 3694 uint32_t u32; 3695 struct cvmx_pcieepx_cfg040_s { 3696#ifdef __BIG_ENDIAN_BITFIELD 3697 uint32_t reserved_17_31 : 15; 3698 uint32_t cdl : 1; /**< Current De-emphasis Level 3699 When the Link is operating at 5 GT/s speed, this bit 3700 reflects the level of de-emphasis. Encodings: 3701 1b: -3.5 dB 3702 0b: -6 dB 3703 Note: The value in this bit is undefined when the Link is 3704 operating at 2.5 GT/s speed */ 3705 uint32_t reserved_13_15 : 3; 3706 uint32_t cde : 1; /**< Compliance De-emphasis 3707 This bit sets the de-emphasis level in Polling. Compliance 3708 state if the entry occurred due to the Tx Compliance 3709 Receive bit being 1b. Encodings: 3710 1b: -3.5 dB 3711 0b: -6 dB 3712 Note: When the Link is operating at 2.5 GT/s, the setting 3713 of this bit has no effect. */ 3714 uint32_t csos : 1; /**< Compliance SOS 3715 When set to 1b, the LTSSM is required to send SKP 3716 Ordered Sets periodically in between the (modified) 3717 compliance patterns. 3718 Note: When the Link is operating at 2.5 GT/s, the setting 3719 of this bit has no effect. */ 3720 uint32_t emc : 1; /**< Enter Modified Compliance 3721 When this bit is set to 1b, the device transmits a modified 3722 compliance pattern if the LTSSM enters Polling. 3723 Compliance state. */ 3724 uint32_t tm : 3; /**< Transmit Margin 3725 This field controls the value of the non-de-emphasized 3726 voltage level at the Transmitter signals: 3727 - 000: 800-1200 mV for full swing 400-600 mV for half-swing 3728 - 001-010: values must be monotonic with a non-zero slope 3729 - 011: 200-400 mV for full-swing and 100-200 mV for halfswing 3730 - 100-111: reserved 3731 This field is reset to 000b on entry to the LTSSM Polling. 3732 Compliance substate. 3733 When operating in 5.0 GT/s mode with full swing, the 3734 de-emphasis ratio must be maintained within +/- 1 dB 3735 from the specification-defined operational value 3736 either -3.5 or -6 dB). */ 3737 uint32_t sde : 1; /**< Selectable De-emphasis 3738 Not applicable for an upstream Port or Endpoint device. 3739 Hardwired to 0. */ 3740 uint32_t hasd : 1; /**< Hardware Autonomous Speed Disable 3741 When asserted, the 3742 application must disable hardware from changing the Link 3743 speed for device-specific reasons other than attempting to 3744 correct unreliable Link operation by reducing Link speed. 3745 Initial transition to the highest supported common link 3746 speed is not blocked by this signal. */ 3747 uint32_t ec : 1; /**< Enter Compliance 3748 Software is permitted to force a link to enter Compliance 3749 mode at the speed indicated in the Target Link Speed 3750 field by setting this bit to 1b in both components on a link 3751 and then initiating a hot reset on the link. */ 3752 uint32_t tls : 4; /**< Target Link Speed 3753 For Downstream ports, this field sets an upper limit on link 3754 operational speed by restricting the values advertised by 3755 the upstream component in its training sequences: 3756 - 0001: 2.5Gb/s Target Link Speed 3757 - 0010: 5Gb/s Target Link Speed 3758 - 0100: 8Gb/s Target Link Speed (Not Supported) 3759 All other encodings are reserved. 3760 If a value is written to this field that does not correspond to 3761 a speed included in the Supported Link Speeds field, the 3762 result is undefined. 3763 For both Upstream and Downstream ports, this field is 3764 used to set the target compliance mode speed when 3765 software is using the Enter Compliance bit to force a link 3766 into compliance mode. 3767 The reset value of this field is controlled by a value sent from 3768 the lsb of the MIO_QLM#_SPD register. 3769 qlm#_spd[0] RST_VALUE NOTE 3770 1 0001b 2.5 GHz supported 3771 0 0010b 5.0 GHz and 2.5 GHz supported */ 3772#else 3773 uint32_t tls : 4; 3774 uint32_t ec : 1; 3775 uint32_t hasd : 1; 3776 uint32_t sde : 1; 3777 uint32_t tm : 3; 3778 uint32_t emc : 1; 3779 uint32_t csos : 1; 3780 uint32_t cde : 1; 3781 uint32_t reserved_13_15 : 3; 3782 uint32_t cdl : 1; 3783 uint32_t reserved_17_31 : 15; 3784#endif 3785 } s; 3786 struct cvmx_pcieepx_cfg040_cn52xx { 3787#ifdef __BIG_ENDIAN_BITFIELD 3788 uint32_t reserved_0_31 : 32; 3789#else 3790 uint32_t reserved_0_31 : 32; 3791#endif 3792 } cn52xx; 3793 struct cvmx_pcieepx_cfg040_cn52xx cn52xxp1; 3794 struct cvmx_pcieepx_cfg040_cn52xx cn56xx; 3795 struct cvmx_pcieepx_cfg040_cn52xx cn56xxp1; 3796 struct cvmx_pcieepx_cfg040_s cn61xx; 3797 struct cvmx_pcieepx_cfg040_s cn63xx; 3798 struct cvmx_pcieepx_cfg040_s cn63xxp1; 3799 struct cvmx_pcieepx_cfg040_s cn66xx; 3800 struct cvmx_pcieepx_cfg040_s cn68xx; 3801 struct cvmx_pcieepx_cfg040_s cn68xxp1; 3802 struct cvmx_pcieepx_cfg040_s cnf71xx; 3803}; 3804typedef union cvmx_pcieepx_cfg040 cvmx_pcieepx_cfg040_t; 3805 3806/** 3807 * cvmx_pcieep#_cfg041 3808 * 3809 * PCIE_CFG041 = Fourty-second 32-bits of PCIE type 0 config space 3810 * (Slot Capabilities 2 Register) 3811 */ 3812union cvmx_pcieepx_cfg041 { 3813 uint32_t u32; 3814 struct cvmx_pcieepx_cfg041_s { 3815#ifdef __BIG_ENDIAN_BITFIELD 3816 uint32_t reserved_0_31 : 32; 3817#else 3818 uint32_t reserved_0_31 : 32; 3819#endif 3820 } s; 3821 struct cvmx_pcieepx_cfg041_s cn52xx; 3822 struct cvmx_pcieepx_cfg041_s cn52xxp1; 3823 struct cvmx_pcieepx_cfg041_s cn56xx; 3824 struct cvmx_pcieepx_cfg041_s cn56xxp1; 3825 struct cvmx_pcieepx_cfg041_s cn63xx; 3826 struct cvmx_pcieepx_cfg041_s cn63xxp1; 3827}; 3828typedef union cvmx_pcieepx_cfg041 cvmx_pcieepx_cfg041_t; 3829 3830/** 3831 * cvmx_pcieep#_cfg042 3832 * 3833 * PCIE_CFG042 = Fourty-third 32-bits of PCIE type 0 config space 3834 * (Slot Control 2 Register/Slot Status 2 Register) 3835 */ 3836union cvmx_pcieepx_cfg042 { 3837 uint32_t u32; 3838 struct cvmx_pcieepx_cfg042_s { 3839#ifdef __BIG_ENDIAN_BITFIELD 3840 uint32_t reserved_0_31 : 32; 3841#else 3842 uint32_t reserved_0_31 : 32; 3843#endif 3844 } s; 3845 struct cvmx_pcieepx_cfg042_s cn52xx; 3846 struct cvmx_pcieepx_cfg042_s cn52xxp1; 3847 struct cvmx_pcieepx_cfg042_s cn56xx; 3848 struct cvmx_pcieepx_cfg042_s cn56xxp1; 3849 struct cvmx_pcieepx_cfg042_s cn63xx; 3850 struct cvmx_pcieepx_cfg042_s cn63xxp1; 3851}; 3852typedef union cvmx_pcieepx_cfg042 cvmx_pcieepx_cfg042_t; 3853 3854/** 3855 * cvmx_pcieep#_cfg064 3856 * 3857 * PCIE_CFG064 = Sixty-fifth 32-bits of PCIE type 0 config space 3858 * (PCI Express Extended Capability Header) 3859 */ 3860union cvmx_pcieepx_cfg064 { 3861 uint32_t u32; 3862 struct cvmx_pcieepx_cfg064_s { 3863#ifdef __BIG_ENDIAN_BITFIELD 3864 uint32_t nco : 12; /**< Next Capability Offset */ 3865 uint32_t cv : 4; /**< Capability Version */ 3866 uint32_t pcieec : 16; /**< PCIE Express Extended Capability */ 3867#else 3868 uint32_t pcieec : 16; 3869 uint32_t cv : 4; 3870 uint32_t nco : 12; 3871#endif 3872 } s; 3873 struct cvmx_pcieepx_cfg064_s cn52xx; 3874 struct cvmx_pcieepx_cfg064_s cn52xxp1; 3875 struct cvmx_pcieepx_cfg064_s cn56xx; 3876 struct cvmx_pcieepx_cfg064_s cn56xxp1; 3877 struct cvmx_pcieepx_cfg064_s cn61xx; 3878 struct cvmx_pcieepx_cfg064_s cn63xx; 3879 struct cvmx_pcieepx_cfg064_s cn63xxp1; 3880 struct cvmx_pcieepx_cfg064_s cn66xx; 3881 struct cvmx_pcieepx_cfg064_s cn68xx; 3882 struct cvmx_pcieepx_cfg064_s cn68xxp1; 3883 struct cvmx_pcieepx_cfg064_s cnf71xx; 3884}; 3885typedef union cvmx_pcieepx_cfg064 cvmx_pcieepx_cfg064_t; 3886 3887/** 3888 * cvmx_pcieep#_cfg065 3889 * 3890 * PCIE_CFG065 = Sixty-sixth 32-bits of PCIE type 0 config space 3891 * (Uncorrectable Error Status Register) 3892 */ 3893union cvmx_pcieepx_cfg065 { 3894 uint32_t u32; 3895 struct cvmx_pcieepx_cfg065_s { 3896#ifdef __BIG_ENDIAN_BITFIELD 3897 uint32_t reserved_25_31 : 7; 3898 uint32_t uatombs : 1; /**< Unsupported AtomicOp Egress Blocked Status */ 3899 uint32_t reserved_23_23 : 1; 3900 uint32_t ucies : 1; /**< Uncorrectable Internal Error Status */ 3901 uint32_t reserved_21_21 : 1; 3902 uint32_t ures : 1; /**< Unsupported Request Error Status */ 3903 uint32_t ecrces : 1; /**< ECRC Error Status */ 3904 uint32_t mtlps : 1; /**< Malformed TLP Status */ 3905 uint32_t ros : 1; /**< Receiver Overflow Status */ 3906 uint32_t ucs : 1; /**< Unexpected Completion Status */ 3907 uint32_t cas : 1; /**< Completer Abort Status */ 3908 uint32_t cts : 1; /**< Completion Timeout Status */ 3909 uint32_t fcpes : 1; /**< Flow Control Protocol Error Status */ 3910 uint32_t ptlps : 1; /**< Poisoned TLP Status */ 3911 uint32_t reserved_6_11 : 6; 3912 uint32_t sdes : 1; /**< Surprise Down Error Status (not supported) */ 3913 uint32_t dlpes : 1; /**< Data Link Protocol Error Status */ 3914 uint32_t reserved_0_3 : 4; 3915#else 3916 uint32_t reserved_0_3 : 4; 3917 uint32_t dlpes : 1; 3918 uint32_t sdes : 1; 3919 uint32_t reserved_6_11 : 6; 3920 uint32_t ptlps : 1; 3921 uint32_t fcpes : 1; 3922 uint32_t cts : 1; 3923 uint32_t cas : 1; 3924 uint32_t ucs : 1; 3925 uint32_t ros : 1; 3926 uint32_t mtlps : 1; 3927 uint32_t ecrces : 1; 3928 uint32_t ures : 1; 3929 uint32_t reserved_21_21 : 1; 3930 uint32_t ucies : 1; 3931 uint32_t reserved_23_23 : 1; 3932 uint32_t uatombs : 1; 3933 uint32_t reserved_25_31 : 7; 3934#endif 3935 } s; 3936 struct cvmx_pcieepx_cfg065_cn52xx { 3937#ifdef __BIG_ENDIAN_BITFIELD 3938 uint32_t reserved_21_31 : 11; 3939 uint32_t ures : 1; /**< Unsupported Request Error Status */ 3940 uint32_t ecrces : 1; /**< ECRC Error Status */ 3941 uint32_t mtlps : 1; /**< Malformed TLP Status */ 3942 uint32_t ros : 1; /**< Receiver Overflow Status */ 3943 uint32_t ucs : 1; /**< Unexpected Completion Status */ 3944 uint32_t cas : 1; /**< Completer Abort Status */ 3945 uint32_t cts : 1; /**< Completion Timeout Status */ 3946 uint32_t fcpes : 1; /**< Flow Control Protocol Error Status */ 3947 uint32_t ptlps : 1; /**< Poisoned TLP Status */ 3948 uint32_t reserved_6_11 : 6; 3949 uint32_t sdes : 1; /**< Surprise Down Error Status (not supported) */ 3950 uint32_t dlpes : 1; /**< Data Link Protocol Error Status */ 3951 uint32_t reserved_0_3 : 4; 3952#else 3953 uint32_t reserved_0_3 : 4; 3954 uint32_t dlpes : 1; 3955 uint32_t sdes : 1; 3956 uint32_t reserved_6_11 : 6; 3957 uint32_t ptlps : 1; 3958 uint32_t fcpes : 1; 3959 uint32_t cts : 1; 3960 uint32_t cas : 1; 3961 uint32_t ucs : 1; 3962 uint32_t ros : 1; 3963 uint32_t mtlps : 1; 3964 uint32_t ecrces : 1; 3965 uint32_t ures : 1; 3966 uint32_t reserved_21_31 : 11; 3967#endif 3968 } cn52xx; 3969 struct cvmx_pcieepx_cfg065_cn52xx cn52xxp1; 3970 struct cvmx_pcieepx_cfg065_cn52xx cn56xx; 3971 struct cvmx_pcieepx_cfg065_cn52xx cn56xxp1; 3972 struct cvmx_pcieepx_cfg065_cn61xx { 3973#ifdef __BIG_ENDIAN_BITFIELD 3974 uint32_t reserved_25_31 : 7; 3975 uint32_t uatombs : 1; /**< Unsupported AtomicOp Egress Blocked Status */ 3976 uint32_t reserved_21_23 : 3; 3977 uint32_t ures : 1; /**< Unsupported Request Error Status */ 3978 uint32_t ecrces : 1; /**< ECRC Error Status */ 3979 uint32_t mtlps : 1; /**< Malformed TLP Status */ 3980 uint32_t ros : 1; /**< Receiver Overflow Status */ 3981 uint32_t ucs : 1; /**< Unexpected Completion Status */ 3982 uint32_t cas : 1; /**< Completer Abort Status */ 3983 uint32_t cts : 1; /**< Completion Timeout Status */ 3984 uint32_t fcpes : 1; /**< Flow Control Protocol Error Status */ 3985 uint32_t ptlps : 1; /**< Poisoned TLP Status */ 3986 uint32_t reserved_6_11 : 6; 3987 uint32_t sdes : 1; /**< Surprise Down Error Status (not supported) */ 3988 uint32_t dlpes : 1; /**< Data Link Protocol Error Status */ 3989 uint32_t reserved_0_3 : 4; 3990#else 3991 uint32_t reserved_0_3 : 4; 3992 uint32_t dlpes : 1; 3993 uint32_t sdes : 1; 3994 uint32_t reserved_6_11 : 6; 3995 uint32_t ptlps : 1; 3996 uint32_t fcpes : 1; 3997 uint32_t cts : 1; 3998 uint32_t cas : 1; 3999 uint32_t ucs : 1; 4000 uint32_t ros : 1; 4001 uint32_t mtlps : 1; 4002 uint32_t ecrces : 1; 4003 uint32_t ures : 1; 4004 uint32_t reserved_21_23 : 3; 4005 uint32_t uatombs : 1; 4006 uint32_t reserved_25_31 : 7; 4007#endif 4008 } cn61xx; 4009 struct cvmx_pcieepx_cfg065_cn52xx cn63xx; 4010 struct cvmx_pcieepx_cfg065_cn52xx cn63xxp1; 4011 struct cvmx_pcieepx_cfg065_cn61xx cn66xx; 4012 struct cvmx_pcieepx_cfg065_cn61xx cn68xx; 4013 struct cvmx_pcieepx_cfg065_cn52xx cn68xxp1; 4014 struct cvmx_pcieepx_cfg065_cnf71xx { 4015#ifdef __BIG_ENDIAN_BITFIELD 4016 uint32_t reserved_25_31 : 7; 4017 uint32_t uatombs : 1; /**< Unsupported AtomicOp Egress Blocked Status */ 4018 uint32_t reserved_23_23 : 1; 4019 uint32_t ucies : 1; /**< Uncorrectable Internal Error Status */ 4020 uint32_t reserved_21_21 : 1; 4021 uint32_t ures : 1; /**< Unsupported Request Error Status */ 4022 uint32_t ecrces : 1; /**< ECRC Error Status */ 4023 uint32_t mtlps : 1; /**< Malformed TLP Status */ 4024 uint32_t ros : 1; /**< Receiver Overflow Status */ 4025 uint32_t ucs : 1; /**< Unexpected Completion Status */ 4026 uint32_t cas : 1; /**< Completer Abort Status */ 4027 uint32_t cts : 1; /**< Completion Timeout Status */ 4028 uint32_t fcpes : 1; /**< Flow Control Protocol Error Status */ 4029 uint32_t ptlps : 1; /**< Poisoned TLP Status */ 4030 uint32_t reserved_5_11 : 7; 4031 uint32_t dlpes : 1; /**< Data Link Protocol Error Status */ 4032 uint32_t reserved_0_3 : 4; 4033#else 4034 uint32_t reserved_0_3 : 4; 4035 uint32_t dlpes : 1; 4036 uint32_t reserved_5_11 : 7; 4037 uint32_t ptlps : 1; 4038 uint32_t fcpes : 1; 4039 uint32_t cts : 1; 4040 uint32_t cas : 1; 4041 uint32_t ucs : 1; 4042 uint32_t ros : 1; 4043 uint32_t mtlps : 1; 4044 uint32_t ecrces : 1; 4045 uint32_t ures : 1; 4046 uint32_t reserved_21_21 : 1; 4047 uint32_t ucies : 1; 4048 uint32_t reserved_23_23 : 1; 4049 uint32_t uatombs : 1; 4050 uint32_t reserved_25_31 : 7; 4051#endif 4052 } cnf71xx; 4053}; 4054typedef union cvmx_pcieepx_cfg065 cvmx_pcieepx_cfg065_t; 4055 4056/** 4057 * cvmx_pcieep#_cfg066 4058 * 4059 * PCIE_CFG066 = Sixty-seventh 32-bits of PCIE type 0 config space 4060 * (Uncorrectable Error Mask Register) 4061 */ 4062union cvmx_pcieepx_cfg066 { 4063 uint32_t u32; 4064 struct cvmx_pcieepx_cfg066_s { 4065#ifdef __BIG_ENDIAN_BITFIELD 4066 uint32_t reserved_25_31 : 7; 4067 uint32_t uatombm : 1; /**< Unsupported AtomicOp Egress Blocked Mask */ 4068 uint32_t reserved_23_23 : 1; 4069 uint32_t uciem : 1; /**< Uncorrectable Internal Error Mask */ 4070 uint32_t reserved_21_21 : 1; 4071 uint32_t urem : 1; /**< Unsupported Request Error Mask */ 4072 uint32_t ecrcem : 1; /**< ECRC Error Mask */ 4073 uint32_t mtlpm : 1; /**< Malformed TLP Mask */ 4074 uint32_t rom : 1; /**< Receiver Overflow Mask */ 4075 uint32_t ucm : 1; /**< Unexpected Completion Mask */ 4076 uint32_t cam : 1; /**< Completer Abort Mask */ 4077 uint32_t ctm : 1; /**< Completion Timeout Mask */ 4078 uint32_t fcpem : 1; /**< Flow Control Protocol Error Mask */ 4079 uint32_t ptlpm : 1; /**< Poisoned TLP Mask */ 4080 uint32_t reserved_6_11 : 6; 4081 uint32_t sdem : 1; /**< Surprise Down Error Mask (not supported) */ 4082 uint32_t dlpem : 1; /**< Data Link Protocol Error Mask */ 4083 uint32_t reserved_0_3 : 4; 4084#else 4085 uint32_t reserved_0_3 : 4; 4086 uint32_t dlpem : 1; 4087 uint32_t sdem : 1; 4088 uint32_t reserved_6_11 : 6; 4089 uint32_t ptlpm : 1; 4090 uint32_t fcpem : 1; 4091 uint32_t ctm : 1; 4092 uint32_t cam : 1; 4093 uint32_t ucm : 1; 4094 uint32_t rom : 1; 4095 uint32_t mtlpm : 1; 4096 uint32_t ecrcem : 1; 4097 uint32_t urem : 1; 4098 uint32_t reserved_21_21 : 1; 4099 uint32_t uciem : 1; 4100 uint32_t reserved_23_23 : 1; 4101 uint32_t uatombm : 1; 4102 uint32_t reserved_25_31 : 7; 4103#endif 4104 } s; 4105 struct cvmx_pcieepx_cfg066_cn52xx { 4106#ifdef __BIG_ENDIAN_BITFIELD 4107 uint32_t reserved_21_31 : 11; 4108 uint32_t urem : 1; /**< Unsupported Request Error Mask */ 4109 uint32_t ecrcem : 1; /**< ECRC Error Mask */ 4110 uint32_t mtlpm : 1; /**< Malformed TLP Mask */ 4111 uint32_t rom : 1; /**< Receiver Overflow Mask */ 4112 uint32_t ucm : 1; /**< Unexpected Completion Mask */ 4113 uint32_t cam : 1; /**< Completer Abort Mask */ 4114 uint32_t ctm : 1; /**< Completion Timeout Mask */ 4115 uint32_t fcpem : 1; /**< Flow Control Protocol Error Mask */ 4116 uint32_t ptlpm : 1; /**< Poisoned TLP Mask */ 4117 uint32_t reserved_6_11 : 6; 4118 uint32_t sdem : 1; /**< Surprise Down Error Mask (not supported) */ 4119 uint32_t dlpem : 1; /**< Data Link Protocol Error Mask */ 4120 uint32_t reserved_0_3 : 4; 4121#else 4122 uint32_t reserved_0_3 : 4; 4123 uint32_t dlpem : 1; 4124 uint32_t sdem : 1; 4125 uint32_t reserved_6_11 : 6; 4126 uint32_t ptlpm : 1; 4127 uint32_t fcpem : 1; 4128 uint32_t ctm : 1; 4129 uint32_t cam : 1; 4130 uint32_t ucm : 1; 4131 uint32_t rom : 1; 4132 uint32_t mtlpm : 1; 4133 uint32_t ecrcem : 1; 4134 uint32_t urem : 1; 4135 uint32_t reserved_21_31 : 11; 4136#endif 4137 } cn52xx; 4138 struct cvmx_pcieepx_cfg066_cn52xx cn52xxp1; 4139 struct cvmx_pcieepx_cfg066_cn52xx cn56xx; 4140 struct cvmx_pcieepx_cfg066_cn52xx cn56xxp1; 4141 struct cvmx_pcieepx_cfg066_cn61xx { 4142#ifdef __BIG_ENDIAN_BITFIELD 4143 uint32_t reserved_25_31 : 7; 4144 uint32_t uatombm : 1; /**< Unsupported AtomicOp Egress Blocked Mask */ 4145 uint32_t reserved_21_23 : 3; 4146 uint32_t urem : 1; /**< Unsupported Request Error Mask */ 4147 uint32_t ecrcem : 1; /**< ECRC Error Mask */ 4148 uint32_t mtlpm : 1; /**< Malformed TLP Mask */ 4149 uint32_t rom : 1; /**< Receiver Overflow Mask */ 4150 uint32_t ucm : 1; /**< Unexpected Completion Mask */ 4151 uint32_t cam : 1; /**< Completer Abort Mask */ 4152 uint32_t ctm : 1; /**< Completion Timeout Mask */ 4153 uint32_t fcpem : 1; /**< Flow Control Protocol Error Mask */ 4154 uint32_t ptlpm : 1; /**< Poisoned TLP Mask */ 4155 uint32_t reserved_6_11 : 6; 4156 uint32_t sdem : 1; /**< Surprise Down Error Mask (not supported) */ 4157 uint32_t dlpem : 1; /**< Data Link Protocol Error Mask */ 4158 uint32_t reserved_0_3 : 4; 4159#else 4160 uint32_t reserved_0_3 : 4; 4161 uint32_t dlpem : 1; 4162 uint32_t sdem : 1; 4163 uint32_t reserved_6_11 : 6; 4164 uint32_t ptlpm : 1; 4165 uint32_t fcpem : 1; 4166 uint32_t ctm : 1; 4167 uint32_t cam : 1; 4168 uint32_t ucm : 1; 4169 uint32_t rom : 1; 4170 uint32_t mtlpm : 1; 4171 uint32_t ecrcem : 1; 4172 uint32_t urem : 1; 4173 uint32_t reserved_21_23 : 3; 4174 uint32_t uatombm : 1; 4175 uint32_t reserved_25_31 : 7; 4176#endif 4177 } cn61xx; 4178 struct cvmx_pcieepx_cfg066_cn52xx cn63xx; 4179 struct cvmx_pcieepx_cfg066_cn52xx cn63xxp1; 4180 struct cvmx_pcieepx_cfg066_cn61xx cn66xx; 4181 struct cvmx_pcieepx_cfg066_cn61xx cn68xx; 4182 struct cvmx_pcieepx_cfg066_cn52xx cn68xxp1; 4183 struct cvmx_pcieepx_cfg066_cnf71xx { 4184#ifdef __BIG_ENDIAN_BITFIELD 4185 uint32_t reserved_25_31 : 7; 4186 uint32_t uatombm : 1; /**< Unsupported AtomicOp Egress Blocked Mask */ 4187 uint32_t reserved_23_23 : 1; 4188 uint32_t uciem : 1; /**< Uncorrectable Internal Error Mask */ 4189 uint32_t reserved_21_21 : 1; 4190 uint32_t urem : 1; /**< Unsupported Request Error Mask */ 4191 uint32_t ecrcem : 1; /**< ECRC Error Mask */ 4192 uint32_t mtlpm : 1; /**< Malformed TLP Mask */ 4193 uint32_t rom : 1; /**< Receiver Overflow Mask */ 4194 uint32_t ucm : 1; /**< Unexpected Completion Mask */ 4195 uint32_t cam : 1; /**< Completer Abort Mask */ 4196 uint32_t ctm : 1; /**< Completion Timeout Mask */ 4197 uint32_t fcpem : 1; /**< Flow Control Protocol Error Mask */ 4198 uint32_t ptlpm : 1; /**< Poisoned TLP Mask */ 4199 uint32_t reserved_5_11 : 7; 4200 uint32_t dlpem : 1; /**< Data Link Protocol Error Mask */ 4201 uint32_t reserved_0_3 : 4; 4202#else 4203 uint32_t reserved_0_3 : 4; 4204 uint32_t dlpem : 1; 4205 uint32_t reserved_5_11 : 7; 4206 uint32_t ptlpm : 1; 4207 uint32_t fcpem : 1; 4208 uint32_t ctm : 1; 4209 uint32_t cam : 1; 4210 uint32_t ucm : 1; 4211 uint32_t rom : 1; 4212 uint32_t mtlpm : 1; 4213 uint32_t ecrcem : 1; 4214 uint32_t urem : 1; 4215 uint32_t reserved_21_21 : 1; 4216 uint32_t uciem : 1; 4217 uint32_t reserved_23_23 : 1; 4218 uint32_t uatombm : 1; 4219 uint32_t reserved_25_31 : 7; 4220#endif 4221 } cnf71xx; 4222}; 4223typedef union cvmx_pcieepx_cfg066 cvmx_pcieepx_cfg066_t; 4224 4225/** 4226 * cvmx_pcieep#_cfg067 4227 * 4228 * PCIE_CFG067 = Sixty-eighth 32-bits of PCIE type 0 config space 4229 * (Uncorrectable Error Severity Register) 4230 */ 4231union cvmx_pcieepx_cfg067 { 4232 uint32_t u32; 4233 struct cvmx_pcieepx_cfg067_s { 4234#ifdef __BIG_ENDIAN_BITFIELD 4235 uint32_t reserved_25_31 : 7; 4236 uint32_t uatombs : 1; /**< Unsupported AtomicOp Egress Blocked Severity */ 4237 uint32_t reserved_23_23 : 1; 4238 uint32_t ucies : 1; /**< Uncorrectable Internal Error Severity */ 4239 uint32_t reserved_21_21 : 1; 4240 uint32_t ures : 1; /**< Unsupported Request Error Severity */ 4241 uint32_t ecrces : 1; /**< ECRC Error Severity */ 4242 uint32_t mtlps : 1; /**< Malformed TLP Severity */ 4243 uint32_t ros : 1; /**< Receiver Overflow Severity */ 4244 uint32_t ucs : 1; /**< Unexpected Completion Severity */ 4245 uint32_t cas : 1; /**< Completer Abort Severity */ 4246 uint32_t cts : 1; /**< Completion Timeout Severity */ 4247 uint32_t fcpes : 1; /**< Flow Control Protocol Error Severity */ 4248 uint32_t ptlps : 1; /**< Poisoned TLP Severity */ 4249 uint32_t reserved_6_11 : 6; 4250 uint32_t sdes : 1; /**< Surprise Down Error Severity (not supported) */ 4251 uint32_t dlpes : 1; /**< Data Link Protocol Error Severity */ 4252 uint32_t reserved_0_3 : 4; 4253#else 4254 uint32_t reserved_0_3 : 4; 4255 uint32_t dlpes : 1; 4256 uint32_t sdes : 1; 4257 uint32_t reserved_6_11 : 6; 4258 uint32_t ptlps : 1; 4259 uint32_t fcpes : 1; 4260 uint32_t cts : 1; 4261 uint32_t cas : 1; 4262 uint32_t ucs : 1; 4263 uint32_t ros : 1; 4264 uint32_t mtlps : 1; 4265 uint32_t ecrces : 1; 4266 uint32_t ures : 1; 4267 uint32_t reserved_21_21 : 1; 4268 uint32_t ucies : 1; 4269 uint32_t reserved_23_23 : 1; 4270 uint32_t uatombs : 1; 4271 uint32_t reserved_25_31 : 7; 4272#endif 4273 } s; 4274 struct cvmx_pcieepx_cfg067_cn52xx { 4275#ifdef __BIG_ENDIAN_BITFIELD 4276 uint32_t reserved_21_31 : 11; 4277 uint32_t ures : 1; /**< Unsupported Request Error Severity */ 4278 uint32_t ecrces : 1; /**< ECRC Error Severity */ 4279 uint32_t mtlps : 1; /**< Malformed TLP Severity */ 4280 uint32_t ros : 1; /**< Receiver Overflow Severity */ 4281 uint32_t ucs : 1; /**< Unexpected Completion Severity */ 4282 uint32_t cas : 1; /**< Completer Abort Severity */ 4283 uint32_t cts : 1; /**< Completion Timeout Severity */ 4284 uint32_t fcpes : 1; /**< Flow Control Protocol Error Severity */ 4285 uint32_t ptlps : 1; /**< Poisoned TLP Severity */ 4286 uint32_t reserved_6_11 : 6; 4287 uint32_t sdes : 1; /**< Surprise Down Error Severity (not supported) */ 4288 uint32_t dlpes : 1; /**< Data Link Protocol Error Severity */ 4289 uint32_t reserved_0_3 : 4; 4290#else 4291 uint32_t reserved_0_3 : 4; 4292 uint32_t dlpes : 1; 4293 uint32_t sdes : 1; 4294 uint32_t reserved_6_11 : 6; 4295 uint32_t ptlps : 1; 4296 uint32_t fcpes : 1; 4297 uint32_t cts : 1; 4298 uint32_t cas : 1; 4299 uint32_t ucs : 1; 4300 uint32_t ros : 1; 4301 uint32_t mtlps : 1; 4302 uint32_t ecrces : 1; 4303 uint32_t ures : 1; 4304 uint32_t reserved_21_31 : 11; 4305#endif 4306 } cn52xx; 4307 struct cvmx_pcieepx_cfg067_cn52xx cn52xxp1; 4308 struct cvmx_pcieepx_cfg067_cn52xx cn56xx; 4309 struct cvmx_pcieepx_cfg067_cn52xx cn56xxp1; 4310 struct cvmx_pcieepx_cfg067_cn61xx { 4311#ifdef __BIG_ENDIAN_BITFIELD 4312 uint32_t reserved_25_31 : 7; 4313 uint32_t uatombs : 1; /**< Unsupported AtomicOp Egress Blocked Severity */ 4314 uint32_t reserved_21_23 : 3; 4315 uint32_t ures : 1; /**< Unsupported Request Error Severity */ 4316 uint32_t ecrces : 1; /**< ECRC Error Severity */ 4317 uint32_t mtlps : 1; /**< Malformed TLP Severity */ 4318 uint32_t ros : 1; /**< Receiver Overflow Severity */ 4319 uint32_t ucs : 1; /**< Unexpected Completion Severity */ 4320 uint32_t cas : 1; /**< Completer Abort Severity */ 4321 uint32_t cts : 1; /**< Completion Timeout Severity */ 4322 uint32_t fcpes : 1; /**< Flow Control Protocol Error Severity */ 4323 uint32_t ptlps : 1; /**< Poisoned TLP Severity */ 4324 uint32_t reserved_6_11 : 6; 4325 uint32_t sdes : 1; /**< Surprise Down Error Severity (not supported) */ 4326 uint32_t dlpes : 1; /**< Data Link Protocol Error Severity */ 4327 uint32_t reserved_0_3 : 4; 4328#else 4329 uint32_t reserved_0_3 : 4; 4330 uint32_t dlpes : 1; 4331 uint32_t sdes : 1; 4332 uint32_t reserved_6_11 : 6; 4333 uint32_t ptlps : 1; 4334 uint32_t fcpes : 1; 4335 uint32_t cts : 1; 4336 uint32_t cas : 1; 4337 uint32_t ucs : 1; 4338 uint32_t ros : 1; 4339 uint32_t mtlps : 1; 4340 uint32_t ecrces : 1; 4341 uint32_t ures : 1; 4342 uint32_t reserved_21_23 : 3; 4343 uint32_t uatombs : 1; 4344 uint32_t reserved_25_31 : 7; 4345#endif 4346 } cn61xx; 4347 struct cvmx_pcieepx_cfg067_cn52xx cn63xx; 4348 struct cvmx_pcieepx_cfg067_cn52xx cn63xxp1; 4349 struct cvmx_pcieepx_cfg067_cn61xx cn66xx; 4350 struct cvmx_pcieepx_cfg067_cn61xx cn68xx; 4351 struct cvmx_pcieepx_cfg067_cn52xx cn68xxp1; 4352 struct cvmx_pcieepx_cfg067_cnf71xx { 4353#ifdef __BIG_ENDIAN_BITFIELD 4354 uint32_t reserved_25_31 : 7; 4355 uint32_t uatombs : 1; /**< Unsupported AtomicOp Egress Blocked Severity */ 4356 uint32_t reserved_23_23 : 1; 4357 uint32_t ucies : 1; /**< Uncorrectable Internal Error Severity */ 4358 uint32_t reserved_21_21 : 1; 4359 uint32_t ures : 1; /**< Unsupported Request Error Severity */ 4360 uint32_t ecrces : 1; /**< ECRC Error Severity */ 4361 uint32_t mtlps : 1; /**< Malformed TLP Severity */ 4362 uint32_t ros : 1; /**< Receiver Overflow Severity */ 4363 uint32_t ucs : 1; /**< Unexpected Completion Severity */ 4364 uint32_t cas : 1; /**< Completer Abort Severity */ 4365 uint32_t cts : 1; /**< Completion Timeout Severity */ 4366 uint32_t fcpes : 1; /**< Flow Control Protocol Error Severity */ 4367 uint32_t ptlps : 1; /**< Poisoned TLP Severity */ 4368 uint32_t reserved_5_11 : 7; 4369 uint32_t dlpes : 1; /**< Data Link Protocol Error Severity */ 4370 uint32_t reserved_0_3 : 4; 4371#else 4372 uint32_t reserved_0_3 : 4; 4373 uint32_t dlpes : 1; 4374 uint32_t reserved_5_11 : 7; 4375 uint32_t ptlps : 1; 4376 uint32_t fcpes : 1; 4377 uint32_t cts : 1; 4378 uint32_t cas : 1; 4379 uint32_t ucs : 1; 4380 uint32_t ros : 1; 4381 uint32_t mtlps : 1; 4382 uint32_t ecrces : 1; 4383 uint32_t ures : 1; 4384 uint32_t reserved_21_21 : 1; 4385 uint32_t ucies : 1; 4386 uint32_t reserved_23_23 : 1; 4387 uint32_t uatombs : 1; 4388 uint32_t reserved_25_31 : 7; 4389#endif 4390 } cnf71xx; 4391}; 4392typedef union cvmx_pcieepx_cfg067 cvmx_pcieepx_cfg067_t; 4393 4394/** 4395 * cvmx_pcieep#_cfg068 4396 * 4397 * PCIE_CFG068 = Sixty-ninth 32-bits of PCIE type 0 config space 4398 * (Correctable Error Status Register) 4399 */ 4400union cvmx_pcieepx_cfg068 { 4401 uint32_t u32; 4402 struct cvmx_pcieepx_cfg068_s { 4403#ifdef __BIG_ENDIAN_BITFIELD 4404 uint32_t reserved_15_31 : 17; 4405 uint32_t cies : 1; /**< Corrected Internal Error Status */ 4406 uint32_t anfes : 1; /**< Advisory Non-Fatal Error Status */ 4407 uint32_t rtts : 1; /**< Reply Timer Timeout Status */ 4408 uint32_t reserved_9_11 : 3; 4409 uint32_t rnrs : 1; /**< REPLAY_NUM Rollover Status */ 4410 uint32_t bdllps : 1; /**< Bad DLLP Status */ 4411 uint32_t btlps : 1; /**< Bad TLP Status */ 4412 uint32_t reserved_1_5 : 5; 4413 uint32_t res : 1; /**< Receiver Error Status */ 4414#else 4415 uint32_t res : 1; 4416 uint32_t reserved_1_5 : 5; 4417 uint32_t btlps : 1; 4418 uint32_t bdllps : 1; 4419 uint32_t rnrs : 1; 4420 uint32_t reserved_9_11 : 3; 4421 uint32_t rtts : 1; 4422 uint32_t anfes : 1; 4423 uint32_t cies : 1; 4424 uint32_t reserved_15_31 : 17; 4425#endif 4426 } s; 4427 struct cvmx_pcieepx_cfg068_cn52xx { 4428#ifdef __BIG_ENDIAN_BITFIELD 4429 uint32_t reserved_14_31 : 18; 4430 uint32_t anfes : 1; /**< Advisory Non-Fatal Error Status */ 4431 uint32_t rtts : 1; /**< Reply Timer Timeout Status */ 4432 uint32_t reserved_9_11 : 3; 4433 uint32_t rnrs : 1; /**< REPLAY_NUM Rollover Status */ 4434 uint32_t bdllps : 1; /**< Bad DLLP Status */ 4435 uint32_t btlps : 1; /**< Bad TLP Status */ 4436 uint32_t reserved_1_5 : 5; 4437 uint32_t res : 1; /**< Receiver Error Status */ 4438#else 4439 uint32_t res : 1; 4440 uint32_t reserved_1_5 : 5; 4441 uint32_t btlps : 1; 4442 uint32_t bdllps : 1; 4443 uint32_t rnrs : 1; 4444 uint32_t reserved_9_11 : 3; 4445 uint32_t rtts : 1; 4446 uint32_t anfes : 1; 4447 uint32_t reserved_14_31 : 18; 4448#endif 4449 } cn52xx; 4450 struct cvmx_pcieepx_cfg068_cn52xx cn52xxp1; 4451 struct cvmx_pcieepx_cfg068_cn52xx cn56xx; 4452 struct cvmx_pcieepx_cfg068_cn52xx cn56xxp1; 4453 struct cvmx_pcieepx_cfg068_cn52xx cn61xx; 4454 struct cvmx_pcieepx_cfg068_cn52xx cn63xx; 4455 struct cvmx_pcieepx_cfg068_cn52xx cn63xxp1; 4456 struct cvmx_pcieepx_cfg068_cn52xx cn66xx; 4457 struct cvmx_pcieepx_cfg068_cn52xx cn68xx; 4458 struct cvmx_pcieepx_cfg068_cn52xx cn68xxp1; 4459 struct cvmx_pcieepx_cfg068_s cnf71xx; 4460}; 4461typedef union cvmx_pcieepx_cfg068 cvmx_pcieepx_cfg068_t; 4462 4463/** 4464 * cvmx_pcieep#_cfg069 4465 * 4466 * PCIE_CFG069 = Seventieth 32-bits of PCIE type 0 config space 4467 * (Correctable Error Mask Register) 4468 */ 4469union cvmx_pcieepx_cfg069 { 4470 uint32_t u32; 4471 struct cvmx_pcieepx_cfg069_s { 4472#ifdef __BIG_ENDIAN_BITFIELD 4473 uint32_t reserved_15_31 : 17; 4474 uint32_t ciem : 1; /**< Corrected Internal Error Mask */ 4475 uint32_t anfem : 1; /**< Advisory Non-Fatal Error Mask */ 4476 uint32_t rttm : 1; /**< Reply Timer Timeout Mask */ 4477 uint32_t reserved_9_11 : 3; 4478 uint32_t rnrm : 1; /**< REPLAY_NUM Rollover Mask */ 4479 uint32_t bdllpm : 1; /**< Bad DLLP Mask */ 4480 uint32_t btlpm : 1; /**< Bad TLP Mask */ 4481 uint32_t reserved_1_5 : 5; 4482 uint32_t rem : 1; /**< Receiver Error Mask */ 4483#else 4484 uint32_t rem : 1; 4485 uint32_t reserved_1_5 : 5; 4486 uint32_t btlpm : 1; 4487 uint32_t bdllpm : 1; 4488 uint32_t rnrm : 1; 4489 uint32_t reserved_9_11 : 3; 4490 uint32_t rttm : 1; 4491 uint32_t anfem : 1; 4492 uint32_t ciem : 1; 4493 uint32_t reserved_15_31 : 17; 4494#endif 4495 } s; 4496 struct cvmx_pcieepx_cfg069_cn52xx { 4497#ifdef __BIG_ENDIAN_BITFIELD 4498 uint32_t reserved_14_31 : 18; 4499 uint32_t anfem : 1; /**< Advisory Non-Fatal Error Mask */ 4500 uint32_t rttm : 1; /**< Reply Timer Timeout Mask */ 4501 uint32_t reserved_9_11 : 3; 4502 uint32_t rnrm : 1; /**< REPLAY_NUM Rollover Mask */ 4503 uint32_t bdllpm : 1; /**< Bad DLLP Mask */ 4504 uint32_t btlpm : 1; /**< Bad TLP Mask */ 4505 uint32_t reserved_1_5 : 5; 4506 uint32_t rem : 1; /**< Receiver Error Mask */ 4507#else 4508 uint32_t rem : 1; 4509 uint32_t reserved_1_5 : 5; 4510 uint32_t btlpm : 1; 4511 uint32_t bdllpm : 1; 4512 uint32_t rnrm : 1; 4513 uint32_t reserved_9_11 : 3; 4514 uint32_t rttm : 1; 4515 uint32_t anfem : 1; 4516 uint32_t reserved_14_31 : 18; 4517#endif 4518 } cn52xx; 4519 struct cvmx_pcieepx_cfg069_cn52xx cn52xxp1; 4520 struct cvmx_pcieepx_cfg069_cn52xx cn56xx; 4521 struct cvmx_pcieepx_cfg069_cn52xx cn56xxp1; 4522 struct cvmx_pcieepx_cfg069_cn52xx cn61xx; 4523 struct cvmx_pcieepx_cfg069_cn52xx cn63xx; 4524 struct cvmx_pcieepx_cfg069_cn52xx cn63xxp1; 4525 struct cvmx_pcieepx_cfg069_cn52xx cn66xx; 4526 struct cvmx_pcieepx_cfg069_cn52xx cn68xx; 4527 struct cvmx_pcieepx_cfg069_cn52xx cn68xxp1; 4528 struct cvmx_pcieepx_cfg069_s cnf71xx; 4529}; 4530typedef union cvmx_pcieepx_cfg069 cvmx_pcieepx_cfg069_t; 4531 4532/** 4533 * cvmx_pcieep#_cfg070 4534 * 4535 * PCIE_CFG070 = Seventy-first 32-bits of PCIE type 0 config space 4536 * (Advanced Error Capabilities and Control Register) 4537 */ 4538union cvmx_pcieepx_cfg070 { 4539 uint32_t u32; 4540 struct cvmx_pcieepx_cfg070_s { 4541#ifdef __BIG_ENDIAN_BITFIELD 4542 uint32_t reserved_9_31 : 23; 4543 uint32_t ce : 1; /**< ECRC Check Enable */ 4544 uint32_t cc : 1; /**< ECRC Check Capable */ 4545 uint32_t ge : 1; /**< ECRC Generation Enable */ 4546 uint32_t gc : 1; /**< ECRC Generation Capability */ 4547 uint32_t fep : 5; /**< First Error Pointer */ 4548#else 4549 uint32_t fep : 5; 4550 uint32_t gc : 1; 4551 uint32_t ge : 1; 4552 uint32_t cc : 1; 4553 uint32_t ce : 1; 4554 uint32_t reserved_9_31 : 23; 4555#endif 4556 } s; 4557 struct cvmx_pcieepx_cfg070_s cn52xx; 4558 struct cvmx_pcieepx_cfg070_s cn52xxp1; 4559 struct cvmx_pcieepx_cfg070_s cn56xx; 4560 struct cvmx_pcieepx_cfg070_s cn56xxp1; 4561 struct cvmx_pcieepx_cfg070_s cn61xx; 4562 struct cvmx_pcieepx_cfg070_s cn63xx; 4563 struct cvmx_pcieepx_cfg070_s cn63xxp1; 4564 struct cvmx_pcieepx_cfg070_s cn66xx; 4565 struct cvmx_pcieepx_cfg070_s cn68xx; 4566 struct cvmx_pcieepx_cfg070_s cn68xxp1; 4567 struct cvmx_pcieepx_cfg070_s cnf71xx; 4568}; 4569typedef union cvmx_pcieepx_cfg070 cvmx_pcieepx_cfg070_t; 4570 4571/** 4572 * cvmx_pcieep#_cfg071 4573 * 4574 * PCIE_CFG071 = Seventy-second 32-bits of PCIE type 0 config space 4575 * (Header Log Register 1) 4576 */ 4577union cvmx_pcieepx_cfg071 { 4578 uint32_t u32; 4579 struct cvmx_pcieepx_cfg071_s { 4580#ifdef __BIG_ENDIAN_BITFIELD 4581 uint32_t dword1 : 32; /**< Header Log Register (first DWORD) */ 4582#else 4583 uint32_t dword1 : 32; 4584#endif 4585 } s; 4586 struct cvmx_pcieepx_cfg071_s cn52xx; 4587 struct cvmx_pcieepx_cfg071_s cn52xxp1; 4588 struct cvmx_pcieepx_cfg071_s cn56xx; 4589 struct cvmx_pcieepx_cfg071_s cn56xxp1; 4590 struct cvmx_pcieepx_cfg071_s cn61xx; 4591 struct cvmx_pcieepx_cfg071_s cn63xx; 4592 struct cvmx_pcieepx_cfg071_s cn63xxp1; 4593 struct cvmx_pcieepx_cfg071_s cn66xx; 4594 struct cvmx_pcieepx_cfg071_s cn68xx; 4595 struct cvmx_pcieepx_cfg071_s cn68xxp1; 4596 struct cvmx_pcieepx_cfg071_s cnf71xx; 4597}; 4598typedef union cvmx_pcieepx_cfg071 cvmx_pcieepx_cfg071_t; 4599 4600/** 4601 * cvmx_pcieep#_cfg072 4602 * 4603 * PCIE_CFG072 = Seventy-third 32-bits of PCIE type 0 config space 4604 * (Header Log Register 2) 4605 */ 4606union cvmx_pcieepx_cfg072 { 4607 uint32_t u32; 4608 struct cvmx_pcieepx_cfg072_s { 4609#ifdef __BIG_ENDIAN_BITFIELD 4610 uint32_t dword2 : 32; /**< Header Log Register (second DWORD) */ 4611#else 4612 uint32_t dword2 : 32; 4613#endif 4614 } s; 4615 struct cvmx_pcieepx_cfg072_s cn52xx; 4616 struct cvmx_pcieepx_cfg072_s cn52xxp1; 4617 struct cvmx_pcieepx_cfg072_s cn56xx; 4618 struct cvmx_pcieepx_cfg072_s cn56xxp1; 4619 struct cvmx_pcieepx_cfg072_s cn61xx; 4620 struct cvmx_pcieepx_cfg072_s cn63xx; 4621 struct cvmx_pcieepx_cfg072_s cn63xxp1; 4622 struct cvmx_pcieepx_cfg072_s cn66xx; 4623 struct cvmx_pcieepx_cfg072_s cn68xx; 4624 struct cvmx_pcieepx_cfg072_s cn68xxp1; 4625 struct cvmx_pcieepx_cfg072_s cnf71xx; 4626}; 4627typedef union cvmx_pcieepx_cfg072 cvmx_pcieepx_cfg072_t; 4628 4629/** 4630 * cvmx_pcieep#_cfg073 4631 * 4632 * PCIE_CFG073 = Seventy-fourth 32-bits of PCIE type 0 config space 4633 * (Header Log Register 3) 4634 */ 4635union cvmx_pcieepx_cfg073 { 4636 uint32_t u32; 4637 struct cvmx_pcieepx_cfg073_s { 4638#ifdef __BIG_ENDIAN_BITFIELD 4639 uint32_t dword3 : 32; /**< Header Log Register (third DWORD) */ 4640#else 4641 uint32_t dword3 : 32; 4642#endif 4643 } s; 4644 struct cvmx_pcieepx_cfg073_s cn52xx; 4645 struct cvmx_pcieepx_cfg073_s cn52xxp1; 4646 struct cvmx_pcieepx_cfg073_s cn56xx; 4647 struct cvmx_pcieepx_cfg073_s cn56xxp1; 4648 struct cvmx_pcieepx_cfg073_s cn61xx; 4649 struct cvmx_pcieepx_cfg073_s cn63xx; 4650 struct cvmx_pcieepx_cfg073_s cn63xxp1; 4651 struct cvmx_pcieepx_cfg073_s cn66xx; 4652 struct cvmx_pcieepx_cfg073_s cn68xx; 4653 struct cvmx_pcieepx_cfg073_s cn68xxp1; 4654 struct cvmx_pcieepx_cfg073_s cnf71xx; 4655}; 4656typedef union cvmx_pcieepx_cfg073 cvmx_pcieepx_cfg073_t; 4657 4658/** 4659 * cvmx_pcieep#_cfg074 4660 * 4661 * PCIE_CFG074 = Seventy-fifth 32-bits of PCIE type 0 config space 4662 * (Header Log Register 4) 4663 */ 4664union cvmx_pcieepx_cfg074 { 4665 uint32_t u32; 4666 struct cvmx_pcieepx_cfg074_s { 4667#ifdef __BIG_ENDIAN_BITFIELD 4668 uint32_t dword4 : 32; /**< Header Log Register (fourth DWORD) */ 4669#else 4670 uint32_t dword4 : 32; 4671#endif 4672 } s; 4673 struct cvmx_pcieepx_cfg074_s cn52xx; 4674 struct cvmx_pcieepx_cfg074_s cn52xxp1; 4675 struct cvmx_pcieepx_cfg074_s cn56xx; 4676 struct cvmx_pcieepx_cfg074_s cn56xxp1; 4677 struct cvmx_pcieepx_cfg074_s cn61xx; 4678 struct cvmx_pcieepx_cfg074_s cn63xx; 4679 struct cvmx_pcieepx_cfg074_s cn63xxp1; 4680 struct cvmx_pcieepx_cfg074_s cn66xx; 4681 struct cvmx_pcieepx_cfg074_s cn68xx; 4682 struct cvmx_pcieepx_cfg074_s cn68xxp1; 4683 struct cvmx_pcieepx_cfg074_s cnf71xx; 4684}; 4685typedef union cvmx_pcieepx_cfg074 cvmx_pcieepx_cfg074_t; 4686 4687/** 4688 * cvmx_pcieep#_cfg448 4689 * 4690 * PCIE_CFG448 = Four hundred forty-ninth 32-bits of PCIE type 0 config space 4691 * (Ack Latency Timer and Replay Timer Register) 4692 */ 4693union cvmx_pcieepx_cfg448 { 4694 uint32_t u32; 4695 struct cvmx_pcieepx_cfg448_s { 4696#ifdef __BIG_ENDIAN_BITFIELD 4697 uint32_t rtl : 16; /**< Replay Time Limit 4698 The replay timer expires when it reaches this limit. The PCI 4699 Express bus initiates a replay upon reception of a Nak or when 4700 the replay timer expires. 4701 This value will be set correctly by the hardware out of reset 4702 or when the negotiated Link-Width or Payload-Size changes. If 4703 the user changes this value through a CSR write or by an 4704 EEPROM load then they should refer to the PCIe Specification 4705 for the correct value. */ 4706 uint32_t rtltl : 16; /**< Round Trip Latency Time Limit 4707 The Ack/Nak latency timer expires when it reaches this limit. 4708 This value will be set correctly by the hardware out of reset 4709 or when the negotiated Link-Width or Payload-Size changes. If 4710 the user changes this value through a CSR write or by an 4711 EEPROM load then they should refer to the PCIe Specification 4712 for the correct value. */ 4713#else 4714 uint32_t rtltl : 16; 4715 uint32_t rtl : 16; 4716#endif 4717 } s; 4718 struct cvmx_pcieepx_cfg448_s cn52xx; 4719 struct cvmx_pcieepx_cfg448_s cn52xxp1; 4720 struct cvmx_pcieepx_cfg448_s cn56xx; 4721 struct cvmx_pcieepx_cfg448_s cn56xxp1; 4722 struct cvmx_pcieepx_cfg448_s cn61xx; 4723 struct cvmx_pcieepx_cfg448_s cn63xx; 4724 struct cvmx_pcieepx_cfg448_s cn63xxp1; 4725 struct cvmx_pcieepx_cfg448_s cn66xx; 4726 struct cvmx_pcieepx_cfg448_s cn68xx; 4727 struct cvmx_pcieepx_cfg448_s cn68xxp1; 4728 struct cvmx_pcieepx_cfg448_s cnf71xx; 4729}; 4730typedef union cvmx_pcieepx_cfg448 cvmx_pcieepx_cfg448_t; 4731 4732/** 4733 * cvmx_pcieep#_cfg449 4734 * 4735 * PCIE_CFG449 = Four hundred fiftieth 32-bits of PCIE type 0 config space 4736 * (Other Message Register) 4737 */ 4738union cvmx_pcieepx_cfg449 { 4739 uint32_t u32; 4740 struct cvmx_pcieepx_cfg449_s { 4741#ifdef __BIG_ENDIAN_BITFIELD 4742 uint32_t omr : 32; /**< Other Message Register 4743 This register can be used for either of the following purposes: 4744 o To send a specific PCI Express Message, the application 4745 writes the payload of the Message into this register, then 4746 sets bit 0 of the Port Link Control Register to send the 4747 Message. 4748 o To store a corruption pattern for corrupting the LCRC on all 4749 TLPs, the application places a 32-bit corruption pattern into 4750 this register and enables this function by setting bit 25 of 4751 the Port Link Control Register. When enabled, the transmit 4752 LCRC result is XOR'd with this pattern before inserting 4753 it into the packet. */ 4754#else 4755 uint32_t omr : 32; 4756#endif 4757 } s; 4758 struct cvmx_pcieepx_cfg449_s cn52xx; 4759 struct cvmx_pcieepx_cfg449_s cn52xxp1; 4760 struct cvmx_pcieepx_cfg449_s cn56xx; 4761 struct cvmx_pcieepx_cfg449_s cn56xxp1; 4762 struct cvmx_pcieepx_cfg449_s cn61xx; 4763 struct cvmx_pcieepx_cfg449_s cn63xx; 4764 struct cvmx_pcieepx_cfg449_s cn63xxp1; 4765 struct cvmx_pcieepx_cfg449_s cn66xx; 4766 struct cvmx_pcieepx_cfg449_s cn68xx; 4767 struct cvmx_pcieepx_cfg449_s cn68xxp1; 4768 struct cvmx_pcieepx_cfg449_s cnf71xx; 4769}; 4770typedef union cvmx_pcieepx_cfg449 cvmx_pcieepx_cfg449_t; 4771 4772/** 4773 * cvmx_pcieep#_cfg450 4774 * 4775 * PCIE_CFG450 = Four hundred fifty-first 32-bits of PCIE type 0 config space 4776 * (Port Force Link Register) 4777 */ 4778union cvmx_pcieepx_cfg450 { 4779 uint32_t u32; 4780 struct cvmx_pcieepx_cfg450_s { 4781#ifdef __BIG_ENDIAN_BITFIELD 4782 uint32_t lpec : 8; /**< Low Power Entrance Count 4783 The Power Management state will wait for this many clock cycles 4784 for the associated completion of a CfgWr to PCIE_CFG017 register 4785 Power State (PS) field register to go low-power. This register 4786 is intended for applications that do not let the PCI Express 4787 bus handle a completion for configuration request to the 4788 Power Management Control and Status (PCIE_CFG017) register. */ 4789 uint32_t reserved_22_23 : 2; 4790 uint32_t link_state : 6; /**< Link State 4791 The Link state that the PCI Express Bus will be forced to 4792 when bit 15 (Force Link) is set. 4793 State encoding: 4794 o DETECT_QUIET 00h 4795 o DETECT_ACT 01h 4796 o POLL_ACTIVE 02h 4797 o POLL_COMPLIANCE 03h 4798 o POLL_CONFIG 04h 4799 o PRE_DETECT_QUIET 05h 4800 o DETECT_WAIT 06h 4801 o CFG_LINKWD_START 07h 4802 o CFG_LINKWD_ACEPT 08h 4803 o CFG_LANENUM_WAIT 09h 4804 o CFG_LANENUM_ACEPT 0Ah 4805 o CFG_COMPLETE 0Bh 4806 o CFG_IDLE 0Ch 4807 o RCVRY_LOCK 0Dh 4808 o RCVRY_SPEED 0Eh 4809 o RCVRY_RCVRCFG 0Fh 4810 o RCVRY_IDLE 10h 4811 o L0 11h 4812 o L0S 12h 4813 o L123_SEND_EIDLE 13h 4814 o L1_IDLE 14h 4815 o L2_IDLE 15h 4816 o L2_WAKE 16h 4817 o DISABLED_ENTRY 17h 4818 o DISABLED_IDLE 18h 4819 o DISABLED 19h 4820 o LPBK_ENTRY 1Ah 4821 o LPBK_ACTIVE 1Bh 4822 o LPBK_EXIT 1Ch 4823 o LPBK_EXIT_TIMEOUT 1Dh 4824 o HOT_RESET_ENTRY 1Eh 4825 o HOT_RESET 1Fh */ 4826 uint32_t force_link : 1; /**< Force Link 4827 Forces the Link to the state specified by the Link State field. 4828 The Force Link pulse will trigger Link re-negotiation. 4829 * As the The Force Link is a pulse, writing a 1 to it does 4830 trigger the forced link state event, even thought reading it 4831 always returns a 0. */ 4832 uint32_t reserved_8_14 : 7; 4833 uint32_t link_num : 8; /**< Link Number 4834 Not used for Endpoint */ 4835#else 4836 uint32_t link_num : 8; 4837 uint32_t reserved_8_14 : 7; 4838 uint32_t force_link : 1; 4839 uint32_t link_state : 6; 4840 uint32_t reserved_22_23 : 2; 4841 uint32_t lpec : 8; 4842#endif 4843 } s; 4844 struct cvmx_pcieepx_cfg450_s cn52xx; 4845 struct cvmx_pcieepx_cfg450_s cn52xxp1; 4846 struct cvmx_pcieepx_cfg450_s cn56xx; 4847 struct cvmx_pcieepx_cfg450_s cn56xxp1; 4848 struct cvmx_pcieepx_cfg450_s cn61xx; 4849 struct cvmx_pcieepx_cfg450_s cn63xx; 4850 struct cvmx_pcieepx_cfg450_s cn63xxp1; 4851 struct cvmx_pcieepx_cfg450_s cn66xx; 4852 struct cvmx_pcieepx_cfg450_s cn68xx; 4853 struct cvmx_pcieepx_cfg450_s cn68xxp1; 4854 struct cvmx_pcieepx_cfg450_s cnf71xx; 4855}; 4856typedef union cvmx_pcieepx_cfg450 cvmx_pcieepx_cfg450_t; 4857 4858/** 4859 * cvmx_pcieep#_cfg451 4860 * 4861 * PCIE_CFG451 = Four hundred fifty-second 32-bits of PCIE type 0 config space 4862 * (Ack Frequency Register) 4863 */ 4864union cvmx_pcieepx_cfg451 { 4865 uint32_t u32; 4866 struct cvmx_pcieepx_cfg451_s { 4867#ifdef __BIG_ENDIAN_BITFIELD 4868 uint32_t reserved_31_31 : 1; 4869 uint32_t easpml1 : 1; /**< Enter ASPM L1 without receive in L0s 4870 Allow core to enter ASPM L1 even when link partner did 4871 not go to L0s (receive is not in L0s). 4872 When not set, core goes to ASPM L1 only after idle period 4873 during which both receive and transmit are in L0s. */ 4874 uint32_t l1el : 3; /**< L1 Entrance Latency 4875 Values correspond to: 4876 o 000: 1 ms 4877 o 001: 2 ms 4878 o 010: 4 ms 4879 o 011: 8 ms 4880 o 100: 16 ms 4881 o 101: 32 ms 4882 o 110 or 111: 64 ms */ 4883 uint32_t l0el : 3; /**< L0s Entrance Latency 4884 Values correspond to: 4885 o 000: 1 ms 4886 o 001: 2 ms 4887 o 010: 3 ms 4888 o 011: 4 ms 4889 o 100: 5 ms 4890 o 101: 6 ms 4891 o 110 or 111: 7 ms */ 4892 uint32_t n_fts_cc : 8; /**< N_FTS when common clock is used. 4893 The number of Fast Training Sequence ordered sets to be 4894 transmitted when transitioning from L0s to L0. The maximum 4895 number of FTS ordered-sets that a component can request is 255. 4896 Note: A value of zero is not supported; a value of 4897 zero can cause the LTSSM to go into the recovery state 4898 when exiting from L0s. */ 4899 uint32_t n_fts : 8; /**< N_FTS 4900 The number of Fast Training Sequence ordered sets to be 4901 transmitted when transitioning from L0s to L0. The maximum 4902 number of FTS ordered-sets that a component can request is 255. 4903 Note: A value of zero is not supported; a value of 4904 zero can cause the LTSSM to go into the recovery state 4905 when exiting from L0s. */ 4906 uint32_t ack_freq : 8; /**< Ack Frequency 4907 The number of pending Ack's specified here (up to 255) before 4908 sending an Ack. */ 4909#else 4910 uint32_t ack_freq : 8; 4911 uint32_t n_fts : 8; 4912 uint32_t n_fts_cc : 8; 4913 uint32_t l0el : 3; 4914 uint32_t l1el : 3; 4915 uint32_t easpml1 : 1; 4916 uint32_t reserved_31_31 : 1; 4917#endif 4918 } s; 4919 struct cvmx_pcieepx_cfg451_cn52xx { 4920#ifdef __BIG_ENDIAN_BITFIELD 4921 uint32_t reserved_30_31 : 2; 4922 uint32_t l1el : 3; /**< L1 Entrance Latency 4923 Values correspond to: 4924 o 000: 1 ms 4925 o 001: 2 ms 4926 o 010: 4 ms 4927 o 011: 8 ms 4928 o 100: 16 ms 4929 o 101: 32 ms 4930 o 110 or 111: 64 ms */ 4931 uint32_t l0el : 3; /**< L0s Entrance Latency 4932 Values correspond to: 4933 o 000: 1 ms 4934 o 001: 2 ms 4935 o 010: 3 ms 4936 o 011: 4 ms 4937 o 100: 5 ms 4938 o 101: 6 ms 4939 o 110 or 111: 7 ms */ 4940 uint32_t n_fts_cc : 8; /**< N_FTS when common clock is used. 4941 The number of Fast Training Sequence ordered sets to be 4942 transmitted when transitioning from L0s to L0. The maximum 4943 number of FTS ordered-sets that a component can request is 255. 4944 Note: A value of zero is not supported; a value of 4945 zero can cause the LTSSM to go into the recovery state 4946 when exiting from L0s. */ 4947 uint32_t n_fts : 8; /**< N_FTS 4948 The number of Fast Training Sequence ordered sets to be 4949 transmitted when transitioning from L0s to L0. The maximum 4950 number of FTS ordered-sets that a component can request is 255. 4951 Note: A value of zero is not supported; a value of 4952 zero can cause the LTSSM to go into the recovery state 4953 when exiting from L0s. */ 4954 uint32_t ack_freq : 8; /**< Ack Frequency 4955 The number of pending Ack's specified here (up to 255) before 4956 sending an Ack. */ 4957#else 4958 uint32_t ack_freq : 8; 4959 uint32_t n_fts : 8; 4960 uint32_t n_fts_cc : 8; 4961 uint32_t l0el : 3; 4962 uint32_t l1el : 3; 4963 uint32_t reserved_30_31 : 2; 4964#endif 4965 } cn52xx; 4966 struct cvmx_pcieepx_cfg451_cn52xx cn52xxp1; 4967 struct cvmx_pcieepx_cfg451_cn52xx cn56xx; 4968 struct cvmx_pcieepx_cfg451_cn52xx cn56xxp1; 4969 struct cvmx_pcieepx_cfg451_s cn61xx; 4970 struct cvmx_pcieepx_cfg451_cn52xx cn63xx; 4971 struct cvmx_pcieepx_cfg451_cn52xx cn63xxp1; 4972 struct cvmx_pcieepx_cfg451_s cn66xx; 4973 struct cvmx_pcieepx_cfg451_s cn68xx; 4974 struct cvmx_pcieepx_cfg451_s cn68xxp1; 4975 struct cvmx_pcieepx_cfg451_s cnf71xx; 4976}; 4977typedef union cvmx_pcieepx_cfg451 cvmx_pcieepx_cfg451_t; 4978 4979/** 4980 * cvmx_pcieep#_cfg452 4981 * 4982 * PCIE_CFG452 = Four hundred fifty-third 32-bits of PCIE type 0 config space 4983 * (Port Link Control Register) 4984 */ 4985union cvmx_pcieepx_cfg452 { 4986 uint32_t u32; 4987 struct cvmx_pcieepx_cfg452_s { 4988#ifdef __BIG_ENDIAN_BITFIELD 4989 uint32_t reserved_26_31 : 6; 4990 uint32_t eccrc : 1; /**< Enable Corrupted CRC 4991 Causes corrupt LCRC for TLPs when set, 4992 using the pattern contained in the Other Message register. 4993 This is a test feature, not to be used in normal operation. */ 4994 uint32_t reserved_22_24 : 3; 4995 uint32_t lme : 6; /**< Link Mode Enable 4996 o 000001: x1 4997 o 000011: x2 (not supported) 4998 o 000111: x4 (not supported) 4999 o 001111: x8 (not supported) 5000 o 011111: x16 (not supported) 5001 o 111111: x32 (not supported) 5002 This field indicates the MAXIMUM number of lanes supported 5003 by the PCIe port. 5004 See also MLW. 5005 (Note: The value of this field does NOT indicate the number 5006 of lanes in use by the PCIe. LME sets the max number of lanes 5007 in the PCIe core that COULD be used. As per the PCIe specs, 5008 the PCIe core can negotiate a smaller link width) */ 5009 uint32_t reserved_8_15 : 8; 5010 uint32_t flm : 1; /**< Fast Link Mode 5011 Sets all internal timers to fast mode for simulation purposes. 5012 If during an eeprom load, the first word loaded is 0xffffffff, 5013 then the EEPROM load will be terminated and this bit will be set. */ 5014 uint32_t reserved_6_6 : 1; 5015 uint32_t dllle : 1; /**< DLL Link Enable 5016 Enables Link initialization. If DLL Link Enable = 0, the PCI 5017 Express bus does not transmit InitFC DLLPs and does not 5018 establish a Link. */ 5019 uint32_t reserved_4_4 : 1; 5020 uint32_t ra : 1; /**< Reset Assert 5021 Triggers a recovery and forces the LTSSM to the Hot Reset 5022 state (downstream port only). */ 5023 uint32_t le : 1; /**< Loopback Enable 5024 Initiate loopback mode as a master. On a 0->1 transition, 5025 the PCIe core sends TS ordered sets with the loopback bit set 5026 to cause the link partner to enter into loopback mode as a 5027 slave. Normal transmission is not possible when LE=1. To exit 5028 loopback mode, take the link through a reset sequence. */ 5029 uint32_t sd : 1; /**< Scramble Disable 5030 Turns off data scrambling. */ 5031 uint32_t omr : 1; /**< Other Message Request 5032 When software writes a `1' to this bit, the PCI Express bus 5033 transmits the Message contained in the Other Message register. */ 5034#else 5035 uint32_t omr : 1; 5036 uint32_t sd : 1; 5037 uint32_t le : 1; 5038 uint32_t ra : 1; 5039 uint32_t reserved_4_4 : 1; 5040 uint32_t dllle : 1; 5041 uint32_t reserved_6_6 : 1; 5042 uint32_t flm : 1; 5043 uint32_t reserved_8_15 : 8; 5044 uint32_t lme : 6; 5045 uint32_t reserved_22_24 : 3; 5046 uint32_t eccrc : 1; 5047 uint32_t reserved_26_31 : 6; 5048#endif 5049 } s; 5050 struct cvmx_pcieepx_cfg452_s cn52xx; 5051 struct cvmx_pcieepx_cfg452_s cn52xxp1; 5052 struct cvmx_pcieepx_cfg452_s cn56xx; 5053 struct cvmx_pcieepx_cfg452_s cn56xxp1; 5054 struct cvmx_pcieepx_cfg452_cn61xx { 5055#ifdef __BIG_ENDIAN_BITFIELD 5056 uint32_t reserved_22_31 : 10; 5057 uint32_t lme : 6; /**< Link Mode Enable 5058 o 000001: x1 5059 o 000011: x2 5060 o 000111: x4 5061 o 001111: x8 (not supported) 5062 o 011111: x16 (not supported) 5063 o 111111: x32 (not supported) 5064 This field indicates the MAXIMUM number of lanes supported 5065 by the PCIe port. The value can be set less than 0x7 5066 to limit the number of lanes the PCIe will attempt to use. 5067 If the value of 0x7 set by the HW is not desired, 5068 this field can be programmed to a smaller value (i.e. EEPROM) 5069 See also MLW. 5070 (Note: The value of this field does NOT indicate the number 5071 of lanes in use by the PCIe. LME sets the max number of lanes 5072 in the PCIe core that COULD be used. As per the PCIe specs, 5073 the PCIe core can negotiate a smaller link width, so all 5074 of x4, x2, and x1 are supported when LME=0x7, 5075 for example.) */ 5076 uint32_t reserved_8_15 : 8; 5077 uint32_t flm : 1; /**< Fast Link Mode 5078 Sets all internal timers to fast mode for simulation purposes. 5079 If during an eeprom load, the first word loaded is 0xffffffff, 5080 then the EEPROM load will be terminated and this bit will be set. */ 5081 uint32_t reserved_6_6 : 1; 5082 uint32_t dllle : 1; /**< DLL Link Enable 5083 Enables Link initialization. If DLL Link Enable = 0, the PCI 5084 Express bus does not transmit InitFC DLLPs and does not 5085 establish a Link. */ 5086 uint32_t reserved_4_4 : 1; 5087 uint32_t ra : 1; /**< Reset Assert 5088 Triggers a recovery and forces the LTSSM to the Hot Reset 5089 state (downstream port only). */ 5090 uint32_t le : 1; /**< Loopback Enable 5091 Initiate loopback mode as a master. On a 0->1 transition, 5092 the PCIe core sends TS ordered sets with the loopback bit set 5093 to cause the link partner to enter into loopback mode as a 5094 slave. Normal transmission is not possible when LE=1. To exit 5095 loopback mode, take the link through a reset sequence. */ 5096 uint32_t sd : 1; /**< Scramble Disable 5097 Turns off data scrambling. */ 5098 uint32_t omr : 1; /**< Other Message Request 5099 When software writes a `1' to this bit, the PCI Express bus 5100 transmits the Message contained in the Other Message register. */ 5101#else 5102 uint32_t omr : 1; 5103 uint32_t sd : 1; 5104 uint32_t le : 1; 5105 uint32_t ra : 1; 5106 uint32_t reserved_4_4 : 1; 5107 uint32_t dllle : 1; 5108 uint32_t reserved_6_6 : 1; 5109 uint32_t flm : 1; 5110 uint32_t reserved_8_15 : 8; 5111 uint32_t lme : 6; 5112 uint32_t reserved_22_31 : 10; 5113#endif 5114 } cn61xx; 5115 struct cvmx_pcieepx_cfg452_s cn63xx; 5116 struct cvmx_pcieepx_cfg452_s cn63xxp1; 5117 struct cvmx_pcieepx_cfg452_cn61xx cn66xx; 5118 struct cvmx_pcieepx_cfg452_cn61xx cn68xx; 5119 struct cvmx_pcieepx_cfg452_cn61xx cn68xxp1; 5120 struct cvmx_pcieepx_cfg452_cn61xx cnf71xx; 5121}; 5122typedef union cvmx_pcieepx_cfg452 cvmx_pcieepx_cfg452_t; 5123 5124/** 5125 * cvmx_pcieep#_cfg453 5126 * 5127 * PCIE_CFG453 = Four hundred fifty-fourth 32-bits of PCIE type 0 config space 5128 * (Lane Skew Register) 5129 */ 5130union cvmx_pcieepx_cfg453 { 5131 uint32_t u32; 5132 struct cvmx_pcieepx_cfg453_s { 5133#ifdef __BIG_ENDIAN_BITFIELD 5134 uint32_t dlld : 1; /**< Disable Lane-to-Lane Deskew 5135 Disables the internal Lane-to-Lane deskew logic. */ 5136 uint32_t reserved_26_30 : 5; 5137 uint32_t ack_nak : 1; /**< Ack/Nak Disable 5138 Prevents the PCI Express bus from sending Ack and Nak DLLPs. */ 5139 uint32_t fcd : 1; /**< Flow Control Disable 5140 Prevents the PCI Express bus from sending FC DLLPs. */ 5141 uint32_t ilst : 24; /**< Insert Lane Skew for Transmit 5142 Causes skew between lanes for test purposes. There are three 5143 bits per Lane. The value is in units of one symbol time. For 5144 example, the value 010b for a Lane forces a skew of two symbol 5145 times for that Lane. The maximum skew value for any Lane is 5 5146 symbol times. */ 5147#else 5148 uint32_t ilst : 24; 5149 uint32_t fcd : 1; 5150 uint32_t ack_nak : 1; 5151 uint32_t reserved_26_30 : 5; 5152 uint32_t dlld : 1; 5153#endif 5154 } s; 5155 struct cvmx_pcieepx_cfg453_s cn52xx; 5156 struct cvmx_pcieepx_cfg453_s cn52xxp1; 5157 struct cvmx_pcieepx_cfg453_s cn56xx; 5158 struct cvmx_pcieepx_cfg453_s cn56xxp1; 5159 struct cvmx_pcieepx_cfg453_s cn61xx; 5160 struct cvmx_pcieepx_cfg453_s cn63xx; 5161 struct cvmx_pcieepx_cfg453_s cn63xxp1; 5162 struct cvmx_pcieepx_cfg453_s cn66xx; 5163 struct cvmx_pcieepx_cfg453_s cn68xx; 5164 struct cvmx_pcieepx_cfg453_s cn68xxp1; 5165 struct cvmx_pcieepx_cfg453_s cnf71xx; 5166}; 5167typedef union cvmx_pcieepx_cfg453 cvmx_pcieepx_cfg453_t; 5168 5169/** 5170 * cvmx_pcieep#_cfg454 5171 * 5172 * PCIE_CFG454 = Four hundred fifty-fifth 32-bits of PCIE type 0 config space 5173 * (Symbol Number Register) 5174 */ 5175union cvmx_pcieepx_cfg454 { 5176 uint32_t u32; 5177 struct cvmx_pcieepx_cfg454_s { 5178#ifdef __BIG_ENDIAN_BITFIELD 5179 uint32_t cx_nfunc : 3; /**< Number of Functions (minus 1) 5180 Configuration Requests targeted at function numbers above this 5181 value will be returned with unsupported request */ 5182 uint32_t tmfcwt : 5; /**< Timer Modifier for Flow Control Watchdog Timer 5183 Increases the timer value for the Flow Control watchdog timer, 5184 in increments of 16 clock cycles. */ 5185 uint32_t tmanlt : 5; /**< Timer Modifier for Ack/Nak Latency Timer 5186 Increases the timer value for the Ack/Nak latency timer, in 5187 increments of 64 clock cycles. */ 5188 uint32_t tmrt : 5; /**< Timer Modifier for Replay Timer 5189 Increases the timer value for the replay timer, in increments 5190 of 64 clock cycles. */ 5191 uint32_t reserved_11_13 : 3; 5192 uint32_t nskps : 3; /**< Number of SKP Symbols */ 5193 uint32_t reserved_0_7 : 8; 5194#else 5195 uint32_t reserved_0_7 : 8; 5196 uint32_t nskps : 3; 5197 uint32_t reserved_11_13 : 3; 5198 uint32_t tmrt : 5; 5199 uint32_t tmanlt : 5; 5200 uint32_t tmfcwt : 5; 5201 uint32_t cx_nfunc : 3; 5202#endif 5203 } s; 5204 struct cvmx_pcieepx_cfg454_cn52xx { 5205#ifdef __BIG_ENDIAN_BITFIELD 5206 uint32_t reserved_29_31 : 3; 5207 uint32_t tmfcwt : 5; /**< Timer Modifier for Flow Control Watchdog Timer 5208 Increases the timer value for the Flow Control watchdog timer, 5209 in increments of 16 clock cycles. */ 5210 uint32_t tmanlt : 5; /**< Timer Modifier for Ack/Nak Latency Timer 5211 Increases the timer value for the Ack/Nak latency timer, in 5212 increments of 64 clock cycles. */ 5213 uint32_t tmrt : 5; /**< Timer Modifier for Replay Timer 5214 Increases the timer value for the replay timer, in increments 5215 of 64 clock cycles. */ 5216 uint32_t reserved_11_13 : 3; 5217 uint32_t nskps : 3; /**< Number of SKP Symbols */ 5218 uint32_t reserved_4_7 : 4; 5219 uint32_t ntss : 4; /**< Number of TS Symbols 5220 Sets the number of TS identifier symbols that are sent in TS1 5221 and TS2 ordered sets. */ 5222#else 5223 uint32_t ntss : 4; 5224 uint32_t reserved_4_7 : 4; 5225 uint32_t nskps : 3; 5226 uint32_t reserved_11_13 : 3; 5227 uint32_t tmrt : 5; 5228 uint32_t tmanlt : 5; 5229 uint32_t tmfcwt : 5; 5230 uint32_t reserved_29_31 : 3; 5231#endif 5232 } cn52xx; 5233 struct cvmx_pcieepx_cfg454_cn52xx cn52xxp1; 5234 struct cvmx_pcieepx_cfg454_cn52xx cn56xx; 5235 struct cvmx_pcieepx_cfg454_cn52xx cn56xxp1; 5236 struct cvmx_pcieepx_cfg454_cn61xx { 5237#ifdef __BIG_ENDIAN_BITFIELD 5238 uint32_t cx_nfunc : 3; /**< Number of Functions (minus 1) 5239 Configuration Requests targeted at function numbers above this 5240 value will be returned with unsupported request */ 5241 uint32_t tmfcwt : 5; /**< Timer Modifier for Flow Control Watchdog Timer 5242 Increases the timer value for the Flow Control watchdog timer, 5243 in increments of 16 clock cycles. */ 5244 uint32_t tmanlt : 5; /**< Timer Modifier for Ack/Nak Latency Timer 5245 Increases the timer value for the Ack/Nak latency timer, in 5246 increments of 64 clock cycles. */ 5247 uint32_t tmrt : 5; /**< Timer Modifier for Replay Timer 5248 Increases the timer value for the replay timer, in increments 5249 of 64 clock cycles. */ 5250 uint32_t reserved_8_13 : 6; 5251 uint32_t mfuncn : 8; /**< Max Number of Functions Supported */ 5252#else 5253 uint32_t mfuncn : 8; 5254 uint32_t reserved_8_13 : 6; 5255 uint32_t tmrt : 5; 5256 uint32_t tmanlt : 5; 5257 uint32_t tmfcwt : 5; 5258 uint32_t cx_nfunc : 3; 5259#endif 5260 } cn61xx; 5261 struct cvmx_pcieepx_cfg454_cn52xx cn63xx; 5262 struct cvmx_pcieepx_cfg454_cn52xx cn63xxp1; 5263 struct cvmx_pcieepx_cfg454_cn61xx cn66xx; 5264 struct cvmx_pcieepx_cfg454_cn61xx cn68xx; 5265 struct cvmx_pcieepx_cfg454_cn52xx cn68xxp1; 5266 struct cvmx_pcieepx_cfg454_cn61xx cnf71xx; 5267}; 5268typedef union cvmx_pcieepx_cfg454 cvmx_pcieepx_cfg454_t; 5269 5270/** 5271 * cvmx_pcieep#_cfg455 5272 * 5273 * PCIE_CFG455 = Four hundred fifty-sixth 32-bits of PCIE type 0 config space 5274 * (Symbol Timer Register/Filter Mask Register 1) 5275 */ 5276union cvmx_pcieepx_cfg455 { 5277 uint32_t u32; 5278 struct cvmx_pcieepx_cfg455_s { 5279#ifdef __BIG_ENDIAN_BITFIELD 5280 uint32_t m_cfg0_filt : 1; /**< Mask filtering of received Configuration Requests (RC mode only) */ 5281 uint32_t m_io_filt : 1; /**< Mask filtering of received I/O Requests (RC mode only) */ 5282 uint32_t msg_ctrl : 1; /**< Message Control 5283 The application must not change this field. */ 5284 uint32_t m_cpl_ecrc_filt : 1; /**< Mask ECRC error filtering for Completions */ 5285 uint32_t m_ecrc_filt : 1; /**< Mask ECRC error filtering */ 5286 uint32_t m_cpl_len_err : 1; /**< Mask Length mismatch error for received Completions */ 5287 uint32_t m_cpl_attr_err : 1; /**< Mask Attributes mismatch error for received Completions */ 5288 uint32_t m_cpl_tc_err : 1; /**< Mask Traffic Class mismatch error for received Completions */ 5289 uint32_t m_cpl_fun_err : 1; /**< Mask function mismatch error for received Completions */ 5290 uint32_t m_cpl_rid_err : 1; /**< Mask Requester ID mismatch error for received Completions */ 5291 uint32_t m_cpl_tag_err : 1; /**< Mask Tag error rules for received Completions */ 5292 uint32_t m_lk_filt : 1; /**< Mask Locked Request filtering */ 5293 uint32_t m_cfg1_filt : 1; /**< Mask Type 1 Configuration Request filtering */ 5294 uint32_t m_bar_match : 1; /**< Mask BAR match filtering */ 5295 uint32_t m_pois_filt : 1; /**< Mask poisoned TLP filtering */ 5296 uint32_t m_fun : 1; /**< Mask function */ 5297 uint32_t dfcwt : 1; /**< Disable FC Watchdog Timer */ 5298 uint32_t reserved_11_14 : 4; 5299 uint32_t skpiv : 11; /**< SKP Interval Value */ 5300#else 5301 uint32_t skpiv : 11; 5302 uint32_t reserved_11_14 : 4; 5303 uint32_t dfcwt : 1; 5304 uint32_t m_fun : 1; 5305 uint32_t m_pois_filt : 1; 5306 uint32_t m_bar_match : 1; 5307 uint32_t m_cfg1_filt : 1; 5308 uint32_t m_lk_filt : 1; 5309 uint32_t m_cpl_tag_err : 1; 5310 uint32_t m_cpl_rid_err : 1; 5311 uint32_t m_cpl_fun_err : 1; 5312 uint32_t m_cpl_tc_err : 1; 5313 uint32_t m_cpl_attr_err : 1; 5314 uint32_t m_cpl_len_err : 1; 5315 uint32_t m_ecrc_filt : 1; 5316 uint32_t m_cpl_ecrc_filt : 1; 5317 uint32_t msg_ctrl : 1; 5318 uint32_t m_io_filt : 1; 5319 uint32_t m_cfg0_filt : 1; 5320#endif 5321 } s; 5322 struct cvmx_pcieepx_cfg455_s cn52xx; 5323 struct cvmx_pcieepx_cfg455_s cn52xxp1; 5324 struct cvmx_pcieepx_cfg455_s cn56xx; 5325 struct cvmx_pcieepx_cfg455_s cn56xxp1; 5326 struct cvmx_pcieepx_cfg455_s cn61xx; 5327 struct cvmx_pcieepx_cfg455_s cn63xx; 5328 struct cvmx_pcieepx_cfg455_s cn63xxp1; 5329 struct cvmx_pcieepx_cfg455_s cn66xx; 5330 struct cvmx_pcieepx_cfg455_s cn68xx; 5331 struct cvmx_pcieepx_cfg455_s cn68xxp1; 5332 struct cvmx_pcieepx_cfg455_s cnf71xx; 5333}; 5334typedef union cvmx_pcieepx_cfg455 cvmx_pcieepx_cfg455_t; 5335 5336/** 5337 * cvmx_pcieep#_cfg456 5338 * 5339 * PCIE_CFG456 = Four hundred fifty-seventh 32-bits of PCIE type 0 config space 5340 * (Filter Mask Register 2) 5341 */ 5342union cvmx_pcieepx_cfg456 { 5343 uint32_t u32; 5344 struct cvmx_pcieepx_cfg456_s { 5345#ifdef __BIG_ENDIAN_BITFIELD 5346 uint32_t reserved_4_31 : 28; 5347 uint32_t m_handle_flush : 1; /**< Mask Core Filter to handle flush request */ 5348 uint32_t m_dabort_4ucpl : 1; /**< Mask DLLP abort for unexpected CPL */ 5349 uint32_t m_vend1_drp : 1; /**< Mask Vendor MSG Type 1 dropped silently */ 5350 uint32_t m_vend0_drp : 1; /**< Mask Vendor MSG Type 0 dropped with UR error reporting. */ 5351#else 5352 uint32_t m_vend0_drp : 1; 5353 uint32_t m_vend1_drp : 1; 5354 uint32_t m_dabort_4ucpl : 1; 5355 uint32_t m_handle_flush : 1; 5356 uint32_t reserved_4_31 : 28; 5357#endif 5358 } s; 5359 struct cvmx_pcieepx_cfg456_cn52xx { 5360#ifdef __BIG_ENDIAN_BITFIELD 5361 uint32_t reserved_2_31 : 30; 5362 uint32_t m_vend1_drp : 1; /**< Mask Vendor MSG Type 1 dropped silently */ 5363 uint32_t m_vend0_drp : 1; /**< Mask Vendor MSG Type 0 dropped with UR error reporting. */ 5364#else 5365 uint32_t m_vend0_drp : 1; 5366 uint32_t m_vend1_drp : 1; 5367 uint32_t reserved_2_31 : 30; 5368#endif 5369 } cn52xx; 5370 struct cvmx_pcieepx_cfg456_cn52xx cn52xxp1; 5371 struct cvmx_pcieepx_cfg456_cn52xx cn56xx; 5372 struct cvmx_pcieepx_cfg456_cn52xx cn56xxp1; 5373 struct cvmx_pcieepx_cfg456_s cn61xx; 5374 struct cvmx_pcieepx_cfg456_cn52xx cn63xx; 5375 struct cvmx_pcieepx_cfg456_cn52xx cn63xxp1; 5376 struct cvmx_pcieepx_cfg456_s cn66xx; 5377 struct cvmx_pcieepx_cfg456_s cn68xx; 5378 struct cvmx_pcieepx_cfg456_cn52xx cn68xxp1; 5379 struct cvmx_pcieepx_cfg456_s cnf71xx; 5380}; 5381typedef union cvmx_pcieepx_cfg456 cvmx_pcieepx_cfg456_t; 5382 5383/** 5384 * cvmx_pcieep#_cfg458 5385 * 5386 * PCIE_CFG458 = Four hundred fifty-ninth 32-bits of PCIE type 0 config space 5387 * (Debug Register 0) 5388 */ 5389union cvmx_pcieepx_cfg458 { 5390 uint32_t u32; 5391 struct cvmx_pcieepx_cfg458_s { 5392#ifdef __BIG_ENDIAN_BITFIELD 5393 uint32_t dbg_info_l32 : 32; /**< Debug Info Lower 32 Bits */ 5394#else 5395 uint32_t dbg_info_l32 : 32; 5396#endif 5397 } s; 5398 struct cvmx_pcieepx_cfg458_s cn52xx; 5399 struct cvmx_pcieepx_cfg458_s cn52xxp1; 5400 struct cvmx_pcieepx_cfg458_s cn56xx; 5401 struct cvmx_pcieepx_cfg458_s cn56xxp1; 5402 struct cvmx_pcieepx_cfg458_s cn61xx; 5403 struct cvmx_pcieepx_cfg458_s cn63xx; 5404 struct cvmx_pcieepx_cfg458_s cn63xxp1; 5405 struct cvmx_pcieepx_cfg458_s cn66xx; 5406 struct cvmx_pcieepx_cfg458_s cn68xx; 5407 struct cvmx_pcieepx_cfg458_s cn68xxp1; 5408 struct cvmx_pcieepx_cfg458_s cnf71xx; 5409}; 5410typedef union cvmx_pcieepx_cfg458 cvmx_pcieepx_cfg458_t; 5411 5412/** 5413 * cvmx_pcieep#_cfg459 5414 * 5415 * PCIE_CFG459 = Four hundred sixtieth 32-bits of PCIE type 0 config space 5416 * (Debug Register 1) 5417 */ 5418union cvmx_pcieepx_cfg459 { 5419 uint32_t u32; 5420 struct cvmx_pcieepx_cfg459_s { 5421#ifdef __BIG_ENDIAN_BITFIELD 5422 uint32_t dbg_info_u32 : 32; /**< Debug Info Upper 32 Bits */ 5423#else 5424 uint32_t dbg_info_u32 : 32; 5425#endif 5426 } s; 5427 struct cvmx_pcieepx_cfg459_s cn52xx; 5428 struct cvmx_pcieepx_cfg459_s cn52xxp1; 5429 struct cvmx_pcieepx_cfg459_s cn56xx; 5430 struct cvmx_pcieepx_cfg459_s cn56xxp1; 5431 struct cvmx_pcieepx_cfg459_s cn61xx; 5432 struct cvmx_pcieepx_cfg459_s cn63xx; 5433 struct cvmx_pcieepx_cfg459_s cn63xxp1; 5434 struct cvmx_pcieepx_cfg459_s cn66xx; 5435 struct cvmx_pcieepx_cfg459_s cn68xx; 5436 struct cvmx_pcieepx_cfg459_s cn68xxp1; 5437 struct cvmx_pcieepx_cfg459_s cnf71xx; 5438}; 5439typedef union cvmx_pcieepx_cfg459 cvmx_pcieepx_cfg459_t; 5440 5441/** 5442 * cvmx_pcieep#_cfg460 5443 * 5444 * PCIE_CFG460 = Four hundred sixty-first 32-bits of PCIE type 0 config space 5445 * (Transmit Posted FC Credit Status) 5446 */ 5447union cvmx_pcieepx_cfg460 { 5448 uint32_t u32; 5449 struct cvmx_pcieepx_cfg460_s { 5450#ifdef __BIG_ENDIAN_BITFIELD 5451 uint32_t reserved_20_31 : 12; 5452 uint32_t tphfcc : 8; /**< Transmit Posted Header FC Credits 5453 The Posted Header credits advertised by the receiver at the 5454 other end of the Link, updated with each UpdateFC DLLP. */ 5455 uint32_t tpdfcc : 12; /**< Transmit Posted Data FC Credits 5456 The Posted Data credits advertised by the receiver at the other 5457 end of the Link, updated with each UpdateFC DLLP. */ 5458#else 5459 uint32_t tpdfcc : 12; 5460 uint32_t tphfcc : 8; 5461 uint32_t reserved_20_31 : 12; 5462#endif 5463 } s; 5464 struct cvmx_pcieepx_cfg460_s cn52xx; 5465 struct cvmx_pcieepx_cfg460_s cn52xxp1; 5466 struct cvmx_pcieepx_cfg460_s cn56xx; 5467 struct cvmx_pcieepx_cfg460_s cn56xxp1; 5468 struct cvmx_pcieepx_cfg460_s cn61xx; 5469 struct cvmx_pcieepx_cfg460_s cn63xx; 5470 struct cvmx_pcieepx_cfg460_s cn63xxp1; 5471 struct cvmx_pcieepx_cfg460_s cn66xx; 5472 struct cvmx_pcieepx_cfg460_s cn68xx; 5473 struct cvmx_pcieepx_cfg460_s cn68xxp1; 5474 struct cvmx_pcieepx_cfg460_s cnf71xx; 5475}; 5476typedef union cvmx_pcieepx_cfg460 cvmx_pcieepx_cfg460_t; 5477 5478/** 5479 * cvmx_pcieep#_cfg461 5480 * 5481 * PCIE_CFG461 = Four hundred sixty-second 32-bits of PCIE type 0 config space 5482 * (Transmit Non-Posted FC Credit Status) 5483 */ 5484union cvmx_pcieepx_cfg461 { 5485 uint32_t u32; 5486 struct cvmx_pcieepx_cfg461_s { 5487#ifdef __BIG_ENDIAN_BITFIELD 5488 uint32_t reserved_20_31 : 12; 5489 uint32_t tchfcc : 8; /**< Transmit Non-Posted Header FC Credits 5490 The Non-Posted Header credits advertised by the receiver at the 5491 other end of the Link, updated with each UpdateFC DLLP. */ 5492 uint32_t tcdfcc : 12; /**< Transmit Non-Posted Data FC Credits 5493 The Non-Posted Data credits advertised by the receiver at the 5494 other end of the Link, updated with each UpdateFC DLLP. */ 5495#else 5496 uint32_t tcdfcc : 12; 5497 uint32_t tchfcc : 8; 5498 uint32_t reserved_20_31 : 12; 5499#endif 5500 } s; 5501 struct cvmx_pcieepx_cfg461_s cn52xx; 5502 struct cvmx_pcieepx_cfg461_s cn52xxp1; 5503 struct cvmx_pcieepx_cfg461_s cn56xx; 5504 struct cvmx_pcieepx_cfg461_s cn56xxp1; 5505 struct cvmx_pcieepx_cfg461_s cn61xx; 5506 struct cvmx_pcieepx_cfg461_s cn63xx; 5507 struct cvmx_pcieepx_cfg461_s cn63xxp1; 5508 struct cvmx_pcieepx_cfg461_s cn66xx; 5509 struct cvmx_pcieepx_cfg461_s cn68xx; 5510 struct cvmx_pcieepx_cfg461_s cn68xxp1; 5511 struct cvmx_pcieepx_cfg461_s cnf71xx; 5512}; 5513typedef union cvmx_pcieepx_cfg461 cvmx_pcieepx_cfg461_t; 5514 5515/** 5516 * cvmx_pcieep#_cfg462 5517 * 5518 * PCIE_CFG462 = Four hundred sixty-third 32-bits of PCIE type 0 config space 5519 * (Transmit Completion FC Credit Status ) 5520 */ 5521union cvmx_pcieepx_cfg462 { 5522 uint32_t u32; 5523 struct cvmx_pcieepx_cfg462_s { 5524#ifdef __BIG_ENDIAN_BITFIELD 5525 uint32_t reserved_20_31 : 12; 5526 uint32_t tchfcc : 8; /**< Transmit Completion Header FC Credits 5527 The Completion Header credits advertised by the receiver at the 5528 other end of the Link, updated with each UpdateFC DLLP. */ 5529 uint32_t tcdfcc : 12; /**< Transmit Completion Data FC Credits 5530 The Completion Data credits advertised by the receiver at the 5531 other end of the Link, updated with each UpdateFC DLLP. */ 5532#else 5533 uint32_t tcdfcc : 12; 5534 uint32_t tchfcc : 8; 5535 uint32_t reserved_20_31 : 12; 5536#endif 5537 } s; 5538 struct cvmx_pcieepx_cfg462_s cn52xx; 5539 struct cvmx_pcieepx_cfg462_s cn52xxp1; 5540 struct cvmx_pcieepx_cfg462_s cn56xx; 5541 struct cvmx_pcieepx_cfg462_s cn56xxp1; 5542 struct cvmx_pcieepx_cfg462_s cn61xx; 5543 struct cvmx_pcieepx_cfg462_s cn63xx; 5544 struct cvmx_pcieepx_cfg462_s cn63xxp1; 5545 struct cvmx_pcieepx_cfg462_s cn66xx; 5546 struct cvmx_pcieepx_cfg462_s cn68xx; 5547 struct cvmx_pcieepx_cfg462_s cn68xxp1; 5548 struct cvmx_pcieepx_cfg462_s cnf71xx; 5549}; 5550typedef union cvmx_pcieepx_cfg462 cvmx_pcieepx_cfg462_t; 5551 5552/** 5553 * cvmx_pcieep#_cfg463 5554 * 5555 * PCIE_CFG463 = Four hundred sixty-fourth 32-bits of PCIE type 0 config space 5556 * (Queue Status) 5557 */ 5558union cvmx_pcieepx_cfg463 { 5559 uint32_t u32; 5560 struct cvmx_pcieepx_cfg463_s { 5561#ifdef __BIG_ENDIAN_BITFIELD 5562 uint32_t reserved_3_31 : 29; 5563 uint32_t rqne : 1; /**< Received Queue Not Empty 5564 Indicates there is data in one or more of the receive buffers. */ 5565 uint32_t trbne : 1; /**< Transmit Retry Buffer Not Empty 5566 Indicates that there is data in the transmit retry buffer. */ 5567 uint32_t rtlpfccnr : 1; /**< Received TLP FC Credits Not Returned 5568 Indicates that the PCI Express bus has sent a TLP but has not 5569 yet received an UpdateFC DLLP indicating that the credits for 5570 that TLP have been restored by the receiver at the other end of 5571 the Link. */ 5572#else 5573 uint32_t rtlpfccnr : 1; 5574 uint32_t trbne : 1; 5575 uint32_t rqne : 1; 5576 uint32_t reserved_3_31 : 29; 5577#endif 5578 } s; 5579 struct cvmx_pcieepx_cfg463_s cn52xx; 5580 struct cvmx_pcieepx_cfg463_s cn52xxp1; 5581 struct cvmx_pcieepx_cfg463_s cn56xx; 5582 struct cvmx_pcieepx_cfg463_s cn56xxp1; 5583 struct cvmx_pcieepx_cfg463_s cn61xx; 5584 struct cvmx_pcieepx_cfg463_s cn63xx; 5585 struct cvmx_pcieepx_cfg463_s cn63xxp1; 5586 struct cvmx_pcieepx_cfg463_s cn66xx; 5587 struct cvmx_pcieepx_cfg463_s cn68xx; 5588 struct cvmx_pcieepx_cfg463_s cn68xxp1; 5589 struct cvmx_pcieepx_cfg463_s cnf71xx; 5590}; 5591typedef union cvmx_pcieepx_cfg463 cvmx_pcieepx_cfg463_t; 5592 5593/** 5594 * cvmx_pcieep#_cfg464 5595 * 5596 * PCIE_CFG464 = Four hundred sixty-fifth 32-bits of PCIE type 0 config space 5597 * (VC Transmit Arbitration Register 1) 5598 */ 5599union cvmx_pcieepx_cfg464 { 5600 uint32_t u32; 5601 struct cvmx_pcieepx_cfg464_s { 5602#ifdef __BIG_ENDIAN_BITFIELD 5603 uint32_t wrr_vc3 : 8; /**< WRR Weight for VC3 */ 5604 uint32_t wrr_vc2 : 8; /**< WRR Weight for VC2 */ 5605 uint32_t wrr_vc1 : 8; /**< WRR Weight for VC1 */ 5606 uint32_t wrr_vc0 : 8; /**< WRR Weight for VC0 */ 5607#else 5608 uint32_t wrr_vc0 : 8; 5609 uint32_t wrr_vc1 : 8; 5610 uint32_t wrr_vc2 : 8; 5611 uint32_t wrr_vc3 : 8; 5612#endif 5613 } s; 5614 struct cvmx_pcieepx_cfg464_s cn52xx; 5615 struct cvmx_pcieepx_cfg464_s cn52xxp1; 5616 struct cvmx_pcieepx_cfg464_s cn56xx; 5617 struct cvmx_pcieepx_cfg464_s cn56xxp1; 5618 struct cvmx_pcieepx_cfg464_s cn61xx; 5619 struct cvmx_pcieepx_cfg464_s cn63xx; 5620 struct cvmx_pcieepx_cfg464_s cn63xxp1; 5621 struct cvmx_pcieepx_cfg464_s cn66xx; 5622 struct cvmx_pcieepx_cfg464_s cn68xx; 5623 struct cvmx_pcieepx_cfg464_s cn68xxp1; 5624 struct cvmx_pcieepx_cfg464_s cnf71xx; 5625}; 5626typedef union cvmx_pcieepx_cfg464 cvmx_pcieepx_cfg464_t; 5627 5628/** 5629 * cvmx_pcieep#_cfg465 5630 * 5631 * PCIE_CFG465 = Four hundred sixty-sixth 32-bits of PCIE type 0 config space 5632 * (VC Transmit Arbitration Register 2) 5633 */ 5634union cvmx_pcieepx_cfg465 { 5635 uint32_t u32; 5636 struct cvmx_pcieepx_cfg465_s { 5637#ifdef __BIG_ENDIAN_BITFIELD 5638 uint32_t wrr_vc7 : 8; /**< WRR Weight for VC7 */ 5639 uint32_t wrr_vc6 : 8; /**< WRR Weight for VC6 */ 5640 uint32_t wrr_vc5 : 8; /**< WRR Weight for VC5 */ 5641 uint32_t wrr_vc4 : 8; /**< WRR Weight for VC4 */ 5642#else 5643 uint32_t wrr_vc4 : 8; 5644 uint32_t wrr_vc5 : 8; 5645 uint32_t wrr_vc6 : 8; 5646 uint32_t wrr_vc7 : 8; 5647#endif 5648 } s; 5649 struct cvmx_pcieepx_cfg465_s cn52xx; 5650 struct cvmx_pcieepx_cfg465_s cn52xxp1; 5651 struct cvmx_pcieepx_cfg465_s cn56xx; 5652 struct cvmx_pcieepx_cfg465_s cn56xxp1; 5653 struct cvmx_pcieepx_cfg465_s cn61xx; 5654 struct cvmx_pcieepx_cfg465_s cn63xx; 5655 struct cvmx_pcieepx_cfg465_s cn63xxp1; 5656 struct cvmx_pcieepx_cfg465_s cn66xx; 5657 struct cvmx_pcieepx_cfg465_s cn68xx; 5658 struct cvmx_pcieepx_cfg465_s cn68xxp1; 5659 struct cvmx_pcieepx_cfg465_s cnf71xx; 5660}; 5661typedef union cvmx_pcieepx_cfg465 cvmx_pcieepx_cfg465_t; 5662 5663/** 5664 * cvmx_pcieep#_cfg466 5665 * 5666 * PCIE_CFG466 = Four hundred sixty-seventh 32-bits of PCIE type 0 config space 5667 * (VC0 Posted Receive Queue Control) 5668 */ 5669union cvmx_pcieepx_cfg466 { 5670 uint32_t u32; 5671 struct cvmx_pcieepx_cfg466_s { 5672#ifdef __BIG_ENDIAN_BITFIELD 5673 uint32_t rx_queue_order : 1; /**< VC Ordering for Receive Queues 5674 Determines the VC ordering rule for the receive queues, used 5675 only in the segmented-buffer configuration, 5676 writable through PEM(0..1)_CFG_WR: 5677 o 1: Strict ordering, higher numbered VCs have higher priority 5678 o 0: Round robin 5679 However, the application must not change this field. */ 5680 uint32_t type_ordering : 1; /**< TLP Type Ordering for VC0 5681 Determines the TLP type ordering rule for VC0 receive queues, 5682 used only in the segmented-buffer configuration, writable 5683 through PEM(0..1)_CFG_WR: 5684 o 1: Ordering of received TLPs follows the rules in 5685 PCI Express Base Specification 5686 o 0: Strict ordering for received TLPs: Posted, then 5687 Completion, then Non-Posted 5688 However, the application must not change this field. */ 5689 uint32_t reserved_24_29 : 6; 5690 uint32_t queue_mode : 3; /**< VC0 Posted TLP Queue Mode 5691 The operating mode of the Posted receive queue for VC0, used 5692 only in the segmented-buffer configuration, writable through 5693 PEM(0..1)_CFG_WR. 5694 However, the application must not change this field. 5695 Only one bit can be set at a time: 5696 o Bit 23: Bypass 5697 o Bit 22: Cut-through 5698 o Bit 21: Store-and-forward */ 5699 uint32_t reserved_20_20 : 1; 5700 uint32_t header_credits : 8; /**< VC0 Posted Header Credits 5701 The number of initial Posted header credits for VC0, used for 5702 all receive queue buffer configurations. 5703 This field is writable through PEM(0..1)_CFG_WR. 5704 However, the application must not change this field. */ 5705 uint32_t data_credits : 12; /**< VC0 Posted Data Credits 5706 The number of initial Posted data credits for VC0, used for all 5707 receive queue buffer configurations. 5708 This field is writable through PEM(0..1)_CFG_WR. 5709 However, the application must not change this field. */ 5710#else 5711 uint32_t data_credits : 12; 5712 uint32_t header_credits : 8; 5713 uint32_t reserved_20_20 : 1; 5714 uint32_t queue_mode : 3; 5715 uint32_t reserved_24_29 : 6; 5716 uint32_t type_ordering : 1; 5717 uint32_t rx_queue_order : 1; 5718#endif 5719 } s; 5720 struct cvmx_pcieepx_cfg466_s cn52xx; 5721 struct cvmx_pcieepx_cfg466_s cn52xxp1; 5722 struct cvmx_pcieepx_cfg466_s cn56xx; 5723 struct cvmx_pcieepx_cfg466_s cn56xxp1; 5724 struct cvmx_pcieepx_cfg466_s cn61xx; 5725 struct cvmx_pcieepx_cfg466_s cn63xx; 5726 struct cvmx_pcieepx_cfg466_s cn63xxp1; 5727 struct cvmx_pcieepx_cfg466_s cn66xx; 5728 struct cvmx_pcieepx_cfg466_s cn68xx; 5729 struct cvmx_pcieepx_cfg466_s cn68xxp1; 5730 struct cvmx_pcieepx_cfg466_s cnf71xx; 5731}; 5732typedef union cvmx_pcieepx_cfg466 cvmx_pcieepx_cfg466_t; 5733 5734/** 5735 * cvmx_pcieep#_cfg467 5736 * 5737 * PCIE_CFG467 = Four hundred sixty-eighth 32-bits of PCIE type 0 config space 5738 * (VC0 Non-Posted Receive Queue Control) 5739 */ 5740union cvmx_pcieepx_cfg467 { 5741 uint32_t u32; 5742 struct cvmx_pcieepx_cfg467_s { 5743#ifdef __BIG_ENDIAN_BITFIELD 5744 uint32_t reserved_24_31 : 8; 5745 uint32_t queue_mode : 3; /**< VC0 Non-Posted TLP Queue Mode 5746 The operating mode of the Non-Posted receive queue for VC0, 5747 used only in the segmented-buffer configuration, writable 5748 through PEM(0..1)_CFG_WR. 5749 Only one bit can be set at a time: 5750 o Bit 23: Bypass 5751 o Bit 22: Cut-through 5752 o Bit 21: Store-and-forward 5753 However, the application must not change this field. */ 5754 uint32_t reserved_20_20 : 1; 5755 uint32_t header_credits : 8; /**< VC0 Non-Posted Header Credits 5756 The number of initial Non-Posted header credits for VC0, used 5757 for all receive queue buffer configurations. 5758 This field is writable through PEM(0..1)_CFG_WR. 5759 However, the application must not change this field. */ 5760 uint32_t data_credits : 12; /**< VC0 Non-Posted Data Credits 5761 The number of initial Non-Posted data credits for VC0, used for 5762 all receive queue buffer configurations. 5763 This field is writable through PEM(0..1)_CFG_WR. 5764 However, the application must not change this field. */ 5765#else 5766 uint32_t data_credits : 12; 5767 uint32_t header_credits : 8; 5768 uint32_t reserved_20_20 : 1; 5769 uint32_t queue_mode : 3; 5770 uint32_t reserved_24_31 : 8; 5771#endif 5772 } s; 5773 struct cvmx_pcieepx_cfg467_s cn52xx; 5774 struct cvmx_pcieepx_cfg467_s cn52xxp1; 5775 struct cvmx_pcieepx_cfg467_s cn56xx; 5776 struct cvmx_pcieepx_cfg467_s cn56xxp1; 5777 struct cvmx_pcieepx_cfg467_s cn61xx; 5778 struct cvmx_pcieepx_cfg467_s cn63xx; 5779 struct cvmx_pcieepx_cfg467_s cn63xxp1; 5780 struct cvmx_pcieepx_cfg467_s cn66xx; 5781 struct cvmx_pcieepx_cfg467_s cn68xx; 5782 struct cvmx_pcieepx_cfg467_s cn68xxp1; 5783 struct cvmx_pcieepx_cfg467_s cnf71xx; 5784}; 5785typedef union cvmx_pcieepx_cfg467 cvmx_pcieepx_cfg467_t; 5786 5787/** 5788 * cvmx_pcieep#_cfg468 5789 * 5790 * PCIE_CFG468 = Four hundred sixty-ninth 32-bits of PCIE type 0 config space 5791 * (VC0 Completion Receive Queue Control) 5792 */ 5793union cvmx_pcieepx_cfg468 { 5794 uint32_t u32; 5795 struct cvmx_pcieepx_cfg468_s { 5796#ifdef __BIG_ENDIAN_BITFIELD 5797 uint32_t reserved_24_31 : 8; 5798 uint32_t queue_mode : 3; /**< VC0 Completion TLP Queue Mode 5799 The operating mode of the Completion receive queue for VC0, 5800 used only in the segmented-buffer configuration, writable 5801 through PEM(0..1)_CFG_WR. 5802 Only one bit can be set at a time: 5803 o Bit 23: Bypass 5804 o Bit 22: Cut-through 5805 o Bit 21: Store-and-forward 5806 However, the application must not change this field. */ 5807 uint32_t reserved_20_20 : 1; 5808 uint32_t header_credits : 8; /**< VC0 Completion Header Credits 5809 The number of initial Completion header credits for VC0, used 5810 for all receive queue buffer configurations. 5811 This field is writable through PEM(0..1)_CFG_WR. 5812 However, the application must not change this field. */ 5813 uint32_t data_credits : 12; /**< VC0 Completion Data Credits 5814 The number of initial Completion data credits for VC0, used for 5815 all receive queue buffer configurations. 5816 This field is writable through PEM(0..1)_CFG_WR. 5817 However, the application must not change this field. */ 5818#else 5819 uint32_t data_credits : 12; 5820 uint32_t header_credits : 8; 5821 uint32_t reserved_20_20 : 1; 5822 uint32_t queue_mode : 3; 5823 uint32_t reserved_24_31 : 8; 5824#endif 5825 } s; 5826 struct cvmx_pcieepx_cfg468_s cn52xx; 5827 struct cvmx_pcieepx_cfg468_s cn52xxp1; 5828 struct cvmx_pcieepx_cfg468_s cn56xx; 5829 struct cvmx_pcieepx_cfg468_s cn56xxp1; 5830 struct cvmx_pcieepx_cfg468_s cn61xx; 5831 struct cvmx_pcieepx_cfg468_s cn63xx; 5832 struct cvmx_pcieepx_cfg468_s cn63xxp1; 5833 struct cvmx_pcieepx_cfg468_s cn66xx; 5834 struct cvmx_pcieepx_cfg468_s cn68xx; 5835 struct cvmx_pcieepx_cfg468_s cn68xxp1; 5836 struct cvmx_pcieepx_cfg468_s cnf71xx; 5837}; 5838typedef union cvmx_pcieepx_cfg468 cvmx_pcieepx_cfg468_t; 5839 5840/** 5841 * cvmx_pcieep#_cfg490 5842 * 5843 * PCIE_CFG490 = Four hundred ninety-first 32-bits of PCIE type 0 config space 5844 * (VC0 Posted Buffer Depth) 5845 */ 5846union cvmx_pcieepx_cfg490 { 5847 uint32_t u32; 5848 struct cvmx_pcieepx_cfg490_s { 5849#ifdef __BIG_ENDIAN_BITFIELD 5850 uint32_t reserved_26_31 : 6; 5851 uint32_t header_depth : 10; /**< VC0 Posted Header Queue Depth 5852 Sets the number of entries in the Posted header queue for VC0 5853 when using the segmented-buffer configuration, writable through 5854 PEM(0..1)_CFG_WR. 5855 However, the application must not change this field. */ 5856 uint32_t reserved_14_15 : 2; 5857 uint32_t data_depth : 14; /**< VC0 Posted Data Queue Depth 5858 Sets the number of entries in the Posted data queue for VC0 5859 when using the segmented-buffer configuration, writable 5860 through PEM(0..1)_CFG_WR. 5861 However, the application must not change this field. */ 5862#else 5863 uint32_t data_depth : 14; 5864 uint32_t reserved_14_15 : 2; 5865 uint32_t header_depth : 10; 5866 uint32_t reserved_26_31 : 6; 5867#endif 5868 } s; 5869 struct cvmx_pcieepx_cfg490_s cn52xx; 5870 struct cvmx_pcieepx_cfg490_s cn52xxp1; 5871 struct cvmx_pcieepx_cfg490_s cn56xx; 5872 struct cvmx_pcieepx_cfg490_s cn56xxp1; 5873 struct cvmx_pcieepx_cfg490_s cn61xx; 5874 struct cvmx_pcieepx_cfg490_s cn63xx; 5875 struct cvmx_pcieepx_cfg490_s cn63xxp1; 5876 struct cvmx_pcieepx_cfg490_s cn66xx; 5877 struct cvmx_pcieepx_cfg490_s cn68xx; 5878 struct cvmx_pcieepx_cfg490_s cn68xxp1; 5879 struct cvmx_pcieepx_cfg490_s cnf71xx; 5880}; 5881typedef union cvmx_pcieepx_cfg490 cvmx_pcieepx_cfg490_t; 5882 5883/** 5884 * cvmx_pcieep#_cfg491 5885 * 5886 * PCIE_CFG491 = Four hundred ninety-second 32-bits of PCIE type 0 config space 5887 * (VC0 Non-Posted Buffer Depth) 5888 */ 5889union cvmx_pcieepx_cfg491 { 5890 uint32_t u32; 5891 struct cvmx_pcieepx_cfg491_s { 5892#ifdef __BIG_ENDIAN_BITFIELD 5893 uint32_t reserved_26_31 : 6; 5894 uint32_t header_depth : 10; /**< VC0 Non-Posted Header Queue Depth 5895 Sets the number of entries in the Non-Posted header queue for 5896 VC0 when using the segmented-buffer configuration, writable 5897 through PEM(0..1)_CFG_WR. 5898 However, the application must not change this field. */ 5899 uint32_t reserved_14_15 : 2; 5900 uint32_t data_depth : 14; /**< VC0 Non-Posted Data Queue Depth 5901 Sets the number of entries in the Non-Posted data queue for VC0 5902 when using the segmented-buffer configuration, writable 5903 through PEM(0..1)_CFG_WR. 5904 However, the application must not change this field. */ 5905#else 5906 uint32_t data_depth : 14; 5907 uint32_t reserved_14_15 : 2; 5908 uint32_t header_depth : 10; 5909 uint32_t reserved_26_31 : 6; 5910#endif 5911 } s; 5912 struct cvmx_pcieepx_cfg491_s cn52xx; 5913 struct cvmx_pcieepx_cfg491_s cn52xxp1; 5914 struct cvmx_pcieepx_cfg491_s cn56xx; 5915 struct cvmx_pcieepx_cfg491_s cn56xxp1; 5916 struct cvmx_pcieepx_cfg491_s cn61xx; 5917 struct cvmx_pcieepx_cfg491_s cn63xx; 5918 struct cvmx_pcieepx_cfg491_s cn63xxp1; 5919 struct cvmx_pcieepx_cfg491_s cn66xx; 5920 struct cvmx_pcieepx_cfg491_s cn68xx; 5921 struct cvmx_pcieepx_cfg491_s cn68xxp1; 5922 struct cvmx_pcieepx_cfg491_s cnf71xx; 5923}; 5924typedef union cvmx_pcieepx_cfg491 cvmx_pcieepx_cfg491_t; 5925 5926/** 5927 * cvmx_pcieep#_cfg492 5928 * 5929 * PCIE_CFG492 = Four hundred ninety-third 32-bits of PCIE type 0 config space 5930 * (VC0 Completion Buffer Depth) 5931 */ 5932union cvmx_pcieepx_cfg492 { 5933 uint32_t u32; 5934 struct cvmx_pcieepx_cfg492_s { 5935#ifdef __BIG_ENDIAN_BITFIELD 5936 uint32_t reserved_26_31 : 6; 5937 uint32_t header_depth : 10; /**< VC0 Completion Header Queue Depth 5938 Sets the number of entries in the Completion header queue for 5939 VC0 when using the segmented-buffer configuration, writable 5940 through PEM(0..1)_CFG_WR. 5941 However, the application must not change this field. */ 5942 uint32_t reserved_14_15 : 2; 5943 uint32_t data_depth : 14; /**< VC0 Completion Data Queue Depth 5944 Sets the number of entries in the Completion data queue for VC0 5945 when using the segmented-buffer configuration, writable 5946 through PEM(0..1)_CFG_WR. 5947 However, the application must not change this field. */ 5948#else 5949 uint32_t data_depth : 14; 5950 uint32_t reserved_14_15 : 2; 5951 uint32_t header_depth : 10; 5952 uint32_t reserved_26_31 : 6; 5953#endif 5954 } s; 5955 struct cvmx_pcieepx_cfg492_s cn52xx; 5956 struct cvmx_pcieepx_cfg492_s cn52xxp1; 5957 struct cvmx_pcieepx_cfg492_s cn56xx; 5958 struct cvmx_pcieepx_cfg492_s cn56xxp1; 5959 struct cvmx_pcieepx_cfg492_s cn61xx; 5960 struct cvmx_pcieepx_cfg492_s cn63xx; 5961 struct cvmx_pcieepx_cfg492_s cn63xxp1; 5962 struct cvmx_pcieepx_cfg492_s cn66xx; 5963 struct cvmx_pcieepx_cfg492_s cn68xx; 5964 struct cvmx_pcieepx_cfg492_s cn68xxp1; 5965 struct cvmx_pcieepx_cfg492_s cnf71xx; 5966}; 5967typedef union cvmx_pcieepx_cfg492 cvmx_pcieepx_cfg492_t; 5968 5969/** 5970 * cvmx_pcieep#_cfg515 5971 * 5972 * PCIE_CFG515 = Five hundred sixteenth 32-bits of PCIE type 0 config space 5973 * (Port Logic Register (Gen2)) 5974 */ 5975union cvmx_pcieepx_cfg515 { 5976 uint32_t u32; 5977 struct cvmx_pcieepx_cfg515_s { 5978#ifdef __BIG_ENDIAN_BITFIELD 5979 uint32_t reserved_21_31 : 11; 5980 uint32_t s_d_e : 1; /**< SEL_DE_EMPHASIS 5981 Used to set the de-emphasis level for upstream ports. */ 5982 uint32_t ctcrb : 1; /**< Config Tx Compliance Receive Bit 5983 When set to 1, signals LTSSM to transmit TS ordered sets 5984 with the compliance receive bit assert (equal to 1). */ 5985 uint32_t cpyts : 1; /**< Config PHY Tx Swing 5986 Indicates the voltage level the PHY should drive. When set to 5987 1, indicates Full Swing. When set to 0, indicates Low Swing */ 5988 uint32_t dsc : 1; /**< Directed Speed Change 5989 o a write of '1' will initiate a speed change 5990 o always reads a zero */ 5991 uint32_t le : 9; /**< Lane Enable 5992 Indicates the number of lanes to check for exit from electrical 5993 idle in Polling.Active and Polling.Compliance. 1 = x1, 2 = x2, 5994 etc. Used to limit the maximum link width to ignore broken 5995 lanes that detect a receiver, but will not exit electrical 5996 idle and 5997 would otherwise prevent a valid link from being configured. */ 5998 uint32_t n_fts : 8; /**< N_FTS 5999 Sets the Number of Fast Training Sequences (N_FTS) that 6000 the core advertises as its N_FTS during GEN2 Link training. 6001 This value is used to inform the Link partner about the PHYs 6002 ability to recover synchronization after a low power state. 6003 Note: Do not set N_FTS to zero; doing so can cause the 6004 LTSSM to go into the recovery state when exiting from 6005 L0s. */ 6006#else 6007 uint32_t n_fts : 8; 6008 uint32_t le : 9; 6009 uint32_t dsc : 1; 6010 uint32_t cpyts : 1; 6011 uint32_t ctcrb : 1; 6012 uint32_t s_d_e : 1; 6013 uint32_t reserved_21_31 : 11; 6014#endif 6015 } s; 6016 struct cvmx_pcieepx_cfg515_s cn61xx; 6017 struct cvmx_pcieepx_cfg515_s cn63xx; 6018 struct cvmx_pcieepx_cfg515_s cn63xxp1; 6019 struct cvmx_pcieepx_cfg515_s cn66xx; 6020 struct cvmx_pcieepx_cfg515_s cn68xx; 6021 struct cvmx_pcieepx_cfg515_s cn68xxp1; 6022 struct cvmx_pcieepx_cfg515_s cnf71xx; 6023}; 6024typedef union cvmx_pcieepx_cfg515 cvmx_pcieepx_cfg515_t; 6025 6026/** 6027 * cvmx_pcieep#_cfg516 6028 * 6029 * PCIE_CFG516 = Five hundred seventeenth 32-bits of PCIE type 0 config space 6030 * (PHY Status Register) 6031 */ 6032union cvmx_pcieepx_cfg516 { 6033 uint32_t u32; 6034 struct cvmx_pcieepx_cfg516_s { 6035#ifdef __BIG_ENDIAN_BITFIELD 6036 uint32_t phy_stat : 32; /**< PHY Status */ 6037#else 6038 uint32_t phy_stat : 32; 6039#endif 6040 } s; 6041 struct cvmx_pcieepx_cfg516_s cn52xx; 6042 struct cvmx_pcieepx_cfg516_s cn52xxp1; 6043 struct cvmx_pcieepx_cfg516_s cn56xx; 6044 struct cvmx_pcieepx_cfg516_s cn56xxp1; 6045 struct cvmx_pcieepx_cfg516_s cn61xx; 6046 struct cvmx_pcieepx_cfg516_s cn63xx; 6047 struct cvmx_pcieepx_cfg516_s cn63xxp1; 6048 struct cvmx_pcieepx_cfg516_s cn66xx; 6049 struct cvmx_pcieepx_cfg516_s cn68xx; 6050 struct cvmx_pcieepx_cfg516_s cn68xxp1; 6051 struct cvmx_pcieepx_cfg516_s cnf71xx; 6052}; 6053typedef union cvmx_pcieepx_cfg516 cvmx_pcieepx_cfg516_t; 6054 6055/** 6056 * cvmx_pcieep#_cfg517 6057 * 6058 * PCIE_CFG517 = Five hundred eighteenth 32-bits of PCIE type 0 config space 6059 * (PHY Control Register) 6060 */ 6061union cvmx_pcieepx_cfg517 { 6062 uint32_t u32; 6063 struct cvmx_pcieepx_cfg517_s { 6064#ifdef __BIG_ENDIAN_BITFIELD 6065 uint32_t phy_ctrl : 32; /**< PHY Control */ 6066#else 6067 uint32_t phy_ctrl : 32; 6068#endif 6069 } s; 6070 struct cvmx_pcieepx_cfg517_s cn52xx; 6071 struct cvmx_pcieepx_cfg517_s cn52xxp1; 6072 struct cvmx_pcieepx_cfg517_s cn56xx; 6073 struct cvmx_pcieepx_cfg517_s cn56xxp1; 6074 struct cvmx_pcieepx_cfg517_s cn61xx; 6075 struct cvmx_pcieepx_cfg517_s cn63xx; 6076 struct cvmx_pcieepx_cfg517_s cn63xxp1; 6077 struct cvmx_pcieepx_cfg517_s cn66xx; 6078 struct cvmx_pcieepx_cfg517_s cn68xx; 6079 struct cvmx_pcieepx_cfg517_s cn68xxp1; 6080 struct cvmx_pcieepx_cfg517_s cnf71xx; 6081}; 6082typedef union cvmx_pcieepx_cfg517 cvmx_pcieepx_cfg517_t; 6083 6084#endif 6085