1/*
2 * Copyright (c) 2007 The DragonFly Project.  All rights reserved.
3 *
4 * This code is derived from software contributed to The DragonFly Project
5 * by Sepherosa Ziehau <sepherosa@gmail.com>
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 *    notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 *    notice, this list of conditions and the following disclaimer in
15 *    the documentation and/or other materials provided with the
16 *    distribution.
17 * 3. Neither the name of The DragonFly Project nor the names of its
18 *    contributors may be used to endorse or promote products derived
19 *    from this software without specific, prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
24 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE
25 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
27 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
28 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
29 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 * SUCH DAMAGE.
33 *
34 * $DragonFly: src/sys/dev/netif/bwi/if_bwi.c,v 1.19 2008/02/15 11:15:38 sephe Exp $
35 */
36
37#include <sys/cdefs.h>
38__FBSDID("$FreeBSD: stable/11/sys/dev/bwi/if_bwi.c 345636 2019-03-28 09:50:25Z avos $");
39
40#include "opt_inet.h"
41#include "opt_bwi.h"
42#include "opt_wlan.h"
43
44#include <sys/param.h>
45#include <sys/endian.h>
46#include <sys/kernel.h>
47#include <sys/bus.h>
48#include <sys/malloc.h>
49#include <sys/proc.h>
50#include <sys/rman.h>
51#include <sys/socket.h>
52#include <sys/sockio.h>
53#include <sys/sysctl.h>
54#include <sys/systm.h>
55#include <sys/taskqueue.h>
56
57#include <net/if.h>
58#include <net/if_var.h>
59#include <net/if_dl.h>
60#include <net/if_media.h>
61#include <net/if_types.h>
62#include <net/if_arp.h>
63#include <net/ethernet.h>
64#include <net/if_llc.h>
65
66#include <net80211/ieee80211_var.h>
67#include <net80211/ieee80211_radiotap.h>
68#include <net80211/ieee80211_regdomain.h>
69#include <net80211/ieee80211_phy.h>
70#include <net80211/ieee80211_ratectl.h>
71
72#include <net/bpf.h>
73
74#ifdef INET
75#include <netinet/in.h>
76#include <netinet/if_ether.h>
77#endif
78
79#include <machine/bus.h>
80
81#include <dev/pci/pcivar.h>
82#include <dev/pci/pcireg.h>
83
84#include <dev/bwi/bitops.h>
85#include <dev/bwi/if_bwireg.h>
86#include <dev/bwi/if_bwivar.h>
87#include <dev/bwi/bwimac.h>
88#include <dev/bwi/bwirf.h>
89
90struct bwi_clock_freq {
91	u_int		clkfreq_min;
92	u_int		clkfreq_max;
93};
94
95struct bwi_myaddr_bssid {
96	uint8_t		myaddr[IEEE80211_ADDR_LEN];
97	uint8_t		bssid[IEEE80211_ADDR_LEN];
98} __packed;
99
100static struct ieee80211vap *bwi_vap_create(struct ieee80211com *,
101		    const char [IFNAMSIZ], int, enum ieee80211_opmode, int,
102		    const uint8_t [IEEE80211_ADDR_LEN],
103		    const uint8_t [IEEE80211_ADDR_LEN]);
104static void	bwi_vap_delete(struct ieee80211vap *);
105static void	bwi_init(struct bwi_softc *);
106static void	bwi_parent(struct ieee80211com *);
107static int	bwi_transmit(struct ieee80211com *, struct mbuf *);
108static void	bwi_start_locked(struct bwi_softc *);
109static int	bwi_raw_xmit(struct ieee80211_node *, struct mbuf *,
110			const struct ieee80211_bpf_params *);
111static void	bwi_watchdog(void *);
112static void	bwi_scan_start(struct ieee80211com *);
113static void	bwi_getradiocaps(struct ieee80211com *, int, int *,
114		    struct ieee80211_channel[]);
115static void	bwi_set_channel(struct ieee80211com *);
116static void	bwi_scan_end(struct ieee80211com *);
117static int	bwi_newstate(struct ieee80211vap *, enum ieee80211_state, int);
118static void	bwi_updateslot(struct ieee80211com *);
119static int	bwi_media_change(struct ifnet *);
120
121static void	bwi_calibrate(void *);
122
123static int	bwi_calc_rssi(struct bwi_softc *, const struct bwi_rxbuf_hdr *);
124static int	bwi_calc_noise(struct bwi_softc *);
125static __inline uint8_t bwi_plcp2rate(uint32_t, enum ieee80211_phytype);
126static void	bwi_rx_radiotap(struct bwi_softc *, struct mbuf *,
127			struct bwi_rxbuf_hdr *, const void *, int, int, int);
128
129static void	bwi_restart(void *, int);
130static void	bwi_init_statechg(struct bwi_softc *, int);
131static void	bwi_stop(struct bwi_softc *, int);
132static void	bwi_stop_locked(struct bwi_softc *, int);
133static int	bwi_newbuf(struct bwi_softc *, int, int);
134static int	bwi_encap(struct bwi_softc *, int, struct mbuf *,
135			  struct ieee80211_node *);
136static int	bwi_encap_raw(struct bwi_softc *, int, struct mbuf *,
137			  struct ieee80211_node *,
138			  const struct ieee80211_bpf_params *);
139
140static void	bwi_init_rxdesc_ring32(struct bwi_softc *, uint32_t,
141				       bus_addr_t, int, int);
142static void	bwi_reset_rx_ring32(struct bwi_softc *, uint32_t);
143
144static int	bwi_init_tx_ring32(struct bwi_softc *, int);
145static int	bwi_init_rx_ring32(struct bwi_softc *);
146static int	bwi_init_txstats32(struct bwi_softc *);
147static void	bwi_free_tx_ring32(struct bwi_softc *, int);
148static void	bwi_free_rx_ring32(struct bwi_softc *);
149static void	bwi_free_txstats32(struct bwi_softc *);
150static void	bwi_setup_rx_desc32(struct bwi_softc *, int, bus_addr_t, int);
151static void	bwi_setup_tx_desc32(struct bwi_softc *, struct bwi_ring_data *,
152				    int, bus_addr_t, int);
153static int	bwi_rxeof32(struct bwi_softc *);
154static void	bwi_start_tx32(struct bwi_softc *, uint32_t, int);
155static void	bwi_txeof_status32(struct bwi_softc *);
156
157static int	bwi_init_tx_ring64(struct bwi_softc *, int);
158static int	bwi_init_rx_ring64(struct bwi_softc *);
159static int	bwi_init_txstats64(struct bwi_softc *);
160static void	bwi_free_tx_ring64(struct bwi_softc *, int);
161static void	bwi_free_rx_ring64(struct bwi_softc *);
162static void	bwi_free_txstats64(struct bwi_softc *);
163static void	bwi_setup_rx_desc64(struct bwi_softc *, int, bus_addr_t, int);
164static void	bwi_setup_tx_desc64(struct bwi_softc *, struct bwi_ring_data *,
165				    int, bus_addr_t, int);
166static int	bwi_rxeof64(struct bwi_softc *);
167static void	bwi_start_tx64(struct bwi_softc *, uint32_t, int);
168static void	bwi_txeof_status64(struct bwi_softc *);
169
170static int	bwi_rxeof(struct bwi_softc *, int);
171static void	_bwi_txeof(struct bwi_softc *, uint16_t, int, int);
172static void	bwi_txeof(struct bwi_softc *);
173static void	bwi_txeof_status(struct bwi_softc *, int);
174static void	bwi_enable_intrs(struct bwi_softc *, uint32_t);
175static void	bwi_disable_intrs(struct bwi_softc *, uint32_t);
176
177static int	bwi_dma_alloc(struct bwi_softc *);
178static void	bwi_dma_free(struct bwi_softc *);
179static int	bwi_dma_ring_alloc(struct bwi_softc *, bus_dma_tag_t,
180				   struct bwi_ring_data *, bus_size_t,
181				   uint32_t);
182static int	bwi_dma_mbuf_create(struct bwi_softc *);
183static void	bwi_dma_mbuf_destroy(struct bwi_softc *, int, int);
184static int	bwi_dma_txstats_alloc(struct bwi_softc *, uint32_t, bus_size_t);
185static void	bwi_dma_txstats_free(struct bwi_softc *);
186static void	bwi_dma_ring_addr(void *, bus_dma_segment_t *, int, int);
187static void	bwi_dma_buf_addr(void *, bus_dma_segment_t *, int,
188				 bus_size_t, int);
189
190static void	bwi_power_on(struct bwi_softc *, int);
191static int	bwi_power_off(struct bwi_softc *, int);
192static int	bwi_set_clock_mode(struct bwi_softc *, enum bwi_clock_mode);
193static int	bwi_set_clock_delay(struct bwi_softc *);
194static void	bwi_get_clock_freq(struct bwi_softc *, struct bwi_clock_freq *);
195static int	bwi_get_pwron_delay(struct bwi_softc *sc);
196static void	bwi_set_addr_filter(struct bwi_softc *, uint16_t,
197				    const uint8_t *);
198static void	bwi_set_bssid(struct bwi_softc *, const uint8_t *);
199
200static void	bwi_get_card_flags(struct bwi_softc *);
201static void	bwi_get_eaddr(struct bwi_softc *, uint16_t, uint8_t *);
202
203static int	bwi_bus_attach(struct bwi_softc *);
204static int	bwi_bbp_attach(struct bwi_softc *);
205static int	bwi_bbp_power_on(struct bwi_softc *, enum bwi_clock_mode);
206static void	bwi_bbp_power_off(struct bwi_softc *);
207
208static const char *bwi_regwin_name(const struct bwi_regwin *);
209static uint32_t	bwi_regwin_disable_bits(struct bwi_softc *);
210static void	bwi_regwin_info(struct bwi_softc *, uint16_t *, uint8_t *);
211static int	bwi_regwin_select(struct bwi_softc *, int);
212
213static void	bwi_led_attach(struct bwi_softc *);
214static void	bwi_led_newstate(struct bwi_softc *, enum ieee80211_state);
215static void	bwi_led_event(struct bwi_softc *, int);
216static void	bwi_led_blink_start(struct bwi_softc *, int, int);
217static void	bwi_led_blink_next(void *);
218static void	bwi_led_blink_end(void *);
219
220static const struct {
221	uint16_t	did_min;
222	uint16_t	did_max;
223	uint16_t	bbp_id;
224} bwi_bbpid_map[] = {
225	{ 0x4301, 0x4301, 0x4301 },
226	{ 0x4305, 0x4307, 0x4307 },
227	{ 0x4402, 0x4403, 0x4402 },
228	{ 0x4610, 0x4615, 0x4610 },
229	{ 0x4710, 0x4715, 0x4710 },
230	{ 0x4720, 0x4725, 0x4309 }
231};
232
233static const struct {
234	uint16_t	bbp_id;
235	int		nregwin;
236} bwi_regwin_count[] = {
237	{ 0x4301, 5 },
238	{ 0x4306, 6 },
239	{ 0x4307, 5 },
240	{ 0x4310, 8 },
241	{ 0x4401, 3 },
242	{ 0x4402, 3 },
243	{ 0x4610, 9 },
244	{ 0x4704, 9 },
245	{ 0x4710, 9 },
246	{ 0x5365, 7 }
247};
248
249#define CLKSRC(src) 				\
250[BWI_CLKSRC_ ## src] = {			\
251	.freq_min = BWI_CLKSRC_ ##src## _FMIN,	\
252	.freq_max = BWI_CLKSRC_ ##src## _FMAX	\
253}
254
255static const struct {
256	u_int	freq_min;
257	u_int	freq_max;
258} bwi_clkfreq[BWI_CLKSRC_MAX] = {
259	CLKSRC(LP_OSC),
260	CLKSRC(CS_OSC),
261	CLKSRC(PCI)
262};
263
264#undef CLKSRC
265
266#define VENDOR_LED_ACT(vendor)				\
267{							\
268	.vid = PCI_VENDOR_##vendor,			\
269	.led_act = { BWI_VENDOR_LED_ACT_##vendor }	\
270}
271
272static const struct {
273#define	PCI_VENDOR_COMPAQ	0x0e11
274#define	PCI_VENDOR_LINKSYS	0x1737
275	uint16_t	vid;
276	uint8_t		led_act[BWI_LED_MAX];
277} bwi_vendor_led_act[] = {
278	VENDOR_LED_ACT(COMPAQ),
279	VENDOR_LED_ACT(LINKSYS)
280#undef PCI_VENDOR_LINKSYS
281#undef PCI_VENDOR_COMPAQ
282};
283
284static const uint8_t bwi_default_led_act[BWI_LED_MAX] =
285	{ BWI_VENDOR_LED_ACT_DEFAULT };
286
287#undef VENDOR_LED_ACT
288
289static const struct {
290	int	on_dur;
291	int	off_dur;
292} bwi_led_duration[109] = {
293	[0]	= { 400, 100 },
294	[2]	= { 150, 75 },
295	[4]	= { 90, 45 },
296	[11]	= { 66, 34 },
297	[12]	= { 53, 26 },
298	[18]	= { 42, 21 },
299	[22]	= { 35, 17 },
300	[24]	= { 32, 16 },
301	[36]	= { 21, 10 },
302	[48]	= { 16, 8 },
303	[72]	= { 11, 5 },
304	[96]	= { 9, 4 },
305	[108]	= { 7, 3 }
306};
307
308#ifdef BWI_DEBUG
309#ifdef BWI_DEBUG_VERBOSE
310static uint32_t bwi_debug = BWI_DBG_ATTACH | BWI_DBG_INIT | BWI_DBG_TXPOWER;
311#else
312static uint32_t	bwi_debug;
313#endif
314TUNABLE_INT("hw.bwi.debug", (int *)&bwi_debug);
315#endif	/* BWI_DEBUG */
316
317static const uint8_t bwi_zero_addr[IEEE80211_ADDR_LEN];
318
319uint16_t
320bwi_read_sprom(struct bwi_softc *sc, uint16_t ofs)
321{
322	return CSR_READ_2(sc, ofs + BWI_SPROM_START);
323}
324
325static __inline void
326bwi_setup_desc32(struct bwi_softc *sc, struct bwi_desc32 *desc_array,
327		 int ndesc, int desc_idx, bus_addr_t paddr, int buf_len,
328		 int tx)
329{
330	struct bwi_desc32 *desc = &desc_array[desc_idx];
331	uint32_t ctrl, addr, addr_hi, addr_lo;
332
333	addr_lo = __SHIFTOUT(paddr, BWI_DESC32_A_ADDR_MASK);
334	addr_hi = __SHIFTOUT(paddr, BWI_DESC32_A_FUNC_MASK);
335
336	addr = __SHIFTIN(addr_lo, BWI_DESC32_A_ADDR_MASK) |
337	       __SHIFTIN(BWI_DESC32_A_FUNC_TXRX, BWI_DESC32_A_FUNC_MASK);
338
339	ctrl = __SHIFTIN(buf_len, BWI_DESC32_C_BUFLEN_MASK) |
340	       __SHIFTIN(addr_hi, BWI_DESC32_C_ADDRHI_MASK);
341	if (desc_idx == ndesc - 1)
342		ctrl |= BWI_DESC32_C_EOR;
343	if (tx) {
344		/* XXX */
345		ctrl |= BWI_DESC32_C_FRAME_START |
346			BWI_DESC32_C_FRAME_END |
347			BWI_DESC32_C_INTR;
348	}
349
350	desc->addr = htole32(addr);
351	desc->ctrl = htole32(ctrl);
352}
353
354int
355bwi_attach(struct bwi_softc *sc)
356{
357	struct ieee80211com *ic = &sc->sc_ic;
358	device_t dev = sc->sc_dev;
359	struct bwi_mac *mac;
360	struct bwi_phy *phy;
361	int i, error;
362
363	BWI_LOCK_INIT(sc);
364
365	/*
366	 * Initialize taskq and various tasks
367	 */
368	sc->sc_tq = taskqueue_create("bwi_taskq", M_NOWAIT | M_ZERO,
369		taskqueue_thread_enqueue, &sc->sc_tq);
370	taskqueue_start_threads(&sc->sc_tq, 1, PI_NET, "%s taskq",
371		device_get_nameunit(dev));
372	TASK_INIT(&sc->sc_restart_task, 0, bwi_restart, sc);
373	callout_init_mtx(&sc->sc_calib_ch, &sc->sc_mtx, 0);
374	mbufq_init(&sc->sc_snd, ifqmaxlen);
375
376	/*
377	 * Initialize sysctl variables
378	 */
379	sc->sc_fw_version = BWI_FW_VERSION3;
380	sc->sc_led_idle = (2350 * hz) / 1000;
381	sc->sc_led_ticks = ticks - sc->sc_led_idle;
382	sc->sc_led_blink = 1;
383	sc->sc_txpwr_calib = 1;
384#ifdef BWI_DEBUG
385	sc->sc_debug = bwi_debug;
386#endif
387	bwi_power_on(sc, 1);
388
389	error = bwi_bbp_attach(sc);
390	if (error)
391		goto fail;
392
393	error = bwi_bbp_power_on(sc, BWI_CLOCK_MODE_FAST);
394	if (error)
395		goto fail;
396
397	if (BWI_REGWIN_EXIST(&sc->sc_com_regwin)) {
398		error = bwi_set_clock_delay(sc);
399		if (error)
400			goto fail;
401
402		error = bwi_set_clock_mode(sc, BWI_CLOCK_MODE_FAST);
403		if (error)
404			goto fail;
405
406		error = bwi_get_pwron_delay(sc);
407		if (error)
408			goto fail;
409	}
410
411	error = bwi_bus_attach(sc);
412	if (error)
413		goto fail;
414
415	bwi_get_card_flags(sc);
416
417	bwi_led_attach(sc);
418
419	for (i = 0; i < sc->sc_nmac; ++i) {
420		struct bwi_regwin *old;
421
422		mac = &sc->sc_mac[i];
423		error = bwi_regwin_switch(sc, &mac->mac_regwin, &old);
424		if (error)
425			goto fail;
426
427		error = bwi_mac_lateattach(mac);
428		if (error)
429			goto fail;
430
431		error = bwi_regwin_switch(sc, old, NULL);
432		if (error)
433			goto fail;
434	}
435
436	/*
437	 * XXX First MAC is known to exist
438	 * TODO2
439	 */
440	mac = &sc->sc_mac[0];
441	phy = &mac->mac_phy;
442
443	bwi_bbp_power_off(sc);
444
445	error = bwi_dma_alloc(sc);
446	if (error)
447		goto fail;
448
449	error = bwi_mac_fw_alloc(mac);
450	if (error)
451		goto fail;
452
453	callout_init_mtx(&sc->sc_watchdog_timer, &sc->sc_mtx, 0);
454
455	/*
456	 * Setup ratesets, phytype, channels and get MAC address
457	 */
458	if (phy->phy_mode == IEEE80211_MODE_11B ||
459	    phy->phy_mode == IEEE80211_MODE_11G) {
460		if (phy->phy_mode == IEEE80211_MODE_11B) {
461			ic->ic_phytype = IEEE80211_T_DS;
462		} else {
463			ic->ic_phytype = IEEE80211_T_OFDM;
464		}
465
466		bwi_get_eaddr(sc, BWI_SPROM_11BG_EADDR, ic->ic_macaddr);
467		if (IEEE80211_IS_MULTICAST(ic->ic_macaddr)) {
468			bwi_get_eaddr(sc, BWI_SPROM_11A_EADDR, ic->ic_macaddr);
469			if (IEEE80211_IS_MULTICAST(ic->ic_macaddr)) {
470				device_printf(dev,
471				    "invalid MAC address: %6D\n",
472				    ic->ic_macaddr, ":");
473			}
474		}
475	} else if (phy->phy_mode == IEEE80211_MODE_11A) {
476		/* TODO:11A */
477		error = ENXIO;
478		goto fail;
479	} else {
480		panic("unknown phymode %d\n", phy->phy_mode);
481	}
482
483	/* Get locale */
484	sc->sc_locale = __SHIFTOUT(bwi_read_sprom(sc, BWI_SPROM_CARD_INFO),
485				   BWI_SPROM_CARD_INFO_LOCALE);
486	DPRINTF(sc, BWI_DBG_ATTACH, "locale: %d\n", sc->sc_locale);
487	/* XXX use locale */
488
489	ic->ic_softc = sc;
490
491	bwi_getradiocaps(ic, IEEE80211_CHAN_MAX, &ic->ic_nchans,
492	    ic->ic_channels);
493
494	ic->ic_name = device_get_nameunit(dev);
495	ic->ic_caps = IEEE80211_C_STA |
496		      IEEE80211_C_SHSLOT |
497		      IEEE80211_C_SHPREAMBLE |
498		      IEEE80211_C_WPA |
499		      IEEE80211_C_BGSCAN |
500		      IEEE80211_C_MONITOR;
501	ic->ic_opmode = IEEE80211_M_STA;
502	ieee80211_ifattach(ic);
503
504	ic->ic_headroom = sizeof(struct bwi_txbuf_hdr);
505
506	/* override default methods */
507	ic->ic_vap_create = bwi_vap_create;
508	ic->ic_vap_delete = bwi_vap_delete;
509	ic->ic_raw_xmit = bwi_raw_xmit;
510	ic->ic_updateslot = bwi_updateslot;
511	ic->ic_scan_start = bwi_scan_start;
512	ic->ic_scan_end = bwi_scan_end;
513	ic->ic_getradiocaps = bwi_getradiocaps;
514	ic->ic_set_channel = bwi_set_channel;
515	ic->ic_transmit = bwi_transmit;
516	ic->ic_parent = bwi_parent;
517
518	sc->sc_rates = ieee80211_get_ratetable(ic->ic_curchan);
519
520	ieee80211_radiotap_attach(ic,
521	    &sc->sc_tx_th.wt_ihdr, sizeof(sc->sc_tx_th),
522		BWI_TX_RADIOTAP_PRESENT,
523	    &sc->sc_rx_th.wr_ihdr, sizeof(sc->sc_rx_th),
524		BWI_RX_RADIOTAP_PRESENT);
525
526	/*
527	 * Add sysctl nodes
528	 */
529	SYSCTL_ADD_INT(device_get_sysctl_ctx(dev),
530		        SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
531		        "fw_version", CTLFLAG_RD, &sc->sc_fw_version, 0,
532		        "Firmware version");
533	SYSCTL_ADD_INT(device_get_sysctl_ctx(dev),
534		        SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
535		        "led_idle", CTLFLAG_RW, &sc->sc_led_idle, 0,
536		        "# ticks before LED enters idle state");
537	SYSCTL_ADD_INT(device_get_sysctl_ctx(dev),
538		       SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
539		       "led_blink", CTLFLAG_RW, &sc->sc_led_blink, 0,
540		       "Allow LED to blink");
541	SYSCTL_ADD_INT(device_get_sysctl_ctx(dev),
542		       SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
543		       "txpwr_calib", CTLFLAG_RW, &sc->sc_txpwr_calib, 0,
544		       "Enable software TX power calibration");
545#ifdef BWI_DEBUG
546	SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev),
547		        SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
548		        "debug", CTLFLAG_RW, &sc->sc_debug, 0, "Debug flags");
549#endif
550	if (bootverbose)
551		ieee80211_announce(ic);
552
553	return (0);
554fail:
555	BWI_LOCK_DESTROY(sc);
556	return (error);
557}
558
559int
560bwi_detach(struct bwi_softc *sc)
561{
562	struct ieee80211com *ic = &sc->sc_ic;
563	int i;
564
565	bwi_stop(sc, 1);
566	callout_drain(&sc->sc_led_blink_ch);
567	callout_drain(&sc->sc_calib_ch);
568	callout_drain(&sc->sc_watchdog_timer);
569	ieee80211_ifdetach(ic);
570
571	for (i = 0; i < sc->sc_nmac; ++i)
572		bwi_mac_detach(&sc->sc_mac[i]);
573	bwi_dma_free(sc);
574	taskqueue_free(sc->sc_tq);
575	mbufq_drain(&sc->sc_snd);
576
577	BWI_LOCK_DESTROY(sc);
578
579	return (0);
580}
581
582static struct ieee80211vap *
583bwi_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit,
584    enum ieee80211_opmode opmode, int flags,
585    const uint8_t bssid[IEEE80211_ADDR_LEN],
586    const uint8_t mac[IEEE80211_ADDR_LEN])
587{
588	struct bwi_vap *bvp;
589	struct ieee80211vap *vap;
590
591	if (!TAILQ_EMPTY(&ic->ic_vaps))		/* only one at a time */
592		return NULL;
593	bvp = malloc(sizeof(struct bwi_vap), M_80211_VAP, M_WAITOK | M_ZERO);
594	vap = &bvp->bv_vap;
595	/* enable s/w bmiss handling for sta mode */
596	ieee80211_vap_setup(ic, vap, name, unit, opmode,
597	    flags | IEEE80211_CLONE_NOBEACONS, bssid);
598
599	/* override default methods */
600	bvp->bv_newstate = vap->iv_newstate;
601	vap->iv_newstate = bwi_newstate;
602#if 0
603	vap->iv_update_beacon = bwi_beacon_update;
604#endif
605	ieee80211_ratectl_init(vap);
606
607	/* complete setup */
608	ieee80211_vap_attach(vap, bwi_media_change, ieee80211_media_status,
609	    mac);
610	ic->ic_opmode = opmode;
611	return vap;
612}
613
614static void
615bwi_vap_delete(struct ieee80211vap *vap)
616{
617	struct bwi_vap *bvp = BWI_VAP(vap);
618
619	ieee80211_ratectl_deinit(vap);
620	ieee80211_vap_detach(vap);
621	free(bvp, M_80211_VAP);
622}
623
624void
625bwi_suspend(struct bwi_softc *sc)
626{
627	bwi_stop(sc, 1);
628}
629
630void
631bwi_resume(struct bwi_softc *sc)
632{
633
634	if (sc->sc_ic.ic_nrunning > 0)
635		bwi_init(sc);
636}
637
638int
639bwi_shutdown(struct bwi_softc *sc)
640{
641	bwi_stop(sc, 1);
642	return 0;
643}
644
645static void
646bwi_power_on(struct bwi_softc *sc, int with_pll)
647{
648	uint32_t gpio_in, gpio_out, gpio_en;
649	uint16_t status;
650
651	gpio_in = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_IN, 4);
652	if (gpio_in & BWI_PCIM_GPIO_PWR_ON)
653		goto back;
654
655	gpio_out = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, 4);
656	gpio_en = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, 4);
657
658	gpio_out |= BWI_PCIM_GPIO_PWR_ON;
659	gpio_en |= BWI_PCIM_GPIO_PWR_ON;
660	if (with_pll) {
661		/* Turn off PLL first */
662		gpio_out |= BWI_PCIM_GPIO_PLL_PWR_OFF;
663		gpio_en |= BWI_PCIM_GPIO_PLL_PWR_OFF;
664	}
665
666	pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, gpio_out, 4);
667	pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, gpio_en, 4);
668	DELAY(1000);
669
670	if (with_pll) {
671		/* Turn on PLL */
672		gpio_out &= ~BWI_PCIM_GPIO_PLL_PWR_OFF;
673		pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, gpio_out, 4);
674		DELAY(5000);
675	}
676
677back:
678	/* Clear "Signaled Target Abort" */
679	status = pci_read_config(sc->sc_dev, PCIR_STATUS, 2);
680	status &= ~PCIM_STATUS_STABORT;
681	pci_write_config(sc->sc_dev, PCIR_STATUS, status, 2);
682}
683
684static int
685bwi_power_off(struct bwi_softc *sc, int with_pll)
686{
687	uint32_t gpio_out, gpio_en;
688
689	pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_IN, 4); /* dummy read */
690	gpio_out = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, 4);
691	gpio_en = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, 4);
692
693	gpio_out &= ~BWI_PCIM_GPIO_PWR_ON;
694	gpio_en |= BWI_PCIM_GPIO_PWR_ON;
695	if (with_pll) {
696		gpio_out |= BWI_PCIM_GPIO_PLL_PWR_OFF;
697		gpio_en |= BWI_PCIM_GPIO_PLL_PWR_OFF;
698	}
699
700	pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, gpio_out, 4);
701	pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, gpio_en, 4);
702	return 0;
703}
704
705int
706bwi_regwin_switch(struct bwi_softc *sc, struct bwi_regwin *rw,
707		  struct bwi_regwin **old_rw)
708{
709	int error;
710
711	if (old_rw != NULL)
712		*old_rw = NULL;
713
714	if (!BWI_REGWIN_EXIST(rw))
715		return EINVAL;
716
717	if (sc->sc_cur_regwin != rw) {
718		error = bwi_regwin_select(sc, rw->rw_id);
719		if (error) {
720			device_printf(sc->sc_dev, "can't select regwin %d\n",
721				  rw->rw_id);
722			return error;
723		}
724	}
725
726	if (old_rw != NULL)
727		*old_rw = sc->sc_cur_regwin;
728	sc->sc_cur_regwin = rw;
729	return 0;
730}
731
732static int
733bwi_regwin_select(struct bwi_softc *sc, int id)
734{
735	uint32_t win = BWI_PCIM_REGWIN(id);
736	int i;
737
738#define RETRY_MAX	50
739	for (i = 0; i < RETRY_MAX; ++i) {
740		pci_write_config(sc->sc_dev, BWI_PCIR_SEL_REGWIN, win, 4);
741		if (pci_read_config(sc->sc_dev, BWI_PCIR_SEL_REGWIN, 4) == win)
742			return 0;
743		DELAY(10);
744	}
745#undef RETRY_MAX
746
747	return ENXIO;
748}
749
750static void
751bwi_regwin_info(struct bwi_softc *sc, uint16_t *type, uint8_t *rev)
752{
753	uint32_t val;
754
755	val = CSR_READ_4(sc, BWI_ID_HI);
756	*type = BWI_ID_HI_REGWIN_TYPE(val);
757	*rev = BWI_ID_HI_REGWIN_REV(val);
758
759	DPRINTF(sc, BWI_DBG_ATTACH, "regwin: type 0x%03x, rev %d, "
760		"vendor 0x%04x\n", *type, *rev,
761		__SHIFTOUT(val, BWI_ID_HI_REGWIN_VENDOR_MASK));
762}
763
764static int
765bwi_bbp_attach(struct bwi_softc *sc)
766{
767	uint16_t bbp_id, rw_type;
768	uint8_t rw_rev;
769	uint32_t info;
770	int error, nregwin, i;
771
772	/*
773	 * Get 0th regwin information
774	 * NOTE: 0th regwin should exist
775	 */
776	error = bwi_regwin_select(sc, 0);
777	if (error) {
778		device_printf(sc->sc_dev, "can't select regwin 0\n");
779		return error;
780	}
781	bwi_regwin_info(sc, &rw_type, &rw_rev);
782
783	/*
784	 * Find out BBP id
785	 */
786	bbp_id = 0;
787	info = 0;
788	if (rw_type == BWI_REGWIN_T_COM) {
789		info = CSR_READ_4(sc, BWI_INFO);
790		bbp_id = __SHIFTOUT(info, BWI_INFO_BBPID_MASK);
791
792		BWI_CREATE_REGWIN(&sc->sc_com_regwin, 0, rw_type, rw_rev);
793
794		sc->sc_cap = CSR_READ_4(sc, BWI_CAPABILITY);
795	} else {
796		for (i = 0; i < nitems(bwi_bbpid_map); ++i) {
797			if (sc->sc_pci_did >= bwi_bbpid_map[i].did_min &&
798			    sc->sc_pci_did <= bwi_bbpid_map[i].did_max) {
799				bbp_id = bwi_bbpid_map[i].bbp_id;
800				break;
801			}
802		}
803		if (bbp_id == 0) {
804			device_printf(sc->sc_dev, "no BBP id for device id "
805				      "0x%04x\n", sc->sc_pci_did);
806			return ENXIO;
807		}
808
809		info = __SHIFTIN(sc->sc_pci_revid, BWI_INFO_BBPREV_MASK) |
810		       __SHIFTIN(0, BWI_INFO_BBPPKG_MASK);
811	}
812
813	/*
814	 * Find out number of regwins
815	 */
816	nregwin = 0;
817	if (rw_type == BWI_REGWIN_T_COM && rw_rev >= 4) {
818		nregwin = __SHIFTOUT(info, BWI_INFO_NREGWIN_MASK);
819	} else {
820		for (i = 0; i < nitems(bwi_regwin_count); ++i) {
821			if (bwi_regwin_count[i].bbp_id == bbp_id) {
822				nregwin = bwi_regwin_count[i].nregwin;
823				break;
824			}
825		}
826		if (nregwin == 0) {
827			device_printf(sc->sc_dev, "no number of win for "
828				      "BBP id 0x%04x\n", bbp_id);
829			return ENXIO;
830		}
831	}
832
833	/* Record BBP id/rev for later using */
834	sc->sc_bbp_id = bbp_id;
835	sc->sc_bbp_rev = __SHIFTOUT(info, BWI_INFO_BBPREV_MASK);
836	sc->sc_bbp_pkg = __SHIFTOUT(info, BWI_INFO_BBPPKG_MASK);
837	device_printf(sc->sc_dev, "BBP: id 0x%04x, rev 0x%x, pkg %d\n",
838		      sc->sc_bbp_id, sc->sc_bbp_rev, sc->sc_bbp_pkg);
839
840	DPRINTF(sc, BWI_DBG_ATTACH, "nregwin %d, cap 0x%08x\n",
841		nregwin, sc->sc_cap);
842
843	/*
844	 * Create rest of the regwins
845	 */
846
847	/* Don't re-create common regwin, if it is already created */
848	i = BWI_REGWIN_EXIST(&sc->sc_com_regwin) ? 1 : 0;
849
850	for (; i < nregwin; ++i) {
851		/*
852		 * Get regwin information
853		 */
854		error = bwi_regwin_select(sc, i);
855		if (error) {
856			device_printf(sc->sc_dev,
857				      "can't select regwin %d\n", i);
858			return error;
859		}
860		bwi_regwin_info(sc, &rw_type, &rw_rev);
861
862		/*
863		 * Try attach:
864		 * 1) Bus (PCI/PCIE) regwin
865		 * 2) MAC regwin
866		 * Ignore rest types of regwin
867		 */
868		if (rw_type == BWI_REGWIN_T_BUSPCI ||
869		    rw_type == BWI_REGWIN_T_BUSPCIE) {
870			if (BWI_REGWIN_EXIST(&sc->sc_bus_regwin)) {
871				device_printf(sc->sc_dev,
872					      "bus regwin already exists\n");
873			} else {
874				BWI_CREATE_REGWIN(&sc->sc_bus_regwin, i,
875						  rw_type, rw_rev);
876			}
877		} else if (rw_type == BWI_REGWIN_T_MAC) {
878			/* XXX ignore return value */
879			bwi_mac_attach(sc, i, rw_rev);
880		}
881	}
882
883	/* At least one MAC shold exist */
884	if (!BWI_REGWIN_EXIST(&sc->sc_mac[0].mac_regwin)) {
885		device_printf(sc->sc_dev, "no MAC was found\n");
886		return ENXIO;
887	}
888	KASSERT(sc->sc_nmac > 0, ("no mac's"));
889
890	/* Bus regwin must exist */
891	if (!BWI_REGWIN_EXIST(&sc->sc_bus_regwin)) {
892		device_printf(sc->sc_dev, "no bus regwin was found\n");
893		return ENXIO;
894	}
895
896	/* Start with first MAC */
897	error = bwi_regwin_switch(sc, &sc->sc_mac[0].mac_regwin, NULL);
898	if (error)
899		return error;
900
901	return 0;
902}
903
904int
905bwi_bus_init(struct bwi_softc *sc, struct bwi_mac *mac)
906{
907	struct bwi_regwin *old, *bus;
908	uint32_t val;
909	int error;
910
911	bus = &sc->sc_bus_regwin;
912	KASSERT(sc->sc_cur_regwin == &mac->mac_regwin, ("not cur regwin"));
913
914	/*
915	 * Tell bus to generate requested interrupts
916	 */
917	if (bus->rw_rev < 6 && bus->rw_type == BWI_REGWIN_T_BUSPCI) {
918		/*
919		 * NOTE: Read BWI_FLAGS from MAC regwin
920		 */
921		val = CSR_READ_4(sc, BWI_FLAGS);
922
923		error = bwi_regwin_switch(sc, bus, &old);
924		if (error)
925			return error;
926
927		CSR_SETBITS_4(sc, BWI_INTRVEC, (val & BWI_FLAGS_INTR_MASK));
928	} else {
929		uint32_t mac_mask;
930
931		mac_mask = 1 << mac->mac_id;
932
933		error = bwi_regwin_switch(sc, bus, &old);
934		if (error)
935			return error;
936
937		val = pci_read_config(sc->sc_dev, BWI_PCIR_INTCTL, 4);
938		val |= mac_mask << 8;
939		pci_write_config(sc->sc_dev, BWI_PCIR_INTCTL, val, 4);
940	}
941
942	if (sc->sc_flags & BWI_F_BUS_INITED)
943		goto back;
944
945	if (bus->rw_type == BWI_REGWIN_T_BUSPCI) {
946		/*
947		 * Enable prefetch and burst
948		 */
949		CSR_SETBITS_4(sc, BWI_BUS_CONFIG,
950			      BWI_BUS_CONFIG_PREFETCH | BWI_BUS_CONFIG_BURST);
951
952		if (bus->rw_rev < 5) {
953			struct bwi_regwin *com = &sc->sc_com_regwin;
954
955			/*
956			 * Configure timeouts for bus operation
957			 */
958
959			/*
960			 * Set service timeout and request timeout
961			 */
962			CSR_SETBITS_4(sc, BWI_CONF_LO,
963			__SHIFTIN(BWI_CONF_LO_SERVTO, BWI_CONF_LO_SERVTO_MASK) |
964			__SHIFTIN(BWI_CONF_LO_REQTO, BWI_CONF_LO_REQTO_MASK));
965
966			/*
967			 * If there is common regwin, we switch to that regwin
968			 * and switch back to bus regwin once we have done.
969			 */
970			if (BWI_REGWIN_EXIST(com)) {
971				error = bwi_regwin_switch(sc, com, NULL);
972				if (error)
973					return error;
974			}
975
976			/* Let bus know what we have changed */
977			CSR_WRITE_4(sc, BWI_BUS_ADDR, BWI_BUS_ADDR_MAGIC);
978			CSR_READ_4(sc, BWI_BUS_ADDR); /* Flush */
979			CSR_WRITE_4(sc, BWI_BUS_DATA, 0);
980			CSR_READ_4(sc, BWI_BUS_DATA); /* Flush */
981
982			if (BWI_REGWIN_EXIST(com)) {
983				error = bwi_regwin_switch(sc, bus, NULL);
984				if (error)
985					return error;
986			}
987		} else if (bus->rw_rev >= 11) {
988			/*
989			 * Enable memory read multiple
990			 */
991			CSR_SETBITS_4(sc, BWI_BUS_CONFIG, BWI_BUS_CONFIG_MRM);
992		}
993	} else {
994		/* TODO:PCIE */
995	}
996
997	sc->sc_flags |= BWI_F_BUS_INITED;
998back:
999	return bwi_regwin_switch(sc, old, NULL);
1000}
1001
1002static void
1003bwi_get_card_flags(struct bwi_softc *sc)
1004{
1005#define	PCI_VENDOR_APPLE 0x106b
1006#define	PCI_VENDOR_DELL  0x1028
1007	sc->sc_card_flags = bwi_read_sprom(sc, BWI_SPROM_CARD_FLAGS);
1008	if (sc->sc_card_flags == 0xffff)
1009		sc->sc_card_flags = 0;
1010
1011	if (sc->sc_pci_subvid == PCI_VENDOR_DELL &&
1012	    sc->sc_bbp_id == BWI_BBPID_BCM4301 &&
1013	    sc->sc_pci_revid == 0x74)
1014		sc->sc_card_flags |= BWI_CARD_F_BT_COEXIST;
1015
1016	if (sc->sc_pci_subvid == PCI_VENDOR_APPLE &&
1017	    sc->sc_pci_subdid == 0x4e && /* XXX */
1018	    sc->sc_pci_revid > 0x40)
1019		sc->sc_card_flags |= BWI_CARD_F_PA_GPIO9;
1020
1021	DPRINTF(sc, BWI_DBG_ATTACH, "card flags 0x%04x\n", sc->sc_card_flags);
1022#undef PCI_VENDOR_DELL
1023#undef PCI_VENDOR_APPLE
1024}
1025
1026static void
1027bwi_get_eaddr(struct bwi_softc *sc, uint16_t eaddr_ofs, uint8_t *eaddr)
1028{
1029	int i;
1030
1031	for (i = 0; i < 3; ++i) {
1032		*((uint16_t *)eaddr + i) =
1033			htobe16(bwi_read_sprom(sc, eaddr_ofs + 2 * i));
1034	}
1035}
1036
1037static void
1038bwi_get_clock_freq(struct bwi_softc *sc, struct bwi_clock_freq *freq)
1039{
1040	struct bwi_regwin *com;
1041	uint32_t val;
1042	u_int div;
1043	int src;
1044
1045	bzero(freq, sizeof(*freq));
1046	com = &sc->sc_com_regwin;
1047
1048	KASSERT(BWI_REGWIN_EXIST(com), ("regwin does not exist"));
1049	KASSERT(sc->sc_cur_regwin == com, ("wrong regwin"));
1050	KASSERT(sc->sc_cap & BWI_CAP_CLKMODE, ("wrong clock mode"));
1051
1052	/*
1053	 * Calculate clock frequency
1054	 */
1055	src = -1;
1056	div = 0;
1057	if (com->rw_rev < 6) {
1058		val = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, 4);
1059		if (val & BWI_PCIM_GPIO_OUT_CLKSRC) {
1060			src = BWI_CLKSRC_PCI;
1061			div = 64;
1062		} else {
1063			src = BWI_CLKSRC_CS_OSC;
1064			div = 32;
1065		}
1066	} else if (com->rw_rev < 10) {
1067		val = CSR_READ_4(sc, BWI_CLOCK_CTRL);
1068
1069		src = __SHIFTOUT(val, BWI_CLOCK_CTRL_CLKSRC);
1070		if (src == BWI_CLKSRC_LP_OSC) {
1071			div = 1;
1072		} else {
1073			div = (__SHIFTOUT(val, BWI_CLOCK_CTRL_FDIV) + 1) << 2;
1074
1075			/* Unknown source */
1076			if (src >= BWI_CLKSRC_MAX)
1077				src = BWI_CLKSRC_CS_OSC;
1078		}
1079	} else {
1080		val = CSR_READ_4(sc, BWI_CLOCK_INFO);
1081
1082		src = BWI_CLKSRC_CS_OSC;
1083		div = (__SHIFTOUT(val, BWI_CLOCK_INFO_FDIV) + 1) << 2;
1084	}
1085
1086	KASSERT(src >= 0 && src < BWI_CLKSRC_MAX, ("bad src %d", src));
1087	KASSERT(div != 0, ("div zero"));
1088
1089	DPRINTF(sc, BWI_DBG_ATTACH, "clksrc %s\n",
1090		src == BWI_CLKSRC_PCI ? "PCI" :
1091		(src == BWI_CLKSRC_LP_OSC ? "LP_OSC" : "CS_OSC"));
1092
1093	freq->clkfreq_min = bwi_clkfreq[src].freq_min / div;
1094	freq->clkfreq_max = bwi_clkfreq[src].freq_max / div;
1095
1096	DPRINTF(sc, BWI_DBG_ATTACH, "clkfreq min %u, max %u\n",
1097		freq->clkfreq_min, freq->clkfreq_max);
1098}
1099
1100static int
1101bwi_set_clock_mode(struct bwi_softc *sc, enum bwi_clock_mode clk_mode)
1102{
1103	struct bwi_regwin *old, *com;
1104	uint32_t clk_ctrl, clk_src;
1105	int error, pwr_off = 0;
1106
1107	com = &sc->sc_com_regwin;
1108	if (!BWI_REGWIN_EXIST(com))
1109		return 0;
1110
1111	if (com->rw_rev >= 10 || com->rw_rev < 6)
1112		return 0;
1113
1114	/*
1115	 * For common regwin whose rev is [6, 10), the chip
1116	 * must be capable to change clock mode.
1117	 */
1118	if ((sc->sc_cap & BWI_CAP_CLKMODE) == 0)
1119		return 0;
1120
1121	error = bwi_regwin_switch(sc, com, &old);
1122	if (error)
1123		return error;
1124
1125	if (clk_mode == BWI_CLOCK_MODE_FAST)
1126		bwi_power_on(sc, 0);	/* Don't turn on PLL */
1127
1128	clk_ctrl = CSR_READ_4(sc, BWI_CLOCK_CTRL);
1129	clk_src = __SHIFTOUT(clk_ctrl, BWI_CLOCK_CTRL_CLKSRC);
1130
1131	switch (clk_mode) {
1132	case BWI_CLOCK_MODE_FAST:
1133		clk_ctrl &= ~BWI_CLOCK_CTRL_SLOW;
1134		clk_ctrl |= BWI_CLOCK_CTRL_IGNPLL;
1135		break;
1136	case BWI_CLOCK_MODE_SLOW:
1137		clk_ctrl |= BWI_CLOCK_CTRL_SLOW;
1138		break;
1139	case BWI_CLOCK_MODE_DYN:
1140		clk_ctrl &= ~(BWI_CLOCK_CTRL_SLOW |
1141			      BWI_CLOCK_CTRL_IGNPLL |
1142			      BWI_CLOCK_CTRL_NODYN);
1143		if (clk_src != BWI_CLKSRC_CS_OSC) {
1144			clk_ctrl |= BWI_CLOCK_CTRL_NODYN;
1145			pwr_off = 1;
1146		}
1147		break;
1148	}
1149	CSR_WRITE_4(sc, BWI_CLOCK_CTRL, clk_ctrl);
1150
1151	if (pwr_off)
1152		bwi_power_off(sc, 0);	/* Leave PLL as it is */
1153
1154	return bwi_regwin_switch(sc, old, NULL);
1155}
1156
1157static int
1158bwi_set_clock_delay(struct bwi_softc *sc)
1159{
1160	struct bwi_regwin *old, *com;
1161	int error;
1162
1163	com = &sc->sc_com_regwin;
1164	if (!BWI_REGWIN_EXIST(com))
1165		return 0;
1166
1167	error = bwi_regwin_switch(sc, com, &old);
1168	if (error)
1169		return error;
1170
1171	if (sc->sc_bbp_id == BWI_BBPID_BCM4321) {
1172		if (sc->sc_bbp_rev == 0)
1173			CSR_WRITE_4(sc, BWI_CONTROL, BWI_CONTROL_MAGIC0);
1174		else if (sc->sc_bbp_rev == 1)
1175			CSR_WRITE_4(sc, BWI_CONTROL, BWI_CONTROL_MAGIC1);
1176	}
1177
1178	if (sc->sc_cap & BWI_CAP_CLKMODE) {
1179		if (com->rw_rev >= 10) {
1180			CSR_FILT_SETBITS_4(sc, BWI_CLOCK_INFO, 0xffff, 0x40000);
1181		} else {
1182			struct bwi_clock_freq freq;
1183
1184			bwi_get_clock_freq(sc, &freq);
1185			CSR_WRITE_4(sc, BWI_PLL_ON_DELAY,
1186				howmany(freq.clkfreq_max * 150, 1000000));
1187			CSR_WRITE_4(sc, BWI_FREQ_SEL_DELAY,
1188				howmany(freq.clkfreq_max * 15, 1000000));
1189		}
1190	}
1191
1192	return bwi_regwin_switch(sc, old, NULL);
1193}
1194
1195static void
1196bwi_init(struct bwi_softc *sc)
1197{
1198	struct ieee80211com *ic = &sc->sc_ic;
1199
1200	BWI_LOCK(sc);
1201	bwi_init_statechg(sc, 1);
1202	BWI_UNLOCK(sc);
1203
1204	if (sc->sc_flags & BWI_F_RUNNING)
1205		ieee80211_start_all(ic);		/* start all vap's */
1206}
1207
1208static void
1209bwi_init_statechg(struct bwi_softc *sc, int statechg)
1210{
1211	struct bwi_mac *mac;
1212	int error;
1213
1214	BWI_ASSERT_LOCKED(sc);
1215
1216	bwi_stop_locked(sc, statechg);
1217
1218	bwi_bbp_power_on(sc, BWI_CLOCK_MODE_FAST);
1219
1220	/* TODO: 2 MAC */
1221
1222	mac = &sc->sc_mac[0];
1223	error = bwi_regwin_switch(sc, &mac->mac_regwin, NULL);
1224	if (error) {
1225		device_printf(sc->sc_dev, "%s: error %d on regwin switch\n",
1226		    __func__, error);
1227		goto bad;
1228	}
1229	error = bwi_mac_init(mac);
1230	if (error) {
1231		device_printf(sc->sc_dev, "%s: error %d on MAC init\n",
1232		    __func__, error);
1233		goto bad;
1234	}
1235
1236	bwi_bbp_power_on(sc, BWI_CLOCK_MODE_DYN);
1237
1238	bwi_set_bssid(sc, bwi_zero_addr);	/* Clear BSSID */
1239	bwi_set_addr_filter(sc, BWI_ADDR_FILTER_MYADDR, sc->sc_ic.ic_macaddr);
1240
1241	bwi_mac_reset_hwkeys(mac);
1242
1243	if ((mac->mac_flags & BWI_MAC_F_HAS_TXSTATS) == 0) {
1244		int i;
1245
1246#define NRETRY	1000
1247		/*
1248		 * Drain any possible pending TX status
1249		 */
1250		for (i = 0; i < NRETRY; ++i) {
1251			if ((CSR_READ_4(sc, BWI_TXSTATUS0) &
1252			     BWI_TXSTATUS0_VALID) == 0)
1253				break;
1254			CSR_READ_4(sc, BWI_TXSTATUS1);
1255		}
1256		if (i == NRETRY)
1257			device_printf(sc->sc_dev,
1258			    "%s: can't drain TX status\n", __func__);
1259#undef NRETRY
1260	}
1261
1262	if (mac->mac_phy.phy_mode == IEEE80211_MODE_11G)
1263		bwi_mac_updateslot(mac, 1);
1264
1265	/* Start MAC */
1266	error = bwi_mac_start(mac);
1267	if (error) {
1268		device_printf(sc->sc_dev, "%s: error %d starting MAC\n",
1269		    __func__, error);
1270		goto bad;
1271	}
1272
1273	/* Clear stop flag before enabling interrupt */
1274	sc->sc_flags &= ~BWI_F_STOP;
1275	sc->sc_flags |= BWI_F_RUNNING;
1276	callout_reset(&sc->sc_watchdog_timer, hz, bwi_watchdog, sc);
1277
1278	/* Enable intrs */
1279	bwi_enable_intrs(sc, BWI_INIT_INTRS);
1280	return;
1281bad:
1282	bwi_stop_locked(sc, 1);
1283}
1284
1285static void
1286bwi_parent(struct ieee80211com *ic)
1287{
1288	struct bwi_softc *sc = ic->ic_softc;
1289	int startall = 0;
1290
1291	BWI_LOCK(sc);
1292	if (ic->ic_nrunning > 0) {
1293		struct bwi_mac *mac;
1294		int promisc = -1;
1295
1296		KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC,
1297		    ("current regwin type %d",
1298		    sc->sc_cur_regwin->rw_type));
1299		mac = (struct bwi_mac *)sc->sc_cur_regwin;
1300
1301		if (ic->ic_promisc > 0 && (sc->sc_flags & BWI_F_PROMISC) == 0) {
1302			promisc = 1;
1303			sc->sc_flags |= BWI_F_PROMISC;
1304		} else if (ic->ic_promisc == 0 &&
1305		    (sc->sc_flags & BWI_F_PROMISC) != 0) {
1306			promisc = 0;
1307			sc->sc_flags &= ~BWI_F_PROMISC;
1308		}
1309
1310		if (promisc >= 0)
1311			bwi_mac_set_promisc(mac, promisc);
1312	}
1313	if (ic->ic_nrunning > 0) {
1314		if ((sc->sc_flags & BWI_F_RUNNING) == 0) {
1315			bwi_init_statechg(sc, 1);
1316			startall = 1;
1317		}
1318	} else if (sc->sc_flags & BWI_F_RUNNING)
1319		bwi_stop_locked(sc, 1);
1320	BWI_UNLOCK(sc);
1321	if (startall)
1322		ieee80211_start_all(ic);
1323}
1324
1325static int
1326bwi_transmit(struct ieee80211com *ic, struct mbuf *m)
1327{
1328	struct bwi_softc *sc = ic->ic_softc;
1329	int error;
1330
1331	BWI_LOCK(sc);
1332	if ((sc->sc_flags & BWI_F_RUNNING) == 0) {
1333		BWI_UNLOCK(sc);
1334		return (ENXIO);
1335	}
1336	error = mbufq_enqueue(&sc->sc_snd, m);
1337	if (error) {
1338		BWI_UNLOCK(sc);
1339		return (error);
1340	}
1341	bwi_start_locked(sc);
1342	BWI_UNLOCK(sc);
1343	return (0);
1344}
1345
1346static void
1347bwi_start_locked(struct bwi_softc *sc)
1348{
1349	struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[BWI_TX_DATA_RING];
1350	struct ieee80211_frame *wh;
1351	struct ieee80211_node *ni;
1352	struct mbuf *m;
1353	int trans, idx;
1354
1355	BWI_ASSERT_LOCKED(sc);
1356
1357	trans = 0;
1358	idx = tbd->tbd_idx;
1359
1360	while (tbd->tbd_buf[idx].tb_mbuf == NULL &&
1361	    tbd->tbd_used + BWI_TX_NSPRDESC < BWI_TX_NDESC &&
1362	    (m = mbufq_dequeue(&sc->sc_snd)) != NULL) {
1363		ni = (struct ieee80211_node *) m->m_pkthdr.rcvif;
1364		wh = mtod(m, struct ieee80211_frame *);
1365		if ((wh->i_fc[1] & IEEE80211_FC1_PROTECTED) != 0 &&
1366		    ieee80211_crypto_encap(ni, m) == NULL) {
1367			if_inc_counter(ni->ni_vap->iv_ifp,
1368			    IFCOUNTER_OERRORS, 1);
1369			ieee80211_free_node(ni);
1370			m_freem(m);
1371			continue;
1372		}
1373		if (bwi_encap(sc, idx, m, ni) != 0) {
1374			/* 'm' is freed in bwi_encap() if we reach here */
1375			if (ni != NULL) {
1376				if_inc_counter(ni->ni_vap->iv_ifp,
1377				    IFCOUNTER_OERRORS, 1);
1378				ieee80211_free_node(ni);
1379			} else
1380				counter_u64_add(sc->sc_ic.ic_oerrors, 1);
1381			continue;
1382		}
1383		trans = 1;
1384		tbd->tbd_used++;
1385		idx = (idx + 1) % BWI_TX_NDESC;
1386	}
1387
1388	tbd->tbd_idx = idx;
1389	if (trans)
1390		sc->sc_tx_timer = 5;
1391}
1392
1393static int
1394bwi_raw_xmit(struct ieee80211_node *ni, struct mbuf *m,
1395	const struct ieee80211_bpf_params *params)
1396{
1397	struct ieee80211com *ic = ni->ni_ic;
1398	struct bwi_softc *sc = ic->ic_softc;
1399	/* XXX wme? */
1400	struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[BWI_TX_DATA_RING];
1401	int idx, error;
1402
1403	if ((sc->sc_flags & BWI_F_RUNNING) == 0) {
1404		m_freem(m);
1405		return ENETDOWN;
1406	}
1407
1408	BWI_LOCK(sc);
1409	idx = tbd->tbd_idx;
1410	KASSERT(tbd->tbd_buf[idx].tb_mbuf == NULL, ("slot %d not empty", idx));
1411	if (params == NULL) {
1412		/*
1413		 * Legacy path; interpret frame contents to decide
1414		 * precisely how to send the frame.
1415		 */
1416		error = bwi_encap(sc, idx, m, ni);
1417	} else {
1418		/*
1419		 * Caller supplied explicit parameters to use in
1420		 * sending the frame.
1421		 */
1422		error = bwi_encap_raw(sc, idx, m, ni, params);
1423	}
1424	if (error == 0) {
1425		tbd->tbd_used++;
1426		tbd->tbd_idx = (idx + 1) % BWI_TX_NDESC;
1427		sc->sc_tx_timer = 5;
1428	}
1429	BWI_UNLOCK(sc);
1430	return error;
1431}
1432
1433static void
1434bwi_watchdog(void *arg)
1435{
1436	struct bwi_softc *sc;
1437
1438	sc = arg;
1439	BWI_ASSERT_LOCKED(sc);
1440	if (sc->sc_tx_timer != 0 && --sc->sc_tx_timer == 0) {
1441		device_printf(sc->sc_dev, "watchdog timeout\n");
1442		counter_u64_add(sc->sc_ic.ic_oerrors, 1);
1443		taskqueue_enqueue(sc->sc_tq, &sc->sc_restart_task);
1444	}
1445	callout_reset(&sc->sc_watchdog_timer, hz, bwi_watchdog, sc);
1446}
1447
1448static void
1449bwi_stop(struct bwi_softc *sc, int statechg)
1450{
1451	BWI_LOCK(sc);
1452	bwi_stop_locked(sc, statechg);
1453	BWI_UNLOCK(sc);
1454}
1455
1456static void
1457bwi_stop_locked(struct bwi_softc *sc, int statechg)
1458{
1459	struct bwi_mac *mac;
1460	int i, error, pwr_off = 0;
1461
1462	BWI_ASSERT_LOCKED(sc);
1463
1464	callout_stop(&sc->sc_calib_ch);
1465	callout_stop(&sc->sc_led_blink_ch);
1466	sc->sc_led_blinking = 0;
1467	sc->sc_flags |= BWI_F_STOP;
1468
1469	if (sc->sc_flags & BWI_F_RUNNING) {
1470		KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC,
1471		    ("current regwin type %d", sc->sc_cur_regwin->rw_type));
1472		mac = (struct bwi_mac *)sc->sc_cur_regwin;
1473
1474		bwi_disable_intrs(sc, BWI_ALL_INTRS);
1475		CSR_READ_4(sc, BWI_MAC_INTR_MASK);
1476		bwi_mac_stop(mac);
1477	}
1478
1479	for (i = 0; i < sc->sc_nmac; ++i) {
1480		struct bwi_regwin *old_rw;
1481
1482		mac = &sc->sc_mac[i];
1483		if ((mac->mac_flags & BWI_MAC_F_INITED) == 0)
1484			continue;
1485
1486		error = bwi_regwin_switch(sc, &mac->mac_regwin, &old_rw);
1487		if (error)
1488			continue;
1489
1490		bwi_mac_shutdown(mac);
1491		pwr_off = 1;
1492
1493		bwi_regwin_switch(sc, old_rw, NULL);
1494	}
1495
1496	if (pwr_off)
1497		bwi_bbp_power_off(sc);
1498
1499	sc->sc_tx_timer = 0;
1500	callout_stop(&sc->sc_watchdog_timer);
1501	sc->sc_flags &= ~BWI_F_RUNNING;
1502}
1503
1504void
1505bwi_intr(void *xsc)
1506{
1507	struct bwi_softc *sc = xsc;
1508	struct bwi_mac *mac;
1509	uint32_t intr_status;
1510	uint32_t txrx_intr_status[BWI_TXRX_NRING];
1511	int i, txrx_error, tx = 0, rx_data = -1;
1512
1513	BWI_LOCK(sc);
1514
1515	if ((sc->sc_flags & BWI_F_RUNNING) == 0 ||
1516	    (sc->sc_flags & BWI_F_STOP)) {
1517		BWI_UNLOCK(sc);
1518		return;
1519	}
1520	/*
1521	 * Get interrupt status
1522	 */
1523	intr_status = CSR_READ_4(sc, BWI_MAC_INTR_STATUS);
1524	if (intr_status == 0xffffffff) {	/* Not for us */
1525		BWI_UNLOCK(sc);
1526		return;
1527	}
1528
1529	DPRINTF(sc, BWI_DBG_INTR, "intr status 0x%08x\n", intr_status);
1530
1531	intr_status &= CSR_READ_4(sc, BWI_MAC_INTR_MASK);
1532	if (intr_status == 0) {		/* Nothing is interesting */
1533		BWI_UNLOCK(sc);
1534		return;
1535	}
1536
1537	KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC,
1538	    ("current regwin type %d", sc->sc_cur_regwin->rw_type));
1539	mac = (struct bwi_mac *)sc->sc_cur_regwin;
1540
1541	txrx_error = 0;
1542	DPRINTF(sc, BWI_DBG_INTR, "%s\n", "TX/RX intr");
1543	for (i = 0; i < BWI_TXRX_NRING; ++i) {
1544		uint32_t mask;
1545
1546		if (BWI_TXRX_IS_RX(i))
1547			mask = BWI_TXRX_RX_INTRS;
1548		else
1549			mask = BWI_TXRX_TX_INTRS;
1550
1551		txrx_intr_status[i] =
1552		CSR_READ_4(sc, BWI_TXRX_INTR_STATUS(i)) & mask;
1553
1554		_DPRINTF(sc, BWI_DBG_INTR, ", %d 0x%08x",
1555			 i, txrx_intr_status[i]);
1556
1557		if (txrx_intr_status[i] & BWI_TXRX_INTR_ERROR) {
1558			device_printf(sc->sc_dev,
1559			    "%s: intr fatal TX/RX (%d) error 0x%08x\n",
1560			    __func__, i, txrx_intr_status[i]);
1561			txrx_error = 1;
1562		}
1563	}
1564	_DPRINTF(sc, BWI_DBG_INTR, "%s\n", "");
1565
1566	/*
1567	 * Acknowledge interrupt
1568	 */
1569	CSR_WRITE_4(sc, BWI_MAC_INTR_STATUS, intr_status);
1570
1571	for (i = 0; i < BWI_TXRX_NRING; ++i)
1572		CSR_WRITE_4(sc, BWI_TXRX_INTR_STATUS(i), txrx_intr_status[i]);
1573
1574	/* Disable all interrupts */
1575	bwi_disable_intrs(sc, BWI_ALL_INTRS);
1576
1577	/*
1578	 * http://bcm-specs.sipsolutions.net/Interrupts
1579	 * Says for this bit (0x800):
1580	 * "Fatal Error
1581	 *
1582	 * We got this one while testing things when by accident the
1583	 * template ram wasn't set to big endian when it should have
1584	 * been after writing the initial values. It keeps on being
1585	 * triggered, the only way to stop it seems to shut down the
1586	 * chip."
1587	 *
1588	 * Suggesting that we should never get it and if we do we're not
1589	 * feeding TX packets into the MAC correctly if we do...  Apparently,
1590	 * it is valid only on mac version 5 and higher, but I couldn't
1591	 * find a reference for that...  Since I see them from time to time
1592	 * on my card, this suggests an error in the tx path still...
1593	 */
1594	if (intr_status & BWI_INTR_PHY_TXERR) {
1595		if (mac->mac_flags & BWI_MAC_F_PHYE_RESET) {
1596			device_printf(sc->sc_dev, "%s: intr PHY TX error\n",
1597			    __func__);
1598			taskqueue_enqueue(sc->sc_tq, &sc->sc_restart_task);
1599			BWI_UNLOCK(sc);
1600			return;
1601		}
1602	}
1603
1604	if (txrx_error) {
1605		/* TODO: reset device */
1606	}
1607
1608	if (intr_status & BWI_INTR_TBTT)
1609		bwi_mac_config_ps(mac);
1610
1611	if (intr_status & BWI_INTR_EO_ATIM)
1612		device_printf(sc->sc_dev, "EO_ATIM\n");
1613
1614	if (intr_status & BWI_INTR_PMQ) {
1615		for (;;) {
1616			if ((CSR_READ_4(sc, BWI_MAC_PS_STATUS) & 0x8) == 0)
1617				break;
1618		}
1619		CSR_WRITE_2(sc, BWI_MAC_PS_STATUS, 0x2);
1620	}
1621
1622	if (intr_status & BWI_INTR_NOISE)
1623		device_printf(sc->sc_dev, "intr noise\n");
1624
1625	if (txrx_intr_status[0] & BWI_TXRX_INTR_RX) {
1626		rx_data = sc->sc_rxeof(sc);
1627		if (sc->sc_flags & BWI_F_STOP) {
1628			BWI_UNLOCK(sc);
1629			return;
1630		}
1631	}
1632
1633	if (txrx_intr_status[3] & BWI_TXRX_INTR_RX) {
1634		sc->sc_txeof_status(sc);
1635		tx = 1;
1636	}
1637
1638	if (intr_status & BWI_INTR_TX_DONE) {
1639		bwi_txeof(sc);
1640		tx = 1;
1641	}
1642
1643	/* Re-enable interrupts */
1644	bwi_enable_intrs(sc, BWI_INIT_INTRS);
1645
1646	if (sc->sc_blink_led != NULL && sc->sc_led_blink) {
1647		int evt = BWI_LED_EVENT_NONE;
1648
1649		if (tx && rx_data > 0) {
1650			if (sc->sc_rx_rate > sc->sc_tx_rate)
1651				evt = BWI_LED_EVENT_RX;
1652			else
1653				evt = BWI_LED_EVENT_TX;
1654		} else if (tx) {
1655			evt = BWI_LED_EVENT_TX;
1656		} else if (rx_data > 0) {
1657			evt = BWI_LED_EVENT_RX;
1658		} else if (rx_data == 0) {
1659			evt = BWI_LED_EVENT_POLL;
1660		}
1661
1662		if (evt != BWI_LED_EVENT_NONE)
1663			bwi_led_event(sc, evt);
1664	}
1665
1666	BWI_UNLOCK(sc);
1667}
1668
1669static void
1670bwi_scan_start(struct ieee80211com *ic)
1671{
1672	struct bwi_softc *sc = ic->ic_softc;
1673
1674	BWI_LOCK(sc);
1675	/* Enable MAC beacon promiscuity */
1676	CSR_SETBITS_4(sc, BWI_MAC_STATUS, BWI_MAC_STATUS_PASS_BCN);
1677	BWI_UNLOCK(sc);
1678}
1679
1680static void
1681bwi_getradiocaps(struct ieee80211com *ic,
1682    int maxchans, int *nchans, struct ieee80211_channel chans[])
1683{
1684	struct bwi_softc *sc = ic->ic_softc;
1685	struct bwi_mac *mac;
1686	struct bwi_phy *phy;
1687	uint8_t bands[IEEE80211_MODE_BYTES];
1688
1689	/*
1690	 * XXX First MAC is known to exist
1691	 * TODO2
1692	 */
1693	mac = &sc->sc_mac[0];
1694	phy = &mac->mac_phy;
1695
1696	memset(bands, 0, sizeof(bands));
1697	switch (phy->phy_mode) {
1698	case IEEE80211_MODE_11G:
1699		setbit(bands, IEEE80211_MODE_11G);
1700		/* FALLTHROUGH */
1701	case IEEE80211_MODE_11B:
1702		setbit(bands, IEEE80211_MODE_11B);
1703		break;
1704	case IEEE80211_MODE_11A:
1705		/* TODO:11A */
1706		setbit(bands, IEEE80211_MODE_11A);
1707		device_printf(sc->sc_dev, "no 11a support\n");
1708		return;
1709	default:
1710		panic("unknown phymode %d\n", phy->phy_mode);
1711	}
1712
1713	ieee80211_add_channels_default_2ghz(chans, maxchans, nchans, bands, 0);
1714}
1715
1716static void
1717bwi_set_channel(struct ieee80211com *ic)
1718{
1719	struct bwi_softc *sc = ic->ic_softc;
1720	struct ieee80211_channel *c = ic->ic_curchan;
1721	struct bwi_mac *mac;
1722
1723	BWI_LOCK(sc);
1724	KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC,
1725	    ("current regwin type %d", sc->sc_cur_regwin->rw_type));
1726	mac = (struct bwi_mac *)sc->sc_cur_regwin;
1727	bwi_rf_set_chan(mac, ieee80211_chan2ieee(ic, c), 0);
1728
1729	sc->sc_rates = ieee80211_get_ratetable(c);
1730	BWI_UNLOCK(sc);
1731}
1732
1733static void
1734bwi_scan_end(struct ieee80211com *ic)
1735{
1736	struct bwi_softc *sc = ic->ic_softc;
1737
1738	BWI_LOCK(sc);
1739	CSR_CLRBITS_4(sc, BWI_MAC_STATUS, BWI_MAC_STATUS_PASS_BCN);
1740	BWI_UNLOCK(sc);
1741}
1742
1743static int
1744bwi_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg)
1745{
1746	struct bwi_vap *bvp = BWI_VAP(vap);
1747	struct ieee80211com *ic= vap->iv_ic;
1748	struct bwi_softc *sc = ic->ic_softc;
1749	enum ieee80211_state ostate = vap->iv_state;
1750	struct bwi_mac *mac;
1751	int error;
1752
1753	BWI_LOCK(sc);
1754
1755	callout_stop(&sc->sc_calib_ch);
1756
1757	if (nstate == IEEE80211_S_INIT)
1758		sc->sc_txpwrcb_type = BWI_TXPWR_INIT;
1759
1760	bwi_led_newstate(sc, nstate);
1761
1762	error = bvp->bv_newstate(vap, nstate, arg);
1763	if (error != 0)
1764		goto back;
1765
1766	/*
1767	 * Clear the BSSID when we stop a STA
1768	 */
1769	if (vap->iv_opmode == IEEE80211_M_STA) {
1770		if (ostate == IEEE80211_S_RUN && nstate != IEEE80211_S_RUN) {
1771			/*
1772			 * Clear out the BSSID.  If we reassociate to
1773			 * the same AP, this will reinialize things
1774			 * correctly...
1775			 */
1776			if (ic->ic_opmode == IEEE80211_M_STA &&
1777			    !(sc->sc_flags & BWI_F_STOP))
1778				bwi_set_bssid(sc, bwi_zero_addr);
1779		}
1780	}
1781
1782	if (vap->iv_opmode == IEEE80211_M_MONITOR) {
1783		/* Nothing to do */
1784	} else if (nstate == IEEE80211_S_RUN) {
1785		bwi_set_bssid(sc, vap->iv_bss->ni_bssid);
1786
1787		KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC,
1788		    ("current regwin type %d", sc->sc_cur_regwin->rw_type));
1789		mac = (struct bwi_mac *)sc->sc_cur_regwin;
1790
1791		/* Initial TX power calibration */
1792		bwi_mac_calibrate_txpower(mac, BWI_TXPWR_INIT);
1793#ifdef notyet
1794		sc->sc_txpwrcb_type = BWI_TXPWR_FORCE;
1795#else
1796		sc->sc_txpwrcb_type = BWI_TXPWR_CALIB;
1797#endif
1798
1799		callout_reset(&sc->sc_calib_ch, hz, bwi_calibrate, sc);
1800	}
1801back:
1802	BWI_UNLOCK(sc);
1803
1804	return error;
1805}
1806
1807static int
1808bwi_media_change(struct ifnet *ifp)
1809{
1810	int error = ieee80211_media_change(ifp);
1811	/* NB: only the fixed rate can change and that doesn't need a reset */
1812	return (error == ENETRESET ? 0 : error);
1813}
1814
1815static int
1816bwi_dma_alloc(struct bwi_softc *sc)
1817{
1818	int error, i, has_txstats;
1819	bus_addr_t lowaddr = 0;
1820	bus_size_t tx_ring_sz, rx_ring_sz, desc_sz = 0;
1821	uint32_t txrx_ctrl_step = 0;
1822
1823	has_txstats = 0;
1824	for (i = 0; i < sc->sc_nmac; ++i) {
1825		if (sc->sc_mac[i].mac_flags & BWI_MAC_F_HAS_TXSTATS) {
1826			has_txstats = 1;
1827			break;
1828		}
1829	}
1830
1831	switch (sc->sc_bus_space) {
1832	case BWI_BUS_SPACE_30BIT:
1833	case BWI_BUS_SPACE_32BIT:
1834		if (sc->sc_bus_space == BWI_BUS_SPACE_30BIT)
1835			lowaddr = BWI_BUS_SPACE_MAXADDR;
1836		else
1837			lowaddr = BUS_SPACE_MAXADDR_32BIT;
1838		desc_sz = sizeof(struct bwi_desc32);
1839		txrx_ctrl_step = 0x20;
1840
1841		sc->sc_init_tx_ring = bwi_init_tx_ring32;
1842		sc->sc_free_tx_ring = bwi_free_tx_ring32;
1843		sc->sc_init_rx_ring = bwi_init_rx_ring32;
1844		sc->sc_free_rx_ring = bwi_free_rx_ring32;
1845		sc->sc_setup_rxdesc = bwi_setup_rx_desc32;
1846		sc->sc_setup_txdesc = bwi_setup_tx_desc32;
1847		sc->sc_rxeof = bwi_rxeof32;
1848		sc->sc_start_tx = bwi_start_tx32;
1849		if (has_txstats) {
1850			sc->sc_init_txstats = bwi_init_txstats32;
1851			sc->sc_free_txstats = bwi_free_txstats32;
1852			sc->sc_txeof_status = bwi_txeof_status32;
1853		}
1854		break;
1855
1856	case BWI_BUS_SPACE_64BIT:
1857		lowaddr = BUS_SPACE_MAXADDR;	/* XXX */
1858		desc_sz = sizeof(struct bwi_desc64);
1859		txrx_ctrl_step = 0x40;
1860
1861		sc->sc_init_tx_ring = bwi_init_tx_ring64;
1862		sc->sc_free_tx_ring = bwi_free_tx_ring64;
1863		sc->sc_init_rx_ring = bwi_init_rx_ring64;
1864		sc->sc_free_rx_ring = bwi_free_rx_ring64;
1865		sc->sc_setup_rxdesc = bwi_setup_rx_desc64;
1866		sc->sc_setup_txdesc = bwi_setup_tx_desc64;
1867		sc->sc_rxeof = bwi_rxeof64;
1868		sc->sc_start_tx = bwi_start_tx64;
1869		if (has_txstats) {
1870			sc->sc_init_txstats = bwi_init_txstats64;
1871			sc->sc_free_txstats = bwi_free_txstats64;
1872			sc->sc_txeof_status = bwi_txeof_status64;
1873		}
1874		break;
1875	}
1876
1877	KASSERT(lowaddr != 0, ("lowaddr zero"));
1878	KASSERT(desc_sz != 0, ("desc_sz zero"));
1879	KASSERT(txrx_ctrl_step != 0, ("txrx_ctrl_step zero"));
1880
1881	tx_ring_sz = roundup(desc_sz * BWI_TX_NDESC, BWI_RING_ALIGN);
1882	rx_ring_sz = roundup(desc_sz * BWI_RX_NDESC, BWI_RING_ALIGN);
1883
1884	/*
1885	 * Create top level DMA tag
1886	 */
1887	error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev),	/* parent */
1888			       BWI_ALIGN, 0,		/* alignment, bounds */
1889			       lowaddr,			/* lowaddr */
1890			       BUS_SPACE_MAXADDR,	/* highaddr */
1891			       NULL, NULL,		/* filter, filterarg */
1892			       BUS_SPACE_MAXSIZE,	/* maxsize */
1893			       BUS_SPACE_UNRESTRICTED,	/* nsegments */
1894			       BUS_SPACE_MAXSIZE_32BIT,	/* maxsegsize */
1895			       0,			/* flags */
1896			       NULL, NULL,		/* lockfunc, lockarg */
1897			       &sc->sc_parent_dtag);
1898	if (error) {
1899		device_printf(sc->sc_dev, "can't create parent DMA tag\n");
1900		return error;
1901	}
1902
1903#define TXRX_CTRL(idx)	(BWI_TXRX_CTRL_BASE + (idx) * txrx_ctrl_step)
1904
1905	/*
1906	 * Create TX ring DMA stuffs
1907	 */
1908	error = bus_dma_tag_create(sc->sc_parent_dtag,
1909				BWI_RING_ALIGN, 0,
1910				BUS_SPACE_MAXADDR,
1911				BUS_SPACE_MAXADDR,
1912				NULL, NULL,
1913				tx_ring_sz,
1914				1,
1915				tx_ring_sz,
1916				0,
1917				NULL, NULL,
1918				&sc->sc_txring_dtag);
1919	if (error) {
1920		device_printf(sc->sc_dev, "can't create TX ring DMA tag\n");
1921		return error;
1922	}
1923
1924	for (i = 0; i < BWI_TX_NRING; ++i) {
1925		error = bwi_dma_ring_alloc(sc, sc->sc_txring_dtag,
1926					   &sc->sc_tx_rdata[i], tx_ring_sz,
1927					   TXRX_CTRL(i));
1928		if (error) {
1929			device_printf(sc->sc_dev, "%dth TX ring "
1930				      "DMA alloc failed\n", i);
1931			return error;
1932		}
1933	}
1934
1935	/*
1936	 * Create RX ring DMA stuffs
1937	 */
1938	error = bus_dma_tag_create(sc->sc_parent_dtag,
1939				BWI_RING_ALIGN, 0,
1940				BUS_SPACE_MAXADDR,
1941				BUS_SPACE_MAXADDR,
1942				NULL, NULL,
1943				rx_ring_sz,
1944				1,
1945				rx_ring_sz,
1946				0,
1947				NULL, NULL,
1948				&sc->sc_rxring_dtag);
1949	if (error) {
1950		device_printf(sc->sc_dev, "can't create RX ring DMA tag\n");
1951		return error;
1952	}
1953
1954	error = bwi_dma_ring_alloc(sc, sc->sc_rxring_dtag, &sc->sc_rx_rdata,
1955				   rx_ring_sz, TXRX_CTRL(0));
1956	if (error) {
1957		device_printf(sc->sc_dev, "RX ring DMA alloc failed\n");
1958		return error;
1959	}
1960
1961	if (has_txstats) {
1962		error = bwi_dma_txstats_alloc(sc, TXRX_CTRL(3), desc_sz);
1963		if (error) {
1964			device_printf(sc->sc_dev,
1965				      "TX stats DMA alloc failed\n");
1966			return error;
1967		}
1968	}
1969
1970#undef TXRX_CTRL
1971
1972	return bwi_dma_mbuf_create(sc);
1973}
1974
1975static void
1976bwi_dma_free(struct bwi_softc *sc)
1977{
1978	if (sc->sc_txring_dtag != NULL) {
1979		int i;
1980
1981		for (i = 0; i < BWI_TX_NRING; ++i) {
1982			struct bwi_ring_data *rd = &sc->sc_tx_rdata[i];
1983
1984			if (rd->rdata_desc != NULL) {
1985				bus_dmamap_unload(sc->sc_txring_dtag,
1986						  rd->rdata_dmap);
1987				bus_dmamem_free(sc->sc_txring_dtag,
1988						rd->rdata_desc,
1989						rd->rdata_dmap);
1990			}
1991		}
1992		bus_dma_tag_destroy(sc->sc_txring_dtag);
1993	}
1994
1995	if (sc->sc_rxring_dtag != NULL) {
1996		struct bwi_ring_data *rd = &sc->sc_rx_rdata;
1997
1998		if (rd->rdata_desc != NULL) {
1999			bus_dmamap_unload(sc->sc_rxring_dtag, rd->rdata_dmap);
2000			bus_dmamem_free(sc->sc_rxring_dtag, rd->rdata_desc,
2001					rd->rdata_dmap);
2002		}
2003		bus_dma_tag_destroy(sc->sc_rxring_dtag);
2004	}
2005
2006	bwi_dma_txstats_free(sc);
2007	bwi_dma_mbuf_destroy(sc, BWI_TX_NRING, 1);
2008
2009	if (sc->sc_parent_dtag != NULL)
2010		bus_dma_tag_destroy(sc->sc_parent_dtag);
2011}
2012
2013static int
2014bwi_dma_ring_alloc(struct bwi_softc *sc, bus_dma_tag_t dtag,
2015		   struct bwi_ring_data *rd, bus_size_t size,
2016		   uint32_t txrx_ctrl)
2017{
2018	int error;
2019
2020	error = bus_dmamem_alloc(dtag, &rd->rdata_desc,
2021				 BUS_DMA_WAITOK | BUS_DMA_ZERO,
2022				 &rd->rdata_dmap);
2023	if (error) {
2024		device_printf(sc->sc_dev, "can't allocate DMA mem\n");
2025		return error;
2026	}
2027
2028	error = bus_dmamap_load(dtag, rd->rdata_dmap, rd->rdata_desc, size,
2029				bwi_dma_ring_addr, &rd->rdata_paddr,
2030				BUS_DMA_NOWAIT);
2031	if (error) {
2032		device_printf(sc->sc_dev, "can't load DMA mem\n");
2033		bus_dmamem_free(dtag, rd->rdata_desc, rd->rdata_dmap);
2034		rd->rdata_desc = NULL;
2035		return error;
2036	}
2037
2038	rd->rdata_txrx_ctrl = txrx_ctrl;
2039	return 0;
2040}
2041
2042static int
2043bwi_dma_txstats_alloc(struct bwi_softc *sc, uint32_t ctrl_base,
2044		      bus_size_t desc_sz)
2045{
2046	struct bwi_txstats_data *st;
2047	bus_size_t dma_size;
2048	int error;
2049
2050	st = malloc(sizeof(*st), M_DEVBUF, M_NOWAIT | M_ZERO);
2051	if (st == NULL) {
2052		device_printf(sc->sc_dev, "can't allocate txstats data\n");
2053		return ENOMEM;
2054	}
2055	sc->sc_txstats = st;
2056
2057	/*
2058	 * Create TX stats descriptor DMA stuffs
2059	 */
2060	dma_size = roundup(desc_sz * BWI_TXSTATS_NDESC, BWI_RING_ALIGN);
2061
2062	error = bus_dma_tag_create(sc->sc_parent_dtag,
2063				BWI_RING_ALIGN,
2064				0,
2065				BUS_SPACE_MAXADDR,
2066				BUS_SPACE_MAXADDR,
2067				NULL, NULL,
2068				dma_size,
2069				1,
2070				dma_size,
2071				0,
2072				NULL, NULL,
2073				&st->stats_ring_dtag);
2074	if (error) {
2075		device_printf(sc->sc_dev, "can't create txstats ring "
2076			      "DMA tag\n");
2077		return error;
2078	}
2079
2080	error = bus_dmamem_alloc(st->stats_ring_dtag, &st->stats_ring,
2081				 BUS_DMA_WAITOK | BUS_DMA_ZERO,
2082				 &st->stats_ring_dmap);
2083	if (error) {
2084		device_printf(sc->sc_dev, "can't allocate txstats ring "
2085			      "DMA mem\n");
2086		bus_dma_tag_destroy(st->stats_ring_dtag);
2087		st->stats_ring_dtag = NULL;
2088		return error;
2089	}
2090
2091	error = bus_dmamap_load(st->stats_ring_dtag, st->stats_ring_dmap,
2092				st->stats_ring, dma_size,
2093				bwi_dma_ring_addr, &st->stats_ring_paddr,
2094				BUS_DMA_NOWAIT);
2095	if (error) {
2096		device_printf(sc->sc_dev, "can't load txstats ring DMA mem\n");
2097		bus_dmamem_free(st->stats_ring_dtag, st->stats_ring,
2098				st->stats_ring_dmap);
2099		bus_dma_tag_destroy(st->stats_ring_dtag);
2100		st->stats_ring_dtag = NULL;
2101		return error;
2102	}
2103
2104	/*
2105	 * Create TX stats DMA stuffs
2106	 */
2107	dma_size = roundup(sizeof(struct bwi_txstats) * BWI_TXSTATS_NDESC,
2108			   BWI_ALIGN);
2109
2110	error = bus_dma_tag_create(sc->sc_parent_dtag,
2111				BWI_ALIGN,
2112				0,
2113				BUS_SPACE_MAXADDR,
2114				BUS_SPACE_MAXADDR,
2115				NULL, NULL,
2116				dma_size,
2117				1,
2118				dma_size,
2119				0,
2120				NULL, NULL,
2121				&st->stats_dtag);
2122	if (error) {
2123		device_printf(sc->sc_dev, "can't create txstats DMA tag\n");
2124		return error;
2125	}
2126
2127	error = bus_dmamem_alloc(st->stats_dtag, (void **)&st->stats,
2128				 BUS_DMA_WAITOK | BUS_DMA_ZERO,
2129				 &st->stats_dmap);
2130	if (error) {
2131		device_printf(sc->sc_dev, "can't allocate txstats DMA mem\n");
2132		bus_dma_tag_destroy(st->stats_dtag);
2133		st->stats_dtag = NULL;
2134		return error;
2135	}
2136
2137	error = bus_dmamap_load(st->stats_dtag, st->stats_dmap, st->stats,
2138				dma_size, bwi_dma_ring_addr, &st->stats_paddr,
2139				BUS_DMA_NOWAIT);
2140	if (error) {
2141		device_printf(sc->sc_dev, "can't load txstats DMA mem\n");
2142		bus_dmamem_free(st->stats_dtag, st->stats, st->stats_dmap);
2143		bus_dma_tag_destroy(st->stats_dtag);
2144		st->stats_dtag = NULL;
2145		return error;
2146	}
2147
2148	st->stats_ctrl_base = ctrl_base;
2149	return 0;
2150}
2151
2152static void
2153bwi_dma_txstats_free(struct bwi_softc *sc)
2154{
2155	struct bwi_txstats_data *st;
2156
2157	if (sc->sc_txstats == NULL)
2158		return;
2159	st = sc->sc_txstats;
2160
2161	if (st->stats_ring_dtag != NULL) {
2162		bus_dmamap_unload(st->stats_ring_dtag, st->stats_ring_dmap);
2163		bus_dmamem_free(st->stats_ring_dtag, st->stats_ring,
2164				st->stats_ring_dmap);
2165		bus_dma_tag_destroy(st->stats_ring_dtag);
2166	}
2167
2168	if (st->stats_dtag != NULL) {
2169		bus_dmamap_unload(st->stats_dtag, st->stats_dmap);
2170		bus_dmamem_free(st->stats_dtag, st->stats, st->stats_dmap);
2171		bus_dma_tag_destroy(st->stats_dtag);
2172	}
2173
2174	free(st, M_DEVBUF);
2175}
2176
2177static void
2178bwi_dma_ring_addr(void *arg, bus_dma_segment_t *seg, int nseg, int error)
2179{
2180	KASSERT(nseg == 1, ("too many segments\n"));
2181	*((bus_addr_t *)arg) = seg->ds_addr;
2182}
2183
2184static int
2185bwi_dma_mbuf_create(struct bwi_softc *sc)
2186{
2187	struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata;
2188	int i, j, k, ntx, error;
2189
2190	/*
2191	 * Create TX/RX mbuf DMA tag
2192	 */
2193	error = bus_dma_tag_create(sc->sc_parent_dtag,
2194				1,
2195				0,
2196				BUS_SPACE_MAXADDR,
2197				BUS_SPACE_MAXADDR,
2198				NULL, NULL,
2199				MCLBYTES,
2200				1,
2201				MCLBYTES,
2202				BUS_DMA_ALLOCNOW,
2203				NULL, NULL,
2204				&sc->sc_buf_dtag);
2205	if (error) {
2206		device_printf(sc->sc_dev, "can't create mbuf DMA tag\n");
2207		return error;
2208	}
2209
2210	ntx = 0;
2211
2212	/*
2213	 * Create TX mbuf DMA map
2214	 */
2215	for (i = 0; i < BWI_TX_NRING; ++i) {
2216		struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[i];
2217
2218		for (j = 0; j < BWI_TX_NDESC; ++j) {
2219			error = bus_dmamap_create(sc->sc_buf_dtag, 0,
2220						  &tbd->tbd_buf[j].tb_dmap);
2221			if (error) {
2222				device_printf(sc->sc_dev, "can't create "
2223					      "%dth tbd, %dth DMA map\n", i, j);
2224
2225				ntx = i;
2226				for (k = 0; k < j; ++k) {
2227					bus_dmamap_destroy(sc->sc_buf_dtag,
2228						tbd->tbd_buf[k].tb_dmap);
2229				}
2230				goto fail;
2231			}
2232		}
2233	}
2234	ntx = BWI_TX_NRING;
2235
2236	/*
2237	 * Create RX mbuf DMA map and a spare DMA map
2238	 */
2239	error = bus_dmamap_create(sc->sc_buf_dtag, 0,
2240				  &rbd->rbd_tmp_dmap);
2241	if (error) {
2242		device_printf(sc->sc_dev,
2243			      "can't create spare RX buf DMA map\n");
2244		goto fail;
2245	}
2246
2247	for (j = 0; j < BWI_RX_NDESC; ++j) {
2248		error = bus_dmamap_create(sc->sc_buf_dtag, 0,
2249					  &rbd->rbd_buf[j].rb_dmap);
2250		if (error) {
2251			device_printf(sc->sc_dev, "can't create %dth "
2252				      "RX buf DMA map\n", j);
2253
2254			for (k = 0; k < j; ++k) {
2255				bus_dmamap_destroy(sc->sc_buf_dtag,
2256					rbd->rbd_buf[j].rb_dmap);
2257			}
2258			bus_dmamap_destroy(sc->sc_buf_dtag,
2259					   rbd->rbd_tmp_dmap);
2260			goto fail;
2261		}
2262	}
2263
2264	return 0;
2265fail:
2266	bwi_dma_mbuf_destroy(sc, ntx, 0);
2267	return error;
2268}
2269
2270static void
2271bwi_dma_mbuf_destroy(struct bwi_softc *sc, int ntx, int nrx)
2272{
2273	int i, j;
2274
2275	if (sc->sc_buf_dtag == NULL)
2276		return;
2277
2278	for (i = 0; i < ntx; ++i) {
2279		struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[i];
2280
2281		for (j = 0; j < BWI_TX_NDESC; ++j) {
2282			struct bwi_txbuf *tb = &tbd->tbd_buf[j];
2283
2284			if (tb->tb_mbuf != NULL) {
2285				bus_dmamap_unload(sc->sc_buf_dtag,
2286						  tb->tb_dmap);
2287				m_freem(tb->tb_mbuf);
2288			}
2289			if (tb->tb_ni != NULL)
2290				ieee80211_free_node(tb->tb_ni);
2291			bus_dmamap_destroy(sc->sc_buf_dtag, tb->tb_dmap);
2292		}
2293	}
2294
2295	if (nrx) {
2296		struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata;
2297
2298		bus_dmamap_destroy(sc->sc_buf_dtag, rbd->rbd_tmp_dmap);
2299		for (j = 0; j < BWI_RX_NDESC; ++j) {
2300			struct bwi_rxbuf *rb = &rbd->rbd_buf[j];
2301
2302			if (rb->rb_mbuf != NULL) {
2303				bus_dmamap_unload(sc->sc_buf_dtag,
2304						  rb->rb_dmap);
2305				m_freem(rb->rb_mbuf);
2306			}
2307			bus_dmamap_destroy(sc->sc_buf_dtag, rb->rb_dmap);
2308		}
2309	}
2310
2311	bus_dma_tag_destroy(sc->sc_buf_dtag);
2312	sc->sc_buf_dtag = NULL;
2313}
2314
2315static void
2316bwi_enable_intrs(struct bwi_softc *sc, uint32_t enable_intrs)
2317{
2318	CSR_SETBITS_4(sc, BWI_MAC_INTR_MASK, enable_intrs);
2319}
2320
2321static void
2322bwi_disable_intrs(struct bwi_softc *sc, uint32_t disable_intrs)
2323{
2324	CSR_CLRBITS_4(sc, BWI_MAC_INTR_MASK, disable_intrs);
2325}
2326
2327static int
2328bwi_init_tx_ring32(struct bwi_softc *sc, int ring_idx)
2329{
2330	struct bwi_ring_data *rd;
2331	struct bwi_txbuf_data *tbd;
2332	uint32_t val, addr_hi, addr_lo;
2333
2334	KASSERT(ring_idx < BWI_TX_NRING, ("ring_idx %d", ring_idx));
2335	rd = &sc->sc_tx_rdata[ring_idx];
2336	tbd = &sc->sc_tx_bdata[ring_idx];
2337
2338	tbd->tbd_idx = 0;
2339	tbd->tbd_used = 0;
2340
2341	bzero(rd->rdata_desc, sizeof(struct bwi_desc32) * BWI_TX_NDESC);
2342	bus_dmamap_sync(sc->sc_txring_dtag, rd->rdata_dmap,
2343			BUS_DMASYNC_PREWRITE);
2344
2345	addr_lo = __SHIFTOUT(rd->rdata_paddr, BWI_TXRX32_RINGINFO_ADDR_MASK);
2346	addr_hi = __SHIFTOUT(rd->rdata_paddr, BWI_TXRX32_RINGINFO_FUNC_MASK);
2347
2348	val = __SHIFTIN(addr_lo, BWI_TXRX32_RINGINFO_ADDR_MASK) |
2349	      __SHIFTIN(BWI_TXRX32_RINGINFO_FUNC_TXRX,
2350	      		BWI_TXRX32_RINGINFO_FUNC_MASK);
2351	CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_RINGINFO, val);
2352
2353	val = __SHIFTIN(addr_hi, BWI_TXRX32_CTRL_ADDRHI_MASK) |
2354	      BWI_TXRX32_CTRL_ENABLE;
2355	CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_CTRL, val);
2356
2357	return 0;
2358}
2359
2360static void
2361bwi_init_rxdesc_ring32(struct bwi_softc *sc, uint32_t ctrl_base,
2362		       bus_addr_t paddr, int hdr_size, int ndesc)
2363{
2364	uint32_t val, addr_hi, addr_lo;
2365
2366	addr_lo = __SHIFTOUT(paddr, BWI_TXRX32_RINGINFO_ADDR_MASK);
2367	addr_hi = __SHIFTOUT(paddr, BWI_TXRX32_RINGINFO_FUNC_MASK);
2368
2369	val = __SHIFTIN(addr_lo, BWI_TXRX32_RINGINFO_ADDR_MASK) |
2370	      __SHIFTIN(BWI_TXRX32_RINGINFO_FUNC_TXRX,
2371	      		BWI_TXRX32_RINGINFO_FUNC_MASK);
2372	CSR_WRITE_4(sc, ctrl_base + BWI_RX32_RINGINFO, val);
2373
2374	val = __SHIFTIN(hdr_size, BWI_RX32_CTRL_HDRSZ_MASK) |
2375	      __SHIFTIN(addr_hi, BWI_TXRX32_CTRL_ADDRHI_MASK) |
2376	      BWI_TXRX32_CTRL_ENABLE;
2377	CSR_WRITE_4(sc, ctrl_base + BWI_RX32_CTRL, val);
2378
2379	CSR_WRITE_4(sc, ctrl_base + BWI_RX32_INDEX,
2380		    (ndesc - 1) * sizeof(struct bwi_desc32));
2381}
2382
2383static int
2384bwi_init_rx_ring32(struct bwi_softc *sc)
2385{
2386	struct bwi_ring_data *rd = &sc->sc_rx_rdata;
2387	int i, error;
2388
2389	sc->sc_rx_bdata.rbd_idx = 0;
2390
2391	for (i = 0; i < BWI_RX_NDESC; ++i) {
2392		error = bwi_newbuf(sc, i, 1);
2393		if (error) {
2394			device_printf(sc->sc_dev,
2395				  "can't allocate %dth RX buffer\n", i);
2396			return error;
2397		}
2398	}
2399	bus_dmamap_sync(sc->sc_rxring_dtag, rd->rdata_dmap,
2400			BUS_DMASYNC_PREWRITE);
2401
2402	bwi_init_rxdesc_ring32(sc, rd->rdata_txrx_ctrl, rd->rdata_paddr,
2403			       sizeof(struct bwi_rxbuf_hdr), BWI_RX_NDESC);
2404	return 0;
2405}
2406
2407static int
2408bwi_init_txstats32(struct bwi_softc *sc)
2409{
2410	struct bwi_txstats_data *st = sc->sc_txstats;
2411	bus_addr_t stats_paddr;
2412	int i;
2413
2414	bzero(st->stats, BWI_TXSTATS_NDESC * sizeof(struct bwi_txstats));
2415	bus_dmamap_sync(st->stats_dtag, st->stats_dmap, BUS_DMASYNC_PREWRITE);
2416
2417	st->stats_idx = 0;
2418
2419	stats_paddr = st->stats_paddr;
2420	for (i = 0; i < BWI_TXSTATS_NDESC; ++i) {
2421		bwi_setup_desc32(sc, st->stats_ring, BWI_TXSTATS_NDESC, i,
2422				 stats_paddr, sizeof(struct bwi_txstats), 0);
2423		stats_paddr += sizeof(struct bwi_txstats);
2424	}
2425	bus_dmamap_sync(st->stats_ring_dtag, st->stats_ring_dmap,
2426			BUS_DMASYNC_PREWRITE);
2427
2428	bwi_init_rxdesc_ring32(sc, st->stats_ctrl_base,
2429			       st->stats_ring_paddr, 0, BWI_TXSTATS_NDESC);
2430	return 0;
2431}
2432
2433static void
2434bwi_setup_rx_desc32(struct bwi_softc *sc, int buf_idx, bus_addr_t paddr,
2435		    int buf_len)
2436{
2437	struct bwi_ring_data *rd = &sc->sc_rx_rdata;
2438
2439	KASSERT(buf_idx < BWI_RX_NDESC, ("buf_idx %d", buf_idx));
2440	bwi_setup_desc32(sc, rd->rdata_desc, BWI_RX_NDESC, buf_idx,
2441			 paddr, buf_len, 0);
2442}
2443
2444static void
2445bwi_setup_tx_desc32(struct bwi_softc *sc, struct bwi_ring_data *rd,
2446		    int buf_idx, bus_addr_t paddr, int buf_len)
2447{
2448	KASSERT(buf_idx < BWI_TX_NDESC, ("buf_idx %d", buf_idx));
2449	bwi_setup_desc32(sc, rd->rdata_desc, BWI_TX_NDESC, buf_idx,
2450			 paddr, buf_len, 1);
2451}
2452
2453static int
2454bwi_init_tx_ring64(struct bwi_softc *sc, int ring_idx)
2455{
2456	/* TODO:64 */
2457	return EOPNOTSUPP;
2458}
2459
2460static int
2461bwi_init_rx_ring64(struct bwi_softc *sc)
2462{
2463	/* TODO:64 */
2464	return EOPNOTSUPP;
2465}
2466
2467static int
2468bwi_init_txstats64(struct bwi_softc *sc)
2469{
2470	/* TODO:64 */
2471	return EOPNOTSUPP;
2472}
2473
2474static void
2475bwi_setup_rx_desc64(struct bwi_softc *sc, int buf_idx, bus_addr_t paddr,
2476		    int buf_len)
2477{
2478	/* TODO:64 */
2479}
2480
2481static void
2482bwi_setup_tx_desc64(struct bwi_softc *sc, struct bwi_ring_data *rd,
2483		    int buf_idx, bus_addr_t paddr, int buf_len)
2484{
2485	/* TODO:64 */
2486}
2487
2488static void
2489bwi_dma_buf_addr(void *arg, bus_dma_segment_t *seg, int nseg,
2490		 bus_size_t mapsz __unused, int error)
2491{
2492        if (!error) {
2493		KASSERT(nseg == 1, ("too many segments(%d)\n", nseg));
2494		*((bus_addr_t *)arg) = seg->ds_addr;
2495	}
2496}
2497
2498static int
2499bwi_newbuf(struct bwi_softc *sc, int buf_idx, int init)
2500{
2501	struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata;
2502	struct bwi_rxbuf *rxbuf = &rbd->rbd_buf[buf_idx];
2503	struct bwi_rxbuf_hdr *hdr;
2504	bus_dmamap_t map;
2505	bus_addr_t paddr;
2506	struct mbuf *m;
2507	int error;
2508
2509	KASSERT(buf_idx < BWI_RX_NDESC, ("buf_idx %d", buf_idx));
2510
2511	m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
2512	if (m == NULL) {
2513		error = ENOBUFS;
2514
2515		/*
2516		 * If the NIC is up and running, we need to:
2517		 * - Clear RX buffer's header.
2518		 * - Restore RX descriptor settings.
2519		 */
2520		if (init)
2521			return error;
2522		else
2523			goto back;
2524	}
2525	m->m_len = m->m_pkthdr.len = MCLBYTES;
2526
2527	/*
2528	 * Try to load RX buf into temporary DMA map
2529	 */
2530	error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, rbd->rbd_tmp_dmap, m,
2531				     bwi_dma_buf_addr, &paddr, BUS_DMA_NOWAIT);
2532	if (error) {
2533		m_freem(m);
2534
2535		/*
2536		 * See the comment above
2537		 */
2538		if (init)
2539			return error;
2540		else
2541			goto back;
2542	}
2543
2544	if (!init)
2545		bus_dmamap_unload(sc->sc_buf_dtag, rxbuf->rb_dmap);
2546	rxbuf->rb_mbuf = m;
2547	rxbuf->rb_paddr = paddr;
2548
2549	/*
2550	 * Swap RX buf's DMA map with the loaded temporary one
2551	 */
2552	map = rxbuf->rb_dmap;
2553	rxbuf->rb_dmap = rbd->rbd_tmp_dmap;
2554	rbd->rbd_tmp_dmap = map;
2555
2556back:
2557	/*
2558	 * Clear RX buf header
2559	 */
2560	hdr = mtod(rxbuf->rb_mbuf, struct bwi_rxbuf_hdr *);
2561	bzero(hdr, sizeof(*hdr));
2562	bus_dmamap_sync(sc->sc_buf_dtag, rxbuf->rb_dmap, BUS_DMASYNC_PREWRITE);
2563
2564	/*
2565	 * Setup RX buf descriptor
2566	 */
2567	sc->sc_setup_rxdesc(sc, buf_idx, rxbuf->rb_paddr,
2568			    rxbuf->rb_mbuf->m_len - sizeof(*hdr));
2569	return error;
2570}
2571
2572static void
2573bwi_set_addr_filter(struct bwi_softc *sc, uint16_t addr_ofs,
2574		    const uint8_t *addr)
2575{
2576	int i;
2577
2578	CSR_WRITE_2(sc, BWI_ADDR_FILTER_CTRL,
2579		    BWI_ADDR_FILTER_CTRL_SET | addr_ofs);
2580
2581	for (i = 0; i < (IEEE80211_ADDR_LEN / 2); ++i) {
2582		uint16_t addr_val;
2583
2584		addr_val = (uint16_t)addr[i * 2] |
2585			   (((uint16_t)addr[(i * 2) + 1]) << 8);
2586		CSR_WRITE_2(sc, BWI_ADDR_FILTER_DATA, addr_val);
2587	}
2588}
2589
2590static int
2591bwi_rxeof(struct bwi_softc *sc, int end_idx)
2592{
2593	struct bwi_ring_data *rd = &sc->sc_rx_rdata;
2594	struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata;
2595	struct ieee80211com *ic = &sc->sc_ic;
2596	int idx, rx_data = 0;
2597
2598	idx = rbd->rbd_idx;
2599	while (idx != end_idx) {
2600		struct bwi_rxbuf *rb = &rbd->rbd_buf[idx];
2601		struct bwi_rxbuf_hdr *hdr;
2602		struct ieee80211_frame_min *wh;
2603		struct ieee80211_node *ni;
2604		struct mbuf *m;
2605		uint32_t plcp;
2606		uint16_t flags2;
2607		int buflen, wh_ofs, hdr_extra, rssi, noise, type, rate;
2608
2609		m = rb->rb_mbuf;
2610		bus_dmamap_sync(sc->sc_buf_dtag, rb->rb_dmap,
2611				BUS_DMASYNC_POSTREAD);
2612
2613		if (bwi_newbuf(sc, idx, 0)) {
2614			counter_u64_add(ic->ic_ierrors, 1);
2615			goto next;
2616		}
2617
2618		hdr = mtod(m, struct bwi_rxbuf_hdr *);
2619		flags2 = le16toh(hdr->rxh_flags2);
2620
2621		hdr_extra = 0;
2622		if (flags2 & BWI_RXH_F2_TYPE2FRAME)
2623			hdr_extra = 2;
2624		wh_ofs = hdr_extra + 6;	/* XXX magic number */
2625
2626		buflen = le16toh(hdr->rxh_buflen);
2627		if (buflen < BWI_FRAME_MIN_LEN(wh_ofs)) {
2628			device_printf(sc->sc_dev,
2629			    "%s: zero length data, hdr_extra %d\n",
2630			    __func__, hdr_extra);
2631			counter_u64_add(ic->ic_ierrors, 1);
2632			m_freem(m);
2633			goto next;
2634		}
2635
2636	        bcopy((uint8_t *)(hdr + 1) + hdr_extra, &plcp, sizeof(plcp));
2637		rssi = bwi_calc_rssi(sc, hdr);
2638		noise = bwi_calc_noise(sc);
2639
2640		m->m_len = m->m_pkthdr.len = buflen + sizeof(*hdr);
2641		m_adj(m, sizeof(*hdr) + wh_ofs);
2642
2643		if (htole16(hdr->rxh_flags1) & BWI_RXH_F1_OFDM)
2644			rate = bwi_plcp2rate(plcp, IEEE80211_T_OFDM);
2645		else
2646			rate = bwi_plcp2rate(plcp, IEEE80211_T_CCK);
2647
2648		/* RX radio tap */
2649		if (ieee80211_radiotap_active(ic))
2650			bwi_rx_radiotap(sc, m, hdr, &plcp, rate, rssi, noise);
2651
2652		m_adj(m, -IEEE80211_CRC_LEN);
2653
2654		BWI_UNLOCK(sc);
2655
2656		wh = mtod(m, struct ieee80211_frame_min *);
2657		ni = ieee80211_find_rxnode(ic, wh);
2658		if (ni != NULL) {
2659			type = ieee80211_input(ni, m, rssi - noise, noise);
2660			ieee80211_free_node(ni);
2661		} else
2662			type = ieee80211_input_all(ic, m, rssi - noise, noise);
2663		if (type == IEEE80211_FC0_TYPE_DATA) {
2664			rx_data = 1;
2665			sc->sc_rx_rate = rate;
2666		}
2667
2668		BWI_LOCK(sc);
2669next:
2670		idx = (idx + 1) % BWI_RX_NDESC;
2671
2672		if (sc->sc_flags & BWI_F_STOP) {
2673			/*
2674			 * Take the fast lane, don't do
2675			 * any damage to softc
2676			 */
2677			return -1;
2678		}
2679	}
2680
2681	rbd->rbd_idx = idx;
2682	bus_dmamap_sync(sc->sc_rxring_dtag, rd->rdata_dmap,
2683			BUS_DMASYNC_PREWRITE);
2684
2685	return rx_data;
2686}
2687
2688static int
2689bwi_rxeof32(struct bwi_softc *sc)
2690{
2691	uint32_t val, rx_ctrl;
2692	int end_idx, rx_data;
2693
2694	rx_ctrl = sc->sc_rx_rdata.rdata_txrx_ctrl;
2695
2696	val = CSR_READ_4(sc, rx_ctrl + BWI_RX32_STATUS);
2697	end_idx = __SHIFTOUT(val, BWI_RX32_STATUS_INDEX_MASK) /
2698		  sizeof(struct bwi_desc32);
2699
2700	rx_data = bwi_rxeof(sc, end_idx);
2701	if (rx_data >= 0) {
2702		CSR_WRITE_4(sc, rx_ctrl + BWI_RX32_INDEX,
2703			    end_idx * sizeof(struct bwi_desc32));
2704	}
2705	return rx_data;
2706}
2707
2708static int
2709bwi_rxeof64(struct bwi_softc *sc)
2710{
2711	/* TODO:64 */
2712	return 0;
2713}
2714
2715static void
2716bwi_reset_rx_ring32(struct bwi_softc *sc, uint32_t rx_ctrl)
2717{
2718	int i;
2719
2720	CSR_WRITE_4(sc, rx_ctrl + BWI_RX32_CTRL, 0);
2721
2722#define NRETRY 10
2723
2724	for (i = 0; i < NRETRY; ++i) {
2725		uint32_t status;
2726
2727		status = CSR_READ_4(sc, rx_ctrl + BWI_RX32_STATUS);
2728		if (__SHIFTOUT(status, BWI_RX32_STATUS_STATE_MASK) ==
2729		    BWI_RX32_STATUS_STATE_DISABLED)
2730			break;
2731
2732		DELAY(1000);
2733	}
2734	if (i == NRETRY)
2735		device_printf(sc->sc_dev, "reset rx ring timedout\n");
2736
2737#undef NRETRY
2738
2739	CSR_WRITE_4(sc, rx_ctrl + BWI_RX32_RINGINFO, 0);
2740}
2741
2742static void
2743bwi_free_txstats32(struct bwi_softc *sc)
2744{
2745	bwi_reset_rx_ring32(sc, sc->sc_txstats->stats_ctrl_base);
2746}
2747
2748static void
2749bwi_free_rx_ring32(struct bwi_softc *sc)
2750{
2751	struct bwi_ring_data *rd = &sc->sc_rx_rdata;
2752	struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata;
2753	int i;
2754
2755	bwi_reset_rx_ring32(sc, rd->rdata_txrx_ctrl);
2756
2757	for (i = 0; i < BWI_RX_NDESC; ++i) {
2758		struct bwi_rxbuf *rb = &rbd->rbd_buf[i];
2759
2760		if (rb->rb_mbuf != NULL) {
2761			bus_dmamap_unload(sc->sc_buf_dtag, rb->rb_dmap);
2762			m_freem(rb->rb_mbuf);
2763			rb->rb_mbuf = NULL;
2764		}
2765	}
2766}
2767
2768static void
2769bwi_free_tx_ring32(struct bwi_softc *sc, int ring_idx)
2770{
2771	struct bwi_ring_data *rd;
2772	struct bwi_txbuf_data *tbd;
2773	uint32_t state, val;
2774	int i;
2775
2776	KASSERT(ring_idx < BWI_TX_NRING, ("ring_idx %d", ring_idx));
2777	rd = &sc->sc_tx_rdata[ring_idx];
2778	tbd = &sc->sc_tx_bdata[ring_idx];
2779
2780#define NRETRY 10
2781
2782	for (i = 0; i < NRETRY; ++i) {
2783		val = CSR_READ_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_STATUS);
2784		state = __SHIFTOUT(val, BWI_TX32_STATUS_STATE_MASK);
2785		if (state == BWI_TX32_STATUS_STATE_DISABLED ||
2786		    state == BWI_TX32_STATUS_STATE_IDLE ||
2787		    state == BWI_TX32_STATUS_STATE_STOPPED)
2788			break;
2789
2790		DELAY(1000);
2791	}
2792	if (i == NRETRY) {
2793		device_printf(sc->sc_dev,
2794		    "%s: wait for TX ring(%d) stable timed out\n",
2795		    __func__, ring_idx);
2796	}
2797
2798	CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_CTRL, 0);
2799	for (i = 0; i < NRETRY; ++i) {
2800		val = CSR_READ_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_STATUS);
2801		state = __SHIFTOUT(val, BWI_TX32_STATUS_STATE_MASK);
2802		if (state == BWI_TX32_STATUS_STATE_DISABLED)
2803			break;
2804
2805		DELAY(1000);
2806	}
2807	if (i == NRETRY)
2808		device_printf(sc->sc_dev, "%s: reset TX ring (%d) timed out\n",
2809		     __func__, ring_idx);
2810
2811#undef NRETRY
2812
2813	DELAY(1000);
2814
2815	CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_RINGINFO, 0);
2816
2817	for (i = 0; i < BWI_TX_NDESC; ++i) {
2818		struct bwi_txbuf *tb = &tbd->tbd_buf[i];
2819
2820		if (tb->tb_mbuf != NULL) {
2821			bus_dmamap_unload(sc->sc_buf_dtag, tb->tb_dmap);
2822			m_freem(tb->tb_mbuf);
2823			tb->tb_mbuf = NULL;
2824		}
2825		if (tb->tb_ni != NULL) {
2826			ieee80211_free_node(tb->tb_ni);
2827			tb->tb_ni = NULL;
2828		}
2829	}
2830}
2831
2832static void
2833bwi_free_txstats64(struct bwi_softc *sc)
2834{
2835	/* TODO:64 */
2836}
2837
2838static void
2839bwi_free_rx_ring64(struct bwi_softc *sc)
2840{
2841	/* TODO:64 */
2842}
2843
2844static void
2845bwi_free_tx_ring64(struct bwi_softc *sc, int ring_idx)
2846{
2847	/* TODO:64 */
2848}
2849
2850/* XXX does not belong here */
2851#define IEEE80211_OFDM_PLCP_RATE_MASK	__BITS(3, 0)
2852#define IEEE80211_OFDM_PLCP_LEN_MASK	__BITS(16, 5)
2853
2854static __inline void
2855bwi_ofdm_plcp_header(uint32_t *plcp0, int pkt_len, uint8_t rate)
2856{
2857	uint32_t plcp;
2858
2859	plcp = __SHIFTIN(ieee80211_rate2plcp(rate, IEEE80211_T_OFDM),
2860		    IEEE80211_OFDM_PLCP_RATE_MASK) |
2861	       __SHIFTIN(pkt_len, IEEE80211_OFDM_PLCP_LEN_MASK);
2862	*plcp0 = htole32(plcp);
2863}
2864
2865static __inline void
2866bwi_ds_plcp_header(struct ieee80211_ds_plcp_hdr *plcp, int pkt_len,
2867		   uint8_t rate)
2868{
2869	int len, service, pkt_bitlen;
2870
2871	pkt_bitlen = pkt_len * NBBY;
2872	len = howmany(pkt_bitlen * 2, rate);
2873
2874	service = IEEE80211_PLCP_SERVICE_LOCKED;
2875	if (rate == (11 * 2)) {
2876		int pkt_bitlen1;
2877
2878		/*
2879		 * PLCP service field needs to be adjusted,
2880		 * if TX rate is 11Mbytes/s
2881		 */
2882		pkt_bitlen1 = len * 11;
2883		if (pkt_bitlen1 - pkt_bitlen >= NBBY)
2884			service |= IEEE80211_PLCP_SERVICE_LENEXT7;
2885	}
2886
2887	plcp->i_signal = ieee80211_rate2plcp(rate, IEEE80211_T_CCK);
2888	plcp->i_service = service;
2889	plcp->i_length = htole16(len);
2890	/* NOTE: do NOT touch i_crc */
2891}
2892
2893static __inline void
2894bwi_plcp_header(const struct ieee80211_rate_table *rt,
2895	void *plcp, int pkt_len, uint8_t rate)
2896{
2897	enum ieee80211_phytype modtype;
2898
2899	/*
2900	 * Assume caller has zeroed 'plcp'
2901	 */
2902	modtype = ieee80211_rate2phytype(rt, rate);
2903	if (modtype == IEEE80211_T_OFDM)
2904		bwi_ofdm_plcp_header(plcp, pkt_len, rate);
2905	else if (modtype == IEEE80211_T_DS)
2906		bwi_ds_plcp_header(plcp, pkt_len, rate);
2907	else
2908		panic("unsupport modulation type %u\n", modtype);
2909}
2910
2911static int
2912bwi_encap(struct bwi_softc *sc, int idx, struct mbuf *m,
2913	  struct ieee80211_node *ni)
2914{
2915	struct ieee80211vap *vap = ni->ni_vap;
2916	struct ieee80211com *ic = &sc->sc_ic;
2917	struct bwi_ring_data *rd = &sc->sc_tx_rdata[BWI_TX_DATA_RING];
2918	struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[BWI_TX_DATA_RING];
2919	struct bwi_txbuf *tb = &tbd->tbd_buf[idx];
2920	struct bwi_mac *mac;
2921	struct bwi_txbuf_hdr *hdr;
2922	struct ieee80211_frame *wh;
2923	const struct ieee80211_txparam *tp;
2924	uint8_t rate, rate_fb;
2925	uint32_t mac_ctrl;
2926	uint16_t phy_ctrl;
2927	bus_addr_t paddr;
2928	int type, ismcast, pkt_len, error, rix;
2929#if 0
2930	const uint8_t *p;
2931	int i;
2932#endif
2933
2934	KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC,
2935	    ("current regwin type %d", sc->sc_cur_regwin->rw_type));
2936	mac = (struct bwi_mac *)sc->sc_cur_regwin;
2937
2938	wh = mtod(m, struct ieee80211_frame *);
2939	type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK;
2940	ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1);
2941
2942	/* Get 802.11 frame len before prepending TX header */
2943	pkt_len = m->m_pkthdr.len + IEEE80211_CRC_LEN;
2944
2945	/*
2946	 * Find TX rate
2947	 */
2948	tp = &vap->iv_txparms[ieee80211_chan2mode(ic->ic_curchan)];
2949	if (type != IEEE80211_FC0_TYPE_DATA || (m->m_flags & M_EAPOL)) {
2950		rate = rate_fb = tp->mgmtrate;
2951	} else if (ismcast) {
2952		rate = rate_fb = tp->mcastrate;
2953	} else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) {
2954		rate = rate_fb = tp->ucastrate;
2955	} else {
2956		rix = ieee80211_ratectl_rate(ni, NULL, pkt_len);
2957		rate = ni->ni_txrate;
2958
2959		if (rix > 0) {
2960			rate_fb = ni->ni_rates.rs_rates[rix-1] &
2961				  IEEE80211_RATE_VAL;
2962		} else {
2963			rate_fb = rate;
2964		}
2965	}
2966	tb->tb_rate[0] = rate;
2967	tb->tb_rate[1] = rate_fb;
2968	sc->sc_tx_rate = rate;
2969
2970	/*
2971	 * TX radio tap
2972	 */
2973	if (ieee80211_radiotap_active_vap(vap)) {
2974		sc->sc_tx_th.wt_flags = 0;
2975		if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED)
2976			sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP;
2977		if (ieee80211_rate2phytype(sc->sc_rates, rate) == IEEE80211_T_DS &&
2978		    (ic->ic_flags & IEEE80211_F_SHPREAMBLE) &&
2979		    rate != (1 * 2)) {
2980			sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
2981		}
2982		sc->sc_tx_th.wt_rate = rate;
2983
2984		ieee80211_radiotap_tx(vap, m);
2985	}
2986
2987	/*
2988	 * Setup the embedded TX header
2989	 */
2990	M_PREPEND(m, sizeof(*hdr), M_NOWAIT);
2991	if (m == NULL) {
2992		device_printf(sc->sc_dev, "%s: prepend TX header failed\n",
2993		    __func__);
2994		return ENOBUFS;
2995	}
2996	hdr = mtod(m, struct bwi_txbuf_hdr *);
2997
2998	bzero(hdr, sizeof(*hdr));
2999
3000	bcopy(wh->i_fc, hdr->txh_fc, sizeof(hdr->txh_fc));
3001	bcopy(wh->i_addr1, hdr->txh_addr1, sizeof(hdr->txh_addr1));
3002
3003	if (!ismcast) {
3004		uint16_t dur;
3005
3006		dur = ieee80211_ack_duration(sc->sc_rates, rate,
3007		    ic->ic_flags & ~IEEE80211_F_SHPREAMBLE);
3008
3009		hdr->txh_fb_duration = htole16(dur);
3010	}
3011
3012	hdr->txh_id = __SHIFTIN(BWI_TX_DATA_RING, BWI_TXH_ID_RING_MASK) |
3013		      __SHIFTIN(idx, BWI_TXH_ID_IDX_MASK);
3014
3015	bwi_plcp_header(sc->sc_rates, hdr->txh_plcp, pkt_len, rate);
3016	bwi_plcp_header(sc->sc_rates, hdr->txh_fb_plcp, pkt_len, rate_fb);
3017
3018	phy_ctrl = __SHIFTIN(mac->mac_rf.rf_ant_mode,
3019			     BWI_TXH_PHY_C_ANTMODE_MASK);
3020	if (ieee80211_rate2phytype(sc->sc_rates, rate) == IEEE80211_T_OFDM)
3021		phy_ctrl |= BWI_TXH_PHY_C_OFDM;
3022	else if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) && rate != (2 * 1))
3023		phy_ctrl |= BWI_TXH_PHY_C_SHPREAMBLE;
3024
3025	mac_ctrl = BWI_TXH_MAC_C_HWSEQ | BWI_TXH_MAC_C_FIRST_FRAG;
3026	if (!ismcast)
3027		mac_ctrl |= BWI_TXH_MAC_C_ACK;
3028	if (ieee80211_rate2phytype(sc->sc_rates, rate_fb) == IEEE80211_T_OFDM)
3029		mac_ctrl |= BWI_TXH_MAC_C_FB_OFDM;
3030
3031	hdr->txh_mac_ctrl = htole32(mac_ctrl);
3032	hdr->txh_phy_ctrl = htole16(phy_ctrl);
3033
3034	/* Catch any further usage */
3035	hdr = NULL;
3036	wh = NULL;
3037
3038	/* DMA load */
3039	error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, tb->tb_dmap, m,
3040				     bwi_dma_buf_addr, &paddr, BUS_DMA_NOWAIT);
3041	if (error && error != EFBIG) {
3042		device_printf(sc->sc_dev, "%s: can't load TX buffer (1) %d\n",
3043		    __func__, error);
3044		goto back;
3045	}
3046
3047	if (error) {	/* error == EFBIG */
3048		struct mbuf *m_new;
3049
3050		m_new = m_defrag(m, M_NOWAIT);
3051		if (m_new == NULL) {
3052			device_printf(sc->sc_dev,
3053			    "%s: can't defrag TX buffer\n", __func__);
3054			error = ENOBUFS;
3055			goto back;
3056		} else {
3057			m = m_new;
3058		}
3059
3060		error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, tb->tb_dmap, m,
3061					     bwi_dma_buf_addr, &paddr,
3062					     BUS_DMA_NOWAIT);
3063		if (error) {
3064			device_printf(sc->sc_dev,
3065			    "%s: can't load TX buffer (2) %d\n",
3066			    __func__, error);
3067			goto back;
3068		}
3069	}
3070	error = 0;
3071
3072	bus_dmamap_sync(sc->sc_buf_dtag, tb->tb_dmap, BUS_DMASYNC_PREWRITE);
3073
3074	tb->tb_mbuf = m;
3075	tb->tb_ni = ni;
3076
3077#if 0
3078	p = mtod(m, const uint8_t *);
3079	for (i = 0; i < m->m_pkthdr.len; ++i) {
3080		if (i != 0 && i % 8 == 0)
3081			printf("\n");
3082		printf("%02x ", p[i]);
3083	}
3084	printf("\n");
3085#endif
3086	DPRINTF(sc, BWI_DBG_TX, "idx %d, pkt_len %d, buflen %d\n",
3087		idx, pkt_len, m->m_pkthdr.len);
3088
3089	/* Setup TX descriptor */
3090	sc->sc_setup_txdesc(sc, rd, idx, paddr, m->m_pkthdr.len);
3091	bus_dmamap_sync(sc->sc_txring_dtag, rd->rdata_dmap,
3092			BUS_DMASYNC_PREWRITE);
3093
3094	/* Kick start */
3095	sc->sc_start_tx(sc, rd->rdata_txrx_ctrl, idx);
3096
3097back:
3098	if (error)
3099		m_freem(m);
3100	return error;
3101}
3102
3103static int
3104bwi_encap_raw(struct bwi_softc *sc, int idx, struct mbuf *m,
3105	  struct ieee80211_node *ni, const struct ieee80211_bpf_params *params)
3106{
3107	struct ieee80211vap *vap = ni->ni_vap;
3108	struct ieee80211com *ic = ni->ni_ic;
3109	struct bwi_ring_data *rd = &sc->sc_tx_rdata[BWI_TX_DATA_RING];
3110	struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[BWI_TX_DATA_RING];
3111	struct bwi_txbuf *tb = &tbd->tbd_buf[idx];
3112	struct bwi_mac *mac;
3113	struct bwi_txbuf_hdr *hdr;
3114	struct ieee80211_frame *wh;
3115	uint8_t rate, rate_fb;
3116	uint32_t mac_ctrl;
3117	uint16_t phy_ctrl;
3118	bus_addr_t paddr;
3119	int ismcast, pkt_len, error;
3120
3121	KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC,
3122	    ("current regwin type %d", sc->sc_cur_regwin->rw_type));
3123	mac = (struct bwi_mac *)sc->sc_cur_regwin;
3124
3125	wh = mtod(m, struct ieee80211_frame *);
3126	ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1);
3127
3128	/* Get 802.11 frame len before prepending TX header */
3129	pkt_len = m->m_pkthdr.len + IEEE80211_CRC_LEN;
3130
3131	/*
3132	 * Find TX rate
3133	 */
3134	rate = params->ibp_rate0;
3135	if (!ieee80211_isratevalid(ic->ic_rt, rate)) {
3136		/* XXX fall back to mcast/mgmt rate? */
3137		m_freem(m);
3138		return EINVAL;
3139	}
3140	if (params->ibp_try1 != 0) {
3141		rate_fb = params->ibp_rate1;
3142		if (!ieee80211_isratevalid(ic->ic_rt, rate_fb)) {
3143			/* XXX fall back to rate0? */
3144			m_freem(m);
3145			return EINVAL;
3146		}
3147	} else
3148		rate_fb = rate;
3149	tb->tb_rate[0] = rate;
3150	tb->tb_rate[1] = rate_fb;
3151	sc->sc_tx_rate = rate;
3152
3153	/*
3154	 * TX radio tap
3155	 */
3156	if (ieee80211_radiotap_active_vap(vap)) {
3157		sc->sc_tx_th.wt_flags = 0;
3158		/* XXX IEEE80211_BPF_CRYPTO */
3159		if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED)
3160			sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP;
3161		if (params->ibp_flags & IEEE80211_BPF_SHORTPRE)
3162			sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
3163		sc->sc_tx_th.wt_rate = rate;
3164
3165		ieee80211_radiotap_tx(vap, m);
3166	}
3167
3168	/*
3169	 * Setup the embedded TX header
3170	 */
3171	M_PREPEND(m, sizeof(*hdr), M_NOWAIT);
3172	if (m == NULL) {
3173		device_printf(sc->sc_dev, "%s: prepend TX header failed\n",
3174		    __func__);
3175		return ENOBUFS;
3176	}
3177	hdr = mtod(m, struct bwi_txbuf_hdr *);
3178
3179	bzero(hdr, sizeof(*hdr));
3180
3181	bcopy(wh->i_fc, hdr->txh_fc, sizeof(hdr->txh_fc));
3182	bcopy(wh->i_addr1, hdr->txh_addr1, sizeof(hdr->txh_addr1));
3183
3184	mac_ctrl = BWI_TXH_MAC_C_HWSEQ | BWI_TXH_MAC_C_FIRST_FRAG;
3185	if (!ismcast && (params->ibp_flags & IEEE80211_BPF_NOACK) == 0) {
3186		uint16_t dur;
3187
3188		dur = ieee80211_ack_duration(sc->sc_rates, rate_fb, 0);
3189
3190		hdr->txh_fb_duration = htole16(dur);
3191		mac_ctrl |= BWI_TXH_MAC_C_ACK;
3192	}
3193
3194	hdr->txh_id = __SHIFTIN(BWI_TX_DATA_RING, BWI_TXH_ID_RING_MASK) |
3195		      __SHIFTIN(idx, BWI_TXH_ID_IDX_MASK);
3196
3197	bwi_plcp_header(sc->sc_rates, hdr->txh_plcp, pkt_len, rate);
3198	bwi_plcp_header(sc->sc_rates, hdr->txh_fb_plcp, pkt_len, rate_fb);
3199
3200	phy_ctrl = __SHIFTIN(mac->mac_rf.rf_ant_mode,
3201			     BWI_TXH_PHY_C_ANTMODE_MASK);
3202	if (ieee80211_rate2phytype(sc->sc_rates, rate) == IEEE80211_T_OFDM) {
3203		phy_ctrl |= BWI_TXH_PHY_C_OFDM;
3204		mac_ctrl |= BWI_TXH_MAC_C_FB_OFDM;
3205	} else if (params->ibp_flags & IEEE80211_BPF_SHORTPRE)
3206		phy_ctrl |= BWI_TXH_PHY_C_SHPREAMBLE;
3207
3208	hdr->txh_mac_ctrl = htole32(mac_ctrl);
3209	hdr->txh_phy_ctrl = htole16(phy_ctrl);
3210
3211	/* Catch any further usage */
3212	hdr = NULL;
3213	wh = NULL;
3214
3215	/* DMA load */
3216	error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, tb->tb_dmap, m,
3217				     bwi_dma_buf_addr, &paddr, BUS_DMA_NOWAIT);
3218	if (error != 0) {
3219		struct mbuf *m_new;
3220
3221		if (error != EFBIG) {
3222			device_printf(sc->sc_dev,
3223			    "%s: can't load TX buffer (1) %d\n",
3224			    __func__, error);
3225			goto back;
3226		}
3227		m_new = m_defrag(m, M_NOWAIT);
3228		if (m_new == NULL) {
3229			device_printf(sc->sc_dev,
3230			    "%s: can't defrag TX buffer\n", __func__);
3231			error = ENOBUFS;
3232			goto back;
3233		}
3234		m = m_new;
3235		error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, tb->tb_dmap, m,
3236					     bwi_dma_buf_addr, &paddr,
3237					     BUS_DMA_NOWAIT);
3238		if (error) {
3239			device_printf(sc->sc_dev,
3240			    "%s: can't load TX buffer (2) %d\n",
3241			    __func__, error);
3242			goto back;
3243		}
3244	}
3245
3246	bus_dmamap_sync(sc->sc_buf_dtag, tb->tb_dmap, BUS_DMASYNC_PREWRITE);
3247
3248	tb->tb_mbuf = m;
3249	tb->tb_ni = ni;
3250
3251	DPRINTF(sc, BWI_DBG_TX, "idx %d, pkt_len %d, buflen %d\n",
3252		idx, pkt_len, m->m_pkthdr.len);
3253
3254	/* Setup TX descriptor */
3255	sc->sc_setup_txdesc(sc, rd, idx, paddr, m->m_pkthdr.len);
3256	bus_dmamap_sync(sc->sc_txring_dtag, rd->rdata_dmap,
3257			BUS_DMASYNC_PREWRITE);
3258
3259	/* Kick start */
3260	sc->sc_start_tx(sc, rd->rdata_txrx_ctrl, idx);
3261back:
3262	if (error)
3263		m_freem(m);
3264	return error;
3265}
3266
3267static void
3268bwi_start_tx32(struct bwi_softc *sc, uint32_t tx_ctrl, int idx)
3269{
3270	idx = (idx + 1) % BWI_TX_NDESC;
3271	CSR_WRITE_4(sc, tx_ctrl + BWI_TX32_INDEX,
3272		    idx * sizeof(struct bwi_desc32));
3273}
3274
3275static void
3276bwi_start_tx64(struct bwi_softc *sc, uint32_t tx_ctrl, int idx)
3277{
3278	/* TODO:64 */
3279}
3280
3281static void
3282bwi_txeof_status32(struct bwi_softc *sc)
3283{
3284	uint32_t val, ctrl_base;
3285	int end_idx;
3286
3287	ctrl_base = sc->sc_txstats->stats_ctrl_base;
3288
3289	val = CSR_READ_4(sc, ctrl_base + BWI_RX32_STATUS);
3290	end_idx = __SHIFTOUT(val, BWI_RX32_STATUS_INDEX_MASK) /
3291		  sizeof(struct bwi_desc32);
3292
3293	bwi_txeof_status(sc, end_idx);
3294
3295	CSR_WRITE_4(sc, ctrl_base + BWI_RX32_INDEX,
3296		    end_idx * sizeof(struct bwi_desc32));
3297
3298	bwi_start_locked(sc);
3299}
3300
3301static void
3302bwi_txeof_status64(struct bwi_softc *sc)
3303{
3304	/* TODO:64 */
3305}
3306
3307static void
3308_bwi_txeof(struct bwi_softc *sc, uint16_t tx_id, int acked, int data_txcnt)
3309{
3310	struct bwi_txbuf_data *tbd;
3311	struct bwi_txbuf *tb;
3312	int ring_idx, buf_idx;
3313	struct ieee80211_node *ni;
3314	struct ieee80211vap *vap;
3315
3316	if (tx_id == 0) {
3317		device_printf(sc->sc_dev, "%s: zero tx id\n", __func__);
3318		return;
3319	}
3320
3321	ring_idx = __SHIFTOUT(tx_id, BWI_TXH_ID_RING_MASK);
3322	buf_idx = __SHIFTOUT(tx_id, BWI_TXH_ID_IDX_MASK);
3323
3324	KASSERT(ring_idx == BWI_TX_DATA_RING, ("ring_idx %d", ring_idx));
3325	KASSERT(buf_idx < BWI_TX_NDESC, ("buf_idx %d", buf_idx));
3326
3327	tbd = &sc->sc_tx_bdata[ring_idx];
3328	KASSERT(tbd->tbd_used > 0, ("tbd_used %d", tbd->tbd_used));
3329	tbd->tbd_used--;
3330
3331	tb = &tbd->tbd_buf[buf_idx];
3332	DPRINTF(sc, BWI_DBG_TXEOF, "txeof idx %d, "
3333		"acked %d, data_txcnt %d, ni %p\n",
3334		buf_idx, acked, data_txcnt, tb->tb_ni);
3335
3336	bus_dmamap_unload(sc->sc_buf_dtag, tb->tb_dmap);
3337
3338	if ((ni = tb->tb_ni) != NULL) {
3339		const struct bwi_txbuf_hdr *hdr =
3340		    mtod(tb->tb_mbuf, const struct bwi_txbuf_hdr *);
3341		vap = ni->ni_vap;
3342
3343		/* NB: update rate control only for unicast frames */
3344		if (hdr->txh_mac_ctrl & htole32(BWI_TXH_MAC_C_ACK)) {
3345			/*
3346			 * Feed back 'acked and data_txcnt'.  Note that the
3347			 * generic AMRR code only understands one tx rate
3348			 * and the estimator doesn't handle real retry counts
3349			 * well so to avoid over-aggressive downshifting we
3350			 * treat any number of retries as "1".
3351			 */
3352			ieee80211_ratectl_tx_complete(vap, ni,
3353			    (data_txcnt > 1) ? IEEE80211_RATECTL_TX_SUCCESS :
3354			        IEEE80211_RATECTL_TX_FAILURE, &acked, NULL);
3355		}
3356		ieee80211_tx_complete(ni, tb->tb_mbuf, !acked);
3357		tb->tb_ni = NULL;
3358	} else
3359		m_freem(tb->tb_mbuf);
3360	tb->tb_mbuf = NULL;
3361
3362	if (tbd->tbd_used == 0)
3363		sc->sc_tx_timer = 0;
3364}
3365
3366static void
3367bwi_txeof_status(struct bwi_softc *sc, int end_idx)
3368{
3369	struct bwi_txstats_data *st = sc->sc_txstats;
3370	int idx;
3371
3372	bus_dmamap_sync(st->stats_dtag, st->stats_dmap, BUS_DMASYNC_POSTREAD);
3373
3374	idx = st->stats_idx;
3375	while (idx != end_idx) {
3376		const struct bwi_txstats *stats = &st->stats[idx];
3377
3378		if ((stats->txs_flags & BWI_TXS_F_PENDING) == 0) {
3379			int data_txcnt;
3380
3381			data_txcnt = __SHIFTOUT(stats->txs_txcnt,
3382						BWI_TXS_TXCNT_DATA);
3383			_bwi_txeof(sc, le16toh(stats->txs_id),
3384				   stats->txs_flags & BWI_TXS_F_ACKED,
3385				   data_txcnt);
3386		}
3387		idx = (idx + 1) % BWI_TXSTATS_NDESC;
3388	}
3389	st->stats_idx = idx;
3390}
3391
3392static void
3393bwi_txeof(struct bwi_softc *sc)
3394{
3395
3396	for (;;) {
3397		uint32_t tx_status0, tx_status1;
3398		uint16_t tx_id;
3399		int data_txcnt;
3400
3401		tx_status0 = CSR_READ_4(sc, BWI_TXSTATUS0);
3402		if ((tx_status0 & BWI_TXSTATUS0_VALID) == 0)
3403			break;
3404		tx_status1 = CSR_READ_4(sc, BWI_TXSTATUS1);
3405
3406		tx_id = __SHIFTOUT(tx_status0, BWI_TXSTATUS0_TXID_MASK);
3407		data_txcnt = __SHIFTOUT(tx_status0,
3408				BWI_TXSTATUS0_DATA_TXCNT_MASK);
3409
3410		if (tx_status0 & (BWI_TXSTATUS0_AMPDU | BWI_TXSTATUS0_PENDING))
3411			continue;
3412
3413		_bwi_txeof(sc, le16toh(tx_id), tx_status0 & BWI_TXSTATUS0_ACKED,
3414		    data_txcnt);
3415	}
3416
3417	bwi_start_locked(sc);
3418}
3419
3420static int
3421bwi_bbp_power_on(struct bwi_softc *sc, enum bwi_clock_mode clk_mode)
3422{
3423	bwi_power_on(sc, 1);
3424	return bwi_set_clock_mode(sc, clk_mode);
3425}
3426
3427static void
3428bwi_bbp_power_off(struct bwi_softc *sc)
3429{
3430	bwi_set_clock_mode(sc, BWI_CLOCK_MODE_SLOW);
3431	bwi_power_off(sc, 1);
3432}
3433
3434static int
3435bwi_get_pwron_delay(struct bwi_softc *sc)
3436{
3437	struct bwi_regwin *com, *old;
3438	struct bwi_clock_freq freq;
3439	uint32_t val;
3440	int error;
3441
3442	com = &sc->sc_com_regwin;
3443	KASSERT(BWI_REGWIN_EXIST(com), ("no regwin"));
3444
3445	if ((sc->sc_cap & BWI_CAP_CLKMODE) == 0)
3446		return 0;
3447
3448	error = bwi_regwin_switch(sc, com, &old);
3449	if (error)
3450		return error;
3451
3452	bwi_get_clock_freq(sc, &freq);
3453
3454	val = CSR_READ_4(sc, BWI_PLL_ON_DELAY);
3455	sc->sc_pwron_delay = howmany((val + 2) * 1000000, freq.clkfreq_min);
3456	DPRINTF(sc, BWI_DBG_ATTACH, "power on delay %u\n", sc->sc_pwron_delay);
3457
3458	return bwi_regwin_switch(sc, old, NULL);
3459}
3460
3461static int
3462bwi_bus_attach(struct bwi_softc *sc)
3463{
3464	struct bwi_regwin *bus, *old;
3465	int error;
3466
3467	bus = &sc->sc_bus_regwin;
3468
3469	error = bwi_regwin_switch(sc, bus, &old);
3470	if (error)
3471		return error;
3472
3473	if (!bwi_regwin_is_enabled(sc, bus))
3474		bwi_regwin_enable(sc, bus, 0);
3475
3476	/* Disable interripts */
3477	CSR_WRITE_4(sc, BWI_INTRVEC, 0);
3478
3479	return bwi_regwin_switch(sc, old, NULL);
3480}
3481
3482static const char *
3483bwi_regwin_name(const struct bwi_regwin *rw)
3484{
3485	switch (rw->rw_type) {
3486	case BWI_REGWIN_T_COM:
3487		return "COM";
3488	case BWI_REGWIN_T_BUSPCI:
3489		return "PCI";
3490	case BWI_REGWIN_T_MAC:
3491		return "MAC";
3492	case BWI_REGWIN_T_BUSPCIE:
3493		return "PCIE";
3494	}
3495	panic("unknown regwin type 0x%04x\n", rw->rw_type);
3496	return NULL;
3497}
3498
3499static uint32_t
3500bwi_regwin_disable_bits(struct bwi_softc *sc)
3501{
3502	uint32_t busrev;
3503
3504	/* XXX cache this */
3505	busrev = __SHIFTOUT(CSR_READ_4(sc, BWI_ID_LO), BWI_ID_LO_BUSREV_MASK);
3506	DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT | BWI_DBG_MISC,
3507		"bus rev %u\n", busrev);
3508
3509	if (busrev == BWI_BUSREV_0)
3510		return BWI_STATE_LO_DISABLE1;
3511	else if (busrev == BWI_BUSREV_1)
3512		return BWI_STATE_LO_DISABLE2;
3513	else
3514		return (BWI_STATE_LO_DISABLE1 | BWI_STATE_LO_DISABLE2);
3515}
3516
3517int
3518bwi_regwin_is_enabled(struct bwi_softc *sc, struct bwi_regwin *rw)
3519{
3520	uint32_t val, disable_bits;
3521
3522	disable_bits = bwi_regwin_disable_bits(sc);
3523	val = CSR_READ_4(sc, BWI_STATE_LO);
3524
3525	if ((val & (BWI_STATE_LO_CLOCK |
3526		    BWI_STATE_LO_RESET |
3527		    disable_bits)) == BWI_STATE_LO_CLOCK) {
3528		DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT, "%s is enabled\n",
3529			bwi_regwin_name(rw));
3530		return 1;
3531	} else {
3532		DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT, "%s is disabled\n",
3533			bwi_regwin_name(rw));
3534		return 0;
3535	}
3536}
3537
3538void
3539bwi_regwin_disable(struct bwi_softc *sc, struct bwi_regwin *rw, uint32_t flags)
3540{
3541	uint32_t state_lo, disable_bits;
3542	int i;
3543
3544	state_lo = CSR_READ_4(sc, BWI_STATE_LO);
3545
3546	/*
3547	 * If current regwin is in 'reset' state, it was already disabled.
3548	 */
3549	if (state_lo & BWI_STATE_LO_RESET) {
3550		DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT,
3551			"%s was already disabled\n", bwi_regwin_name(rw));
3552		return;
3553	}
3554
3555	disable_bits = bwi_regwin_disable_bits(sc);
3556
3557	/*
3558	 * Disable normal clock
3559	 */
3560	state_lo = BWI_STATE_LO_CLOCK | disable_bits;
3561	CSR_WRITE_4(sc, BWI_STATE_LO, state_lo);
3562
3563	/*
3564	 * Wait until normal clock is disabled
3565	 */
3566#define NRETRY	1000
3567	for (i = 0; i < NRETRY; ++i) {
3568		state_lo = CSR_READ_4(sc, BWI_STATE_LO);
3569		if (state_lo & disable_bits)
3570			break;
3571		DELAY(10);
3572	}
3573	if (i == NRETRY) {
3574		device_printf(sc->sc_dev, "%s disable clock timeout\n",
3575			      bwi_regwin_name(rw));
3576	}
3577
3578	for (i = 0; i < NRETRY; ++i) {
3579		uint32_t state_hi;
3580
3581		state_hi = CSR_READ_4(sc, BWI_STATE_HI);
3582		if ((state_hi & BWI_STATE_HI_BUSY) == 0)
3583			break;
3584		DELAY(10);
3585	}
3586	if (i == NRETRY) {
3587		device_printf(sc->sc_dev, "%s wait BUSY unset timeout\n",
3588			      bwi_regwin_name(rw));
3589	}
3590#undef NRETRY
3591
3592	/*
3593	 * Reset and disable regwin with gated clock
3594	 */
3595	state_lo = BWI_STATE_LO_RESET | disable_bits |
3596		   BWI_STATE_LO_CLOCK | BWI_STATE_LO_GATED_CLOCK |
3597		   __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK);
3598	CSR_WRITE_4(sc, BWI_STATE_LO, state_lo);
3599
3600	/* Flush pending bus write */
3601	CSR_READ_4(sc, BWI_STATE_LO);
3602	DELAY(1);
3603
3604	/* Reset and disable regwin */
3605	state_lo = BWI_STATE_LO_RESET | disable_bits |
3606		   __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK);
3607	CSR_WRITE_4(sc, BWI_STATE_LO, state_lo);
3608
3609	/* Flush pending bus write */
3610	CSR_READ_4(sc, BWI_STATE_LO);
3611	DELAY(1);
3612}
3613
3614void
3615bwi_regwin_enable(struct bwi_softc *sc, struct bwi_regwin *rw, uint32_t flags)
3616{
3617	uint32_t state_lo, state_hi, imstate;
3618
3619	bwi_regwin_disable(sc, rw, flags);
3620
3621	/* Reset regwin with gated clock */
3622	state_lo = BWI_STATE_LO_RESET |
3623		   BWI_STATE_LO_CLOCK |
3624		   BWI_STATE_LO_GATED_CLOCK |
3625		   __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK);
3626	CSR_WRITE_4(sc, BWI_STATE_LO, state_lo);
3627
3628	/* Flush pending bus write */
3629	CSR_READ_4(sc, BWI_STATE_LO);
3630	DELAY(1);
3631
3632	state_hi = CSR_READ_4(sc, BWI_STATE_HI);
3633	if (state_hi & BWI_STATE_HI_SERROR)
3634		CSR_WRITE_4(sc, BWI_STATE_HI, 0);
3635
3636	imstate = CSR_READ_4(sc, BWI_IMSTATE);
3637	if (imstate & (BWI_IMSTATE_INBAND_ERR | BWI_IMSTATE_TIMEOUT)) {
3638		imstate &= ~(BWI_IMSTATE_INBAND_ERR | BWI_IMSTATE_TIMEOUT);
3639		CSR_WRITE_4(sc, BWI_IMSTATE, imstate);
3640	}
3641
3642	/* Enable regwin with gated clock */
3643	state_lo = BWI_STATE_LO_CLOCK |
3644		   BWI_STATE_LO_GATED_CLOCK |
3645		   __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK);
3646	CSR_WRITE_4(sc, BWI_STATE_LO, state_lo);
3647
3648	/* Flush pending bus write */
3649	CSR_READ_4(sc, BWI_STATE_LO);
3650	DELAY(1);
3651
3652	/* Enable regwin with normal clock */
3653	state_lo = BWI_STATE_LO_CLOCK |
3654		   __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK);
3655	CSR_WRITE_4(sc, BWI_STATE_LO, state_lo);
3656
3657	/* Flush pending bus write */
3658	CSR_READ_4(sc, BWI_STATE_LO);
3659	DELAY(1);
3660}
3661
3662static void
3663bwi_set_bssid(struct bwi_softc *sc, const uint8_t *bssid)
3664{
3665	struct bwi_mac *mac;
3666	struct bwi_myaddr_bssid buf;
3667	const uint8_t *p;
3668	uint32_t val;
3669	int n, i;
3670
3671	KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC,
3672	    ("current regwin type %d", sc->sc_cur_regwin->rw_type));
3673	mac = (struct bwi_mac *)sc->sc_cur_regwin;
3674
3675	bwi_set_addr_filter(sc, BWI_ADDR_FILTER_BSSID, bssid);
3676
3677	bcopy(sc->sc_ic.ic_macaddr, buf.myaddr, sizeof(buf.myaddr));
3678	bcopy(bssid, buf.bssid, sizeof(buf.bssid));
3679
3680	n = sizeof(buf) / sizeof(val);
3681	p = (const uint8_t *)&buf;
3682	for (i = 0; i < n; ++i) {
3683		int j;
3684
3685		val = 0;
3686		for (j = 0; j < sizeof(val); ++j)
3687			val |= ((uint32_t)(*p++)) << (j * 8);
3688
3689		TMPLT_WRITE_4(mac, 0x20 + (i * sizeof(val)), val);
3690	}
3691}
3692
3693static void
3694bwi_updateslot(struct ieee80211com *ic)
3695{
3696	struct bwi_softc *sc = ic->ic_softc;
3697	struct bwi_mac *mac;
3698
3699	BWI_LOCK(sc);
3700	if (sc->sc_flags & BWI_F_RUNNING) {
3701		DPRINTF(sc, BWI_DBG_80211, "%s\n", __func__);
3702
3703		KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC,
3704		    ("current regwin type %d", sc->sc_cur_regwin->rw_type));
3705		mac = (struct bwi_mac *)sc->sc_cur_regwin;
3706
3707		bwi_mac_updateslot(mac, (ic->ic_flags & IEEE80211_F_SHSLOT));
3708	}
3709	BWI_UNLOCK(sc);
3710}
3711
3712static void
3713bwi_calibrate(void *xsc)
3714{
3715	struct bwi_softc *sc = xsc;
3716	struct bwi_mac *mac;
3717
3718	BWI_ASSERT_LOCKED(sc);
3719
3720	KASSERT(sc->sc_ic.ic_opmode != IEEE80211_M_MONITOR,
3721	    ("opmode %d", sc->sc_ic.ic_opmode));
3722
3723	KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC,
3724	    ("current regwin type %d", sc->sc_cur_regwin->rw_type));
3725	mac = (struct bwi_mac *)sc->sc_cur_regwin;
3726
3727	bwi_mac_calibrate_txpower(mac, sc->sc_txpwrcb_type);
3728	sc->sc_txpwrcb_type = BWI_TXPWR_CALIB;
3729
3730	/* XXX 15 seconds */
3731	callout_reset(&sc->sc_calib_ch, hz * 15, bwi_calibrate, sc);
3732}
3733
3734static int
3735bwi_calc_rssi(struct bwi_softc *sc, const struct bwi_rxbuf_hdr *hdr)
3736{
3737	struct bwi_mac *mac;
3738
3739	KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC,
3740	    ("current regwin type %d", sc->sc_cur_regwin->rw_type));
3741	mac = (struct bwi_mac *)sc->sc_cur_regwin;
3742
3743	return bwi_rf_calc_rssi(mac, hdr);
3744}
3745
3746static int
3747bwi_calc_noise(struct bwi_softc *sc)
3748{
3749	struct bwi_mac *mac;
3750
3751	KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC,
3752	    ("current regwin type %d", sc->sc_cur_regwin->rw_type));
3753	mac = (struct bwi_mac *)sc->sc_cur_regwin;
3754
3755	return bwi_rf_calc_noise(mac);
3756}
3757
3758static __inline uint8_t
3759bwi_plcp2rate(const uint32_t plcp0, enum ieee80211_phytype type)
3760{
3761	uint32_t plcp = le32toh(plcp0) & IEEE80211_OFDM_PLCP_RATE_MASK;
3762	return (ieee80211_plcp2rate(plcp, type));
3763}
3764
3765static void
3766bwi_rx_radiotap(struct bwi_softc *sc, struct mbuf *m,
3767    struct bwi_rxbuf_hdr *hdr, const void *plcp, int rate, int rssi, int noise)
3768{
3769	const struct ieee80211_frame_min *wh;
3770
3771	sc->sc_rx_th.wr_flags = IEEE80211_RADIOTAP_F_FCS;
3772	if (htole16(hdr->rxh_flags1) & BWI_RXH_F1_SHPREAMBLE)
3773		sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
3774
3775	wh = mtod(m, const struct ieee80211_frame_min *);
3776	if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED)
3777		sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_WEP;
3778
3779	sc->sc_rx_th.wr_tsf = hdr->rxh_tsf; /* No endian conversion */
3780	sc->sc_rx_th.wr_rate = rate;
3781	sc->sc_rx_th.wr_antsignal = rssi;
3782	sc->sc_rx_th.wr_antnoise = noise;
3783}
3784
3785static void
3786bwi_led_attach(struct bwi_softc *sc)
3787{
3788	const uint8_t *led_act = NULL;
3789	uint16_t gpio, val[BWI_LED_MAX];
3790	int i;
3791
3792	for (i = 0; i < nitems(bwi_vendor_led_act); ++i) {
3793		if (sc->sc_pci_subvid == bwi_vendor_led_act[i].vid) {
3794			led_act = bwi_vendor_led_act[i].led_act;
3795			break;
3796		}
3797	}
3798	if (led_act == NULL)
3799		led_act = bwi_default_led_act;
3800
3801	gpio = bwi_read_sprom(sc, BWI_SPROM_GPIO01);
3802	val[0] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_0);
3803	val[1] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_1);
3804
3805	gpio = bwi_read_sprom(sc, BWI_SPROM_GPIO23);
3806	val[2] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_2);
3807	val[3] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_3);
3808
3809	for (i = 0; i < BWI_LED_MAX; ++i) {
3810		struct bwi_led *led = &sc->sc_leds[i];
3811
3812		if (val[i] == 0xff) {
3813			led->l_act = led_act[i];
3814		} else {
3815			if (val[i] & BWI_LED_ACT_LOW)
3816				led->l_flags |= BWI_LED_F_ACTLOW;
3817			led->l_act = __SHIFTOUT(val[i], BWI_LED_ACT_MASK);
3818		}
3819		led->l_mask = (1 << i);
3820
3821		if (led->l_act == BWI_LED_ACT_BLINK_SLOW ||
3822		    led->l_act == BWI_LED_ACT_BLINK_POLL ||
3823		    led->l_act == BWI_LED_ACT_BLINK) {
3824			led->l_flags |= BWI_LED_F_BLINK;
3825			if (led->l_act == BWI_LED_ACT_BLINK_POLL)
3826				led->l_flags |= BWI_LED_F_POLLABLE;
3827			else if (led->l_act == BWI_LED_ACT_BLINK_SLOW)
3828				led->l_flags |= BWI_LED_F_SLOW;
3829
3830			if (sc->sc_blink_led == NULL) {
3831				sc->sc_blink_led = led;
3832				if (led->l_flags & BWI_LED_F_SLOW)
3833					BWI_LED_SLOWDOWN(sc->sc_led_idle);
3834			}
3835		}
3836
3837		DPRINTF(sc, BWI_DBG_LED | BWI_DBG_ATTACH,
3838			"%dth led, act %d, lowact %d\n", i,
3839			led->l_act, led->l_flags & BWI_LED_F_ACTLOW);
3840	}
3841	callout_init_mtx(&sc->sc_led_blink_ch, &sc->sc_mtx, 0);
3842}
3843
3844static __inline uint16_t
3845bwi_led_onoff(const struct bwi_led *led, uint16_t val, int on)
3846{
3847	if (led->l_flags & BWI_LED_F_ACTLOW)
3848		on = !on;
3849	if (on)
3850		val |= led->l_mask;
3851	else
3852		val &= ~led->l_mask;
3853	return val;
3854}
3855
3856static void
3857bwi_led_newstate(struct bwi_softc *sc, enum ieee80211_state nstate)
3858{
3859	struct ieee80211com *ic = &sc->sc_ic;
3860	uint16_t val;
3861	int i;
3862
3863	if (nstate == IEEE80211_S_INIT) {
3864		callout_stop(&sc->sc_led_blink_ch);
3865		sc->sc_led_blinking = 0;
3866	}
3867
3868	if ((sc->sc_flags & BWI_F_RUNNING) == 0)
3869		return;
3870
3871	val = CSR_READ_2(sc, BWI_MAC_GPIO_CTRL);
3872	for (i = 0; i < BWI_LED_MAX; ++i) {
3873		struct bwi_led *led = &sc->sc_leds[i];
3874		int on;
3875
3876		if (led->l_act == BWI_LED_ACT_UNKN ||
3877		    led->l_act == BWI_LED_ACT_NULL)
3878			continue;
3879
3880		if ((led->l_flags & BWI_LED_F_BLINK) &&
3881		    nstate != IEEE80211_S_INIT)
3882		    	continue;
3883
3884		switch (led->l_act) {
3885		case BWI_LED_ACT_ON:	/* Always on */
3886			on = 1;
3887			break;
3888		case BWI_LED_ACT_OFF:	/* Always off */
3889		case BWI_LED_ACT_5GHZ:	/* TODO: 11A */
3890			on = 0;
3891			break;
3892		default:
3893			on = 1;
3894			switch (nstate) {
3895			case IEEE80211_S_INIT:
3896				on = 0;
3897				break;
3898			case IEEE80211_S_RUN:
3899				if (led->l_act == BWI_LED_ACT_11G &&
3900				    ic->ic_curmode != IEEE80211_MODE_11G)
3901					on = 0;
3902				break;
3903			default:
3904				if (led->l_act == BWI_LED_ACT_ASSOC)
3905					on = 0;
3906				break;
3907			}
3908			break;
3909		}
3910
3911		val = bwi_led_onoff(led, val, on);
3912	}
3913	CSR_WRITE_2(sc, BWI_MAC_GPIO_CTRL, val);
3914}
3915static void
3916bwi_led_event(struct bwi_softc *sc, int event)
3917{
3918	struct bwi_led *led = sc->sc_blink_led;
3919	int rate;
3920
3921	if (event == BWI_LED_EVENT_POLL) {
3922		if ((led->l_flags & BWI_LED_F_POLLABLE) == 0)
3923			return;
3924		if (ticks - sc->sc_led_ticks < sc->sc_led_idle)
3925			return;
3926	}
3927
3928	sc->sc_led_ticks = ticks;
3929	if (sc->sc_led_blinking)
3930		return;
3931
3932	switch (event) {
3933	case BWI_LED_EVENT_RX:
3934		rate = sc->sc_rx_rate;
3935		break;
3936	case BWI_LED_EVENT_TX:
3937		rate = sc->sc_tx_rate;
3938		break;
3939	case BWI_LED_EVENT_POLL:
3940		rate = 0;
3941		break;
3942	default:
3943		panic("unknown LED event %d\n", event);
3944		break;
3945	}
3946	bwi_led_blink_start(sc, bwi_led_duration[rate].on_dur,
3947	    bwi_led_duration[rate].off_dur);
3948}
3949
3950static void
3951bwi_led_blink_start(struct bwi_softc *sc, int on_dur, int off_dur)
3952{
3953	struct bwi_led *led = sc->sc_blink_led;
3954	uint16_t val;
3955
3956	val = CSR_READ_2(sc, BWI_MAC_GPIO_CTRL);
3957	val = bwi_led_onoff(led, val, 1);
3958	CSR_WRITE_2(sc, BWI_MAC_GPIO_CTRL, val);
3959
3960	if (led->l_flags & BWI_LED_F_SLOW) {
3961		BWI_LED_SLOWDOWN(on_dur);
3962		BWI_LED_SLOWDOWN(off_dur);
3963	}
3964
3965	sc->sc_led_blinking = 1;
3966	sc->sc_led_blink_offdur = off_dur;
3967
3968	callout_reset(&sc->sc_led_blink_ch, on_dur, bwi_led_blink_next, sc);
3969}
3970
3971static void
3972bwi_led_blink_next(void *xsc)
3973{
3974	struct bwi_softc *sc = xsc;
3975	uint16_t val;
3976
3977	val = CSR_READ_2(sc, BWI_MAC_GPIO_CTRL);
3978	val = bwi_led_onoff(sc->sc_blink_led, val, 0);
3979	CSR_WRITE_2(sc, BWI_MAC_GPIO_CTRL, val);
3980
3981	callout_reset(&sc->sc_led_blink_ch, sc->sc_led_blink_offdur,
3982	    bwi_led_blink_end, sc);
3983}
3984
3985static void
3986bwi_led_blink_end(void *xsc)
3987{
3988	struct bwi_softc *sc = xsc;
3989	sc->sc_led_blinking = 0;
3990}
3991
3992static void
3993bwi_restart(void *xsc, int pending)
3994{
3995	struct bwi_softc *sc = xsc;
3996
3997	device_printf(sc->sc_dev, "%s begin, help!\n", __func__);
3998	BWI_LOCK(sc);
3999	bwi_init_statechg(sc, 0);
4000#if 0
4001	bwi_start_locked(sc);
4002#endif
4003	BWI_UNLOCK(sc);
4004}
4005