1177867Sjfv/****************************************************************************** 2169240Sjfv 3286833Ssbruno Copyright (c) 2001-2015, Intel Corporation 4169240Sjfv All rights reserved. 5169240Sjfv 6169240Sjfv Redistribution and use in source and binary forms, with or without 7169240Sjfv modification, are permitted provided that the following conditions are met: 8169240Sjfv 9169240Sjfv 1. Redistributions of source code must retain the above copyright notice, 10169240Sjfv this list of conditions and the following disclaimer. 11169240Sjfv 12169240Sjfv 2. Redistributions in binary form must reproduce the above copyright 13169240Sjfv notice, this list of conditions and the following disclaimer in the 14169240Sjfv documentation and/or other materials provided with the distribution. 15169240Sjfv 16169240Sjfv 3. Neither the name of the Intel Corporation nor the names of its 17169240Sjfv contributors may be used to endorse or promote products derived from 18169240Sjfv this software without specific prior written permission. 19169240Sjfv 20169240Sjfv THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21169240Sjfv AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22169240Sjfv IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23169240Sjfv ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24169240Sjfv LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25169240Sjfv CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26169240Sjfv SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27169240Sjfv INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28169240Sjfv CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29169240Sjfv ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30169240Sjfv POSSIBILITY OF SUCH DAMAGE. 31169240Sjfv 32177867Sjfv******************************************************************************/ 33177867Sjfv/*$FreeBSD: stable/11/sys/dev/e1000/e1000_ich8lan.c 360688 2020-05-06 11:10:13Z dim $*/ 34169240Sjfv 35247064Sjfv/* 82562G 10/100 Network Connection 36185353Sjfv * 82562G-2 10/100 Network Connection 37185353Sjfv * 82562GT 10/100 Network Connection 38185353Sjfv * 82562GT-2 10/100 Network Connection 39185353Sjfv * 82562V 10/100 Network Connection 40185353Sjfv * 82562V-2 10/100 Network Connection 41185353Sjfv * 82566DC-2 Gigabit Network Connection 42185353Sjfv * 82566DC Gigabit Network Connection 43185353Sjfv * 82566DM-2 Gigabit Network Connection 44185353Sjfv * 82566DM Gigabit Network Connection 45185353Sjfv * 82566MC Gigabit Network Connection 46185353Sjfv * 82566MM Gigabit Network Connection 47185353Sjfv * 82567LM Gigabit Network Connection 48185353Sjfv * 82567LF Gigabit Network Connection 49185353Sjfv * 82567V Gigabit Network Connection 50185353Sjfv * 82567LM-2 Gigabit Network Connection 51185353Sjfv * 82567LF-2 Gigabit Network Connection 52185353Sjfv * 82567V-2 Gigabit Network Connection 53185353Sjfv * 82567LF-3 Gigabit Network Connection 54185353Sjfv * 82567LM-3 Gigabit Network Connection 55185353Sjfv * 82567LM-4 Gigabit Network Connection 56194865Sjfv * 82577LM Gigabit Network Connection 57194865Sjfv * 82577LC Gigabit Network Connection 58194865Sjfv * 82578DM Gigabit Network Connection 59194865Sjfv * 82578DC Gigabit Network Connection 60213234Sjfv * 82579LM Gigabit Network Connection 61213234Sjfv * 82579V Gigabit Network Connection 62256200Sjfv * Ethernet Connection I217-LM 63256200Sjfv * Ethernet Connection I217-V 64256200Sjfv * Ethernet Connection I218-V 65256200Sjfv * Ethernet Connection I218-LM 66267935Sjfv * Ethernet Connection (2) I218-LM 67267935Sjfv * Ethernet Connection (2) I218-V 68267935Sjfv * Ethernet Connection (3) I218-LM 69267935Sjfv * Ethernet Connection (3) I218-V 70169240Sjfv */ 71169240Sjfv 72169589Sjfv#include "e1000_api.h" 73169240Sjfv 74177867Sjfvstatic s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw); 75177867Sjfvstatic void e1000_release_swflag_ich8lan(struct e1000_hw *hw); 76200243Sjfvstatic s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw); 77200243Sjfvstatic void e1000_release_nvm_ich8lan(struct e1000_hw *hw); 78177867Sjfvstatic bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw); 79213234Sjfvstatic bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw); 80267935Sjfvstatic int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index); 81267935Sjfvstatic int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index); 82256200Sjfvstatic s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw); 83218588Sjfvstatic void e1000_update_mc_addr_list_pch2lan(struct e1000_hw *hw, 84228386Sjfv u8 *mc_addr_list, 85228386Sjfv u32 mc_addr_count); 86177867Sjfvstatic s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw); 87177867Sjfvstatic s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw); 88200243Sjfvstatic s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active); 89177867Sjfvstatic s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, 90228386Sjfv bool active); 91177867Sjfvstatic s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, 92228386Sjfv bool active); 93177867Sjfvstatic s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, 94228386Sjfv u16 words, u16 *data); 95295323Serjstatic s32 e1000_read_nvm_spt(struct e1000_hw *hw, u16 offset, u16 words, 96295323Serj u16 *data); 97177867Sjfvstatic s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, 98228386Sjfv u16 words, u16 *data); 99177867Sjfvstatic s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw); 100177867Sjfvstatic s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw); 101295323Serjstatic s32 e1000_update_nvm_checksum_spt(struct e1000_hw *hw); 102177867Sjfvstatic s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, 103228386Sjfv u16 *data); 104194865Sjfvstatic s32 e1000_id_led_init_pchlan(struct e1000_hw *hw); 105177867Sjfvstatic s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw); 106177867Sjfvstatic s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw); 107177867Sjfvstatic s32 e1000_init_hw_ich8lan(struct e1000_hw *hw); 108177867Sjfvstatic s32 e1000_setup_link_ich8lan(struct e1000_hw *hw); 109177867Sjfvstatic s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw); 110247064Sjfvstatic s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw); 111177867Sjfvstatic s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, 112228386Sjfv u16 *speed, u16 *duplex); 113177867Sjfvstatic s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw); 114177867Sjfvstatic s32 e1000_led_on_ich8lan(struct e1000_hw *hw); 115177867Sjfvstatic s32 e1000_led_off_ich8lan(struct e1000_hw *hw); 116200243Sjfvstatic s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link); 117194865Sjfvstatic s32 e1000_setup_led_pchlan(struct e1000_hw *hw); 118194865Sjfvstatic s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw); 119194865Sjfvstatic s32 e1000_led_on_pchlan(struct e1000_hw *hw); 120194865Sjfvstatic s32 e1000_led_off_pchlan(struct e1000_hw *hw); 121177867Sjfvstatic void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw); 122177867Sjfvstatic s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank); 123173788Sjfvstatic void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw); 124173788Sjfvstatic s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw); 125178523Sjfvstatic s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, 126228386Sjfv u32 offset, u8 *data); 127173788Sjfvstatic s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, 128228386Sjfv u8 size, u16 *data); 129295323Serjstatic s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset, 130295323Serj u32 *data); 131295323Serjstatic s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw, 132295323Serj u32 offset, u32 *data); 133295323Serjstatic s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw, 134295323Serj u32 offset, u32 data); 135295323Serjstatic s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw, 136295323Serj u32 offset, u32 dword); 137177867Sjfvstatic s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, 138228386Sjfv u32 offset, u16 *data); 139173788Sjfvstatic s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw, 140228386Sjfv u32 offset, u8 byte); 141177867Sjfvstatic s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw); 142177867Sjfvstatic void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw); 143200243Sjfvstatic s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw); 144203049Sjfvstatic s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw); 145213234Sjfvstatic s32 e1000_k1_workaround_lv(struct e1000_hw *hw); 146213234Sjfvstatic void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate); 147287990Ssbrunostatic s32 e1000_set_obff_timer_pch_lpt(struct e1000_hw *hw, u32 itr); 148169240Sjfv 149169240Sjfv/* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */ 150169240Sjfv/* Offset 04h HSFSTS */ 151169240Sjfvunion ich8_hws_flash_status { 152169240Sjfv struct ich8_hsfsts { 153228386Sjfv u16 flcdone:1; /* bit 0 Flash Cycle Done */ 154228386Sjfv u16 flcerr:1; /* bit 1 Flash Cycle Error */ 155228386Sjfv u16 dael:1; /* bit 2 Direct Access error Log */ 156228386Sjfv u16 berasesz:2; /* bit 4:3 Sector Erase Size */ 157228386Sjfv u16 flcinprog:1; /* bit 5 flash cycle in Progress */ 158228386Sjfv u16 reserved1:2; /* bit 13:6 Reserved */ 159228386Sjfv u16 reserved2:6; /* bit 13:6 Reserved */ 160228386Sjfv u16 fldesvalid:1; /* bit 14 Flash Descriptor Valid */ 161228386Sjfv u16 flockdn:1; /* bit 15 Flash Config Lock-Down */ 162169240Sjfv } hsf_status; 163169240Sjfv u16 regval; 164169240Sjfv}; 165169240Sjfv 166169240Sjfv/* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */ 167169240Sjfv/* Offset 06h FLCTL */ 168169240Sjfvunion ich8_hws_flash_ctrl { 169169240Sjfv struct ich8_hsflctl { 170228386Sjfv u16 flcgo:1; /* 0 Flash Cycle Go */ 171228386Sjfv u16 flcycle:2; /* 2:1 Flash Cycle */ 172228386Sjfv u16 reserved:5; /* 7:3 Reserved */ 173228386Sjfv u16 fldbcount:2; /* 9:8 Flash Data Byte Count */ 174228386Sjfv u16 flockdn:6; /* 15:10 Reserved */ 175169240Sjfv } hsf_ctrl; 176169240Sjfv u16 regval; 177169240Sjfv}; 178169240Sjfv 179169240Sjfv/* ICH Flash Region Access Permissions */ 180169240Sjfvunion ich8_hws_flash_regacc { 181169240Sjfv struct ich8_flracc { 182228386Sjfv u32 grra:8; /* 0:7 GbE region Read Access */ 183228386Sjfv u32 grwa:8; /* 8:15 GbE region Write Access */ 184228386Sjfv u32 gmrag:8; /* 23:16 GbE Master Read Access Grant */ 185228386Sjfv u32 gmwag:8; /* 31:24 GbE Master Write Access Grant */ 186169240Sjfv } hsf_flregacc; 187169240Sjfv u16 regval; 188169240Sjfv}; 189169240Sjfv 190247064Sjfv/** 191247064Sjfv * e1000_phy_is_accessible_pchlan - Check if able to access PHY registers 192247064Sjfv * @hw: pointer to the HW structure 193247064Sjfv * 194247064Sjfv * Test access to the PHY registers by reading the PHY ID registers. If 195247064Sjfv * the PHY ID is already known (e.g. resume path) compare it with known ID, 196247064Sjfv * otherwise assume the read PHY ID is correct if it is valid. 197247064Sjfv * 198247064Sjfv * Assumes the sw/fw/hw semaphore is already acquired. 199247064Sjfv **/ 200247064Sjfvstatic bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw) 201228386Sjfv{ 202247064Sjfv u16 phy_reg = 0; 203247064Sjfv u32 phy_id = 0; 204256200Sjfv s32 ret_val = 0; 205247064Sjfv u16 retry_count; 206256200Sjfv u32 mac_reg = 0; 207228386Sjfv 208247064Sjfv for (retry_count = 0; retry_count < 2; retry_count++) { 209247064Sjfv ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID1, &phy_reg); 210247064Sjfv if (ret_val || (phy_reg == 0xFFFF)) 211247064Sjfv continue; 212247064Sjfv phy_id = (u32)(phy_reg << 16); 213228386Sjfv 214247064Sjfv ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID2, &phy_reg); 215247064Sjfv if (ret_val || (phy_reg == 0xFFFF)) { 216247064Sjfv phy_id = 0; 217247064Sjfv continue; 218247064Sjfv } 219247064Sjfv phy_id |= (u32)(phy_reg & PHY_REVISION_MASK); 220247064Sjfv break; 221247064Sjfv } 222247064Sjfv 223247064Sjfv if (hw->phy.id) { 224247064Sjfv if (hw->phy.id == phy_id) 225256200Sjfv goto out; 226247064Sjfv } else if (phy_id) { 227247064Sjfv hw->phy.id = phy_id; 228247064Sjfv hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK); 229256200Sjfv goto out; 230247064Sjfv } 231247064Sjfv 232247064Sjfv /* In case the PHY needs to be in mdio slow mode, 233247064Sjfv * set slow mode and try to get the PHY id again. 234247064Sjfv */ 235256200Sjfv if (hw->mac.type < e1000_pch_lpt) { 236256200Sjfv hw->phy.ops.release(hw); 237256200Sjfv ret_val = e1000_set_mdio_slow_mode_hv(hw); 238256200Sjfv if (!ret_val) 239256200Sjfv ret_val = e1000_get_phy_id(hw); 240256200Sjfv hw->phy.ops.acquire(hw); 241256200Sjfv } 242247064Sjfv 243256200Sjfv if (ret_val) 244256200Sjfv return FALSE; 245256200Sjfvout: 246322955Smarius if (hw->mac.type >= e1000_pch_lpt) { 247295323Serj /* Only unforce SMBus if ME is not active */ 248295323Serj if (!(E1000_READ_REG(hw, E1000_FWSM) & 249295323Serj E1000_ICH_FWSM_FW_VALID)) { 250295323Serj /* Unforce SMBus mode in PHY */ 251295323Serj hw->phy.ops.read_reg_locked(hw, CV_SMB_CTRL, &phy_reg); 252295323Serj phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS; 253295323Serj hw->phy.ops.write_reg_locked(hw, CV_SMB_CTRL, phy_reg); 254256200Sjfv 255295323Serj /* Unforce SMBus mode in MAC */ 256295323Serj mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 257295323Serj mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS; 258295323Serj E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg); 259295323Serj } 260256200Sjfv } 261256200Sjfv 262256200Sjfv return TRUE; 263228386Sjfv} 264228386Sjfv 265169240Sjfv/** 266256200Sjfv * e1000_toggle_lanphypc_pch_lpt - toggle the LANPHYPC pin value 267256200Sjfv * @hw: pointer to the HW structure 268256200Sjfv * 269256200Sjfv * Toggling the LANPHYPC pin value fully power-cycles the PHY and is 270256200Sjfv * used to reset the PHY to a quiescent state when necessary. 271256200Sjfv **/ 272267935Sjfvstatic void e1000_toggle_lanphypc_pch_lpt(struct e1000_hw *hw) 273256200Sjfv{ 274256200Sjfv u32 mac_reg; 275256200Sjfv 276256200Sjfv DEBUGFUNC("e1000_toggle_lanphypc_pch_lpt"); 277256200Sjfv 278256200Sjfv /* Set Phy Config Counter to 50msec */ 279256200Sjfv mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM3); 280256200Sjfv mac_reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK; 281256200Sjfv mac_reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC; 282256200Sjfv E1000_WRITE_REG(hw, E1000_FEXTNVM3, mac_reg); 283256200Sjfv 284256200Sjfv /* Toggle LANPHYPC Value bit */ 285256200Sjfv mac_reg = E1000_READ_REG(hw, E1000_CTRL); 286256200Sjfv mac_reg |= E1000_CTRL_LANPHYPC_OVERRIDE; 287256200Sjfv mac_reg &= ~E1000_CTRL_LANPHYPC_VALUE; 288256200Sjfv E1000_WRITE_REG(hw, E1000_CTRL, mac_reg); 289256200Sjfv E1000_WRITE_FLUSH(hw); 290304337Ssbruno msec_delay(1); 291256200Sjfv mac_reg &= ~E1000_CTRL_LANPHYPC_OVERRIDE; 292256200Sjfv E1000_WRITE_REG(hw, E1000_CTRL, mac_reg); 293256200Sjfv E1000_WRITE_FLUSH(hw); 294256200Sjfv 295256200Sjfv if (hw->mac.type < e1000_pch_lpt) { 296256200Sjfv msec_delay(50); 297256200Sjfv } else { 298256200Sjfv u16 count = 20; 299256200Sjfv 300256200Sjfv do { 301256200Sjfv msec_delay(5); 302256200Sjfv } while (!(E1000_READ_REG(hw, E1000_CTRL_EXT) & 303256200Sjfv E1000_CTRL_EXT_LPCD) && count--); 304256200Sjfv 305256200Sjfv msec_delay(30); 306256200Sjfv } 307256200Sjfv} 308256200Sjfv 309256200Sjfv/** 310247064Sjfv * e1000_init_phy_workarounds_pchlan - PHY initialization workarounds 311247064Sjfv * @hw: pointer to the HW structure 312247064Sjfv * 313247064Sjfv * Workarounds/flow necessary for PHY initialization during driver load 314247064Sjfv * and resume paths. 315247064Sjfv **/ 316247064Sjfvstatic s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw) 317247064Sjfv{ 318247064Sjfv u32 mac_reg, fwsm = E1000_READ_REG(hw, E1000_FWSM); 319247064Sjfv s32 ret_val; 320247064Sjfv 321247064Sjfv DEBUGFUNC("e1000_init_phy_workarounds_pchlan"); 322247064Sjfv 323247064Sjfv /* Gate automatic PHY configuration by hardware on managed and 324247064Sjfv * non-managed 82579 and newer adapters. 325247064Sjfv */ 326247064Sjfv e1000_gate_hw_phy_config_ich8lan(hw, TRUE); 327247064Sjfv 328267935Sjfv /* It is not possible to be certain of the current state of ULP 329267935Sjfv * so forcibly disable it. 330267935Sjfv */ 331267935Sjfv hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_unknown; 332267935Sjfv e1000_disable_ulp_lpt_lp(hw, TRUE); 333267935Sjfv 334247064Sjfv ret_val = hw->phy.ops.acquire(hw); 335247064Sjfv if (ret_val) { 336247064Sjfv DEBUGOUT("Failed to initialize PHY flow\n"); 337247064Sjfv goto out; 338247064Sjfv } 339247064Sjfv 340247064Sjfv /* The MAC-PHY interconnect may be in SMBus mode. If the PHY is 341247064Sjfv * inaccessible and resetting the PHY is not blocked, toggle the 342247064Sjfv * LANPHYPC Value bit to force the interconnect to PCIe mode. 343247064Sjfv */ 344247064Sjfv switch (hw->mac.type) { 345247064Sjfv case e1000_pch_lpt: 346295323Serj case e1000_pch_spt: 347333213Smarius case e1000_pch_cnp: 348247064Sjfv if (e1000_phy_is_accessible_pchlan(hw)) 349247064Sjfv break; 350247064Sjfv 351247064Sjfv /* Before toggling LANPHYPC, see if PHY is accessible by 352247064Sjfv * forcing MAC to SMBus mode first. 353247064Sjfv */ 354247064Sjfv mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 355247064Sjfv mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS; 356247064Sjfv E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg); 357247064Sjfv 358256200Sjfv /* Wait 50 milliseconds for MAC to finish any retries 359256200Sjfv * that it might be trying to perform from previous 360256200Sjfv * attempts to acknowledge any phy read requests. 361256200Sjfv */ 362256200Sjfv msec_delay(50); 363256200Sjfv 364247064Sjfv /* fall-through */ 365247064Sjfv case e1000_pch2lan: 366256200Sjfv if (e1000_phy_is_accessible_pchlan(hw)) 367247064Sjfv break; 368247064Sjfv 369247064Sjfv /* fall-through */ 370247064Sjfv case e1000_pchlan: 371247064Sjfv if ((hw->mac.type == e1000_pchlan) && 372247064Sjfv (fwsm & E1000_ICH_FWSM_FW_VALID)) 373247064Sjfv break; 374247064Sjfv 375247064Sjfv if (hw->phy.ops.check_reset_block(hw)) { 376247064Sjfv DEBUGOUT("Required LANPHYPC toggle blocked by ME\n"); 377256200Sjfv ret_val = -E1000_ERR_PHY; 378247064Sjfv break; 379247064Sjfv } 380247064Sjfv 381256200Sjfv /* Toggle LANPHYPC Value bit */ 382256200Sjfv e1000_toggle_lanphypc_pch_lpt(hw); 383256200Sjfv if (hw->mac.type >= e1000_pch_lpt) { 384256200Sjfv if (e1000_phy_is_accessible_pchlan(hw)) 385256200Sjfv break; 386247064Sjfv 387247064Sjfv /* Toggling LANPHYPC brings the PHY out of SMBus mode 388256200Sjfv * so ensure that the MAC is also out of SMBus mode 389247064Sjfv */ 390247064Sjfv mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 391247064Sjfv mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS; 392247064Sjfv E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg); 393247064Sjfv 394256200Sjfv if (e1000_phy_is_accessible_pchlan(hw)) 395256200Sjfv break; 396256200Sjfv 397256200Sjfv ret_val = -E1000_ERR_PHY; 398247064Sjfv } 399247064Sjfv break; 400247064Sjfv default: 401247064Sjfv break; 402247064Sjfv } 403247064Sjfv 404247064Sjfv hw->phy.ops.release(hw); 405256200Sjfv if (!ret_val) { 406247064Sjfv 407256200Sjfv /* Check to see if able to reset PHY. Print error if not */ 408256200Sjfv if (hw->phy.ops.check_reset_block(hw)) { 409256200Sjfv ERROR_REPORT("Reset blocked by ME\n"); 410256200Sjfv goto out; 411256200Sjfv } 412247064Sjfv 413256200Sjfv /* Reset the PHY before any access to it. Doing so, ensures 414256200Sjfv * that the PHY is in a known good state before we read/write 415256200Sjfv * PHY registers. The generic reset is sufficient here, 416256200Sjfv * because we haven't determined the PHY type yet. 417256200Sjfv */ 418256200Sjfv ret_val = e1000_phy_hw_reset_generic(hw); 419256200Sjfv if (ret_val) 420256200Sjfv goto out; 421256200Sjfv 422256200Sjfv /* On a successful reset, possibly need to wait for the PHY 423256200Sjfv * to quiesce to an accessible state before returning control 424256200Sjfv * to the calling function. If the PHY does not quiesce, then 425256200Sjfv * return E1000E_BLK_PHY_RESET, as this is the condition that 426256200Sjfv * the PHY is in. 427256200Sjfv */ 428256200Sjfv ret_val = hw->phy.ops.check_reset_block(hw); 429256200Sjfv if (ret_val) 430256200Sjfv ERROR_REPORT("ME blocked access to PHY after reset\n"); 431256200Sjfv } 432256200Sjfv 433247064Sjfvout: 434247064Sjfv /* Ungate automatic PHY configuration on non-managed 82579 */ 435247064Sjfv if ((hw->mac.type == e1000_pch2lan) && 436247064Sjfv !(fwsm & E1000_ICH_FWSM_FW_VALID)) { 437247064Sjfv msec_delay(10); 438247064Sjfv e1000_gate_hw_phy_config_ich8lan(hw, FALSE); 439247064Sjfv } 440247064Sjfv 441247064Sjfv return ret_val; 442247064Sjfv} 443247064Sjfv 444247064Sjfv/** 445194865Sjfv * e1000_init_phy_params_pchlan - Initialize PHY function pointers 446194865Sjfv * @hw: pointer to the HW structure 447194865Sjfv * 448194865Sjfv * Initialize family-specific PHY parameters and function pointers. 449194865Sjfv **/ 450194865Sjfvstatic s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw) 451194865Sjfv{ 452194865Sjfv struct e1000_phy_info *phy = &hw->phy; 453247064Sjfv s32 ret_val; 454194865Sjfv 455194865Sjfv DEBUGFUNC("e1000_init_phy_params_pchlan"); 456194865Sjfv 457228386Sjfv phy->addr = 1; 458228386Sjfv phy->reset_delay_us = 100; 459194865Sjfv 460228386Sjfv phy->ops.acquire = e1000_acquire_swflag_ich8lan; 461228386Sjfv phy->ops.check_reset_block = e1000_check_reset_block_ich8lan; 462228386Sjfv phy->ops.get_cfg_done = e1000_get_cfg_done_ich8lan; 463228386Sjfv phy->ops.set_page = e1000_set_page_igp; 464228386Sjfv phy->ops.read_reg = e1000_read_phy_reg_hv; 465228386Sjfv phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked; 466228386Sjfv phy->ops.read_reg_page = e1000_read_phy_reg_page_hv; 467228386Sjfv phy->ops.release = e1000_release_swflag_ich8lan; 468228386Sjfv phy->ops.reset = e1000_phy_hw_reset_ich8lan; 469228386Sjfv phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan; 470228386Sjfv phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan; 471228386Sjfv phy->ops.write_reg = e1000_write_phy_reg_hv; 472228386Sjfv phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked; 473228386Sjfv phy->ops.write_reg_page = e1000_write_phy_reg_page_hv; 474228386Sjfv phy->ops.power_up = e1000_power_up_phy_copper; 475228386Sjfv phy->ops.power_down = e1000_power_down_phy_copper_ich8lan; 476228386Sjfv phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 477194865Sjfv 478247064Sjfv phy->id = e1000_phy_unknown; 479228386Sjfv 480247064Sjfv ret_val = e1000_init_phy_workarounds_pchlan(hw); 481247064Sjfv if (ret_val) 482247064Sjfv return ret_val; 483213234Sjfv 484247064Sjfv if (phy->id == e1000_phy_unknown) 485247064Sjfv switch (hw->mac.type) { 486247064Sjfv default: 487247064Sjfv ret_val = e1000_get_phy_id(hw); 488247064Sjfv if (ret_val) 489247064Sjfv return ret_val; 490247064Sjfv if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK)) 491247064Sjfv break; 492247064Sjfv /* fall-through */ 493247064Sjfv case e1000_pch2lan: 494247064Sjfv case e1000_pch_lpt: 495295323Serj case e1000_pch_spt: 496333213Smarius case e1000_pch_cnp: 497247064Sjfv /* In case the PHY needs to be in mdio slow mode, 498247064Sjfv * set slow mode and try to get the PHY id again. 499247064Sjfv */ 500247064Sjfv ret_val = e1000_set_mdio_slow_mode_hv(hw); 501247064Sjfv if (ret_val) 502247064Sjfv return ret_val; 503247064Sjfv ret_val = e1000_get_phy_id(hw); 504247064Sjfv if (ret_val) 505247064Sjfv return ret_val; 506247064Sjfv break; 507228386Sjfv } 508194865Sjfv phy->type = e1000_get_phy_type_from_id(phy->id); 509194865Sjfv 510200243Sjfv switch (phy->type) { 511200243Sjfv case e1000_phy_82577: 512213234Sjfv case e1000_phy_82579: 513247064Sjfv case e1000_phy_i217: 514194865Sjfv phy->ops.check_polarity = e1000_check_polarity_82577; 515194865Sjfv phy->ops.force_speed_duplex = 516194865Sjfv e1000_phy_force_speed_duplex_82577; 517200243Sjfv phy->ops.get_cable_length = e1000_get_cable_length_82577; 518194865Sjfv phy->ops.get_info = e1000_get_phy_info_82577; 519194865Sjfv phy->ops.commit = e1000_phy_sw_reset_generic; 520205869Sjfv break; 521200243Sjfv case e1000_phy_82578: 522200243Sjfv phy->ops.check_polarity = e1000_check_polarity_m88; 523200243Sjfv phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88; 524200243Sjfv phy->ops.get_cable_length = e1000_get_cable_length_m88; 525200243Sjfv phy->ops.get_info = e1000_get_phy_info_m88; 526200243Sjfv break; 527200243Sjfv default: 528200243Sjfv ret_val = -E1000_ERR_PHY; 529200243Sjfv break; 530194865Sjfv } 531194865Sjfv 532194865Sjfv return ret_val; 533194865Sjfv} 534194865Sjfv 535194865Sjfv/** 536169240Sjfv * e1000_init_phy_params_ich8lan - Initialize PHY function pointers 537169589Sjfv * @hw: pointer to the HW structure 538169240Sjfv * 539169240Sjfv * Initialize family-specific PHY parameters and function pointers. 540169240Sjfv **/ 541177867Sjfvstatic s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw) 542169240Sjfv{ 543169240Sjfv struct e1000_phy_info *phy = &hw->phy; 544247064Sjfv s32 ret_val; 545169589Sjfv u16 i = 0; 546169240Sjfv 547169240Sjfv DEBUGFUNC("e1000_init_phy_params_ich8lan"); 548169240Sjfv 549228386Sjfv phy->addr = 1; 550228386Sjfv phy->reset_delay_us = 100; 551169240Sjfv 552228386Sjfv phy->ops.acquire = e1000_acquire_swflag_ich8lan; 553228386Sjfv phy->ops.check_reset_block = e1000_check_reset_block_ich8lan; 554228386Sjfv phy->ops.get_cable_length = e1000_get_cable_length_igp_2; 555228386Sjfv phy->ops.get_cfg_done = e1000_get_cfg_done_ich8lan; 556228386Sjfv phy->ops.read_reg = e1000_read_phy_reg_igp; 557228386Sjfv phy->ops.release = e1000_release_swflag_ich8lan; 558228386Sjfv phy->ops.reset = e1000_phy_hw_reset_ich8lan; 559228386Sjfv phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan; 560228386Sjfv phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan; 561228386Sjfv phy->ops.write_reg = e1000_write_phy_reg_igp; 562228386Sjfv phy->ops.power_up = e1000_power_up_phy_copper; 563228386Sjfv phy->ops.power_down = e1000_power_down_phy_copper_ich8lan; 564169240Sjfv 565247064Sjfv /* We may need to do this twice - once for IGP and if that fails, 566176667Sjfv * we'll set BM func pointers and try again 567176667Sjfv */ 568176667Sjfv ret_val = e1000_determine_phy_address(hw); 569176667Sjfv if (ret_val) { 570177867Sjfv phy->ops.write_reg = e1000_write_phy_reg_bm; 571177867Sjfv phy->ops.read_reg = e1000_read_phy_reg_bm; 572176667Sjfv ret_val = e1000_determine_phy_address(hw); 573176667Sjfv if (ret_val) { 574190872Sjfv DEBUGOUT("Cannot determine PHY addr. Erroring out\n"); 575247064Sjfv return ret_val; 576176667Sjfv } 577176667Sjfv } 578169240Sjfv 579169589Sjfv phy->id = 0; 580169589Sjfv while ((e1000_phy_unknown == e1000_get_phy_type_from_id(phy->id)) && 581169589Sjfv (i++ < 100)) { 582169589Sjfv msec_delay(1); 583169589Sjfv ret_val = e1000_get_phy_id(hw); 584169589Sjfv if (ret_val) 585247064Sjfv return ret_val; 586169589Sjfv } 587169589Sjfv 588169240Sjfv /* Verify phy id */ 589169240Sjfv switch (phy->id) { 590169240Sjfv case IGP03E1000_E_PHY_ID: 591169240Sjfv phy->type = e1000_phy_igp_3; 592169240Sjfv phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 593200243Sjfv phy->ops.read_reg_locked = e1000_read_phy_reg_igp_locked; 594200243Sjfv phy->ops.write_reg_locked = e1000_write_phy_reg_igp_locked; 595200243Sjfv phy->ops.get_info = e1000_get_phy_info_igp; 596200243Sjfv phy->ops.check_polarity = e1000_check_polarity_igp; 597200243Sjfv phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp; 598169240Sjfv break; 599169240Sjfv case IFE_E_PHY_ID: 600169240Sjfv case IFE_PLUS_E_PHY_ID: 601169240Sjfv case IFE_C_E_PHY_ID: 602169240Sjfv phy->type = e1000_phy_ife; 603169240Sjfv phy->autoneg_mask = E1000_ALL_NOT_GIG; 604200243Sjfv phy->ops.get_info = e1000_get_phy_info_ife; 605200243Sjfv phy->ops.check_polarity = e1000_check_polarity_ife; 606200243Sjfv phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife; 607169240Sjfv break; 608176667Sjfv case BME1000_E_PHY_ID: 609176667Sjfv phy->type = e1000_phy_bm; 610176667Sjfv phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 611177867Sjfv phy->ops.read_reg = e1000_read_phy_reg_bm; 612177867Sjfv phy->ops.write_reg = e1000_write_phy_reg_bm; 613177867Sjfv phy->ops.commit = e1000_phy_sw_reset_generic; 614200243Sjfv phy->ops.get_info = e1000_get_phy_info_m88; 615200243Sjfv phy->ops.check_polarity = e1000_check_polarity_m88; 616200243Sjfv phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88; 617176667Sjfv break; 618169240Sjfv default: 619247064Sjfv return -E1000_ERR_PHY; 620247064Sjfv break; 621169240Sjfv } 622169240Sjfv 623247064Sjfv return E1000_SUCCESS; 624169240Sjfv} 625169240Sjfv 626169240Sjfv/** 627169240Sjfv * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers 628169589Sjfv * @hw: pointer to the HW structure 629169240Sjfv * 630169240Sjfv * Initialize family-specific NVM parameters and function 631169240Sjfv * pointers. 632169240Sjfv **/ 633177867Sjfvstatic s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw) 634169240Sjfv{ 635169240Sjfv struct e1000_nvm_info *nvm = &hw->nvm; 636185353Sjfv struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 637169240Sjfv u32 gfpreg, sector_base_addr, sector_end_addr; 638169240Sjfv u16 i; 639295323Serj u32 nvm_size; 640169240Sjfv 641169240Sjfv DEBUGFUNC("e1000_init_nvm_params_ich8lan"); 642169240Sjfv 643267935Sjfv nvm->type = e1000_nvm_flash_sw; 644169240Sjfv 645322955Smarius if (hw->mac.type >= e1000_pch_spt) { 646295323Serj /* in SPT, gfpreg doesn't exist. NVM size is taken from the 647295323Serj * STRAP register. This is because in SPT the GbE Flash region 648295323Serj * is no longer accessed through the flash registers. Instead, 649295323Serj * the mechanism has changed, and the Flash region access 650295323Serj * registers are now implemented in GbE memory space. 651295323Serj */ 652295323Serj nvm->flash_base_addr = 0; 653295323Serj nvm_size = 654295323Serj (((E1000_READ_REG(hw, E1000_STRAP) >> 1) & 0x1F) + 1) 655295323Serj * NVM_SIZE_MULTIPLIER; 656295323Serj nvm->flash_bank_size = nvm_size / 2; 657295323Serj /* Adjust to word count */ 658295323Serj nvm->flash_bank_size /= sizeof(u16); 659295323Serj /* Set the base address for flash register access */ 660295323Serj hw->flash_address = hw->hw_addr + E1000_FLASH_BASE_ADDR; 661295323Serj } else { 662295323Serj /* Can't read flash registers if register set isn't mapped. */ 663295323Serj if (!hw->flash_address) { 664295323Serj DEBUGOUT("ERROR: Flash registers not mapped\n"); 665295323Serj return -E1000_ERR_CONFIG; 666295323Serj } 667169240Sjfv 668295323Serj gfpreg = E1000_READ_FLASH_REG(hw, ICH_FLASH_GFPREG); 669169240Sjfv 670295323Serj /* sector_X_addr is a "sector"-aligned address (4096 bytes) 671295323Serj * Add 1 to sector_end_addr since this sector is included in 672295323Serj * the overall size. 673295323Serj */ 674295323Serj sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK; 675295323Serj sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1; 676169240Sjfv 677295323Serj /* flash_base_addr is byte-aligned */ 678295323Serj nvm->flash_base_addr = sector_base_addr 679295323Serj << FLASH_SECTOR_ADDR_SHIFT; 680169240Sjfv 681295323Serj /* find total size of the NVM, then cut in half since the total 682295323Serj * size represents two separate NVM banks. 683295323Serj */ 684295323Serj nvm->flash_bank_size = ((sector_end_addr - sector_base_addr) 685295323Serj << FLASH_SECTOR_ADDR_SHIFT); 686295323Serj nvm->flash_bank_size /= 2; 687295323Serj /* Adjust to word count */ 688295323Serj nvm->flash_bank_size /= sizeof(u16); 689295323Serj } 690295323Serj 691185353Sjfv nvm->word_size = E1000_SHADOW_RAM_WORDS; 692169240Sjfv 693169240Sjfv /* Clear shadow ram */ 694169240Sjfv for (i = 0; i < nvm->word_size; i++) { 695169240Sjfv dev_spec->shadow_ram[i].modified = FALSE; 696169240Sjfv dev_spec->shadow_ram[i].value = 0xFFFF; 697169240Sjfv } 698169240Sjfv 699200243Sjfv E1000_MUTEX_INIT(&dev_spec->nvm_mutex); 700200243Sjfv E1000_MUTEX_INIT(&dev_spec->swflag_mutex); 701200243Sjfv 702169240Sjfv /* Function Pointers */ 703228386Sjfv nvm->ops.acquire = e1000_acquire_nvm_ich8lan; 704228386Sjfv nvm->ops.release = e1000_release_nvm_ich8lan; 705322955Smarius if (hw->mac.type >= e1000_pch_spt) { 706295323Serj nvm->ops.read = e1000_read_nvm_spt; 707295323Serj nvm->ops.update = e1000_update_nvm_checksum_spt; 708295323Serj } else { 709295323Serj nvm->ops.read = e1000_read_nvm_ich8lan; 710295323Serj nvm->ops.update = e1000_update_nvm_checksum_ich8lan; 711295323Serj } 712177867Sjfv nvm->ops.valid_led_default = e1000_valid_led_default_ich8lan; 713228386Sjfv nvm->ops.validate = e1000_validate_nvm_checksum_ich8lan; 714228386Sjfv nvm->ops.write = e1000_write_nvm_ich8lan; 715169240Sjfv 716247064Sjfv return E1000_SUCCESS; 717169240Sjfv} 718169240Sjfv 719169240Sjfv/** 720169240Sjfv * e1000_init_mac_params_ich8lan - Initialize MAC function pointers 721169589Sjfv * @hw: pointer to the HW structure 722169240Sjfv * 723169240Sjfv * Initialize family-specific MAC parameters and function 724169240Sjfv * pointers. 725169240Sjfv **/ 726177867Sjfvstatic s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw) 727169240Sjfv{ 728169240Sjfv struct e1000_mac_info *mac = &hw->mac; 729169240Sjfv 730169240Sjfv DEBUGFUNC("e1000_init_mac_params_ich8lan"); 731169240Sjfv 732169240Sjfv /* Set media type function pointer */ 733173788Sjfv hw->phy.media_type = e1000_media_type_copper; 734169240Sjfv 735169240Sjfv /* Set mta register count */ 736169240Sjfv mac->mta_reg_count = 32; 737169240Sjfv /* Set rar entry count */ 738169240Sjfv mac->rar_entry_count = E1000_ICH_RAR_ENTRIES; 739169240Sjfv if (mac->type == e1000_ich8lan) 740169240Sjfv mac->rar_entry_count--; 741169240Sjfv /* Set if part includes ASF firmware */ 742169240Sjfv mac->asf_firmware_present = TRUE; 743205869Sjfv /* FWSM register */ 744205869Sjfv mac->has_fwsm = TRUE; 745205869Sjfv /* ARC subsystem not supported */ 746205869Sjfv mac->arc_subsystem_valid = FALSE; 747200243Sjfv /* Adaptive IFS supported */ 748200243Sjfv mac->adaptive_ifs = TRUE; 749169240Sjfv 750169240Sjfv /* Function pointers */ 751169240Sjfv 752169240Sjfv /* bus type/speed/width */ 753177867Sjfv mac->ops.get_bus_info = e1000_get_bus_info_ich8lan; 754185353Sjfv /* function id */ 755185353Sjfv mac->ops.set_lan_id = e1000_set_lan_id_single_port; 756169240Sjfv /* reset */ 757177867Sjfv mac->ops.reset_hw = e1000_reset_hw_ich8lan; 758169240Sjfv /* hw initialization */ 759177867Sjfv mac->ops.init_hw = e1000_init_hw_ich8lan; 760169240Sjfv /* link setup */ 761177867Sjfv mac->ops.setup_link = e1000_setup_link_ich8lan; 762169240Sjfv /* physical interface setup */ 763177867Sjfv mac->ops.setup_physical_interface = e1000_setup_copper_link_ich8lan; 764169240Sjfv /* check for link */ 765200243Sjfv mac->ops.check_for_link = e1000_check_for_copper_link_ich8lan; 766169240Sjfv /* link info */ 767177867Sjfv mac->ops.get_link_up_info = e1000_get_link_up_info_ich8lan; 768169240Sjfv /* multicast address update */ 769177867Sjfv mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic; 770169240Sjfv /* clear hardware counters */ 771177867Sjfv mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan; 772169240Sjfv 773247064Sjfv /* LED and other operations */ 774190872Sjfv switch (mac->type) { 775190872Sjfv case e1000_ich8lan: 776190872Sjfv case e1000_ich9lan: 777190872Sjfv case e1000_ich10lan: 778213234Sjfv /* check management mode */ 779213234Sjfv mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan; 780190872Sjfv /* ID LED init */ 781190872Sjfv mac->ops.id_led_init = e1000_id_led_init_generic; 782190872Sjfv /* blink LED */ 783190872Sjfv mac->ops.blink_led = e1000_blink_led_generic; 784190872Sjfv /* setup LED */ 785190872Sjfv mac->ops.setup_led = e1000_setup_led_generic; 786190872Sjfv /* cleanup LED */ 787190872Sjfv mac->ops.cleanup_led = e1000_cleanup_led_ich8lan; 788190872Sjfv /* turn on/off LED */ 789190872Sjfv mac->ops.led_on = e1000_led_on_ich8lan; 790190872Sjfv mac->ops.led_off = e1000_led_off_ich8lan; 791190872Sjfv break; 792213234Sjfv case e1000_pch2lan: 793213234Sjfv mac->rar_entry_count = E1000_PCH2_RAR_ENTRIES; 794213234Sjfv mac->ops.rar_set = e1000_rar_set_pch2lan; 795247064Sjfv /* fall-through */ 796247064Sjfv case e1000_pch_lpt: 797295323Serj case e1000_pch_spt: 798333213Smarius case e1000_pch_cnp: 799218588Sjfv /* multicast address update for pch2 */ 800218588Sjfv mac->ops.update_mc_addr_list = 801218588Sjfv e1000_update_mc_addr_list_pch2lan; 802295323Serj /* fall-through */ 803194865Sjfv case e1000_pchlan: 804213234Sjfv /* check management mode */ 805213234Sjfv mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan; 806194865Sjfv /* ID LED init */ 807194865Sjfv mac->ops.id_led_init = e1000_id_led_init_pchlan; 808194865Sjfv /* setup LED */ 809194865Sjfv mac->ops.setup_led = e1000_setup_led_pchlan; 810194865Sjfv /* cleanup LED */ 811194865Sjfv mac->ops.cleanup_led = e1000_cleanup_led_pchlan; 812194865Sjfv /* turn on/off LED */ 813194865Sjfv mac->ops.led_on = e1000_led_on_pchlan; 814194865Sjfv mac->ops.led_off = e1000_led_off_pchlan; 815194865Sjfv break; 816190872Sjfv default: 817190872Sjfv break; 818190872Sjfv } 819190872Sjfv 820322955Smarius if (mac->type >= e1000_pch_lpt) { 821247064Sjfv mac->rar_entry_count = E1000_PCH_LPT_RAR_ENTRIES; 822247064Sjfv mac->ops.rar_set = e1000_rar_set_pch_lpt; 823247064Sjfv mac->ops.setup_physical_interface = e1000_setup_copper_link_pch_lpt; 824287990Ssbruno mac->ops.set_obff_timer = e1000_set_obff_timer_pch_lpt; 825228386Sjfv } 826228386Sjfv 827169240Sjfv /* Enable PCS Lock-loss workaround for ICH8 */ 828169240Sjfv if (mac->type == e1000_ich8lan) 829169240Sjfv e1000_set_kmrn_lock_loss_workaround_ich8lan(hw, TRUE); 830169240Sjfv 831185353Sjfv return E1000_SUCCESS; 832169240Sjfv} 833169240Sjfv 834169240Sjfv/** 835247064Sjfv * __e1000_access_emi_reg_locked - Read/write EMI register 836247064Sjfv * @hw: pointer to the HW structure 837247064Sjfv * @addr: EMI address to program 838247064Sjfv * @data: pointer to value to read/write from/to the EMI address 839247064Sjfv * @read: boolean flag to indicate read or write 840247064Sjfv * 841247064Sjfv * This helper function assumes the SW/FW/HW Semaphore is already acquired. 842247064Sjfv **/ 843247064Sjfvstatic s32 __e1000_access_emi_reg_locked(struct e1000_hw *hw, u16 address, 844247064Sjfv u16 *data, bool read) 845247064Sjfv{ 846247064Sjfv s32 ret_val; 847247064Sjfv 848247064Sjfv DEBUGFUNC("__e1000_access_emi_reg_locked"); 849247064Sjfv 850247064Sjfv ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_ADDR, address); 851247064Sjfv if (ret_val) 852247064Sjfv return ret_val; 853247064Sjfv 854247064Sjfv if (read) 855247064Sjfv ret_val = hw->phy.ops.read_reg_locked(hw, I82579_EMI_DATA, 856247064Sjfv data); 857247064Sjfv else 858247064Sjfv ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_DATA, 859247064Sjfv *data); 860247064Sjfv 861247064Sjfv return ret_val; 862247064Sjfv} 863247064Sjfv 864247064Sjfv/** 865247064Sjfv * e1000_read_emi_reg_locked - Read Extended Management Interface register 866247064Sjfv * @hw: pointer to the HW structure 867247064Sjfv * @addr: EMI address to program 868247064Sjfv * @data: value to be read from the EMI address 869247064Sjfv * 870247064Sjfv * Assumes the SW/FW/HW Semaphore is already acquired. 871247064Sjfv **/ 872247064Sjfvs32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data) 873247064Sjfv{ 874247064Sjfv DEBUGFUNC("e1000_read_emi_reg_locked"); 875247064Sjfv 876247064Sjfv return __e1000_access_emi_reg_locked(hw, addr, data, TRUE); 877247064Sjfv} 878247064Sjfv 879247064Sjfv/** 880247064Sjfv * e1000_write_emi_reg_locked - Write Extended Management Interface register 881247064Sjfv * @hw: pointer to the HW structure 882247064Sjfv * @addr: EMI address to program 883247064Sjfv * @data: value to be written to the EMI address 884247064Sjfv * 885247064Sjfv * Assumes the SW/FW/HW Semaphore is already acquired. 886247064Sjfv **/ 887256200Sjfvs32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data) 888247064Sjfv{ 889247064Sjfv DEBUGFUNC("e1000_read_emi_reg_locked"); 890247064Sjfv 891247064Sjfv return __e1000_access_emi_reg_locked(hw, addr, &data, FALSE); 892247064Sjfv} 893247064Sjfv 894247064Sjfv/** 895213234Sjfv * e1000_set_eee_pchlan - Enable/disable EEE support 896213234Sjfv * @hw: pointer to the HW structure 897213234Sjfv * 898247064Sjfv * Enable/disable EEE based on setting in dev_spec structure, the duplex of 899247064Sjfv * the link and the EEE capabilities of the link partner. The LPI Control 900247064Sjfv * register bits will remain set only if/when link is up. 901256200Sjfv * 902256200Sjfv * EEE LPI must not be asserted earlier than one second after link is up. 903256200Sjfv * On 82579, EEE LPI should not be enabled until such time otherwise there 904256200Sjfv * can be link issues with some switches. Other devices can have EEE LPI 905256200Sjfv * enabled immediately upon link up since they have a timer in hardware which 906256200Sjfv * prevents LPI from being asserted too early. 907213234Sjfv **/ 908256200Sjfvs32 e1000_set_eee_pchlan(struct e1000_hw *hw) 909213234Sjfv{ 910228386Sjfv struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 911247064Sjfv s32 ret_val; 912256200Sjfv u16 lpa, pcs_status, adv, adv_addr, lpi_ctrl, data; 913213234Sjfv 914213234Sjfv DEBUGFUNC("e1000_set_eee_pchlan"); 915213234Sjfv 916256200Sjfv switch (hw->phy.type) { 917256200Sjfv case e1000_phy_82579: 918256200Sjfv lpa = I82579_EEE_LP_ABILITY; 919256200Sjfv pcs_status = I82579_EEE_PCS_STATUS; 920256200Sjfv adv_addr = I82579_EEE_ADVERTISEMENT; 921256200Sjfv break; 922256200Sjfv case e1000_phy_i217: 923256200Sjfv lpa = I217_EEE_LP_ABILITY; 924256200Sjfv pcs_status = I217_EEE_PCS_STATUS; 925256200Sjfv adv_addr = I217_EEE_ADVERTISEMENT; 926256200Sjfv break; 927256200Sjfv default: 928247064Sjfv return E1000_SUCCESS; 929256200Sjfv } 930213234Sjfv 931247064Sjfv ret_val = hw->phy.ops.acquire(hw); 932213234Sjfv if (ret_val) 933247064Sjfv return ret_val; 934213234Sjfv 935247064Sjfv ret_val = hw->phy.ops.read_reg_locked(hw, I82579_LPI_CTRL, &lpi_ctrl); 936247064Sjfv if (ret_val) 937247064Sjfv goto release; 938213234Sjfv 939247064Sjfv /* Clear bits that enable EEE in various speeds */ 940247064Sjfv lpi_ctrl &= ~I82579_LPI_CTRL_ENABLE_MASK; 941247064Sjfv 942247064Sjfv /* Enable EEE if not disabled by user */ 943247064Sjfv if (!dev_spec->eee_disable) { 944247064Sjfv /* Save off link partner's EEE ability */ 945247064Sjfv ret_val = e1000_read_emi_reg_locked(hw, lpa, 946247064Sjfv &dev_spec->eee_lp_ability); 947247064Sjfv if (ret_val) 948247064Sjfv goto release; 949247064Sjfv 950256200Sjfv /* Read EEE advertisement */ 951256200Sjfv ret_val = e1000_read_emi_reg_locked(hw, adv_addr, &adv); 952256200Sjfv if (ret_val) 953256200Sjfv goto release; 954256200Sjfv 955247064Sjfv /* Enable EEE only for speeds in which the link partner is 956256200Sjfv * EEE capable and for which we advertise EEE. 957247064Sjfv */ 958256200Sjfv if (adv & dev_spec->eee_lp_ability & I82579_EEE_1000_SUPPORTED) 959247064Sjfv lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE; 960247064Sjfv 961256200Sjfv if (adv & dev_spec->eee_lp_ability & I82579_EEE_100_SUPPORTED) { 962247064Sjfv hw->phy.ops.read_reg_locked(hw, PHY_LP_ABILITY, &data); 963247064Sjfv if (data & NWAY_LPAR_100TX_FD_CAPS) 964247064Sjfv lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE; 965247064Sjfv else 966247064Sjfv /* EEE is not supported in 100Half, so ignore 967247064Sjfv * partner's EEE in 100 ability if full-duplex 968247064Sjfv * is not advertised. 969247064Sjfv */ 970247064Sjfv dev_spec->eee_lp_ability &= 971247064Sjfv ~I82579_EEE_100_SUPPORTED; 972247064Sjfv } 973247064Sjfv } 974247064Sjfv 975267935Sjfv if (hw->phy.type == e1000_phy_82579) { 976267935Sjfv ret_val = e1000_read_emi_reg_locked(hw, I82579_LPI_PLL_SHUT, 977267935Sjfv &data); 978267935Sjfv if (ret_val) 979267935Sjfv goto release; 980267935Sjfv 981267935Sjfv data &= ~I82579_LPI_100_PLL_SHUT; 982267935Sjfv ret_val = e1000_write_emi_reg_locked(hw, I82579_LPI_PLL_SHUT, 983267935Sjfv data); 984267935Sjfv } 985267935Sjfv 986256200Sjfv /* R/Clr IEEE MMD 3.1 bits 11:10 - Tx/Rx LPI Received */ 987256200Sjfv ret_val = e1000_read_emi_reg_locked(hw, pcs_status, &data); 988256200Sjfv if (ret_val) 989256200Sjfv goto release; 990256200Sjfv 991247064Sjfv ret_val = hw->phy.ops.write_reg_locked(hw, I82579_LPI_CTRL, lpi_ctrl); 992247064Sjfvrelease: 993247064Sjfv hw->phy.ops.release(hw); 994247064Sjfv 995213234Sjfv return ret_val; 996213234Sjfv} 997213234Sjfv 998213234Sjfv/** 999247064Sjfv * e1000_k1_workaround_lpt_lp - K1 workaround on Lynxpoint-LP 1000247064Sjfv * @hw: pointer to the HW structure 1001247064Sjfv * @link: link up bool flag 1002247064Sjfv * 1003247064Sjfv * When K1 is enabled for 1Gbps, the MAC can miss 2 DMA completion indications 1004247064Sjfv * preventing further DMA write requests. Workaround the issue by disabling 1005247064Sjfv * the de-assertion of the clock request when in 1Gpbs mode. 1006256200Sjfv * Also, set appropriate Tx re-transmission timeouts for 10 and 100Half link 1007256200Sjfv * speeds in order to avoid Tx hangs. 1008247064Sjfv **/ 1009247064Sjfvstatic s32 e1000_k1_workaround_lpt_lp(struct e1000_hw *hw, bool link) 1010247064Sjfv{ 1011247064Sjfv u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6); 1012256200Sjfv u32 status = E1000_READ_REG(hw, E1000_STATUS); 1013247064Sjfv s32 ret_val = E1000_SUCCESS; 1014256200Sjfv u16 reg; 1015247064Sjfv 1016256200Sjfv if (link && (status & E1000_STATUS_SPEED_1000)) { 1017247064Sjfv ret_val = hw->phy.ops.acquire(hw); 1018247064Sjfv if (ret_val) 1019247064Sjfv return ret_val; 1020247064Sjfv 1021247064Sjfv ret_val = 1022247064Sjfv e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG, 1023256200Sjfv ®); 1024247064Sjfv if (ret_val) 1025247064Sjfv goto release; 1026247064Sjfv 1027247064Sjfv ret_val = 1028247064Sjfv e1000_write_kmrn_reg_locked(hw, 1029247064Sjfv E1000_KMRNCTRLSTA_K1_CONFIG, 1030256200Sjfv reg & 1031247064Sjfv ~E1000_KMRNCTRLSTA_K1_ENABLE); 1032247064Sjfv if (ret_val) 1033247064Sjfv goto release; 1034247064Sjfv 1035247064Sjfv usec_delay(10); 1036247064Sjfv 1037247064Sjfv E1000_WRITE_REG(hw, E1000_FEXTNVM6, 1038247064Sjfv fextnvm6 | E1000_FEXTNVM6_REQ_PLL_CLK); 1039247064Sjfv 1040247064Sjfv ret_val = 1041247064Sjfv e1000_write_kmrn_reg_locked(hw, 1042247064Sjfv E1000_KMRNCTRLSTA_K1_CONFIG, 1043256200Sjfv reg); 1044247064Sjfvrelease: 1045247064Sjfv hw->phy.ops.release(hw); 1046247064Sjfv } else { 1047247064Sjfv /* clear FEXTNVM6 bit 8 on link down or 10/100 */ 1048256200Sjfv fextnvm6 &= ~E1000_FEXTNVM6_REQ_PLL_CLK; 1049256200Sjfv 1050295323Serj if ((hw->phy.revision > 5) || !link || 1051295323Serj ((status & E1000_STATUS_SPEED_100) && 1052295323Serj (status & E1000_STATUS_FD))) 1053256200Sjfv goto update_fextnvm6; 1054256200Sjfv 1055256200Sjfv ret_val = hw->phy.ops.read_reg(hw, I217_INBAND_CTRL, ®); 1056256200Sjfv if (ret_val) 1057256200Sjfv return ret_val; 1058256200Sjfv 1059256200Sjfv /* Clear link status transmit timeout */ 1060256200Sjfv reg &= ~I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK; 1061256200Sjfv 1062256200Sjfv if (status & E1000_STATUS_SPEED_100) { 1063256200Sjfv /* Set inband Tx timeout to 5x10us for 100Half */ 1064256200Sjfv reg |= 5 << I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT; 1065256200Sjfv 1066256200Sjfv /* Do not extend the K1 entry latency for 100Half */ 1067256200Sjfv fextnvm6 &= ~E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION; 1068256200Sjfv } else { 1069256200Sjfv /* Set inband Tx timeout to 50x10us for 10Full/Half */ 1070256200Sjfv reg |= 50 << 1071256200Sjfv I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT; 1072256200Sjfv 1073256200Sjfv /* Extend the K1 entry latency for 10 Mbps */ 1074256200Sjfv fextnvm6 |= E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION; 1075256200Sjfv } 1076256200Sjfv 1077256200Sjfv ret_val = hw->phy.ops.write_reg(hw, I217_INBAND_CTRL, reg); 1078256200Sjfv if (ret_val) 1079256200Sjfv return ret_val; 1080256200Sjfv 1081256200Sjfvupdate_fextnvm6: 1082256200Sjfv E1000_WRITE_REG(hw, E1000_FEXTNVM6, fextnvm6); 1083247064Sjfv } 1084247064Sjfv 1085247064Sjfv return ret_val; 1086247064Sjfv} 1087247064Sjfv 1088287990Ssbrunostatic u64 e1000_ltr2ns(u16 ltr) 1089287990Ssbruno{ 1090287990Ssbruno u32 value, scale; 1091287990Ssbruno 1092287990Ssbruno /* Determine the latency in nsec based on the LTR value & scale */ 1093287990Ssbruno value = ltr & E1000_LTRV_VALUE_MASK; 1094287990Ssbruno scale = (ltr & E1000_LTRV_SCALE_MASK) >> E1000_LTRV_SCALE_SHIFT; 1095287990Ssbruno 1096287990Ssbruno return value * (1 << (scale * E1000_LTRV_SCALE_FACTOR)); 1097287990Ssbruno} 1098287990Ssbruno 1099247064Sjfv/** 1100287990Ssbruno * e1000_platform_pm_pch_lpt - Set platform power management values 1101287990Ssbruno * @hw: pointer to the HW structure 1102287990Ssbruno * @link: bool indicating link status 1103287990Ssbruno * 1104287990Ssbruno * Set the Latency Tolerance Reporting (LTR) values for the "PCIe-like" 1105287990Ssbruno * GbE MAC in the Lynx Point PCH based on Rx buffer size and link speed 1106287990Ssbruno * when link is up (which must not exceed the maximum latency supported 1107287990Ssbruno * by the platform), otherwise specify there is no LTR requirement. 1108287990Ssbruno * Unlike TRUE-PCIe devices which set the LTR maximum snoop/no-snoop 1109287990Ssbruno * latencies in the LTR Extended Capability Structure in the PCIe Extended 1110287990Ssbruno * Capability register set, on this device LTR is set by writing the 1111287990Ssbruno * equivalent snoop/no-snoop latencies in the LTRV register in the MAC and 1112287990Ssbruno * set the SEND bit to send an Intel On-chip System Fabric sideband (IOSF-SB) 1113287990Ssbruno * message to the PMC. 1114287990Ssbruno * 1115287990Ssbruno * Use the LTR value to calculate the Optimized Buffer Flush/Fill (OBFF) 1116287990Ssbruno * high-water mark. 1117287990Ssbruno **/ 1118287990Ssbrunostatic s32 e1000_platform_pm_pch_lpt(struct e1000_hw *hw, bool link) 1119287990Ssbruno{ 1120287990Ssbruno u32 reg = link << (E1000_LTRV_REQ_SHIFT + E1000_LTRV_NOSNOOP_SHIFT) | 1121287990Ssbruno link << E1000_LTRV_REQ_SHIFT | E1000_LTRV_SEND; 1122287990Ssbruno u16 lat_enc = 0; /* latency encoded */ 1123287990Ssbruno s32 obff_hwm = 0; 1124287990Ssbruno 1125287990Ssbruno DEBUGFUNC("e1000_platform_pm_pch_lpt"); 1126287990Ssbruno 1127287990Ssbruno if (link) { 1128287990Ssbruno u16 speed, duplex, scale = 0; 1129287990Ssbruno u16 max_snoop, max_nosnoop; 1130287990Ssbruno u16 max_ltr_enc; /* max LTR latency encoded */ 1131287990Ssbruno s64 lat_ns; 1132287990Ssbruno s64 value; 1133287990Ssbruno u32 rxa; 1134287990Ssbruno 1135287990Ssbruno if (!hw->mac.max_frame_size) { 1136287990Ssbruno DEBUGOUT("max_frame_size not set.\n"); 1137287990Ssbruno return -E1000_ERR_CONFIG; 1138287990Ssbruno } 1139287990Ssbruno 1140287990Ssbruno hw->mac.ops.get_link_up_info(hw, &speed, &duplex); 1141287990Ssbruno if (!speed) { 1142287990Ssbruno DEBUGOUT("Speed not set.\n"); 1143287990Ssbruno return -E1000_ERR_CONFIG; 1144287990Ssbruno } 1145287990Ssbruno 1146287990Ssbruno /* Rx Packet Buffer Allocation size (KB) */ 1147287990Ssbruno rxa = E1000_READ_REG(hw, E1000_PBA) & E1000_PBA_RXA_MASK; 1148287990Ssbruno 1149287990Ssbruno /* Determine the maximum latency tolerated by the device. 1150287990Ssbruno * 1151287990Ssbruno * Per the PCIe spec, the tolerated latencies are encoded as 1152287990Ssbruno * a 3-bit encoded scale (only 0-5 are valid) multiplied by 1153287990Ssbruno * a 10-bit value (0-1023) to provide a range from 1 ns to 1154287990Ssbruno * 2^25*(2^10-1) ns. The scale is encoded as 0=2^0ns, 1155287990Ssbruno * 1=2^5ns, 2=2^10ns,...5=2^25ns. 1156287990Ssbruno */ 1157287990Ssbruno lat_ns = ((s64)rxa * 1024 - 1158287990Ssbruno (2 * (s64)hw->mac.max_frame_size)) * 8 * 1000; 1159287990Ssbruno if (lat_ns < 0) 1160287990Ssbruno lat_ns = 0; 1161287990Ssbruno else 1162287990Ssbruno lat_ns /= speed; 1163287990Ssbruno value = lat_ns; 1164287990Ssbruno 1165287990Ssbruno while (value > E1000_LTRV_VALUE_MASK) { 1166287990Ssbruno scale++; 1167287990Ssbruno value = E1000_DIVIDE_ROUND_UP(value, (1 << 5)); 1168287990Ssbruno } 1169287990Ssbruno if (scale > E1000_LTRV_SCALE_MAX) { 1170287990Ssbruno DEBUGOUT1("Invalid LTR latency scale %d\n", scale); 1171287990Ssbruno return -E1000_ERR_CONFIG; 1172287990Ssbruno } 1173287990Ssbruno lat_enc = (u16)((scale << E1000_LTRV_SCALE_SHIFT) | value); 1174287990Ssbruno 1175287990Ssbruno /* Determine the maximum latency tolerated by the platform */ 1176287990Ssbruno e1000_read_pci_cfg(hw, E1000_PCI_LTR_CAP_LPT, &max_snoop); 1177287990Ssbruno e1000_read_pci_cfg(hw, E1000_PCI_LTR_CAP_LPT + 2, &max_nosnoop); 1178287990Ssbruno max_ltr_enc = E1000_MAX(max_snoop, max_nosnoop); 1179287990Ssbruno 1180287990Ssbruno if (lat_enc > max_ltr_enc) { 1181287990Ssbruno lat_enc = max_ltr_enc; 1182287990Ssbruno lat_ns = e1000_ltr2ns(max_ltr_enc); 1183287990Ssbruno } 1184287990Ssbruno 1185287990Ssbruno if (lat_ns) { 1186287990Ssbruno lat_ns *= speed * 1000; 1187287990Ssbruno lat_ns /= 8; 1188287990Ssbruno lat_ns /= 1000000000; 1189287990Ssbruno obff_hwm = (s32)(rxa - lat_ns); 1190287990Ssbruno } 1191287990Ssbruno if ((obff_hwm < 0) || (obff_hwm > E1000_SVT_OFF_HWM_MASK)) { 1192287990Ssbruno DEBUGOUT1("Invalid high water mark %d\n", obff_hwm); 1193287990Ssbruno return -E1000_ERR_CONFIG; 1194287990Ssbruno } 1195287990Ssbruno } 1196287990Ssbruno 1197287990Ssbruno /* Set Snoop and No-Snoop latencies the same */ 1198287990Ssbruno reg |= lat_enc | (lat_enc << E1000_LTRV_NOSNOOP_SHIFT); 1199287990Ssbruno E1000_WRITE_REG(hw, E1000_LTRV, reg); 1200287990Ssbruno 1201287990Ssbruno /* Set OBFF high water mark */ 1202287990Ssbruno reg = E1000_READ_REG(hw, E1000_SVT) & ~E1000_SVT_OFF_HWM_MASK; 1203287990Ssbruno reg |= obff_hwm; 1204287990Ssbruno E1000_WRITE_REG(hw, E1000_SVT, reg); 1205287990Ssbruno 1206287990Ssbruno /* Enable OBFF */ 1207287990Ssbruno reg = E1000_READ_REG(hw, E1000_SVCR); 1208287990Ssbruno reg |= E1000_SVCR_OFF_EN; 1209287990Ssbruno /* Always unblock interrupts to the CPU even when the system is 1210287990Ssbruno * in OBFF mode. This ensures that small round-robin traffic 1211287990Ssbruno * (like ping) does not get dropped or experience long latency. 1212287990Ssbruno */ 1213287990Ssbruno reg |= E1000_SVCR_OFF_MASKINT; 1214287990Ssbruno E1000_WRITE_REG(hw, E1000_SVCR, reg); 1215287990Ssbruno 1216287990Ssbruno return E1000_SUCCESS; 1217287990Ssbruno} 1218287990Ssbruno 1219287990Ssbruno/** 1220287990Ssbruno * e1000_set_obff_timer_pch_lpt - Update Optimized Buffer Flush/Fill timer 1221287990Ssbruno * @hw: pointer to the HW structure 1222287990Ssbruno * @itr: interrupt throttling rate 1223287990Ssbruno * 1224287990Ssbruno * Configure OBFF with the updated interrupt rate. 1225287990Ssbruno **/ 1226287990Ssbrunostatic s32 e1000_set_obff_timer_pch_lpt(struct e1000_hw *hw, u32 itr) 1227287990Ssbruno{ 1228287990Ssbruno u32 svcr; 1229287990Ssbruno s32 timer; 1230287990Ssbruno 1231287990Ssbruno DEBUGFUNC("e1000_set_obff_timer_pch_lpt"); 1232287990Ssbruno 1233287990Ssbruno /* Convert ITR value into microseconds for OBFF timer */ 1234287990Ssbruno timer = itr & E1000_ITR_MASK; 1235287990Ssbruno timer = (timer * E1000_ITR_MULT) / 1000; 1236287990Ssbruno 1237287990Ssbruno if ((timer < 0) || (timer > E1000_ITR_MASK)) { 1238287990Ssbruno DEBUGOUT1("Invalid OBFF timer %d\n", timer); 1239287990Ssbruno return -E1000_ERR_CONFIG; 1240287990Ssbruno } 1241287990Ssbruno 1242287990Ssbruno svcr = E1000_READ_REG(hw, E1000_SVCR); 1243287990Ssbruno svcr &= ~E1000_SVCR_OFF_TIMER_MASK; 1244287990Ssbruno svcr |= timer << E1000_SVCR_OFF_TIMER_SHIFT; 1245287990Ssbruno E1000_WRITE_REG(hw, E1000_SVCR, svcr); 1246287990Ssbruno 1247287990Ssbruno return E1000_SUCCESS; 1248287990Ssbruno} 1249287990Ssbruno 1250287990Ssbruno/** 1251267935Sjfv * e1000_enable_ulp_lpt_lp - configure Ultra Low Power mode for LynxPoint-LP 1252267935Sjfv * @hw: pointer to the HW structure 1253267935Sjfv * @to_sx: boolean indicating a system power state transition to Sx 1254267935Sjfv * 1255267935Sjfv * When link is down, configure ULP mode to significantly reduce the power 1256267935Sjfv * to the PHY. If on a Manageability Engine (ME) enabled system, tell the 1257267935Sjfv * ME firmware to start the ULP configuration. If not on an ME enabled 1258267935Sjfv * system, configure the ULP mode by software. 1259267935Sjfv */ 1260267935Sjfvs32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx) 1261267935Sjfv{ 1262267935Sjfv u32 mac_reg; 1263267935Sjfv s32 ret_val = E1000_SUCCESS; 1264267935Sjfv u16 phy_reg; 1265295323Serj u16 oem_reg = 0; 1266267935Sjfv 1267267935Sjfv if ((hw->mac.type < e1000_pch_lpt) || 1268267935Sjfv (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_LM) || 1269267935Sjfv (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_V) || 1270267935Sjfv (hw->device_id == E1000_DEV_ID_PCH_I218_LM2) || 1271267935Sjfv (hw->device_id == E1000_DEV_ID_PCH_I218_V2) || 1272267935Sjfv (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_on)) 1273267935Sjfv return 0; 1274267935Sjfv 1275267935Sjfv if (E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID) { 1276267935Sjfv /* Request ME configure ULP mode in the PHY */ 1277267935Sjfv mac_reg = E1000_READ_REG(hw, E1000_H2ME); 1278267935Sjfv mac_reg |= E1000_H2ME_ULP | E1000_H2ME_ENFORCE_SETTINGS; 1279267935Sjfv E1000_WRITE_REG(hw, E1000_H2ME, mac_reg); 1280267935Sjfv 1281267935Sjfv goto out; 1282267935Sjfv } 1283267935Sjfv 1284267935Sjfv if (!to_sx) { 1285267935Sjfv int i = 0; 1286267935Sjfv 1287267935Sjfv /* Poll up to 5 seconds for Cable Disconnected indication */ 1288267935Sjfv while (!(E1000_READ_REG(hw, E1000_FEXT) & 1289267935Sjfv E1000_FEXT_PHY_CABLE_DISCONNECTED)) { 1290267935Sjfv /* Bail if link is re-acquired */ 1291267935Sjfv if (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU) 1292267935Sjfv return -E1000_ERR_PHY; 1293267935Sjfv 1294267935Sjfv if (i++ == 100) 1295267935Sjfv break; 1296267935Sjfv 1297267935Sjfv msec_delay(50); 1298267935Sjfv } 1299267935Sjfv DEBUGOUT2("CABLE_DISCONNECTED %s set after %dmsec\n", 1300267935Sjfv (E1000_READ_REG(hw, E1000_FEXT) & 1301267935Sjfv E1000_FEXT_PHY_CABLE_DISCONNECTED) ? "" : "not", 1302267935Sjfv i * 50); 1303267935Sjfv } 1304267935Sjfv 1305267935Sjfv ret_val = hw->phy.ops.acquire(hw); 1306267935Sjfv if (ret_val) 1307267935Sjfv goto out; 1308267935Sjfv 1309267935Sjfv /* Force SMBus mode in PHY */ 1310267935Sjfv ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg); 1311267935Sjfv if (ret_val) 1312267935Sjfv goto release; 1313267935Sjfv phy_reg |= CV_SMB_CTRL_FORCE_SMBUS; 1314267935Sjfv e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg); 1315267935Sjfv 1316267935Sjfv /* Force SMBus mode in MAC */ 1317267935Sjfv mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 1318267935Sjfv mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS; 1319267935Sjfv E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg); 1320267935Sjfv 1321295323Serj /* Si workaround for ULP entry flow on i127/rev6 h/w. Enable 1322295323Serj * LPLU and disable Gig speed when entering ULP 1323295323Serj */ 1324295323Serj if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6)) { 1325295323Serj ret_val = e1000_read_phy_reg_hv_locked(hw, HV_OEM_BITS, 1326295323Serj &oem_reg); 1327295323Serj if (ret_val) 1328295323Serj goto release; 1329295323Serj 1330295323Serj phy_reg = oem_reg; 1331295323Serj phy_reg |= HV_OEM_BITS_LPLU | HV_OEM_BITS_GBE_DIS; 1332295323Serj 1333295323Serj ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS, 1334295323Serj phy_reg); 1335295323Serj 1336295323Serj if (ret_val) 1337295323Serj goto release; 1338295323Serj } 1339295323Serj 1340267935Sjfv /* Set Inband ULP Exit, Reset to SMBus mode and 1341267935Sjfv * Disable SMBus Release on PERST# in PHY 1342267935Sjfv */ 1343267935Sjfv ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg); 1344267935Sjfv if (ret_val) 1345267935Sjfv goto release; 1346267935Sjfv phy_reg |= (I218_ULP_CONFIG1_RESET_TO_SMBUS | 1347267935Sjfv I218_ULP_CONFIG1_DISABLE_SMB_PERST); 1348267935Sjfv if (to_sx) { 1349267935Sjfv if (E1000_READ_REG(hw, E1000_WUFC) & E1000_WUFC_LNKC) 1350267935Sjfv phy_reg |= I218_ULP_CONFIG1_WOL_HOST; 1351295323Serj else 1352295323Serj phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST; 1353267935Sjfv 1354267935Sjfv phy_reg |= I218_ULP_CONFIG1_STICKY_ULP; 1355295323Serj phy_reg &= ~I218_ULP_CONFIG1_INBAND_EXIT; 1356267935Sjfv } else { 1357267935Sjfv phy_reg |= I218_ULP_CONFIG1_INBAND_EXIT; 1358295323Serj phy_reg &= ~I218_ULP_CONFIG1_STICKY_ULP; 1359295323Serj phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST; 1360267935Sjfv } 1361267935Sjfv e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg); 1362267935Sjfv 1363267935Sjfv /* Set Disable SMBus Release on PERST# in MAC */ 1364267935Sjfv mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM7); 1365267935Sjfv mac_reg |= E1000_FEXTNVM7_DISABLE_SMB_PERST; 1366267935Sjfv E1000_WRITE_REG(hw, E1000_FEXTNVM7, mac_reg); 1367267935Sjfv 1368267935Sjfv /* Commit ULP changes in PHY by starting auto ULP configuration */ 1369267935Sjfv phy_reg |= I218_ULP_CONFIG1_START; 1370267935Sjfv e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg); 1371295323Serj 1372295323Serj if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6) && 1373295323Serj to_sx && (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) { 1374295323Serj ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS, 1375295323Serj oem_reg); 1376295323Serj if (ret_val) 1377295323Serj goto release; 1378295323Serj } 1379295323Serj 1380267935Sjfvrelease: 1381267935Sjfv hw->phy.ops.release(hw); 1382267935Sjfvout: 1383267935Sjfv if (ret_val) 1384267935Sjfv DEBUGOUT1("Error in ULP enable flow: %d\n", ret_val); 1385267935Sjfv else 1386267935Sjfv hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_on; 1387267935Sjfv 1388267935Sjfv return ret_val; 1389267935Sjfv} 1390267935Sjfv 1391267935Sjfv/** 1392267935Sjfv * e1000_disable_ulp_lpt_lp - unconfigure Ultra Low Power mode for LynxPoint-LP 1393267935Sjfv * @hw: pointer to the HW structure 1394267935Sjfv * @force: boolean indicating whether or not to force disabling ULP 1395267935Sjfv * 1396267935Sjfv * Un-configure ULP mode when link is up, the system is transitioned from 1397267935Sjfv * Sx or the driver is unloaded. If on a Manageability Engine (ME) enabled 1398267935Sjfv * system, poll for an indication from ME that ULP has been un-configured. 1399267935Sjfv * If not on an ME enabled system, un-configure the ULP mode by software. 1400267935Sjfv * 1401267935Sjfv * During nominal operation, this function is called when link is acquired 1402267935Sjfv * to disable ULP mode (force=FALSE); otherwise, for example when unloading 1403267935Sjfv * the driver or during Sx->S0 transitions, this is called with force=TRUE 1404267935Sjfv * to forcibly disable ULP. 1405267935Sjfv */ 1406267935Sjfvs32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force) 1407267935Sjfv{ 1408267935Sjfv s32 ret_val = E1000_SUCCESS; 1409267935Sjfv u32 mac_reg; 1410267935Sjfv u16 phy_reg; 1411267935Sjfv int i = 0; 1412267935Sjfv 1413267935Sjfv if ((hw->mac.type < e1000_pch_lpt) || 1414267935Sjfv (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_LM) || 1415267935Sjfv (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_V) || 1416267935Sjfv (hw->device_id == E1000_DEV_ID_PCH_I218_LM2) || 1417267935Sjfv (hw->device_id == E1000_DEV_ID_PCH_I218_V2) || 1418267935Sjfv (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_off)) 1419267935Sjfv return 0; 1420267935Sjfv 1421267935Sjfv if (E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID) { 1422267935Sjfv if (force) { 1423267935Sjfv /* Request ME un-configure ULP mode in the PHY */ 1424267935Sjfv mac_reg = E1000_READ_REG(hw, E1000_H2ME); 1425267935Sjfv mac_reg &= ~E1000_H2ME_ULP; 1426267935Sjfv mac_reg |= E1000_H2ME_ENFORCE_SETTINGS; 1427267935Sjfv E1000_WRITE_REG(hw, E1000_H2ME, mac_reg); 1428267935Sjfv } 1429267935Sjfv 1430295323Serj /* Poll up to 300msec for ME to clear ULP_CFG_DONE. */ 1431267935Sjfv while (E1000_READ_REG(hw, E1000_FWSM) & 1432267935Sjfv E1000_FWSM_ULP_CFG_DONE) { 1433295323Serj if (i++ == 30) { 1434267935Sjfv ret_val = -E1000_ERR_PHY; 1435267935Sjfv goto out; 1436267935Sjfv } 1437267935Sjfv 1438267935Sjfv msec_delay(10); 1439267935Sjfv } 1440267935Sjfv DEBUGOUT1("ULP_CONFIG_DONE cleared after %dmsec\n", i * 10); 1441267935Sjfv 1442267935Sjfv if (force) { 1443267935Sjfv mac_reg = E1000_READ_REG(hw, E1000_H2ME); 1444267935Sjfv mac_reg &= ~E1000_H2ME_ENFORCE_SETTINGS; 1445267935Sjfv E1000_WRITE_REG(hw, E1000_H2ME, mac_reg); 1446267935Sjfv } else { 1447267935Sjfv /* Clear H2ME.ULP after ME ULP configuration */ 1448267935Sjfv mac_reg = E1000_READ_REG(hw, E1000_H2ME); 1449267935Sjfv mac_reg &= ~E1000_H2ME_ULP; 1450267935Sjfv E1000_WRITE_REG(hw, E1000_H2ME, mac_reg); 1451267935Sjfv } 1452267935Sjfv 1453267935Sjfv goto out; 1454267935Sjfv } 1455267935Sjfv 1456267935Sjfv ret_val = hw->phy.ops.acquire(hw); 1457267935Sjfv if (ret_val) 1458267935Sjfv goto out; 1459267935Sjfv 1460267935Sjfv if (force) 1461267935Sjfv /* Toggle LANPHYPC Value bit */ 1462267935Sjfv e1000_toggle_lanphypc_pch_lpt(hw); 1463267935Sjfv 1464267935Sjfv /* Unforce SMBus mode in PHY */ 1465267935Sjfv ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg); 1466267935Sjfv if (ret_val) { 1467267935Sjfv /* The MAC might be in PCIe mode, so temporarily force to 1468267935Sjfv * SMBus mode in order to access the PHY. 1469267935Sjfv */ 1470267935Sjfv mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 1471267935Sjfv mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS; 1472267935Sjfv E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg); 1473267935Sjfv 1474267935Sjfv msec_delay(50); 1475267935Sjfv 1476267935Sjfv ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, 1477267935Sjfv &phy_reg); 1478267935Sjfv if (ret_val) 1479267935Sjfv goto release; 1480267935Sjfv } 1481267935Sjfv phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS; 1482267935Sjfv e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg); 1483267935Sjfv 1484267935Sjfv /* Unforce SMBus mode in MAC */ 1485267935Sjfv mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 1486267935Sjfv mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS; 1487267935Sjfv E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg); 1488267935Sjfv 1489267935Sjfv /* When ULP mode was previously entered, K1 was disabled by the 1490267935Sjfv * hardware. Re-Enable K1 in the PHY when exiting ULP. 1491267935Sjfv */ 1492267935Sjfv ret_val = e1000_read_phy_reg_hv_locked(hw, HV_PM_CTRL, &phy_reg); 1493267935Sjfv if (ret_val) 1494267935Sjfv goto release; 1495267935Sjfv phy_reg |= HV_PM_CTRL_K1_ENABLE; 1496267935Sjfv e1000_write_phy_reg_hv_locked(hw, HV_PM_CTRL, phy_reg); 1497267935Sjfv 1498267935Sjfv /* Clear ULP enabled configuration */ 1499267935Sjfv ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg); 1500267935Sjfv if (ret_val) 1501267935Sjfv goto release; 1502360688Sdim phy_reg &= ~(I218_ULP_CONFIG1_IND | 1503360688Sdim I218_ULP_CONFIG1_STICKY_ULP | 1504360688Sdim I218_ULP_CONFIG1_RESET_TO_SMBUS | 1505360688Sdim I218_ULP_CONFIG1_WOL_HOST | 1506360688Sdim I218_ULP_CONFIG1_INBAND_EXIT | 1507360688Sdim I218_ULP_CONFIG1_EN_ULP_LANPHYPC | 1508360688Sdim I218_ULP_CONFIG1_DIS_CLR_STICKY_ON_PERST | 1509360688Sdim I218_ULP_CONFIG1_DISABLE_SMB_PERST); 1510360688Sdim e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg); 1511267935Sjfv 1512360688Sdim /* Commit ULP changes by starting auto ULP configuration */ 1513360688Sdim phy_reg |= I218_ULP_CONFIG1_START; 1514360688Sdim e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg); 1515267935Sjfv 1516360688Sdim /* Clear Disable SMBus Release on PERST# in MAC */ 1517360688Sdim mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM7); 1518360688Sdim mac_reg &= ~E1000_FEXTNVM7_DISABLE_SMB_PERST; 1519360688Sdim E1000_WRITE_REG(hw, E1000_FEXTNVM7, mac_reg); 1520267935Sjfv 1521267935Sjfvrelease: 1522267935Sjfv hw->phy.ops.release(hw); 1523267935Sjfv if (force) { 1524267935Sjfv hw->phy.ops.reset(hw); 1525267935Sjfv msec_delay(50); 1526267935Sjfv } 1527267935Sjfvout: 1528267935Sjfv if (ret_val) 1529267935Sjfv DEBUGOUT1("Error in ULP disable flow: %d\n", ret_val); 1530267935Sjfv else 1531267935Sjfv hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_off; 1532267935Sjfv 1533267935Sjfv return ret_val; 1534267935Sjfv} 1535267935Sjfv 1536267935Sjfv/** 1537200243Sjfv * e1000_check_for_copper_link_ich8lan - Check for link (Copper) 1538200243Sjfv * @hw: pointer to the HW structure 1539200243Sjfv * 1540200243Sjfv * Checks to see of the link status of the hardware has changed. If a 1541200243Sjfv * change in link status has been detected, then we read the PHY registers 1542200243Sjfv * to get the current speed/duplex if link exists. 1543200243Sjfv **/ 1544200243Sjfvstatic s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw) 1545200243Sjfv{ 1546200243Sjfv struct e1000_mac_info *mac = &hw->mac; 1547295323Serj s32 ret_val, tipg_reg = 0; 1548295323Serj u16 emi_addr, emi_val = 0; 1549200243Sjfv bool link; 1550228386Sjfv u16 phy_reg; 1551200243Sjfv 1552200243Sjfv DEBUGFUNC("e1000_check_for_copper_link_ich8lan"); 1553200243Sjfv 1554247064Sjfv /* We only want to go out to the PHY registers to see if Auto-Neg 1555200243Sjfv * has completed and/or if our link status has changed. The 1556200243Sjfv * get_link_status flag is set upon receiving a Link Status 1557200243Sjfv * Change or Rx Sequence Error interrupt. 1558200243Sjfv */ 1559247064Sjfv if (!mac->get_link_status) 1560247064Sjfv return E1000_SUCCESS; 1561200243Sjfv 1562360688Sdim /* First we want to see if the MII Status Register reports 1563360688Sdim * link. If so, then we want to get the current speed/duplex 1564360688Sdim * of the PHY. 1565360688Sdim */ 1566360688Sdim ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 1567360688Sdim if (ret_val) 1568360688Sdim return ret_val; 1569200243Sjfv 1570200243Sjfv if (hw->mac.type == e1000_pchlan) { 1571200243Sjfv ret_val = e1000_k1_gig_workaround_hv(hw, link); 1572200243Sjfv if (ret_val) 1573247064Sjfv return ret_val; 1574200243Sjfv } 1575200243Sjfv 1576267935Sjfv /* When connected at 10Mbps half-duplex, some parts are excessively 1577247064Sjfv * aggressive resulting in many collisions. To avoid this, increase 1578247064Sjfv * the IPG and reduce Rx latency in the PHY. 1579247064Sjfv */ 1580322955Smarius if ((hw->mac.type >= e1000_pch2lan) && link) { 1581295323Serj u16 speed, duplex; 1582267935Sjfv 1583295323Serj e1000_get_speed_and_duplex_copper_generic(hw, &speed, &duplex); 1584295323Serj tipg_reg = E1000_READ_REG(hw, E1000_TIPG); 1585295323Serj tipg_reg &= ~E1000_TIPG_IPGT_MASK; 1586247064Sjfv 1587295323Serj if (duplex == HALF_DUPLEX && speed == SPEED_10) { 1588295323Serj tipg_reg |= 0xFF; 1589247064Sjfv /* Reduce Rx latency in analog PHY */ 1590295323Serj emi_val = 0; 1591322955Smarius } else if (hw->mac.type >= e1000_pch_spt && 1592295323Serj duplex == FULL_DUPLEX && speed != SPEED_1000) { 1593295323Serj tipg_reg |= 0xC; 1594295323Serj emi_val = 1; 1595295323Serj } else { 1596295323Serj /* Roll back the default values */ 1597295323Serj tipg_reg |= 0x08; 1598295323Serj emi_val = 1; 1599295323Serj } 1600247064Sjfv 1601295323Serj E1000_WRITE_REG(hw, E1000_TIPG, tipg_reg); 1602295323Serj 1603295323Serj ret_val = hw->phy.ops.acquire(hw); 1604295323Serj if (ret_val) 1605295323Serj return ret_val; 1606295323Serj 1607295323Serj if (hw->mac.type == e1000_pch2lan) 1608295323Serj emi_addr = I82579_RX_CONFIG; 1609295323Serj else 1610295323Serj emi_addr = I217_RX_CONFIG; 1611295323Serj ret_val = e1000_write_emi_reg_locked(hw, emi_addr, emi_val); 1612295323Serj 1613322955Smarius 1614322955Smarius if (hw->mac.type >= e1000_pch_lpt) { 1615295323Serj u16 phy_reg; 1616295323Serj 1617295323Serj hw->phy.ops.read_reg_locked(hw, I217_PLL_CLOCK_GATE_REG, 1618295323Serj &phy_reg); 1619295323Serj phy_reg &= ~I217_PLL_CLOCK_GATE_MASK; 1620295323Serj if (speed == SPEED_100 || speed == SPEED_10) 1621295323Serj phy_reg |= 0x3E8; 1622287990Ssbruno else 1623295323Serj phy_reg |= 0xFA; 1624295323Serj hw->phy.ops.write_reg_locked(hw, 1625295323Serj I217_PLL_CLOCK_GATE_REG, 1626295323Serj phy_reg); 1627304337Ssbruno 1628304337Ssbruno if (speed == SPEED_1000) { 1629304337Ssbruno hw->phy.ops.read_reg_locked(hw, HV_PM_CTRL, 1630304337Ssbruno &phy_reg); 1631304337Ssbruno 1632304337Ssbruno phy_reg |= HV_PM_CTRL_K1_CLK_REQ; 1633304337Ssbruno 1634304337Ssbruno hw->phy.ops.write_reg_locked(hw, HV_PM_CTRL, 1635304337Ssbruno phy_reg); 1636304337Ssbruno } 1637304337Ssbruno } 1638295323Serj hw->phy.ops.release(hw); 1639247064Sjfv 1640295323Serj if (ret_val) 1641295323Serj return ret_val; 1642247064Sjfv 1643322955Smarius if (hw->mac.type >= e1000_pch_spt) { 1644295323Serj u16 data; 1645295323Serj u16 ptr_gap; 1646295323Serj 1647295323Serj if (speed == SPEED_1000) { 1648295323Serj ret_val = hw->phy.ops.acquire(hw); 1649295323Serj if (ret_val) 1650295323Serj return ret_val; 1651295323Serj 1652295323Serj ret_val = hw->phy.ops.read_reg_locked(hw, 1653295323Serj PHY_REG(776, 20), 1654295323Serj &data); 1655295323Serj if (ret_val) { 1656295323Serj hw->phy.ops.release(hw); 1657295323Serj return ret_val; 1658295323Serj } 1659295323Serj 1660295323Serj ptr_gap = (data & (0x3FF << 2)) >> 2; 1661295323Serj if (ptr_gap < 0x18) { 1662295323Serj data &= ~(0x3FF << 2); 1663295323Serj data |= (0x18 << 2); 1664295323Serj ret_val = 1665295323Serj hw->phy.ops.write_reg_locked(hw, 1666295323Serj PHY_REG(776, 20), data); 1667295323Serj } 1668295323Serj hw->phy.ops.release(hw); 1669295323Serj if (ret_val) 1670295323Serj return ret_val; 1671295323Serj } else { 1672295323Serj ret_val = hw->phy.ops.acquire(hw); 1673295323Serj if (ret_val) 1674295323Serj return ret_val; 1675295323Serj 1676295323Serj ret_val = hw->phy.ops.write_reg_locked(hw, 1677295323Serj PHY_REG(776, 20), 1678295323Serj 0xC023); 1679295323Serj hw->phy.ops.release(hw); 1680295323Serj if (ret_val) 1681295323Serj return ret_val; 1682295323Serj 1683295323Serj } 1684247064Sjfv } 1685247064Sjfv } 1686247064Sjfv 1687295323Serj /* I217 Packet Loss issue: 1688295323Serj * ensure that FEXTNVM4 Beacon Duration is set correctly 1689295323Serj * on power up. 1690295323Serj * Set the Beacon Duration for I217 to 8 usec 1691295323Serj */ 1692322955Smarius if (hw->mac.type >= e1000_pch_lpt) { 1693295323Serj u32 mac_reg; 1694295323Serj 1695295323Serj mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM4); 1696295323Serj mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK; 1697295323Serj mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC; 1698295323Serj E1000_WRITE_REG(hw, E1000_FEXTNVM4, mac_reg); 1699295323Serj } 1700295323Serj 1701247064Sjfv /* Work-around I218 hang issue */ 1702247064Sjfv if ((hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) || 1703267935Sjfv (hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) || 1704267935Sjfv (hw->device_id == E1000_DEV_ID_PCH_I218_LM3) || 1705267935Sjfv (hw->device_id == E1000_DEV_ID_PCH_I218_V3)) { 1706247064Sjfv ret_val = e1000_k1_workaround_lpt_lp(hw, link); 1707247064Sjfv if (ret_val) 1708247064Sjfv return ret_val; 1709247064Sjfv } 1710322955Smarius if (hw->mac.type >= e1000_pch_lpt) { 1711287990Ssbruno /* Set platform power management values for 1712287990Ssbruno * Latency Tolerance Reporting (LTR) 1713287990Ssbruno * Optimized Buffer Flush/Fill (OBFF) 1714287990Ssbruno */ 1715287990Ssbruno ret_val = e1000_platform_pm_pch_lpt(hw, link); 1716287990Ssbruno if (ret_val) 1717287990Ssbruno return ret_val; 1718287990Ssbruno } 1719287990Ssbruno 1720247064Sjfv /* Clear link partner's EEE ability */ 1721247064Sjfv hw->dev_spec.ich8lan.eee_lp_ability = 0; 1722247064Sjfv 1723322955Smarius if (hw->mac.type >= e1000_pch_lpt) { 1724295323Serj u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6); 1725295323Serj 1726322955Smarius if (hw->mac.type == e1000_pch_spt) { 1727322955Smarius /* FEXTNVM6 K1-off workaround - for SPT only */ 1728322955Smarius u32 pcieanacfg = E1000_READ_REG(hw, E1000_PCIEANACFG); 1729322955Smarius 1730322955Smarius if (pcieanacfg & E1000_FEXTNVM6_K1_OFF_ENABLE) 1731322955Smarius fextnvm6 |= E1000_FEXTNVM6_K1_OFF_ENABLE; 1732322955Smarius else 1733322955Smarius fextnvm6 &= ~E1000_FEXTNVM6_K1_OFF_ENABLE; 1734322955Smarius } 1735322955Smarius 1736322955Smarius if (hw->dev_spec.ich8lan.disable_k1_off == TRUE) 1737295323Serj fextnvm6 &= ~E1000_FEXTNVM6_K1_OFF_ENABLE; 1738295323Serj 1739295323Serj E1000_WRITE_REG(hw, E1000_FEXTNVM6, fextnvm6); 1740295323Serj } 1741295323Serj 1742200243Sjfv if (!link) 1743247064Sjfv return E1000_SUCCESS; /* No link detected */ 1744200243Sjfv 1745200243Sjfv mac->get_link_status = FALSE; 1746200243Sjfv 1747228386Sjfv switch (hw->mac.type) { 1748228386Sjfv case e1000_pch2lan: 1749228386Sjfv ret_val = e1000_k1_workaround_lv(hw); 1750200243Sjfv if (ret_val) 1751247064Sjfv return ret_val; 1752228386Sjfv /* fall-thru */ 1753228386Sjfv case e1000_pchlan: 1754228386Sjfv if (hw->phy.type == e1000_phy_82578) { 1755228386Sjfv ret_val = e1000_link_stall_workaround_hv(hw); 1756228386Sjfv if (ret_val) 1757247064Sjfv return ret_val; 1758228386Sjfv } 1759200243Sjfv 1760247064Sjfv /* Workaround for PCHx parts in half-duplex: 1761228386Sjfv * Set the number of preambles removed from the packet 1762228386Sjfv * when it is passed from the PHY to the MAC to prevent 1763228386Sjfv * the MAC from misinterpreting the packet type. 1764228386Sjfv */ 1765228386Sjfv hw->phy.ops.read_reg(hw, HV_KMRN_FIFO_CTRLSTA, &phy_reg); 1766228386Sjfv phy_reg &= ~HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK; 1767228386Sjfv 1768228386Sjfv if ((E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_FD) != 1769228386Sjfv E1000_STATUS_FD) 1770228386Sjfv phy_reg |= (1 << HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT); 1771228386Sjfv 1772228386Sjfv hw->phy.ops.write_reg(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg); 1773228386Sjfv break; 1774228386Sjfv default: 1775228386Sjfv break; 1776213234Sjfv } 1777213234Sjfv 1778247064Sjfv /* Check if there was DownShift, must be checked 1779200243Sjfv * immediately after link-up 1780200243Sjfv */ 1781200243Sjfv e1000_check_downshift_generic(hw); 1782200243Sjfv 1783213234Sjfv /* Enable/Disable EEE after link up */ 1784256200Sjfv if (hw->phy.type > e1000_phy_82579) { 1785256200Sjfv ret_val = e1000_set_eee_pchlan(hw); 1786256200Sjfv if (ret_val) 1787256200Sjfv return ret_val; 1788256200Sjfv } 1789213234Sjfv 1790247064Sjfv /* If we are forcing speed/duplex, then we simply return since 1791200243Sjfv * we have already determined whether we have link or not. 1792200243Sjfv */ 1793247064Sjfv if (!mac->autoneg) 1794247064Sjfv return -E1000_ERR_CONFIG; 1795200243Sjfv 1796247064Sjfv /* Auto-Neg is enabled. Auto Speed Detection takes care 1797200243Sjfv * of MAC speed/duplex configuration. So we only need to 1798200243Sjfv * configure Collision Distance in the MAC. 1799200243Sjfv */ 1800247064Sjfv mac->ops.config_collision_dist(hw); 1801200243Sjfv 1802247064Sjfv /* Configure Flow Control now that Auto-Neg has completed. 1803200243Sjfv * First, we need to restore the desired flow control 1804200243Sjfv * settings because we may have had to re-autoneg with a 1805200243Sjfv * different link partner. 1806200243Sjfv */ 1807200243Sjfv ret_val = e1000_config_fc_after_link_up_generic(hw); 1808200243Sjfv if (ret_val) 1809200243Sjfv DEBUGOUT("Error configuring flow control\n"); 1810200243Sjfv 1811200243Sjfv return ret_val; 1812200243Sjfv} 1813200243Sjfv 1814200243Sjfv/** 1815169240Sjfv * e1000_init_function_pointers_ich8lan - Initialize ICH8 function pointers 1816169589Sjfv * @hw: pointer to the HW structure 1817169240Sjfv * 1818169240Sjfv * Initialize family-specific function pointers for PHY, MAC, and NVM. 1819169240Sjfv **/ 1820173788Sjfvvoid e1000_init_function_pointers_ich8lan(struct e1000_hw *hw) 1821169240Sjfv{ 1822169240Sjfv DEBUGFUNC("e1000_init_function_pointers_ich8lan"); 1823169240Sjfv 1824177867Sjfv hw->mac.ops.init_params = e1000_init_mac_params_ich8lan; 1825177867Sjfv hw->nvm.ops.init_params = e1000_init_nvm_params_ich8lan; 1826194865Sjfv switch (hw->mac.type) { 1827194865Sjfv case e1000_ich8lan: 1828194865Sjfv case e1000_ich9lan: 1829194865Sjfv case e1000_ich10lan: 1830194865Sjfv hw->phy.ops.init_params = e1000_init_phy_params_ich8lan; 1831194865Sjfv break; 1832194865Sjfv case e1000_pchlan: 1833213234Sjfv case e1000_pch2lan: 1834247064Sjfv case e1000_pch_lpt: 1835295323Serj case e1000_pch_spt: 1836333213Smarius case e1000_pch_cnp: 1837194865Sjfv hw->phy.ops.init_params = e1000_init_phy_params_pchlan; 1838194865Sjfv break; 1839194865Sjfv default: 1840194865Sjfv break; 1841194865Sjfv } 1842169240Sjfv} 1843169240Sjfv 1844169240Sjfv/** 1845200243Sjfv * e1000_acquire_nvm_ich8lan - Acquire NVM mutex 1846200243Sjfv * @hw: pointer to the HW structure 1847200243Sjfv * 1848200243Sjfv * Acquires the mutex for performing NVM operations. 1849200243Sjfv **/ 1850200243Sjfvstatic s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw) 1851200243Sjfv{ 1852200243Sjfv DEBUGFUNC("e1000_acquire_nvm_ich8lan"); 1853200243Sjfv 1854200243Sjfv E1000_MUTEX_LOCK(&hw->dev_spec.ich8lan.nvm_mutex); 1855200243Sjfv 1856200243Sjfv return E1000_SUCCESS; 1857200243Sjfv} 1858200243Sjfv 1859200243Sjfv/** 1860200243Sjfv * e1000_release_nvm_ich8lan - Release NVM mutex 1861200243Sjfv * @hw: pointer to the HW structure 1862200243Sjfv * 1863200243Sjfv * Releases the mutex used while performing NVM operations. 1864200243Sjfv **/ 1865200243Sjfvstatic void e1000_release_nvm_ich8lan(struct e1000_hw *hw) 1866200243Sjfv{ 1867200243Sjfv DEBUGFUNC("e1000_release_nvm_ich8lan"); 1868200243Sjfv 1869200243Sjfv E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.nvm_mutex); 1870200243Sjfv 1871200243Sjfv return; 1872200243Sjfv} 1873200243Sjfv 1874200243Sjfv/** 1875169240Sjfv * e1000_acquire_swflag_ich8lan - Acquire software control flag 1876169589Sjfv * @hw: pointer to the HW structure 1877169240Sjfv * 1878200243Sjfv * Acquires the software control flag for performing PHY and select 1879200243Sjfv * MAC CSR accesses. 1880169240Sjfv **/ 1881177867Sjfvstatic s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw) 1882169240Sjfv{ 1883169240Sjfv u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT; 1884169240Sjfv s32 ret_val = E1000_SUCCESS; 1885169240Sjfv 1886169240Sjfv DEBUGFUNC("e1000_acquire_swflag_ich8lan"); 1887169240Sjfv 1888200243Sjfv E1000_MUTEX_LOCK(&hw->dev_spec.ich8lan.swflag_mutex); 1889200243Sjfv 1890169240Sjfv while (timeout) { 1891169240Sjfv extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); 1892200243Sjfv if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)) 1893200243Sjfv break; 1894169240Sjfv 1895200243Sjfv msec_delay_irq(1); 1896200243Sjfv timeout--; 1897200243Sjfv } 1898194865Sjfv 1899200243Sjfv if (!timeout) { 1900228386Sjfv DEBUGOUT("SW has already locked the resource.\n"); 1901200243Sjfv ret_val = -E1000_ERR_CONFIG; 1902200243Sjfv goto out; 1903200243Sjfv } 1904200243Sjfv 1905200243Sjfv timeout = SW_FLAG_TIMEOUT; 1906200243Sjfv 1907200243Sjfv extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG; 1908200243Sjfv E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl); 1909200243Sjfv 1910200243Sjfv while (timeout) { 1911200243Sjfv extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); 1912200243Sjfv if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) 1913200243Sjfv break; 1914200243Sjfv 1915169240Sjfv msec_delay_irq(1); 1916169240Sjfv timeout--; 1917169240Sjfv } 1918169240Sjfv 1919169240Sjfv if (!timeout) { 1920228386Sjfv DEBUGOUT2("Failed to acquire the semaphore, FW or HW has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n", 1921228386Sjfv E1000_READ_REG(hw, E1000_FWSM), extcnf_ctrl); 1922173788Sjfv extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; 1923173788Sjfv E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl); 1924169240Sjfv ret_val = -E1000_ERR_CONFIG; 1925169240Sjfv goto out; 1926169240Sjfv } 1927169240Sjfv 1928169240Sjfvout: 1929200243Sjfv if (ret_val) 1930200243Sjfv E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex); 1931200243Sjfv 1932169240Sjfv return ret_val; 1933169240Sjfv} 1934169240Sjfv 1935169240Sjfv/** 1936169240Sjfv * e1000_release_swflag_ich8lan - Release software control flag 1937169589Sjfv * @hw: pointer to the HW structure 1938169240Sjfv * 1939200243Sjfv * Releases the software control flag for performing PHY and select 1940200243Sjfv * MAC CSR accesses. 1941169240Sjfv **/ 1942177867Sjfvstatic void e1000_release_swflag_ich8lan(struct e1000_hw *hw) 1943169240Sjfv{ 1944169240Sjfv u32 extcnf_ctrl; 1945169240Sjfv 1946169240Sjfv DEBUGFUNC("e1000_release_swflag_ich8lan"); 1947169240Sjfv 1948169240Sjfv extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); 1949169240Sjfv 1950218588Sjfv if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) { 1951218588Sjfv extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; 1952218588Sjfv E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl); 1953218588Sjfv } else { 1954218588Sjfv DEBUGOUT("Semaphore unexpectedly released by sw/fw/hw\n"); 1955218588Sjfv } 1956218588Sjfv 1957200243Sjfv E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex); 1958200243Sjfv 1959169240Sjfv return; 1960169240Sjfv} 1961169240Sjfv 1962169240Sjfv/** 1963169240Sjfv * e1000_check_mng_mode_ich8lan - Checks management mode 1964169589Sjfv * @hw: pointer to the HW structure 1965169240Sjfv * 1966213234Sjfv * This checks if the adapter has any manageability enabled. 1967169240Sjfv * This is a function pointer entry point only called by read/write 1968169240Sjfv * routines for the PHY and NVM parts. 1969169240Sjfv **/ 1970177867Sjfvstatic bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw) 1971169240Sjfv{ 1972169240Sjfv u32 fwsm; 1973169240Sjfv 1974169240Sjfv DEBUGFUNC("e1000_check_mng_mode_ich8lan"); 1975169240Sjfv 1976169240Sjfv fwsm = E1000_READ_REG(hw, E1000_FWSM); 1977169240Sjfv 1978267935Sjfv return (fwsm & E1000_ICH_FWSM_FW_VALID) && 1979267935Sjfv ((fwsm & E1000_FWSM_MODE_MASK) == 1980267935Sjfv (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT)); 1981169240Sjfv} 1982169240Sjfv 1983169240Sjfv/** 1984213234Sjfv * e1000_check_mng_mode_pchlan - Checks management mode 1985213234Sjfv * @hw: pointer to the HW structure 1986213234Sjfv * 1987213234Sjfv * This checks if the adapter has iAMT enabled. 1988213234Sjfv * This is a function pointer entry point only called by read/write 1989213234Sjfv * routines for the PHY and NVM parts. 1990213234Sjfv **/ 1991213234Sjfvstatic bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw) 1992213234Sjfv{ 1993213234Sjfv u32 fwsm; 1994213234Sjfv 1995213234Sjfv DEBUGFUNC("e1000_check_mng_mode_pchlan"); 1996213234Sjfv 1997213234Sjfv fwsm = E1000_READ_REG(hw, E1000_FWSM); 1998213234Sjfv 1999213234Sjfv return (fwsm & E1000_ICH_FWSM_FW_VALID) && 2000213234Sjfv (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT)); 2001213234Sjfv} 2002213234Sjfv 2003213234Sjfv/** 2004213234Sjfv * e1000_rar_set_pch2lan - Set receive address register 2005213234Sjfv * @hw: pointer to the HW structure 2006213234Sjfv * @addr: pointer to the receive address 2007213234Sjfv * @index: receive address array register 2008213234Sjfv * 2009213234Sjfv * Sets the receive address array register at index to the address passed 2010213234Sjfv * in by addr. For 82579, RAR[0] is the base address register that is to 2011213234Sjfv * contain the MAC address but RAR[1-6] are reserved for manageability (ME). 2012213234Sjfv * Use SHRA[0-3] in place of those reserved for ME. 2013213234Sjfv **/ 2014267935Sjfvstatic int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index) 2015213234Sjfv{ 2016213234Sjfv u32 rar_low, rar_high; 2017213234Sjfv 2018213234Sjfv DEBUGFUNC("e1000_rar_set_pch2lan"); 2019213234Sjfv 2020247064Sjfv /* HW expects these in little endian so we reverse the byte order 2021213234Sjfv * from network order (big endian) to little endian 2022213234Sjfv */ 2023213234Sjfv rar_low = ((u32) addr[0] | 2024228386Sjfv ((u32) addr[1] << 8) | 2025228386Sjfv ((u32) addr[2] << 16) | ((u32) addr[3] << 24)); 2026213234Sjfv 2027213234Sjfv rar_high = ((u32) addr[4] | ((u32) addr[5] << 8)); 2028213234Sjfv 2029213234Sjfv /* If MAC address zero, no need to set the AV bit */ 2030213234Sjfv if (rar_low || rar_high) 2031213234Sjfv rar_high |= E1000_RAH_AV; 2032213234Sjfv 2033213234Sjfv if (index == 0) { 2034213234Sjfv E1000_WRITE_REG(hw, E1000_RAL(index), rar_low); 2035213234Sjfv E1000_WRITE_FLUSH(hw); 2036213234Sjfv E1000_WRITE_REG(hw, E1000_RAH(index), rar_high); 2037213234Sjfv E1000_WRITE_FLUSH(hw); 2038267935Sjfv return E1000_SUCCESS; 2039213234Sjfv } 2040213234Sjfv 2041256200Sjfv /* RAR[1-6] are owned by manageability. Skip those and program the 2042256200Sjfv * next address into the SHRA register array. 2043256200Sjfv */ 2044267935Sjfv if (index < (u32) (hw->mac.rar_entry_count)) { 2045247064Sjfv s32 ret_val; 2046247064Sjfv 2047247064Sjfv ret_val = e1000_acquire_swflag_ich8lan(hw); 2048247064Sjfv if (ret_val) 2049247064Sjfv goto out; 2050247064Sjfv 2051213234Sjfv E1000_WRITE_REG(hw, E1000_SHRAL(index - 1), rar_low); 2052213234Sjfv E1000_WRITE_FLUSH(hw); 2053213234Sjfv E1000_WRITE_REG(hw, E1000_SHRAH(index - 1), rar_high); 2054213234Sjfv E1000_WRITE_FLUSH(hw); 2055213234Sjfv 2056247064Sjfv e1000_release_swflag_ich8lan(hw); 2057247064Sjfv 2058213234Sjfv /* verify the register updates */ 2059213234Sjfv if ((E1000_READ_REG(hw, E1000_SHRAL(index - 1)) == rar_low) && 2060213234Sjfv (E1000_READ_REG(hw, E1000_SHRAH(index - 1)) == rar_high)) 2061267935Sjfv return E1000_SUCCESS; 2062213234Sjfv 2063213234Sjfv DEBUGOUT2("SHRA[%d] might be locked by ME - FWSM=0x%8.8x\n", 2064213234Sjfv (index - 1), E1000_READ_REG(hw, E1000_FWSM)); 2065213234Sjfv } 2066213234Sjfv 2067247064Sjfvout: 2068213234Sjfv DEBUGOUT1("Failed to write receive address at index %d\n", index); 2069267935Sjfv return -E1000_ERR_CONFIG; 2070213234Sjfv} 2071213234Sjfv 2072213234Sjfv/** 2073247064Sjfv * e1000_rar_set_pch_lpt - Set receive address registers 2074247064Sjfv * @hw: pointer to the HW structure 2075247064Sjfv * @addr: pointer to the receive address 2076247064Sjfv * @index: receive address array register 2077247064Sjfv * 2078247064Sjfv * Sets the receive address register array at index to the address passed 2079247064Sjfv * in by addr. For LPT, RAR[0] is the base address register that is to 2080247064Sjfv * contain the MAC address. SHRA[0-10] are the shared receive address 2081247064Sjfv * registers that are shared between the Host and manageability engine (ME). 2082247064Sjfv **/ 2083267935Sjfvstatic int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index) 2084247064Sjfv{ 2085247064Sjfv u32 rar_low, rar_high; 2086247064Sjfv u32 wlock_mac; 2087247064Sjfv 2088247064Sjfv DEBUGFUNC("e1000_rar_set_pch_lpt"); 2089247064Sjfv 2090247064Sjfv /* HW expects these in little endian so we reverse the byte order 2091247064Sjfv * from network order (big endian) to little endian 2092247064Sjfv */ 2093247064Sjfv rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) | 2094247064Sjfv ((u32) addr[2] << 16) | ((u32) addr[3] << 24)); 2095247064Sjfv 2096247064Sjfv rar_high = ((u32) addr[4] | ((u32) addr[5] << 8)); 2097247064Sjfv 2098247064Sjfv /* If MAC address zero, no need to set the AV bit */ 2099247064Sjfv if (rar_low || rar_high) 2100247064Sjfv rar_high |= E1000_RAH_AV; 2101247064Sjfv 2102247064Sjfv if (index == 0) { 2103247064Sjfv E1000_WRITE_REG(hw, E1000_RAL(index), rar_low); 2104247064Sjfv E1000_WRITE_FLUSH(hw); 2105247064Sjfv E1000_WRITE_REG(hw, E1000_RAH(index), rar_high); 2106247064Sjfv E1000_WRITE_FLUSH(hw); 2107267935Sjfv return E1000_SUCCESS; 2108247064Sjfv } 2109247064Sjfv 2110247064Sjfv /* The manageability engine (ME) can lock certain SHRAR registers that 2111247064Sjfv * it is using - those registers are unavailable for use. 2112247064Sjfv */ 2113247064Sjfv if (index < hw->mac.rar_entry_count) { 2114247064Sjfv wlock_mac = E1000_READ_REG(hw, E1000_FWSM) & 2115247064Sjfv E1000_FWSM_WLOCK_MAC_MASK; 2116247064Sjfv wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT; 2117247064Sjfv 2118247064Sjfv /* Check if all SHRAR registers are locked */ 2119247064Sjfv if (wlock_mac == 1) 2120247064Sjfv goto out; 2121247064Sjfv 2122247064Sjfv if ((wlock_mac == 0) || (index <= wlock_mac)) { 2123247064Sjfv s32 ret_val; 2124247064Sjfv 2125247064Sjfv ret_val = e1000_acquire_swflag_ich8lan(hw); 2126247064Sjfv 2127247064Sjfv if (ret_val) 2128247064Sjfv goto out; 2129247064Sjfv 2130247064Sjfv E1000_WRITE_REG(hw, E1000_SHRAL_PCH_LPT(index - 1), 2131247064Sjfv rar_low); 2132247064Sjfv E1000_WRITE_FLUSH(hw); 2133247064Sjfv E1000_WRITE_REG(hw, E1000_SHRAH_PCH_LPT(index - 1), 2134247064Sjfv rar_high); 2135247064Sjfv E1000_WRITE_FLUSH(hw); 2136247064Sjfv 2137247064Sjfv e1000_release_swflag_ich8lan(hw); 2138247064Sjfv 2139247064Sjfv /* verify the register updates */ 2140247064Sjfv if ((E1000_READ_REG(hw, E1000_SHRAL_PCH_LPT(index - 1)) == rar_low) && 2141247064Sjfv (E1000_READ_REG(hw, E1000_SHRAH_PCH_LPT(index - 1)) == rar_high)) 2142267935Sjfv return E1000_SUCCESS; 2143247064Sjfv } 2144247064Sjfv } 2145247064Sjfv 2146247064Sjfvout: 2147247064Sjfv DEBUGOUT1("Failed to write receive address at index %d\n", index); 2148267935Sjfv return -E1000_ERR_CONFIG; 2149247064Sjfv} 2150247064Sjfv 2151247064Sjfv/** 2152218588Sjfv * e1000_update_mc_addr_list_pch2lan - Update Multicast addresses 2153218588Sjfv * @hw: pointer to the HW structure 2154218588Sjfv * @mc_addr_list: array of multicast addresses to program 2155218588Sjfv * @mc_addr_count: number of multicast addresses to program 2156218588Sjfv * 2157218588Sjfv * Updates entire Multicast Table Array of the PCH2 MAC and PHY. 2158218588Sjfv * The caller must have a packed mc_addr_list of multicast addresses. 2159218588Sjfv **/ 2160218588Sjfvstatic void e1000_update_mc_addr_list_pch2lan(struct e1000_hw *hw, 2161228386Sjfv u8 *mc_addr_list, 2162228386Sjfv u32 mc_addr_count) 2163218588Sjfv{ 2164228386Sjfv u16 phy_reg = 0; 2165218588Sjfv int i; 2166228386Sjfv s32 ret_val; 2167218588Sjfv 2168218588Sjfv DEBUGFUNC("e1000_update_mc_addr_list_pch2lan"); 2169218588Sjfv 2170218588Sjfv e1000_update_mc_addr_list_generic(hw, mc_addr_list, mc_addr_count); 2171218588Sjfv 2172228386Sjfv ret_val = hw->phy.ops.acquire(hw); 2173228386Sjfv if (ret_val) 2174228386Sjfv return; 2175228386Sjfv 2176228386Sjfv ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg); 2177228386Sjfv if (ret_val) 2178228386Sjfv goto release; 2179228386Sjfv 2180218588Sjfv for (i = 0; i < hw->mac.mta_reg_count; i++) { 2181228386Sjfv hw->phy.ops.write_reg_page(hw, BM_MTA(i), 2182228386Sjfv (u16)(hw->mac.mta_shadow[i] & 2183228386Sjfv 0xFFFF)); 2184228386Sjfv hw->phy.ops.write_reg_page(hw, (BM_MTA(i) + 1), 2185228386Sjfv (u16)((hw->mac.mta_shadow[i] >> 16) & 2186228386Sjfv 0xFFFF)); 2187218588Sjfv } 2188228386Sjfv 2189228386Sjfv e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg); 2190228386Sjfv 2191228386Sjfvrelease: 2192228386Sjfv hw->phy.ops.release(hw); 2193218588Sjfv} 2194218588Sjfv 2195218588Sjfv/** 2196169240Sjfv * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked 2197169589Sjfv * @hw: pointer to the HW structure 2198169240Sjfv * 2199169240Sjfv * Checks if firmware is blocking the reset of the PHY. 2200169240Sjfv * This is a function pointer entry point only called by 2201169240Sjfv * reset routines. 2202169240Sjfv **/ 2203177867Sjfvstatic s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw) 2204169240Sjfv{ 2205169240Sjfv u32 fwsm; 2206256200Sjfv bool blocked = FALSE; 2207256200Sjfv int i = 0; 2208169240Sjfv 2209169240Sjfv DEBUGFUNC("e1000_check_reset_block_ich8lan"); 2210169240Sjfv 2211256200Sjfv do { 2212256200Sjfv fwsm = E1000_READ_REG(hw, E1000_FWSM); 2213256200Sjfv if (!(fwsm & E1000_ICH_FWSM_RSPCIPHY)) { 2214256200Sjfv blocked = TRUE; 2215256200Sjfv msec_delay(10); 2216256200Sjfv continue; 2217256200Sjfv } 2218256200Sjfv blocked = FALSE; 2219295323Serj } while (blocked && (i++ < 30)); 2220256200Sjfv return blocked ? E1000_BLK_PHY_RESET : E1000_SUCCESS; 2221169240Sjfv} 2222169240Sjfv 2223169240Sjfv/** 2224213234Sjfv * e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states 2225213234Sjfv * @hw: pointer to the HW structure 2226213234Sjfv * 2227213234Sjfv * Assumes semaphore already acquired. 2228213234Sjfv * 2229213234Sjfv **/ 2230213234Sjfvstatic s32 e1000_write_smbus_addr(struct e1000_hw *hw) 2231213234Sjfv{ 2232213234Sjfv u16 phy_data; 2233213234Sjfv u32 strap = E1000_READ_REG(hw, E1000_STRAP); 2234247064Sjfv u32 freq = (strap & E1000_STRAP_SMT_FREQ_MASK) >> 2235247064Sjfv E1000_STRAP_SMT_FREQ_SHIFT; 2236247064Sjfv s32 ret_val; 2237213234Sjfv 2238213234Sjfv strap &= E1000_STRAP_SMBUS_ADDRESS_MASK; 2239213234Sjfv 2240213234Sjfv ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data); 2241213234Sjfv if (ret_val) 2242247064Sjfv return ret_val; 2243213234Sjfv 2244213234Sjfv phy_data &= ~HV_SMB_ADDR_MASK; 2245213234Sjfv phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT); 2246213234Sjfv phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID; 2247213234Sjfv 2248247064Sjfv if (hw->phy.type == e1000_phy_i217) { 2249247064Sjfv /* Restore SMBus frequency */ 2250247064Sjfv if (freq--) { 2251247064Sjfv phy_data &= ~HV_SMB_ADDR_FREQ_MASK; 2252247064Sjfv phy_data |= (freq & (1 << 0)) << 2253247064Sjfv HV_SMB_ADDR_FREQ_LOW_SHIFT; 2254247064Sjfv phy_data |= (freq & (1 << 1)) << 2255247064Sjfv (HV_SMB_ADDR_FREQ_HIGH_SHIFT - 1); 2256247064Sjfv } else { 2257247064Sjfv DEBUGOUT("Unsupported SMB frequency in PHY\n"); 2258247064Sjfv } 2259247064Sjfv } 2260247064Sjfv 2261247064Sjfv return e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data); 2262213234Sjfv} 2263213234Sjfv 2264213234Sjfv/** 2265200243Sjfv * e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration 2266200243Sjfv * @hw: pointer to the HW structure 2267200243Sjfv * 2268200243Sjfv * SW should configure the LCD from the NVM extended configuration region 2269200243Sjfv * as a workaround for certain parts. 2270200243Sjfv **/ 2271200243Sjfvstatic s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw) 2272200243Sjfv{ 2273200243Sjfv struct e1000_phy_info *phy = &hw->phy; 2274200243Sjfv u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask; 2275203049Sjfv s32 ret_val = E1000_SUCCESS; 2276200243Sjfv u16 word_addr, reg_data, reg_addr, phy_page = 0; 2277200243Sjfv 2278213234Sjfv DEBUGFUNC("e1000_sw_lcd_config_ich8lan"); 2279203049Sjfv 2280247064Sjfv /* Initialize the PHY from the NVM on ICH platforms. This 2281200243Sjfv * is needed due to an issue where the NVM configuration is 2282200243Sjfv * not properly autoloaded after power transitions. 2283200243Sjfv * Therefore, after each PHY reset, we will load the 2284200243Sjfv * configuration data out of the NVM manually. 2285200243Sjfv */ 2286213234Sjfv switch (hw->mac.type) { 2287213234Sjfv case e1000_ich8lan: 2288213234Sjfv if (phy->type != e1000_phy_igp_3) 2289213234Sjfv return ret_val; 2290213234Sjfv 2291213234Sjfv if ((hw->device_id == E1000_DEV_ID_ICH8_IGP_AMT) || 2292213234Sjfv (hw->device_id == E1000_DEV_ID_ICH8_IGP_C)) { 2293213234Sjfv sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG; 2294213234Sjfv break; 2295213234Sjfv } 2296213234Sjfv /* Fall-thru */ 2297213234Sjfv case e1000_pchlan: 2298213234Sjfv case e1000_pch2lan: 2299247064Sjfv case e1000_pch_lpt: 2300295323Serj case e1000_pch_spt: 2301333213Smarius case e1000_pch_cnp: 2302203049Sjfv sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M; 2303213234Sjfv break; 2304213234Sjfv default: 2305213234Sjfv return ret_val; 2306213234Sjfv } 2307200243Sjfv 2308213234Sjfv ret_val = hw->phy.ops.acquire(hw); 2309213234Sjfv if (ret_val) 2310213234Sjfv return ret_val; 2311213234Sjfv 2312203049Sjfv data = E1000_READ_REG(hw, E1000_FEXTNVM); 2313203049Sjfv if (!(data & sw_cfg_mask)) 2314247064Sjfv goto release; 2315200243Sjfv 2316247064Sjfv /* Make sure HW does not configure LCD from PHY 2317203049Sjfv * extended configuration before SW configuration 2318203049Sjfv */ 2319203049Sjfv data = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); 2320247064Sjfv if ((hw->mac.type < e1000_pch2lan) && 2321247064Sjfv (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE)) 2322247064Sjfv goto release; 2323203049Sjfv 2324203049Sjfv cnf_size = E1000_READ_REG(hw, E1000_EXTCNF_SIZE); 2325203049Sjfv cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK; 2326203049Sjfv cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT; 2327203049Sjfv if (!cnf_size) 2328247064Sjfv goto release; 2329203049Sjfv 2330203049Sjfv cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK; 2331203049Sjfv cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT; 2332203049Sjfv 2333247064Sjfv if (((hw->mac.type == e1000_pchlan) && 2334247064Sjfv !(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)) || 2335247064Sjfv (hw->mac.type > e1000_pchlan)) { 2336247064Sjfv /* HW configures the SMBus address and LEDs when the 2337203049Sjfv * OEM and LCD Write Enable bits are set in the NVM. 2338203049Sjfv * When both NVM bits are cleared, SW will configure 2339203049Sjfv * them instead. 2340200243Sjfv */ 2341213234Sjfv ret_val = e1000_write_smbus_addr(hw); 2342203049Sjfv if (ret_val) 2343247064Sjfv goto release; 2344200243Sjfv 2345203049Sjfv data = E1000_READ_REG(hw, E1000_LEDCTL); 2346203049Sjfv ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG, 2347203049Sjfv (u16)data); 2348203049Sjfv if (ret_val) 2349247064Sjfv goto release; 2350203049Sjfv } 2351200243Sjfv 2352203049Sjfv /* Configure LCD from extended configuration region. */ 2353200243Sjfv 2354203049Sjfv /* cnf_base_addr is in DWORD */ 2355203049Sjfv word_addr = (u16)(cnf_base_addr << 1); 2356200243Sjfv 2357203049Sjfv for (i = 0; i < cnf_size; i++) { 2358203049Sjfv ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2), 1, 2359203049Sjfv ®_data); 2360203049Sjfv if (ret_val) 2361247064Sjfv goto release; 2362200243Sjfv 2363203049Sjfv ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2 + 1), 2364203049Sjfv 1, ®_addr); 2365203049Sjfv if (ret_val) 2366247064Sjfv goto release; 2367200243Sjfv 2368203049Sjfv /* Save off the PHY page for future writes. */ 2369203049Sjfv if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) { 2370203049Sjfv phy_page = reg_data; 2371203049Sjfv continue; 2372203049Sjfv } 2373200243Sjfv 2374203049Sjfv reg_addr &= PHY_REG_MASK; 2375203049Sjfv reg_addr |= phy_page; 2376200243Sjfv 2377203049Sjfv ret_val = phy->ops.write_reg_locked(hw, (u32)reg_addr, 2378203049Sjfv reg_data); 2379203049Sjfv if (ret_val) 2380247064Sjfv goto release; 2381200243Sjfv } 2382200243Sjfv 2383247064Sjfvrelease: 2384200243Sjfv hw->phy.ops.release(hw); 2385200243Sjfv return ret_val; 2386200243Sjfv} 2387200243Sjfv 2388200243Sjfv/** 2389200243Sjfv * e1000_k1_gig_workaround_hv - K1 Si workaround 2390200243Sjfv * @hw: pointer to the HW structure 2391200243Sjfv * @link: link up bool flag 2392200243Sjfv * 2393200243Sjfv * If K1 is enabled for 1Gbps, the MAC might stall when transitioning 2394200243Sjfv * from a lower speed. This workaround disables K1 whenever link is at 1Gig 2395200243Sjfv * If link is down, the function will restore the default K1 setting located 2396200243Sjfv * in the NVM. 2397200243Sjfv **/ 2398200243Sjfvstatic s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link) 2399200243Sjfv{ 2400200243Sjfv s32 ret_val = E1000_SUCCESS; 2401200243Sjfv u16 status_reg = 0; 2402200243Sjfv bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled; 2403200243Sjfv 2404200243Sjfv DEBUGFUNC("e1000_k1_gig_workaround_hv"); 2405200243Sjfv 2406200243Sjfv if (hw->mac.type != e1000_pchlan) 2407247064Sjfv return E1000_SUCCESS; 2408200243Sjfv 2409200243Sjfv /* Wrap the whole flow with the sw flag */ 2410200243Sjfv ret_val = hw->phy.ops.acquire(hw); 2411200243Sjfv if (ret_val) 2412247064Sjfv return ret_val; 2413200243Sjfv 2414200243Sjfv /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */ 2415200243Sjfv if (link) { 2416200243Sjfv if (hw->phy.type == e1000_phy_82578) { 2417200243Sjfv ret_val = hw->phy.ops.read_reg_locked(hw, BM_CS_STATUS, 2418228386Sjfv &status_reg); 2419200243Sjfv if (ret_val) 2420200243Sjfv goto release; 2421200243Sjfv 2422256200Sjfv status_reg &= (BM_CS_STATUS_LINK_UP | 2423256200Sjfv BM_CS_STATUS_RESOLVED | 2424256200Sjfv BM_CS_STATUS_SPEED_MASK); 2425200243Sjfv 2426200243Sjfv if (status_reg == (BM_CS_STATUS_LINK_UP | 2427228386Sjfv BM_CS_STATUS_RESOLVED | 2428228386Sjfv BM_CS_STATUS_SPEED_1000)) 2429200243Sjfv k1_enable = FALSE; 2430200243Sjfv } 2431200243Sjfv 2432200243Sjfv if (hw->phy.type == e1000_phy_82577) { 2433200243Sjfv ret_val = hw->phy.ops.read_reg_locked(hw, HV_M_STATUS, 2434228386Sjfv &status_reg); 2435200243Sjfv if (ret_val) 2436200243Sjfv goto release; 2437200243Sjfv 2438256200Sjfv status_reg &= (HV_M_STATUS_LINK_UP | 2439256200Sjfv HV_M_STATUS_AUTONEG_COMPLETE | 2440256200Sjfv HV_M_STATUS_SPEED_MASK); 2441200243Sjfv 2442200243Sjfv if (status_reg == (HV_M_STATUS_LINK_UP | 2443228386Sjfv HV_M_STATUS_AUTONEG_COMPLETE | 2444228386Sjfv HV_M_STATUS_SPEED_1000)) 2445200243Sjfv k1_enable = FALSE; 2446200243Sjfv } 2447200243Sjfv 2448200243Sjfv /* Link stall fix for link up */ 2449200243Sjfv ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19), 2450228386Sjfv 0x0100); 2451200243Sjfv if (ret_val) 2452200243Sjfv goto release; 2453200243Sjfv 2454200243Sjfv } else { 2455200243Sjfv /* Link stall fix for link down */ 2456200243Sjfv ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19), 2457228386Sjfv 0x4100); 2458200243Sjfv if (ret_val) 2459200243Sjfv goto release; 2460200243Sjfv } 2461200243Sjfv 2462200243Sjfv ret_val = e1000_configure_k1_ich8lan(hw, k1_enable); 2463200243Sjfv 2464200243Sjfvrelease: 2465200243Sjfv hw->phy.ops.release(hw); 2466247064Sjfv 2467200243Sjfv return ret_val; 2468200243Sjfv} 2469200243Sjfv 2470200243Sjfv/** 2471200243Sjfv * e1000_configure_k1_ich8lan - Configure K1 power state 2472200243Sjfv * @hw: pointer to the HW structure 2473200243Sjfv * @enable: K1 state to configure 2474200243Sjfv * 2475200243Sjfv * Configure the K1 power state based on the provided parameter. 2476200243Sjfv * Assumes semaphore already acquired. 2477200243Sjfv * 2478200243Sjfv * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 2479200243Sjfv **/ 2480200243Sjfvs32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable) 2481200243Sjfv{ 2482247064Sjfv s32 ret_val; 2483200243Sjfv u32 ctrl_reg = 0; 2484200243Sjfv u32 ctrl_ext = 0; 2485200243Sjfv u32 reg = 0; 2486200243Sjfv u16 kmrn_reg = 0; 2487200243Sjfv 2488213234Sjfv DEBUGFUNC("e1000_configure_k1_ich8lan"); 2489213234Sjfv 2490228386Sjfv ret_val = e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG, 2491228386Sjfv &kmrn_reg); 2492200243Sjfv if (ret_val) 2493247064Sjfv return ret_val; 2494200243Sjfv 2495200243Sjfv if (k1_enable) 2496200243Sjfv kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE; 2497200243Sjfv else 2498200243Sjfv kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE; 2499200243Sjfv 2500228386Sjfv ret_val = e1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG, 2501228386Sjfv kmrn_reg); 2502200243Sjfv if (ret_val) 2503247064Sjfv return ret_val; 2504200243Sjfv 2505200243Sjfv usec_delay(20); 2506200243Sjfv ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 2507200243Sjfv ctrl_reg = E1000_READ_REG(hw, E1000_CTRL); 2508200243Sjfv 2509200243Sjfv reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); 2510200243Sjfv reg |= E1000_CTRL_FRCSPD; 2511200243Sjfv E1000_WRITE_REG(hw, E1000_CTRL, reg); 2512200243Sjfv 2513200243Sjfv E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS); 2514228386Sjfv E1000_WRITE_FLUSH(hw); 2515200243Sjfv usec_delay(20); 2516200243Sjfv E1000_WRITE_REG(hw, E1000_CTRL, ctrl_reg); 2517200243Sjfv E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 2518228386Sjfv E1000_WRITE_FLUSH(hw); 2519200243Sjfv usec_delay(20); 2520200243Sjfv 2521247064Sjfv return E1000_SUCCESS; 2522200243Sjfv} 2523200243Sjfv 2524200243Sjfv/** 2525200243Sjfv * e1000_oem_bits_config_ich8lan - SW-based LCD Configuration 2526200243Sjfv * @hw: pointer to the HW structure 2527200243Sjfv * @d0_state: boolean if entering d0 or d3 device state 2528200243Sjfv * 2529200243Sjfv * SW will configure Gbe Disable and LPLU based on the NVM. The four bits are 2530200243Sjfv * collectively called OEM bits. The OEM Write Enable bit and SW Config bit 2531200243Sjfv * in NVM determines whether HW should configure LPLU and Gbe Disable. 2532200243Sjfv **/ 2533228386Sjfvstatic s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state) 2534200243Sjfv{ 2535200243Sjfv s32 ret_val = 0; 2536200243Sjfv u32 mac_reg; 2537200243Sjfv u16 oem_reg; 2538200243Sjfv 2539213234Sjfv DEBUGFUNC("e1000_oem_bits_config_ich8lan"); 2540213234Sjfv 2541247064Sjfv if (hw->mac.type < e1000_pchlan) 2542200243Sjfv return ret_val; 2543200243Sjfv 2544200243Sjfv ret_val = hw->phy.ops.acquire(hw); 2545200243Sjfv if (ret_val) 2546200243Sjfv return ret_val; 2547200243Sjfv 2548247064Sjfv if (hw->mac.type == e1000_pchlan) { 2549213234Sjfv mac_reg = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); 2550213234Sjfv if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE) 2551247064Sjfv goto release; 2552213234Sjfv } 2553200243Sjfv 2554200243Sjfv mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM); 2555200243Sjfv if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M)) 2556247064Sjfv goto release; 2557200243Sjfv 2558200243Sjfv mac_reg = E1000_READ_REG(hw, E1000_PHY_CTRL); 2559200243Sjfv 2560200243Sjfv ret_val = hw->phy.ops.read_reg_locked(hw, HV_OEM_BITS, &oem_reg); 2561200243Sjfv if (ret_val) 2562247064Sjfv goto release; 2563200243Sjfv 2564200243Sjfv oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU); 2565200243Sjfv 2566200243Sjfv if (d0_state) { 2567200243Sjfv if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE) 2568200243Sjfv oem_reg |= HV_OEM_BITS_GBE_DIS; 2569200243Sjfv 2570200243Sjfv if (mac_reg & E1000_PHY_CTRL_D0A_LPLU) 2571200243Sjfv oem_reg |= HV_OEM_BITS_LPLU; 2572200243Sjfv } else { 2573228386Sjfv if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE | 2574228386Sjfv E1000_PHY_CTRL_NOND0A_GBE_DISABLE)) 2575200243Sjfv oem_reg |= HV_OEM_BITS_GBE_DIS; 2576200243Sjfv 2577228386Sjfv if (mac_reg & (E1000_PHY_CTRL_D0A_LPLU | 2578228386Sjfv E1000_PHY_CTRL_NOND0A_LPLU)) 2579200243Sjfv oem_reg |= HV_OEM_BITS_LPLU; 2580200243Sjfv } 2581228386Sjfv 2582247064Sjfv /* Set Restart auto-neg to activate the bits */ 2583247064Sjfv if ((d0_state || (hw->mac.type != e1000_pchlan)) && 2584247064Sjfv !hw->phy.ops.check_reset_block(hw)) 2585247064Sjfv oem_reg |= HV_OEM_BITS_RESTART_AN; 2586247064Sjfv 2587200243Sjfv ret_val = hw->phy.ops.write_reg_locked(hw, HV_OEM_BITS, oem_reg); 2588200243Sjfv 2589247064Sjfvrelease: 2590200243Sjfv hw->phy.ops.release(hw); 2591200243Sjfv 2592200243Sjfv return ret_val; 2593200243Sjfv} 2594200243Sjfv 2595200243Sjfv 2596200243Sjfv/** 2597203049Sjfv * e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode 2598203049Sjfv * @hw: pointer to the HW structure 2599203049Sjfv **/ 2600203049Sjfvstatic s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw) 2601203049Sjfv{ 2602203049Sjfv s32 ret_val; 2603203049Sjfv u16 data; 2604203049Sjfv 2605213234Sjfv DEBUGFUNC("e1000_set_mdio_slow_mode_hv"); 2606213234Sjfv 2607203049Sjfv ret_val = hw->phy.ops.read_reg(hw, HV_KMRN_MODE_CTRL, &data); 2608203049Sjfv if (ret_val) 2609203049Sjfv return ret_val; 2610203049Sjfv 2611203049Sjfv data |= HV_KMRN_MDIO_SLOW; 2612203049Sjfv 2613203049Sjfv ret_val = hw->phy.ops.write_reg(hw, HV_KMRN_MODE_CTRL, data); 2614203049Sjfv 2615203049Sjfv return ret_val; 2616203049Sjfv} 2617203049Sjfv 2618203049Sjfv/** 2619194865Sjfv * e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be 2620194865Sjfv * done after every PHY reset. 2621194865Sjfv **/ 2622194865Sjfvstatic s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw) 2623194865Sjfv{ 2624194865Sjfv s32 ret_val = E1000_SUCCESS; 2625203049Sjfv u16 phy_data; 2626194865Sjfv 2627213234Sjfv DEBUGFUNC("e1000_hv_phy_workarounds_ich8lan"); 2628213234Sjfv 2629194865Sjfv if (hw->mac.type != e1000_pchlan) 2630247064Sjfv return E1000_SUCCESS; 2631194865Sjfv 2632203049Sjfv /* Set MDIO slow mode before any other MDIO access */ 2633203049Sjfv if (hw->phy.type == e1000_phy_82577) { 2634203049Sjfv ret_val = e1000_set_mdio_slow_mode_hv(hw); 2635203049Sjfv if (ret_val) 2636247064Sjfv return ret_val; 2637203049Sjfv } 2638203049Sjfv 2639194865Sjfv if (((hw->phy.type == e1000_phy_82577) && 2640194865Sjfv ((hw->phy.revision == 1) || (hw->phy.revision == 2))) || 2641194865Sjfv ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) { 2642194865Sjfv /* Disable generation of early preamble */ 2643194865Sjfv ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 25), 0x4431); 2644194865Sjfv if (ret_val) 2645247064Sjfv return ret_val; 2646169240Sjfv 2647194865Sjfv /* Preamble tuning for SSC */ 2648228386Sjfv ret_val = hw->phy.ops.write_reg(hw, HV_KMRN_FIFO_CTRLSTA, 2649228386Sjfv 0xA204); 2650194865Sjfv if (ret_val) 2651247064Sjfv return ret_val; 2652194865Sjfv } 2653169240Sjfv 2654194865Sjfv if (hw->phy.type == e1000_phy_82578) { 2655247064Sjfv /* Return registers to default by doing a soft reset then 2656194865Sjfv * writing 0x3140 to the control register. 2657194865Sjfv */ 2658194865Sjfv if (hw->phy.revision < 2) { 2659194865Sjfv e1000_phy_sw_reset_generic(hw); 2660194865Sjfv ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, 2661228386Sjfv 0x3140); 2662333213Smarius if (ret_val) 2663333213Smarius return ret_val; 2664194865Sjfv } 2665194865Sjfv } 2666169240Sjfv 2667194865Sjfv /* Select page 0 */ 2668194865Sjfv ret_val = hw->phy.ops.acquire(hw); 2669169240Sjfv if (ret_val) 2670247064Sjfv return ret_val; 2671200243Sjfv 2672194865Sjfv hw->phy.addr = 1; 2673200243Sjfv ret_val = e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0); 2674203049Sjfv hw->phy.ops.release(hw); 2675200243Sjfv if (ret_val) 2676247064Sjfv return ret_val; 2677169240Sjfv 2678247064Sjfv /* Configure the K1 Si workaround during phy reset assuming there is 2679200243Sjfv * link so that it disables K1 if link is in 1Gbps. 2680200243Sjfv */ 2681200243Sjfv ret_val = e1000_k1_gig_workaround_hv(hw, TRUE); 2682203049Sjfv if (ret_val) 2683247064Sjfv return ret_val; 2684200243Sjfv 2685203049Sjfv /* Workaround for link disconnects on a busy hub in half duplex */ 2686203049Sjfv ret_val = hw->phy.ops.acquire(hw); 2687203049Sjfv if (ret_val) 2688247064Sjfv return ret_val; 2689228386Sjfv ret_val = hw->phy.ops.read_reg_locked(hw, BM_PORT_GEN_CFG, &phy_data); 2690203049Sjfv if (ret_val) 2691203049Sjfv goto release; 2692228386Sjfv ret_val = hw->phy.ops.write_reg_locked(hw, BM_PORT_GEN_CFG, 2693228386Sjfv phy_data & 0x00FF); 2694247064Sjfv if (ret_val) 2695247064Sjfv goto release; 2696247064Sjfv 2697247064Sjfv /* set MSE higher to enable link to stay up when noise is high */ 2698247064Sjfv ret_val = e1000_write_emi_reg_locked(hw, I82577_MSE_THRESHOLD, 0x0034); 2699203049Sjfvrelease: 2700203049Sjfv hw->phy.ops.release(hw); 2701247064Sjfv 2702194865Sjfv return ret_val; 2703194865Sjfv} 2704169240Sjfv 2705194865Sjfv/** 2706213234Sjfv * e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY 2707213234Sjfv * @hw: pointer to the HW structure 2708213234Sjfv **/ 2709213234Sjfvvoid e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw) 2710213234Sjfv{ 2711213234Sjfv u32 mac_reg; 2712228386Sjfv u16 i, phy_reg = 0; 2713228386Sjfv s32 ret_val; 2714213234Sjfv 2715213234Sjfv DEBUGFUNC("e1000_copy_rx_addrs_to_phy_ich8lan"); 2716213234Sjfv 2717228386Sjfv ret_val = hw->phy.ops.acquire(hw); 2718228386Sjfv if (ret_val) 2719228386Sjfv return; 2720228386Sjfv ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg); 2721228386Sjfv if (ret_val) 2722228386Sjfv goto release; 2723228386Sjfv 2724256200Sjfv /* Copy both RAL/H (rar_entry_count) and SHRAL/H to PHY */ 2725256200Sjfv for (i = 0; i < (hw->mac.rar_entry_count); i++) { 2726213234Sjfv mac_reg = E1000_READ_REG(hw, E1000_RAL(i)); 2727228386Sjfv hw->phy.ops.write_reg_page(hw, BM_RAR_L(i), 2728228386Sjfv (u16)(mac_reg & 0xFFFF)); 2729228386Sjfv hw->phy.ops.write_reg_page(hw, BM_RAR_M(i), 2730228386Sjfv (u16)((mac_reg >> 16) & 0xFFFF)); 2731228386Sjfv 2732213234Sjfv mac_reg = E1000_READ_REG(hw, E1000_RAH(i)); 2733228386Sjfv hw->phy.ops.write_reg_page(hw, BM_RAR_H(i), 2734228386Sjfv (u16)(mac_reg & 0xFFFF)); 2735228386Sjfv hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i), 2736228386Sjfv (u16)((mac_reg & E1000_RAH_AV) 2737228386Sjfv >> 16)); 2738213234Sjfv } 2739228386Sjfv 2740228386Sjfv e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg); 2741228386Sjfv 2742228386Sjfvrelease: 2743228386Sjfv hw->phy.ops.release(hw); 2744213234Sjfv} 2745213234Sjfv 2746213234Sjfvstatic u32 e1000_calc_rx_da_crc(u8 mac[]) 2747213234Sjfv{ 2748213234Sjfv u32 poly = 0xEDB88320; /* Polynomial for 802.3 CRC calculation */ 2749213234Sjfv u32 i, j, mask, crc; 2750213234Sjfv 2751213234Sjfv DEBUGFUNC("e1000_calc_rx_da_crc"); 2752213234Sjfv 2753213234Sjfv crc = 0xffffffff; 2754213234Sjfv for (i = 0; i < 6; i++) { 2755213234Sjfv crc = crc ^ mac[i]; 2756213234Sjfv for (j = 8; j > 0; j--) { 2757213234Sjfv mask = (crc & 1) * (-1); 2758213234Sjfv crc = (crc >> 1) ^ (poly & mask); 2759213234Sjfv } 2760213234Sjfv } 2761213234Sjfv return ~crc; 2762213234Sjfv} 2763213234Sjfv 2764213234Sjfv/** 2765213234Sjfv * e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation 2766213234Sjfv * with 82579 PHY 2767213234Sjfv * @hw: pointer to the HW structure 2768213234Sjfv * @enable: flag to enable/disable workaround when enabling/disabling jumbos 2769213234Sjfv **/ 2770213234Sjfvs32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable) 2771213234Sjfv{ 2772213234Sjfv s32 ret_val = E1000_SUCCESS; 2773213234Sjfv u16 phy_reg, data; 2774213234Sjfv u32 mac_reg; 2775213234Sjfv u16 i; 2776213234Sjfv 2777213234Sjfv DEBUGFUNC("e1000_lv_jumbo_workaround_ich8lan"); 2778213234Sjfv 2779247064Sjfv if (hw->mac.type < e1000_pch2lan) 2780247064Sjfv return E1000_SUCCESS; 2781213234Sjfv 2782213234Sjfv /* disable Rx path while enabling/disabling workaround */ 2783213234Sjfv hw->phy.ops.read_reg(hw, PHY_REG(769, 20), &phy_reg); 2784228386Sjfv ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 20), 2785228386Sjfv phy_reg | (1 << 14)); 2786213234Sjfv if (ret_val) 2787247064Sjfv return ret_val; 2788213234Sjfv 2789213234Sjfv if (enable) { 2790256200Sjfv /* Write Rx addresses (rar_entry_count for RAL/H, and 2791213234Sjfv * SHRAL/H) and initial CRC values to the MAC 2792213234Sjfv */ 2793256200Sjfv for (i = 0; i < hw->mac.rar_entry_count; i++) { 2794213234Sjfv u8 mac_addr[ETH_ADDR_LEN] = {0}; 2795213234Sjfv u32 addr_high, addr_low; 2796213234Sjfv 2797213234Sjfv addr_high = E1000_READ_REG(hw, E1000_RAH(i)); 2798213234Sjfv if (!(addr_high & E1000_RAH_AV)) 2799213234Sjfv continue; 2800213234Sjfv addr_low = E1000_READ_REG(hw, E1000_RAL(i)); 2801213234Sjfv mac_addr[0] = (addr_low & 0xFF); 2802213234Sjfv mac_addr[1] = ((addr_low >> 8) & 0xFF); 2803213234Sjfv mac_addr[2] = ((addr_low >> 16) & 0xFF); 2804213234Sjfv mac_addr[3] = ((addr_low >> 24) & 0xFF); 2805213234Sjfv mac_addr[4] = (addr_high & 0xFF); 2806213234Sjfv mac_addr[5] = ((addr_high >> 8) & 0xFF); 2807213234Sjfv 2808213234Sjfv E1000_WRITE_REG(hw, E1000_PCH_RAICC(i), 2809213234Sjfv e1000_calc_rx_da_crc(mac_addr)); 2810213234Sjfv } 2811213234Sjfv 2812213234Sjfv /* Write Rx addresses to the PHY */ 2813213234Sjfv e1000_copy_rx_addrs_to_phy_ich8lan(hw); 2814213234Sjfv 2815213234Sjfv /* Enable jumbo frame workaround in the MAC */ 2816213234Sjfv mac_reg = E1000_READ_REG(hw, E1000_FFLT_DBG); 2817213234Sjfv mac_reg &= ~(1 << 14); 2818213234Sjfv mac_reg |= (7 << 15); 2819213234Sjfv E1000_WRITE_REG(hw, E1000_FFLT_DBG, mac_reg); 2820213234Sjfv 2821213234Sjfv mac_reg = E1000_READ_REG(hw, E1000_RCTL); 2822213234Sjfv mac_reg |= E1000_RCTL_SECRC; 2823213234Sjfv E1000_WRITE_REG(hw, E1000_RCTL, mac_reg); 2824213234Sjfv 2825213234Sjfv ret_val = e1000_read_kmrn_reg_generic(hw, 2826213234Sjfv E1000_KMRNCTRLSTA_CTRL_OFFSET, 2827213234Sjfv &data); 2828213234Sjfv if (ret_val) 2829247064Sjfv return ret_val; 2830213234Sjfv ret_val = e1000_write_kmrn_reg_generic(hw, 2831213234Sjfv E1000_KMRNCTRLSTA_CTRL_OFFSET, 2832213234Sjfv data | (1 << 0)); 2833213234Sjfv if (ret_val) 2834247064Sjfv return ret_val; 2835213234Sjfv ret_val = e1000_read_kmrn_reg_generic(hw, 2836213234Sjfv E1000_KMRNCTRLSTA_HD_CTRL, 2837213234Sjfv &data); 2838213234Sjfv if (ret_val) 2839247064Sjfv return ret_val; 2840213234Sjfv data &= ~(0xF << 8); 2841213234Sjfv data |= (0xB << 8); 2842213234Sjfv ret_val = e1000_write_kmrn_reg_generic(hw, 2843213234Sjfv E1000_KMRNCTRLSTA_HD_CTRL, 2844213234Sjfv data); 2845213234Sjfv if (ret_val) 2846247064Sjfv return ret_val; 2847213234Sjfv 2848213234Sjfv /* Enable jumbo frame workaround in the PHY */ 2849213234Sjfv hw->phy.ops.read_reg(hw, PHY_REG(769, 23), &data); 2850213234Sjfv data &= ~(0x7F << 5); 2851213234Sjfv data |= (0x37 << 5); 2852213234Sjfv ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 23), data); 2853213234Sjfv if (ret_val) 2854247064Sjfv return ret_val; 2855213234Sjfv hw->phy.ops.read_reg(hw, PHY_REG(769, 16), &data); 2856213234Sjfv data &= ~(1 << 13); 2857213234Sjfv ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 16), data); 2858213234Sjfv if (ret_val) 2859247064Sjfv return ret_val; 2860213234Sjfv hw->phy.ops.read_reg(hw, PHY_REG(776, 20), &data); 2861213234Sjfv data &= ~(0x3FF << 2); 2862267935Sjfv data |= (E1000_TX_PTR_GAP << 2); 2863213234Sjfv ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 20), data); 2864213234Sjfv if (ret_val) 2865247064Sjfv return ret_val; 2866228386Sjfv ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 23), 0xF100); 2867213234Sjfv if (ret_val) 2868247064Sjfv return ret_val; 2869213234Sjfv hw->phy.ops.read_reg(hw, HV_PM_CTRL, &data); 2870228386Sjfv ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, data | 2871228386Sjfv (1 << 10)); 2872213234Sjfv if (ret_val) 2873247064Sjfv return ret_val; 2874213234Sjfv } else { 2875213234Sjfv /* Write MAC register values back to h/w defaults */ 2876213234Sjfv mac_reg = E1000_READ_REG(hw, E1000_FFLT_DBG); 2877213234Sjfv mac_reg &= ~(0xF << 14); 2878213234Sjfv E1000_WRITE_REG(hw, E1000_FFLT_DBG, mac_reg); 2879213234Sjfv 2880213234Sjfv mac_reg = E1000_READ_REG(hw, E1000_RCTL); 2881213234Sjfv mac_reg &= ~E1000_RCTL_SECRC; 2882213234Sjfv E1000_WRITE_REG(hw, E1000_RCTL, mac_reg); 2883213234Sjfv 2884213234Sjfv ret_val = e1000_read_kmrn_reg_generic(hw, 2885213234Sjfv E1000_KMRNCTRLSTA_CTRL_OFFSET, 2886213234Sjfv &data); 2887213234Sjfv if (ret_val) 2888247064Sjfv return ret_val; 2889213234Sjfv ret_val = e1000_write_kmrn_reg_generic(hw, 2890213234Sjfv E1000_KMRNCTRLSTA_CTRL_OFFSET, 2891213234Sjfv data & ~(1 << 0)); 2892213234Sjfv if (ret_val) 2893247064Sjfv return ret_val; 2894213234Sjfv ret_val = e1000_read_kmrn_reg_generic(hw, 2895213234Sjfv E1000_KMRNCTRLSTA_HD_CTRL, 2896213234Sjfv &data); 2897213234Sjfv if (ret_val) 2898247064Sjfv return ret_val; 2899213234Sjfv data &= ~(0xF << 8); 2900213234Sjfv data |= (0xB << 8); 2901213234Sjfv ret_val = e1000_write_kmrn_reg_generic(hw, 2902213234Sjfv E1000_KMRNCTRLSTA_HD_CTRL, 2903213234Sjfv data); 2904213234Sjfv if (ret_val) 2905247064Sjfv return ret_val; 2906213234Sjfv 2907213234Sjfv /* Write PHY register values back to h/w defaults */ 2908213234Sjfv hw->phy.ops.read_reg(hw, PHY_REG(769, 23), &data); 2909213234Sjfv data &= ~(0x7F << 5); 2910213234Sjfv ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 23), data); 2911213234Sjfv if (ret_val) 2912247064Sjfv return ret_val; 2913213234Sjfv hw->phy.ops.read_reg(hw, PHY_REG(769, 16), &data); 2914213234Sjfv data |= (1 << 13); 2915213234Sjfv ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 16), data); 2916213234Sjfv if (ret_val) 2917247064Sjfv return ret_val; 2918213234Sjfv hw->phy.ops.read_reg(hw, PHY_REG(776, 20), &data); 2919213234Sjfv data &= ~(0x3FF << 2); 2920213234Sjfv data |= (0x8 << 2); 2921213234Sjfv ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 20), data); 2922213234Sjfv if (ret_val) 2923247064Sjfv return ret_val; 2924213234Sjfv ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 23), 0x7E00); 2925213234Sjfv if (ret_val) 2926247064Sjfv return ret_val; 2927213234Sjfv hw->phy.ops.read_reg(hw, HV_PM_CTRL, &data); 2928228386Sjfv ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, data & 2929228386Sjfv ~(1 << 10)); 2930213234Sjfv if (ret_val) 2931247064Sjfv return ret_val; 2932213234Sjfv } 2933213234Sjfv 2934213234Sjfv /* re-enable Rx path after enabling/disabling workaround */ 2935247064Sjfv return hw->phy.ops.write_reg(hw, PHY_REG(769, 20), phy_reg & 2936247064Sjfv ~(1 << 14)); 2937213234Sjfv} 2938213234Sjfv 2939213234Sjfv/** 2940213234Sjfv * e1000_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be 2941213234Sjfv * done after every PHY reset. 2942213234Sjfv **/ 2943213234Sjfvstatic s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw) 2944213234Sjfv{ 2945213234Sjfv s32 ret_val = E1000_SUCCESS; 2946213234Sjfv 2947213234Sjfv DEBUGFUNC("e1000_lv_phy_workarounds_ich8lan"); 2948213234Sjfv 2949213234Sjfv if (hw->mac.type != e1000_pch2lan) 2950247064Sjfv return E1000_SUCCESS; 2951213234Sjfv 2952213234Sjfv /* Set MDIO slow mode before any other MDIO access */ 2953213234Sjfv ret_val = e1000_set_mdio_slow_mode_hv(hw); 2954247064Sjfv if (ret_val) 2955247064Sjfv return ret_val; 2956213234Sjfv 2957228386Sjfv ret_val = hw->phy.ops.acquire(hw); 2958228386Sjfv if (ret_val) 2959247064Sjfv return ret_val; 2960228386Sjfv /* set MSE higher to enable link to stay up when noise is high */ 2961247064Sjfv ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_THRESHOLD, 0x0034); 2962228386Sjfv if (ret_val) 2963228386Sjfv goto release; 2964228386Sjfv /* drop link after 5 times MSE threshold was reached */ 2965247064Sjfv ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_LINK_DOWN, 0x0005); 2966228386Sjfvrelease: 2967228386Sjfv hw->phy.ops.release(hw); 2968228386Sjfv 2969213234Sjfv return ret_val; 2970213234Sjfv} 2971213234Sjfv 2972213234Sjfv/** 2973213234Sjfv * e1000_k1_gig_workaround_lv - K1 Si workaround 2974213234Sjfv * @hw: pointer to the HW structure 2975213234Sjfv * 2976267935Sjfv * Workaround to set the K1 beacon duration for 82579 parts in 10Mbps 2977267935Sjfv * Disable K1 for 1000 and 100 speeds 2978213234Sjfv **/ 2979213234Sjfvstatic s32 e1000_k1_workaround_lv(struct e1000_hw *hw) 2980213234Sjfv{ 2981213234Sjfv s32 ret_val = E1000_SUCCESS; 2982213234Sjfv u16 status_reg = 0; 2983213234Sjfv 2984213234Sjfv DEBUGFUNC("e1000_k1_workaround_lv"); 2985213234Sjfv 2986213234Sjfv if (hw->mac.type != e1000_pch2lan) 2987247064Sjfv return E1000_SUCCESS; 2988213234Sjfv 2989267935Sjfv /* Set K1 beacon duration based on 10Mbs speed */ 2990213234Sjfv ret_val = hw->phy.ops.read_reg(hw, HV_M_STATUS, &status_reg); 2991213234Sjfv if (ret_val) 2992247064Sjfv return ret_val; 2993213234Sjfv 2994213234Sjfv if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) 2995213234Sjfv == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) { 2996267935Sjfv if (status_reg & 2997267935Sjfv (HV_M_STATUS_SPEED_1000 | HV_M_STATUS_SPEED_100)) { 2998247064Sjfv u16 pm_phy_reg; 2999247064Sjfv 3000267935Sjfv /* LV 1G/100 Packet drop issue wa */ 3001247064Sjfv ret_val = hw->phy.ops.read_reg(hw, HV_PM_CTRL, 3002247064Sjfv &pm_phy_reg); 3003247064Sjfv if (ret_val) 3004247064Sjfv return ret_val; 3005267935Sjfv pm_phy_reg &= ~HV_PM_CTRL_K1_ENABLE; 3006247064Sjfv ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, 3007247064Sjfv pm_phy_reg); 3008247064Sjfv if (ret_val) 3009247064Sjfv return ret_val; 3010228386Sjfv } else { 3011267935Sjfv u32 mac_reg; 3012267935Sjfv mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM4); 3013267935Sjfv mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK; 3014213234Sjfv mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC; 3015267935Sjfv E1000_WRITE_REG(hw, E1000_FEXTNVM4, mac_reg); 3016228386Sjfv } 3017213234Sjfv } 3018213234Sjfv 3019213234Sjfv return ret_val; 3020213234Sjfv} 3021213234Sjfv 3022213234Sjfv/** 3023213234Sjfv * e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware 3024213234Sjfv * @hw: pointer to the HW structure 3025218588Sjfv * @gate: boolean set to TRUE to gate, FALSE to ungate 3026213234Sjfv * 3027213234Sjfv * Gate/ungate the automatic PHY configuration via hardware; perform 3028213234Sjfv * the configuration via software instead. 3029213234Sjfv **/ 3030213234Sjfvstatic void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate) 3031213234Sjfv{ 3032213234Sjfv u32 extcnf_ctrl; 3033213234Sjfv 3034213234Sjfv DEBUGFUNC("e1000_gate_hw_phy_config_ich8lan"); 3035213234Sjfv 3036247064Sjfv if (hw->mac.type < e1000_pch2lan) 3037213234Sjfv return; 3038213234Sjfv 3039213234Sjfv extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); 3040213234Sjfv 3041213234Sjfv if (gate) 3042213234Sjfv extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG; 3043213234Sjfv else 3044213234Sjfv extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG; 3045213234Sjfv 3046213234Sjfv E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl); 3047213234Sjfv} 3048213234Sjfv 3049213234Sjfv/** 3050194865Sjfv * e1000_lan_init_done_ich8lan - Check for PHY config completion 3051194865Sjfv * @hw: pointer to the HW structure 3052194865Sjfv * 3053194865Sjfv * Check the appropriate indication the MAC has finished configuring the 3054194865Sjfv * PHY after a software reset. 3055194865Sjfv **/ 3056194865Sjfvstatic void e1000_lan_init_done_ich8lan(struct e1000_hw *hw) 3057194865Sjfv{ 3058194865Sjfv u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT; 3059169240Sjfv 3060194865Sjfv DEBUGFUNC("e1000_lan_init_done_ich8lan"); 3061169240Sjfv 3062194865Sjfv /* Wait for basic configuration completes before proceeding */ 3063194865Sjfv do { 3064194865Sjfv data = E1000_READ_REG(hw, E1000_STATUS); 3065194865Sjfv data &= E1000_STATUS_LAN_INIT_DONE; 3066194865Sjfv usec_delay(100); 3067194865Sjfv } while ((!data) && --loop); 3068169240Sjfv 3069247064Sjfv /* If basic configuration is incomplete before the above loop 3070194865Sjfv * count reaches 0, loading the configuration from NVM will 3071194865Sjfv * leave the PHY in a bad state possibly resulting in no link. 3072194865Sjfv */ 3073194865Sjfv if (loop == 0) 3074194865Sjfv DEBUGOUT("LAN_INIT_DONE not set, increase timeout\n"); 3075169240Sjfv 3076194865Sjfv /* Clear the Init Done bit for the next init event */ 3077194865Sjfv data = E1000_READ_REG(hw, E1000_STATUS); 3078194865Sjfv data &= ~E1000_STATUS_LAN_INIT_DONE; 3079194865Sjfv E1000_WRITE_REG(hw, E1000_STATUS, data); 3080169240Sjfv} 3081169240Sjfv 3082169240Sjfv/** 3083213234Sjfv * e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset 3084169589Sjfv * @hw: pointer to the HW structure 3085169240Sjfv **/ 3086213234Sjfvstatic s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw) 3087169240Sjfv{ 3088200243Sjfv s32 ret_val = E1000_SUCCESS; 3089200243Sjfv u16 reg; 3090169240Sjfv 3091213234Sjfv DEBUGFUNC("e1000_post_phy_reset_ich8lan"); 3092169240Sjfv 3093213234Sjfv if (hw->phy.ops.check_reset_block(hw)) 3094247064Sjfv return E1000_SUCCESS; 3095169240Sjfv 3096213234Sjfv /* Allow time for h/w to get to quiescent state after reset */ 3097194865Sjfv msec_delay(10); 3098194865Sjfv 3099203049Sjfv /* Perform any necessary post-reset workarounds */ 3100203049Sjfv switch (hw->mac.type) { 3101203049Sjfv case e1000_pchlan: 3102194865Sjfv ret_val = e1000_hv_phy_workarounds_ich8lan(hw); 3103194865Sjfv if (ret_val) 3104247064Sjfv return ret_val; 3105203049Sjfv break; 3106213234Sjfv case e1000_pch2lan: 3107213234Sjfv ret_val = e1000_lv_phy_workarounds_ich8lan(hw); 3108213234Sjfv if (ret_val) 3109247064Sjfv return ret_val; 3110213234Sjfv break; 3111203049Sjfv default: 3112203049Sjfv break; 3113194865Sjfv } 3114194865Sjfv 3115228386Sjfv /* Clear the host wakeup bit after lcd reset */ 3116228386Sjfv if (hw->mac.type >= e1000_pchlan) { 3117228386Sjfv hw->phy.ops.read_reg(hw, BM_PORT_GEN_CFG, ®); 3118228386Sjfv reg &= ~BM_WUC_HOST_WU_BIT; 3119228386Sjfv hw->phy.ops.write_reg(hw, BM_PORT_GEN_CFG, reg); 3120213234Sjfv } 3121213234Sjfv 3122200243Sjfv /* Configure the LCD with the extended configuration region in NVM */ 3123200243Sjfv ret_val = e1000_sw_lcd_config_ich8lan(hw); 3124200243Sjfv if (ret_val) 3125247064Sjfv return ret_val; 3126169240Sjfv 3127200243Sjfv /* Configure the LCD with the OEM bits in NVM */ 3128203049Sjfv ret_val = e1000_oem_bits_config_ich8lan(hw, TRUE); 3129169240Sjfv 3130218588Sjfv if (hw->mac.type == e1000_pch2lan) { 3131218588Sjfv /* Ungate automatic PHY configuration on non-managed 82579 */ 3132218588Sjfv if (!(E1000_READ_REG(hw, E1000_FWSM) & 3133218588Sjfv E1000_ICH_FWSM_FW_VALID)) { 3134218588Sjfv msec_delay(10); 3135218588Sjfv e1000_gate_hw_phy_config_ich8lan(hw, FALSE); 3136218588Sjfv } 3137218588Sjfv 3138218588Sjfv /* Set EEE LPI Update Timer to 200usec */ 3139218588Sjfv ret_val = hw->phy.ops.acquire(hw); 3140218588Sjfv if (ret_val) 3141247064Sjfv return ret_val; 3142247064Sjfv ret_val = e1000_write_emi_reg_locked(hw, 3143247064Sjfv I82579_LPI_UPDATE_TIMER, 3144247064Sjfv 0x1387); 3145218588Sjfv hw->phy.ops.release(hw); 3146213234Sjfv } 3147213234Sjfv 3148169240Sjfv return ret_val; 3149169240Sjfv} 3150169240Sjfv 3151169240Sjfv/** 3152213234Sjfv * e1000_phy_hw_reset_ich8lan - Performs a PHY reset 3153213234Sjfv * @hw: pointer to the HW structure 3154213234Sjfv * 3155213234Sjfv * Resets the PHY 3156213234Sjfv * This is a function pointer entry point called by drivers 3157213234Sjfv * or other shared routines. 3158213234Sjfv **/ 3159213234Sjfvstatic s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw) 3160213234Sjfv{ 3161213234Sjfv s32 ret_val = E1000_SUCCESS; 3162213234Sjfv 3163213234Sjfv DEBUGFUNC("e1000_phy_hw_reset_ich8lan"); 3164213234Sjfv 3165213234Sjfv /* Gate automatic PHY configuration by hardware on non-managed 82579 */ 3166213234Sjfv if ((hw->mac.type == e1000_pch2lan) && 3167213234Sjfv !(E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID)) 3168213234Sjfv e1000_gate_hw_phy_config_ich8lan(hw, TRUE); 3169213234Sjfv 3170213234Sjfv ret_val = e1000_phy_hw_reset_generic(hw); 3171213234Sjfv if (ret_val) 3172247064Sjfv return ret_val; 3173213234Sjfv 3174247064Sjfv return e1000_post_phy_reset_ich8lan(hw); 3175213234Sjfv} 3176213234Sjfv 3177213234Sjfv/** 3178200243Sjfv * e1000_set_lplu_state_pchlan - Set Low Power Link Up state 3179169589Sjfv * @hw: pointer to the HW structure 3180200243Sjfv * @active: TRUE to enable LPLU, FALSE to disable 3181169240Sjfv * 3182200243Sjfv * Sets the LPLU state according to the active flag. For PCH, if OEM write 3183200243Sjfv * bit are disabled in the NVM, writing the LPLU bits in the MAC will not set 3184200243Sjfv * the phy speed. This function will manually set the LPLU bit and restart 3185200243Sjfv * auto-neg as hw would do. D3 and D0 LPLU will call the same function 3186200243Sjfv * since it configures the same bit. 3187169240Sjfv **/ 3188200243Sjfvstatic s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active) 3189169240Sjfv{ 3190247064Sjfv s32 ret_val; 3191200243Sjfv u16 oem_reg; 3192169240Sjfv 3193200243Sjfv DEBUGFUNC("e1000_set_lplu_state_pchlan"); 3194200243Sjfv ret_val = hw->phy.ops.read_reg(hw, HV_OEM_BITS, &oem_reg); 3195169240Sjfv if (ret_val) 3196247064Sjfv return ret_val; 3197169240Sjfv 3198200243Sjfv if (active) 3199200243Sjfv oem_reg |= HV_OEM_BITS_LPLU; 3200200243Sjfv else 3201200243Sjfv oem_reg &= ~HV_OEM_BITS_LPLU; 3202169240Sjfv 3203228386Sjfv if (!hw->phy.ops.check_reset_block(hw)) 3204228386Sjfv oem_reg |= HV_OEM_BITS_RESTART_AN; 3205228386Sjfv 3206247064Sjfv return hw->phy.ops.write_reg(hw, HV_OEM_BITS, oem_reg); 3207169240Sjfv} 3208169240Sjfv 3209169240Sjfv/** 3210169240Sjfv * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state 3211169589Sjfv * @hw: pointer to the HW structure 3212169589Sjfv * @active: TRUE to enable LPLU, FALSE to disable 3213169240Sjfv * 3214169240Sjfv * Sets the LPLU D0 state according to the active flag. When 3215169240Sjfv * activating LPLU this function also disables smart speed 3216169240Sjfv * and vice versa. LPLU will not be activated unless the 3217169240Sjfv * device autonegotiation advertisement meets standards of 3218169240Sjfv * either 10 or 10/100 or 10/100/1000 at all duplexes. 3219169240Sjfv * This is a function pointer entry point only called by 3220169240Sjfv * PHY setup routines. 3221169240Sjfv **/ 3222185353Sjfvstatic s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active) 3223169240Sjfv{ 3224169240Sjfv struct e1000_phy_info *phy = &hw->phy; 3225169240Sjfv u32 phy_ctrl; 3226169240Sjfv s32 ret_val = E1000_SUCCESS; 3227169240Sjfv u16 data; 3228169240Sjfv 3229169240Sjfv DEBUGFUNC("e1000_set_d0_lplu_state_ich8lan"); 3230169240Sjfv 3231173788Sjfv if (phy->type == e1000_phy_ife) 3232247064Sjfv return E1000_SUCCESS; 3233169240Sjfv 3234169240Sjfv phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL); 3235169240Sjfv 3236169240Sjfv if (active) { 3237169240Sjfv phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU; 3238169240Sjfv E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); 3239169240Sjfv 3240194865Sjfv if (phy->type != e1000_phy_igp_3) 3241247064Sjfv return E1000_SUCCESS; 3242194865Sjfv 3243247064Sjfv /* Call gig speed drop workaround on LPLU before accessing 3244173788Sjfv * any PHY registers 3245173788Sjfv */ 3246194865Sjfv if (hw->mac.type == e1000_ich8lan) 3247169240Sjfv e1000_gig_downshift_workaround_ich8lan(hw); 3248169240Sjfv 3249169240Sjfv /* When LPLU is enabled, we should disable SmartSpeed */ 3250177867Sjfv ret_val = phy->ops.read_reg(hw, 3251228386Sjfv IGP01E1000_PHY_PORT_CONFIG, 3252228386Sjfv &data); 3253247064Sjfv if (ret_val) 3254247064Sjfv return ret_val; 3255169240Sjfv data &= ~IGP01E1000_PSCFR_SMART_SPEED; 3256177867Sjfv ret_val = phy->ops.write_reg(hw, 3257228386Sjfv IGP01E1000_PHY_PORT_CONFIG, 3258228386Sjfv data); 3259169240Sjfv if (ret_val) 3260247064Sjfv return ret_val; 3261169240Sjfv } else { 3262169240Sjfv phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU; 3263169240Sjfv E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); 3264169240Sjfv 3265194865Sjfv if (phy->type != e1000_phy_igp_3) 3266247064Sjfv return E1000_SUCCESS; 3267194865Sjfv 3268247064Sjfv /* LPLU and SmartSpeed are mutually exclusive. LPLU is used 3269169240Sjfv * during Dx states where the power conservation is most 3270169240Sjfv * important. During driver activity we should enable 3271173788Sjfv * SmartSpeed, so performance is maintained. 3272173788Sjfv */ 3273169240Sjfv if (phy->smart_speed == e1000_smart_speed_on) { 3274177867Sjfv ret_val = phy->ops.read_reg(hw, 3275228386Sjfv IGP01E1000_PHY_PORT_CONFIG, 3276228386Sjfv &data); 3277169240Sjfv if (ret_val) 3278247064Sjfv return ret_val; 3279169240Sjfv 3280169240Sjfv data |= IGP01E1000_PSCFR_SMART_SPEED; 3281177867Sjfv ret_val = phy->ops.write_reg(hw, 3282228386Sjfv IGP01E1000_PHY_PORT_CONFIG, 3283228386Sjfv data); 3284169240Sjfv if (ret_val) 3285247064Sjfv return ret_val; 3286169240Sjfv } else if (phy->smart_speed == e1000_smart_speed_off) { 3287177867Sjfv ret_val = phy->ops.read_reg(hw, 3288228386Sjfv IGP01E1000_PHY_PORT_CONFIG, 3289228386Sjfv &data); 3290169240Sjfv if (ret_val) 3291247064Sjfv return ret_val; 3292169240Sjfv 3293169240Sjfv data &= ~IGP01E1000_PSCFR_SMART_SPEED; 3294177867Sjfv ret_val = phy->ops.write_reg(hw, 3295228386Sjfv IGP01E1000_PHY_PORT_CONFIG, 3296228386Sjfv data); 3297169240Sjfv if (ret_val) 3298247064Sjfv return ret_val; 3299169240Sjfv } 3300169240Sjfv } 3301169240Sjfv 3302247064Sjfv return E1000_SUCCESS; 3303169240Sjfv} 3304169240Sjfv 3305169240Sjfv/** 3306169240Sjfv * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state 3307169589Sjfv * @hw: pointer to the HW structure 3308169589Sjfv * @active: TRUE to enable LPLU, FALSE to disable 3309169240Sjfv * 3310169240Sjfv * Sets the LPLU D3 state according to the active flag. When 3311169240Sjfv * activating LPLU this function also disables smart speed 3312169240Sjfv * and vice versa. LPLU will not be activated unless the 3313169240Sjfv * device autonegotiation advertisement meets standards of 3314169240Sjfv * either 10 or 10/100 or 10/100/1000 at all duplexes. 3315169240Sjfv * This is a function pointer entry point only called by 3316169240Sjfv * PHY setup routines. 3317169240Sjfv **/ 3318185353Sjfvstatic s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active) 3319169240Sjfv{ 3320169240Sjfv struct e1000_phy_info *phy = &hw->phy; 3321169240Sjfv u32 phy_ctrl; 3322169240Sjfv s32 ret_val = E1000_SUCCESS; 3323169240Sjfv u16 data; 3324169240Sjfv 3325169240Sjfv DEBUGFUNC("e1000_set_d3_lplu_state_ich8lan"); 3326169240Sjfv 3327169240Sjfv phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL); 3328169240Sjfv 3329169240Sjfv if (!active) { 3330169240Sjfv phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU; 3331169240Sjfv E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); 3332194865Sjfv 3333194865Sjfv if (phy->type != e1000_phy_igp_3) 3334247064Sjfv return E1000_SUCCESS; 3335194865Sjfv 3336247064Sjfv /* LPLU and SmartSpeed are mutually exclusive. LPLU is used 3337169240Sjfv * during Dx states where the power conservation is most 3338169240Sjfv * important. During driver activity we should enable 3339173788Sjfv * SmartSpeed, so performance is maintained. 3340173788Sjfv */ 3341169240Sjfv if (phy->smart_speed == e1000_smart_speed_on) { 3342177867Sjfv ret_val = phy->ops.read_reg(hw, 3343228386Sjfv IGP01E1000_PHY_PORT_CONFIG, 3344228386Sjfv &data); 3345169240Sjfv if (ret_val) 3346247064Sjfv return ret_val; 3347169240Sjfv 3348169240Sjfv data |= IGP01E1000_PSCFR_SMART_SPEED; 3349177867Sjfv ret_val = phy->ops.write_reg(hw, 3350228386Sjfv IGP01E1000_PHY_PORT_CONFIG, 3351228386Sjfv data); 3352169240Sjfv if (ret_val) 3353247064Sjfv return ret_val; 3354169240Sjfv } else if (phy->smart_speed == e1000_smart_speed_off) { 3355177867Sjfv ret_val = phy->ops.read_reg(hw, 3356228386Sjfv IGP01E1000_PHY_PORT_CONFIG, 3357228386Sjfv &data); 3358169240Sjfv if (ret_val) 3359247064Sjfv return ret_val; 3360169240Sjfv 3361169240Sjfv data &= ~IGP01E1000_PSCFR_SMART_SPEED; 3362177867Sjfv ret_val = phy->ops.write_reg(hw, 3363228386Sjfv IGP01E1000_PHY_PORT_CONFIG, 3364228386Sjfv data); 3365169240Sjfv if (ret_val) 3366247064Sjfv return ret_val; 3367169240Sjfv } 3368169240Sjfv } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || 3369228386Sjfv (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || 3370228386Sjfv (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { 3371169240Sjfv phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU; 3372169240Sjfv E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); 3373169240Sjfv 3374194865Sjfv if (phy->type != e1000_phy_igp_3) 3375247064Sjfv return E1000_SUCCESS; 3376194865Sjfv 3377247064Sjfv /* Call gig speed drop workaround on LPLU before accessing 3378173788Sjfv * any PHY registers 3379173788Sjfv */ 3380194865Sjfv if (hw->mac.type == e1000_ich8lan) 3381169240Sjfv e1000_gig_downshift_workaround_ich8lan(hw); 3382169240Sjfv 3383169240Sjfv /* When LPLU is enabled, we should disable SmartSpeed */ 3384177867Sjfv ret_val = phy->ops.read_reg(hw, 3385228386Sjfv IGP01E1000_PHY_PORT_CONFIG, 3386228386Sjfv &data); 3387169240Sjfv if (ret_val) 3388247064Sjfv return ret_val; 3389169240Sjfv 3390169240Sjfv data &= ~IGP01E1000_PSCFR_SMART_SPEED; 3391177867Sjfv ret_val = phy->ops.write_reg(hw, 3392228386Sjfv IGP01E1000_PHY_PORT_CONFIG, 3393228386Sjfv data); 3394169240Sjfv } 3395169240Sjfv 3396169240Sjfv return ret_val; 3397169240Sjfv} 3398169240Sjfv 3399169240Sjfv/** 3400173788Sjfv * e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1 3401173788Sjfv * @hw: pointer to the HW structure 3402173788Sjfv * @bank: pointer to the variable that returns the active bank 3403173788Sjfv * 3404173788Sjfv * Reads signature byte from the NVM using the flash access registers. 3405190872Sjfv * Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank. 3406173788Sjfv **/ 3407177867Sjfvstatic s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank) 3408173788Sjfv{ 3409190872Sjfv u32 eecd; 3410178523Sjfv struct e1000_nvm_info *nvm = &hw->nvm; 3411178523Sjfv u32 bank1_offset = nvm->flash_bank_size * sizeof(u16); 3412178523Sjfv u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1; 3413295323Serj u32 nvm_dword = 0; 3414190872Sjfv u8 sig_byte = 0; 3415247064Sjfv s32 ret_val; 3416178523Sjfv 3417213234Sjfv DEBUGFUNC("e1000_valid_nvm_bank_detect_ich8lan"); 3418213234Sjfv 3419190872Sjfv switch (hw->mac.type) { 3420295323Serj case e1000_pch_spt: 3421333213Smarius case e1000_pch_cnp: 3422295323Serj bank1_offset = nvm->flash_bank_size; 3423295323Serj act_offset = E1000_ICH_NVM_SIG_WORD; 3424295323Serj 3425295323Serj /* set bank to 0 in case flash read fails */ 3426295323Serj *bank = 0; 3427295323Serj 3428295323Serj /* Check bank 0 */ 3429295323Serj ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, 3430295323Serj &nvm_dword); 3431295323Serj if (ret_val) 3432295323Serj return ret_val; 3433295323Serj sig_byte = (u8)((nvm_dword & 0xFF00) >> 8); 3434295323Serj if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == 3435295323Serj E1000_ICH_NVM_SIG_VALUE) { 3436295323Serj *bank = 0; 3437295323Serj return E1000_SUCCESS; 3438295323Serj } 3439295323Serj 3440295323Serj /* Check bank 1 */ 3441295323Serj ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset + 3442295323Serj bank1_offset, 3443295323Serj &nvm_dword); 3444295323Serj if (ret_val) 3445295323Serj return ret_val; 3446295323Serj sig_byte = (u8)((nvm_dword & 0xFF00) >> 8); 3447295323Serj if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == 3448295323Serj E1000_ICH_NVM_SIG_VALUE) { 3449295323Serj *bank = 1; 3450295323Serj return E1000_SUCCESS; 3451295323Serj } 3452295323Serj 3453295323Serj DEBUGOUT("ERROR: No valid NVM bank present\n"); 3454295323Serj return -E1000_ERR_NVM; 3455190872Sjfv case e1000_ich8lan: 3456190872Sjfv case e1000_ich9lan: 3457190872Sjfv eecd = E1000_READ_REG(hw, E1000_EECD); 3458190872Sjfv if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) == 3459190872Sjfv E1000_EECD_SEC1VAL_VALID_MASK) { 3460190872Sjfv if (eecd & E1000_EECD_SEC1VAL) 3461190872Sjfv *bank = 1; 3462190872Sjfv else 3463190872Sjfv *bank = 0; 3464190872Sjfv 3465247064Sjfv return E1000_SUCCESS; 3466190872Sjfv } 3467228386Sjfv DEBUGOUT("Unable to determine valid NVM bank via EEC - reading flash signature\n"); 3468190872Sjfv /* fall-thru */ 3469190872Sjfv default: 3470190872Sjfv /* set bank to 0 in case flash read fails */ 3471190872Sjfv *bank = 0; 3472190872Sjfv 3473190872Sjfv /* Check bank 0 */ 3474190872Sjfv ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset, 3475228386Sjfv &sig_byte); 3476190872Sjfv if (ret_val) 3477247064Sjfv return ret_val; 3478190872Sjfv if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == 3479200243Sjfv E1000_ICH_NVM_SIG_VALUE) { 3480178523Sjfv *bank = 0; 3481247064Sjfv return E1000_SUCCESS; 3482190872Sjfv } 3483185353Sjfv 3484190872Sjfv /* Check bank 1 */ 3485190872Sjfv ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset + 3486228386Sjfv bank1_offset, 3487228386Sjfv &sig_byte); 3488190872Sjfv if (ret_val) 3489247064Sjfv return ret_val; 3490190872Sjfv if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == 3491200243Sjfv E1000_ICH_NVM_SIG_VALUE) { 3492190872Sjfv *bank = 1; 3493247064Sjfv return E1000_SUCCESS; 3494178523Sjfv } 3495190872Sjfv 3496190872Sjfv DEBUGOUT("ERROR: No valid NVM bank present\n"); 3497247064Sjfv return -E1000_ERR_NVM; 3498178523Sjfv } 3499173788Sjfv} 3500173788Sjfv 3501173788Sjfv/** 3502295323Serj * e1000_read_nvm_spt - NVM access for SPT 3503295323Serj * @hw: pointer to the HW structure 3504295323Serj * @offset: The offset (in bytes) of the word(s) to read. 3505295323Serj * @words: Size of data to read in words. 3506295323Serj * @data: pointer to the word(s) to read at offset. 3507295323Serj * 3508295323Serj * Reads a word(s) from the NVM 3509295323Serj **/ 3510295323Serjstatic s32 e1000_read_nvm_spt(struct e1000_hw *hw, u16 offset, u16 words, 3511295323Serj u16 *data) 3512295323Serj{ 3513295323Serj struct e1000_nvm_info *nvm = &hw->nvm; 3514295323Serj struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 3515295323Serj u32 act_offset; 3516295323Serj s32 ret_val = E1000_SUCCESS; 3517295323Serj u32 bank = 0; 3518295323Serj u32 dword = 0; 3519295323Serj u16 offset_to_read; 3520295323Serj u16 i; 3521295323Serj 3522295323Serj DEBUGFUNC("e1000_read_nvm_spt"); 3523295323Serj 3524295323Serj if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || 3525295323Serj (words == 0)) { 3526295323Serj DEBUGOUT("nvm parameter(s) out of bounds\n"); 3527295323Serj ret_val = -E1000_ERR_NVM; 3528295323Serj goto out; 3529295323Serj } 3530295323Serj 3531295323Serj nvm->ops.acquire(hw); 3532295323Serj 3533295323Serj ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); 3534295323Serj if (ret_val != E1000_SUCCESS) { 3535295323Serj DEBUGOUT("Could not detect valid bank, assuming bank 0\n"); 3536295323Serj bank = 0; 3537295323Serj } 3538295323Serj 3539295323Serj act_offset = (bank) ? nvm->flash_bank_size : 0; 3540295323Serj act_offset += offset; 3541295323Serj 3542295323Serj ret_val = E1000_SUCCESS; 3543295323Serj 3544295323Serj for (i = 0; i < words; i += 2) { 3545295323Serj if (words - i == 1) { 3546295323Serj if (dev_spec->shadow_ram[offset+i].modified) { 3547295323Serj data[i] = dev_spec->shadow_ram[offset+i].value; 3548295323Serj } else { 3549295323Serj offset_to_read = act_offset + i - 3550295323Serj ((act_offset + i) % 2); 3551295323Serj ret_val = 3552295323Serj e1000_read_flash_dword_ich8lan(hw, 3553295323Serj offset_to_read, 3554295323Serj &dword); 3555295323Serj if (ret_val) 3556295323Serj break; 3557295323Serj if ((act_offset + i) % 2 == 0) 3558295323Serj data[i] = (u16)(dword & 0xFFFF); 3559295323Serj else 3560295323Serj data[i] = (u16)((dword >> 16) & 0xFFFF); 3561295323Serj } 3562295323Serj } else { 3563295323Serj offset_to_read = act_offset + i; 3564295323Serj if (!(dev_spec->shadow_ram[offset+i].modified) || 3565295323Serj !(dev_spec->shadow_ram[offset+i+1].modified)) { 3566295323Serj ret_val = 3567295323Serj e1000_read_flash_dword_ich8lan(hw, 3568295323Serj offset_to_read, 3569295323Serj &dword); 3570295323Serj if (ret_val) 3571295323Serj break; 3572295323Serj } 3573295323Serj if (dev_spec->shadow_ram[offset+i].modified) 3574295323Serj data[i] = dev_spec->shadow_ram[offset+i].value; 3575295323Serj else 3576295323Serj data[i] = (u16) (dword & 0xFFFF); 3577295323Serj if (dev_spec->shadow_ram[offset+i].modified) 3578295323Serj data[i+1] = 3579295323Serj dev_spec->shadow_ram[offset+i+1].value; 3580295323Serj else 3581295323Serj data[i+1] = (u16) (dword >> 16 & 0xFFFF); 3582295323Serj } 3583295323Serj } 3584295323Serj 3585295323Serj nvm->ops.release(hw); 3586295323Serj 3587295323Serjout: 3588295323Serj if (ret_val) 3589295323Serj DEBUGOUT1("NVM read error: %d\n", ret_val); 3590295323Serj 3591295323Serj return ret_val; 3592295323Serj} 3593295323Serj 3594295323Serj/** 3595169240Sjfv * e1000_read_nvm_ich8lan - Read word(s) from the NVM 3596169589Sjfv * @hw: pointer to the HW structure 3597169589Sjfv * @offset: The offset (in bytes) of the word(s) to read. 3598169589Sjfv * @words: Size of data to read in words 3599169589Sjfv * @data: Pointer to the word(s) to read at offset. 3600169240Sjfv * 3601169240Sjfv * Reads a word(s) from the NVM using the flash access registers. 3602169240Sjfv **/ 3603177867Sjfvstatic s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words, 3604228386Sjfv u16 *data) 3605169240Sjfv{ 3606169240Sjfv struct e1000_nvm_info *nvm = &hw->nvm; 3607185353Sjfv struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 3608169240Sjfv u32 act_offset; 3609169240Sjfv s32 ret_val = E1000_SUCCESS; 3610173788Sjfv u32 bank = 0; 3611169240Sjfv u16 i, word; 3612169240Sjfv 3613169240Sjfv DEBUGFUNC("e1000_read_nvm_ich8lan"); 3614169240Sjfv 3615169240Sjfv if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || 3616169240Sjfv (words == 0)) { 3617169240Sjfv DEBUGOUT("nvm parameter(s) out of bounds\n"); 3618169240Sjfv ret_val = -E1000_ERR_NVM; 3619169240Sjfv goto out; 3620169240Sjfv } 3621169240Sjfv 3622200243Sjfv nvm->ops.acquire(hw); 3623169240Sjfv 3624173788Sjfv ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); 3625200243Sjfv if (ret_val != E1000_SUCCESS) { 3626200243Sjfv DEBUGOUT("Could not detect valid bank, assuming bank 0\n"); 3627200243Sjfv bank = 0; 3628200243Sjfv } 3629173788Sjfv 3630173788Sjfv act_offset = (bank) ? nvm->flash_bank_size : 0; 3631169240Sjfv act_offset += offset; 3632169240Sjfv 3633200243Sjfv ret_val = E1000_SUCCESS; 3634169240Sjfv for (i = 0; i < words; i++) { 3635228386Sjfv if (dev_spec->shadow_ram[offset+i].modified) { 3636169240Sjfv data[i] = dev_spec->shadow_ram[offset+i].value; 3637169240Sjfv } else { 3638169240Sjfv ret_val = e1000_read_flash_word_ich8lan(hw, 3639228386Sjfv act_offset + i, 3640228386Sjfv &word); 3641169240Sjfv if (ret_val) 3642169240Sjfv break; 3643169240Sjfv data[i] = word; 3644169240Sjfv } 3645169240Sjfv } 3646169240Sjfv 3647177867Sjfv nvm->ops.release(hw); 3648169240Sjfv 3649169240Sjfvout: 3650190872Sjfv if (ret_val) 3651190872Sjfv DEBUGOUT1("NVM read error: %d\n", ret_val); 3652190872Sjfv 3653169240Sjfv return ret_val; 3654169240Sjfv} 3655169240Sjfv 3656169240Sjfv/** 3657169240Sjfv * e1000_flash_cycle_init_ich8lan - Initialize flash 3658169589Sjfv * @hw: pointer to the HW structure 3659169240Sjfv * 3660169240Sjfv * This function does initial flash setup so that a new read/write/erase cycle 3661169240Sjfv * can be started. 3662169240Sjfv **/ 3663173788Sjfvstatic s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw) 3664169240Sjfv{ 3665169240Sjfv union ich8_hws_flash_status hsfsts; 3666169240Sjfv s32 ret_val = -E1000_ERR_NVM; 3667169240Sjfv 3668169240Sjfv DEBUGFUNC("e1000_flash_cycle_init_ich8lan"); 3669169240Sjfv 3670169240Sjfv hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS); 3671169240Sjfv 3672169240Sjfv /* Check if the flash descriptor is valid */ 3673247064Sjfv if (!hsfsts.hsf_status.fldesvalid) { 3674228386Sjfv DEBUGOUT("Flash descriptor invalid. SW Sequencing must be used.\n"); 3675247064Sjfv return -E1000_ERR_NVM; 3676169240Sjfv } 3677169240Sjfv 3678169240Sjfv /* Clear FCERR and DAEL in hw status by writing 1 */ 3679169240Sjfv hsfsts.hsf_status.flcerr = 1; 3680169240Sjfv hsfsts.hsf_status.dael = 1; 3681322955Smarius if (hw->mac.type >= e1000_pch_spt) 3682295323Serj E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS, 3683295323Serj hsfsts.regval & 0xFFFF); 3684295323Serj else 3685295323Serj E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval); 3686169240Sjfv 3687247064Sjfv /* Either we should have a hardware SPI cycle in progress 3688169240Sjfv * bit to check against, in order to start a new cycle or 3689169240Sjfv * FDONE bit should be changed in the hardware so that it 3690176667Sjfv * is 1 after hardware reset, which can then be used as an 3691169240Sjfv * indication whether a cycle is in progress or has been 3692169240Sjfv * completed. 3693169240Sjfv */ 3694169240Sjfv 3695247064Sjfv if (!hsfsts.hsf_status.flcinprog) { 3696247064Sjfv /* There is no cycle running at present, 3697173788Sjfv * so we can start a cycle. 3698173788Sjfv * Begin by setting Flash Cycle Done. 3699173788Sjfv */ 3700169240Sjfv hsfsts.hsf_status.flcdone = 1; 3701322955Smarius if (hw->mac.type >= e1000_pch_spt) 3702295323Serj E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS, 3703295323Serj hsfsts.regval & 0xFFFF); 3704295323Serj else 3705295323Serj E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, 3706295323Serj hsfsts.regval); 3707169240Sjfv ret_val = E1000_SUCCESS; 3708169240Sjfv } else { 3709218588Sjfv s32 i; 3710218588Sjfv 3711247064Sjfv /* Otherwise poll for sometime so the current 3712173788Sjfv * cycle has a chance to end before giving up. 3713173788Sjfv */ 3714169240Sjfv for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) { 3715169240Sjfv hsfsts.regval = E1000_READ_FLASH_REG16(hw, 3716228386Sjfv ICH_FLASH_HSFSTS); 3717247064Sjfv if (!hsfsts.hsf_status.flcinprog) { 3718169240Sjfv ret_val = E1000_SUCCESS; 3719169240Sjfv break; 3720169240Sjfv } 3721169240Sjfv usec_delay(1); 3722169240Sjfv } 3723169240Sjfv if (ret_val == E1000_SUCCESS) { 3724247064Sjfv /* Successful in waiting for previous cycle to timeout, 3725173788Sjfv * now set the Flash Cycle Done. 3726173788Sjfv */ 3727169240Sjfv hsfsts.hsf_status.flcdone = 1; 3728322955Smarius if (hw->mac.type >= e1000_pch_spt) 3729295323Serj E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS, 3730295323Serj hsfsts.regval & 0xFFFF); 3731295323Serj else 3732295323Serj E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, 3733295323Serj hsfsts.regval); 3734169240Sjfv } else { 3735228386Sjfv DEBUGOUT("Flash controller busy, cannot get access\n"); 3736169240Sjfv } 3737169240Sjfv } 3738169240Sjfv 3739169240Sjfv return ret_val; 3740169240Sjfv} 3741169240Sjfv 3742169240Sjfv/** 3743169240Sjfv * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase) 3744169589Sjfv * @hw: pointer to the HW structure 3745169589Sjfv * @timeout: maximum time to wait for completion 3746169240Sjfv * 3747169240Sjfv * This function starts a flash cycle and waits for its completion. 3748169240Sjfv **/ 3749173788Sjfvstatic s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout) 3750169240Sjfv{ 3751169240Sjfv union ich8_hws_flash_ctrl hsflctl; 3752169240Sjfv union ich8_hws_flash_status hsfsts; 3753169240Sjfv u32 i = 0; 3754169240Sjfv 3755169240Sjfv DEBUGFUNC("e1000_flash_cycle_ich8lan"); 3756169240Sjfv 3757169240Sjfv /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */ 3758322955Smarius if (hw->mac.type >= e1000_pch_spt) 3759295323Serj hsflctl.regval = E1000_READ_FLASH_REG(hw, ICH_FLASH_HSFSTS)>>16; 3760295323Serj else 3761295323Serj hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL); 3762169240Sjfv hsflctl.hsf_ctrl.flcgo = 1; 3763267935Sjfv 3764322955Smarius if (hw->mac.type >= e1000_pch_spt) 3765295323Serj E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS, 3766295323Serj hsflctl.regval << 16); 3767295323Serj else 3768295323Serj E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval); 3769169240Sjfv 3770169240Sjfv /* wait till FDONE bit is set to 1 */ 3771169240Sjfv do { 3772169240Sjfv hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS); 3773247064Sjfv if (hsfsts.hsf_status.flcdone) 3774169240Sjfv break; 3775169240Sjfv usec_delay(1); 3776169240Sjfv } while (i++ < timeout); 3777169240Sjfv 3778247064Sjfv if (hsfsts.hsf_status.flcdone && !hsfsts.hsf_status.flcerr) 3779247064Sjfv return E1000_SUCCESS; 3780169240Sjfv 3781247064Sjfv return -E1000_ERR_NVM; 3782169240Sjfv} 3783169240Sjfv 3784169240Sjfv/** 3785295323Serj * e1000_read_flash_dword_ich8lan - Read dword from flash 3786295323Serj * @hw: pointer to the HW structure 3787295323Serj * @offset: offset to data location 3788295323Serj * @data: pointer to the location for storing the data 3789295323Serj * 3790295323Serj * Reads the flash dword at offset into data. Offset is converted 3791295323Serj * to bytes before read. 3792295323Serj **/ 3793295323Serjstatic s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw, u32 offset, 3794295323Serj u32 *data) 3795295323Serj{ 3796295323Serj DEBUGFUNC("e1000_read_flash_dword_ich8lan"); 3797295323Serj 3798295323Serj if (!data) 3799295323Serj return -E1000_ERR_NVM; 3800295323Serj 3801295323Serj /* Must convert word offset into bytes. */ 3802295323Serj offset <<= 1; 3803295323Serj 3804295323Serj return e1000_read_flash_data32_ich8lan(hw, offset, data); 3805295323Serj} 3806295323Serj 3807295323Serj/** 3808169240Sjfv * e1000_read_flash_word_ich8lan - Read word from flash 3809169589Sjfv * @hw: pointer to the HW structure 3810169589Sjfv * @offset: offset to data location 3811169589Sjfv * @data: pointer to the location for storing the data 3812169240Sjfv * 3813169240Sjfv * Reads the flash word at offset into data. Offset is converted 3814169240Sjfv * to bytes before read. 3815169240Sjfv **/ 3816177867Sjfvstatic s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset, 3817228386Sjfv u16 *data) 3818169240Sjfv{ 3819169240Sjfv DEBUGFUNC("e1000_read_flash_word_ich8lan"); 3820169240Sjfv 3821247064Sjfv if (!data) 3822247064Sjfv return -E1000_ERR_NVM; 3823169240Sjfv 3824169240Sjfv /* Must convert offset into bytes. */ 3825169240Sjfv offset <<= 1; 3826169240Sjfv 3827247064Sjfv return e1000_read_flash_data_ich8lan(hw, offset, 2, data); 3828169240Sjfv} 3829169240Sjfv 3830169240Sjfv/** 3831178523Sjfv * e1000_read_flash_byte_ich8lan - Read byte from flash 3832178523Sjfv * @hw: pointer to the HW structure 3833178523Sjfv * @offset: The offset of the byte to read. 3834178523Sjfv * @data: Pointer to a byte to store the value read. 3835178523Sjfv * 3836178523Sjfv * Reads a single byte from the NVM using the flash access registers. 3837178523Sjfv **/ 3838178523Sjfvstatic s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, 3839228386Sjfv u8 *data) 3840178523Sjfv{ 3841247064Sjfv s32 ret_val; 3842178523Sjfv u16 word = 0; 3843178523Sjfv 3844295323Serj /* In SPT, only 32 bits access is supported, 3845295323Serj * so this function should not be called. 3846295323Serj */ 3847322955Smarius if (hw->mac.type >= e1000_pch_spt) 3848295323Serj return -E1000_ERR_NVM; 3849295323Serj else 3850295323Serj ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word); 3851267935Sjfv 3852178523Sjfv if (ret_val) 3853247064Sjfv return ret_val; 3854178523Sjfv 3855178523Sjfv *data = (u8)word; 3856178523Sjfv 3857247064Sjfv return E1000_SUCCESS; 3858178523Sjfv} 3859178523Sjfv 3860178523Sjfv/** 3861169240Sjfv * e1000_read_flash_data_ich8lan - Read byte or word from NVM 3862169589Sjfv * @hw: pointer to the HW structure 3863169589Sjfv * @offset: The offset (in bytes) of the byte or word to read. 3864169589Sjfv * @size: Size of data to read, 1=byte 2=word 3865169589Sjfv * @data: Pointer to the word to store the value read. 3866169240Sjfv * 3867169240Sjfv * Reads a byte or word from the NVM using the flash access registers. 3868169240Sjfv **/ 3869173788Sjfvstatic s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, 3870228386Sjfv u8 size, u16 *data) 3871169240Sjfv{ 3872169240Sjfv union ich8_hws_flash_status hsfsts; 3873169240Sjfv union ich8_hws_flash_ctrl hsflctl; 3874169240Sjfv u32 flash_linear_addr; 3875169240Sjfv u32 flash_data = 0; 3876169240Sjfv s32 ret_val = -E1000_ERR_NVM; 3877169240Sjfv u8 count = 0; 3878169240Sjfv 3879169240Sjfv DEBUGFUNC("e1000_read_flash_data_ich8lan"); 3880169240Sjfv 3881256200Sjfv if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK) 3882247064Sjfv return -E1000_ERR_NVM; 3883256200Sjfv flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) + 3884256200Sjfv hw->nvm.flash_base_addr); 3885169240Sjfv 3886169240Sjfv do { 3887169240Sjfv usec_delay(1); 3888169240Sjfv /* Steps */ 3889169240Sjfv ret_val = e1000_flash_cycle_init_ich8lan(hw); 3890169240Sjfv if (ret_val != E1000_SUCCESS) 3891169240Sjfv break; 3892267935Sjfv hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL); 3893169240Sjfv 3894169240Sjfv /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ 3895169240Sjfv hsflctl.hsf_ctrl.fldbcount = size - 1; 3896169240Sjfv hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ; 3897169240Sjfv E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval); 3898169240Sjfv E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr); 3899169240Sjfv 3900267935Sjfv ret_val = e1000_flash_cycle_ich8lan(hw, 3901267935Sjfv ICH_FLASH_READ_COMMAND_TIMEOUT); 3902169240Sjfv 3903247064Sjfv /* Check if FCERR is set to 1, if set to 1, clear it 3904169240Sjfv * and try the whole sequence a few more times, else 3905169240Sjfv * read in (shift in) the Flash Data0, the order is 3906173788Sjfv * least significant byte first msb to lsb 3907173788Sjfv */ 3908169240Sjfv if (ret_val == E1000_SUCCESS) { 3909169240Sjfv flash_data = E1000_READ_FLASH_REG(hw, ICH_FLASH_FDATA0); 3910185353Sjfv if (size == 1) 3911169240Sjfv *data = (u8)(flash_data & 0x000000FF); 3912185353Sjfv else if (size == 2) 3913169240Sjfv *data = (u16)(flash_data & 0x0000FFFF); 3914169240Sjfv break; 3915169240Sjfv } else { 3916247064Sjfv /* If we've gotten here, then things are probably 3917169240Sjfv * completely hosed, but if the error condition is 3918169240Sjfv * detected, it won't hurt to give it another try... 3919169240Sjfv * ICH_FLASH_CYCLE_REPEAT_COUNT times. 3920169240Sjfv */ 3921169240Sjfv hsfsts.regval = E1000_READ_FLASH_REG16(hw, 3922228386Sjfv ICH_FLASH_HSFSTS); 3923247064Sjfv if (hsfsts.hsf_status.flcerr) { 3924169240Sjfv /* Repeat for some time before giving up. */ 3925169240Sjfv continue; 3926247064Sjfv } else if (!hsfsts.hsf_status.flcdone) { 3927228386Sjfv DEBUGOUT("Timeout error - flash cycle did not complete.\n"); 3928169240Sjfv break; 3929169240Sjfv } 3930169240Sjfv } 3931169240Sjfv } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 3932169240Sjfv 3933169240Sjfv return ret_val; 3934169240Sjfv} 3935169240Sjfv 3936295323Serj/** 3937295323Serj * e1000_read_flash_data32_ich8lan - Read dword from NVM 3938295323Serj * @hw: pointer to the HW structure 3939295323Serj * @offset: The offset (in bytes) of the dword to read. 3940295323Serj * @data: Pointer to the dword to store the value read. 3941295323Serj * 3942295323Serj * Reads a byte or word from the NVM using the flash access registers. 3943295323Serj **/ 3944295323Serjstatic s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset, 3945295323Serj u32 *data) 3946295323Serj{ 3947295323Serj union ich8_hws_flash_status hsfsts; 3948295323Serj union ich8_hws_flash_ctrl hsflctl; 3949295323Serj u32 flash_linear_addr; 3950295323Serj s32 ret_val = -E1000_ERR_NVM; 3951295323Serj u8 count = 0; 3952267935Sjfv 3953295323Serj DEBUGFUNC("e1000_read_flash_data_ich8lan"); 3954295323Serj 3955295323Serj if (offset > ICH_FLASH_LINEAR_ADDR_MASK || 3956322955Smarius hw->mac.type < e1000_pch_spt) 3957295323Serj return -E1000_ERR_NVM; 3958295323Serj flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) + 3959295323Serj hw->nvm.flash_base_addr); 3960295323Serj 3961295323Serj do { 3962295323Serj usec_delay(1); 3963295323Serj /* Steps */ 3964295323Serj ret_val = e1000_flash_cycle_init_ich8lan(hw); 3965295323Serj if (ret_val != E1000_SUCCESS) 3966295323Serj break; 3967295323Serj /* In SPT, This register is in Lan memory space, not flash. 3968295323Serj * Therefore, only 32 bit access is supported 3969295323Serj */ 3970295323Serj hsflctl.regval = E1000_READ_FLASH_REG(hw, ICH_FLASH_HSFSTS)>>16; 3971295323Serj 3972295323Serj /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ 3973295323Serj hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1; 3974295323Serj hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ; 3975295323Serj /* In SPT, This register is in Lan memory space, not flash. 3976295323Serj * Therefore, only 32 bit access is supported 3977295323Serj */ 3978295323Serj E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS, 3979295323Serj (u32)hsflctl.regval << 16); 3980295323Serj E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr); 3981295323Serj 3982295323Serj ret_val = e1000_flash_cycle_ich8lan(hw, 3983295323Serj ICH_FLASH_READ_COMMAND_TIMEOUT); 3984295323Serj 3985295323Serj /* Check if FCERR is set to 1, if set to 1, clear it 3986295323Serj * and try the whole sequence a few more times, else 3987295323Serj * read in (shift in) the Flash Data0, the order is 3988295323Serj * least significant byte first msb to lsb 3989295323Serj */ 3990295323Serj if (ret_val == E1000_SUCCESS) { 3991295323Serj *data = E1000_READ_FLASH_REG(hw, ICH_FLASH_FDATA0); 3992295323Serj break; 3993295323Serj } else { 3994295323Serj /* If we've gotten here, then things are probably 3995295323Serj * completely hosed, but if the error condition is 3996295323Serj * detected, it won't hurt to give it another try... 3997295323Serj * ICH_FLASH_CYCLE_REPEAT_COUNT times. 3998295323Serj */ 3999295323Serj hsfsts.regval = E1000_READ_FLASH_REG16(hw, 4000295323Serj ICH_FLASH_HSFSTS); 4001295323Serj if (hsfsts.hsf_status.flcerr) { 4002295323Serj /* Repeat for some time before giving up. */ 4003295323Serj continue; 4004295323Serj } else if (!hsfsts.hsf_status.flcdone) { 4005295323Serj DEBUGOUT("Timeout error - flash cycle did not complete.\n"); 4006295323Serj break; 4007295323Serj } 4008295323Serj } 4009295323Serj } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 4010295323Serj 4011295323Serj return ret_val; 4012295323Serj} 4013295323Serj 4014169240Sjfv/** 4015169240Sjfv * e1000_write_nvm_ich8lan - Write word(s) to the NVM 4016169589Sjfv * @hw: pointer to the HW structure 4017169589Sjfv * @offset: The offset (in bytes) of the word(s) to write. 4018169589Sjfv * @words: Size of data to write in words 4019169589Sjfv * @data: Pointer to the word(s) to write at offset. 4020169240Sjfv * 4021169240Sjfv * Writes a byte or word to the NVM using the flash access registers. 4022169240Sjfv **/ 4023177867Sjfvstatic s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words, 4024228386Sjfv u16 *data) 4025169240Sjfv{ 4026169240Sjfv struct e1000_nvm_info *nvm = &hw->nvm; 4027185353Sjfv struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 4028169240Sjfv u16 i; 4029169240Sjfv 4030169240Sjfv DEBUGFUNC("e1000_write_nvm_ich8lan"); 4031169240Sjfv 4032169240Sjfv if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || 4033169240Sjfv (words == 0)) { 4034169240Sjfv DEBUGOUT("nvm parameter(s) out of bounds\n"); 4035247064Sjfv return -E1000_ERR_NVM; 4036169240Sjfv } 4037169240Sjfv 4038200243Sjfv nvm->ops.acquire(hw); 4039169240Sjfv 4040169240Sjfv for (i = 0; i < words; i++) { 4041169240Sjfv dev_spec->shadow_ram[offset+i].modified = TRUE; 4042169240Sjfv dev_spec->shadow_ram[offset+i].value = data[i]; 4043169240Sjfv } 4044169240Sjfv 4045177867Sjfv nvm->ops.release(hw); 4046169240Sjfv 4047247064Sjfv return E1000_SUCCESS; 4048169240Sjfv} 4049169240Sjfv 4050169240Sjfv/** 4051295323Serj * e1000_update_nvm_checksum_spt - Update the checksum for NVM 4052295323Serj * @hw: pointer to the HW structure 4053295323Serj * 4054295323Serj * The NVM checksum is updated by calling the generic update_nvm_checksum, 4055295323Serj * which writes the checksum to the shadow ram. The changes in the shadow 4056295323Serj * ram are then committed to the EEPROM by processing each bank at a time 4057295323Serj * checking for the modified bit and writing only the pending changes. 4058295323Serj * After a successful commit, the shadow ram is cleared and is ready for 4059295323Serj * future writes. 4060295323Serj **/ 4061295323Serjstatic s32 e1000_update_nvm_checksum_spt(struct e1000_hw *hw) 4062295323Serj{ 4063295323Serj struct e1000_nvm_info *nvm = &hw->nvm; 4064295323Serj struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 4065295323Serj u32 i, act_offset, new_bank_offset, old_bank_offset, bank; 4066295323Serj s32 ret_val; 4067295323Serj u32 dword = 0; 4068295323Serj 4069295323Serj DEBUGFUNC("e1000_update_nvm_checksum_spt"); 4070295323Serj 4071295323Serj ret_val = e1000_update_nvm_checksum_generic(hw); 4072295323Serj if (ret_val) 4073295323Serj goto out; 4074295323Serj 4075295323Serj if (nvm->type != e1000_nvm_flash_sw) 4076295323Serj goto out; 4077295323Serj 4078295323Serj nvm->ops.acquire(hw); 4079295323Serj 4080295323Serj /* We're writing to the opposite bank so if we're on bank 1, 4081295323Serj * write to bank 0 etc. We also need to erase the segment that 4082295323Serj * is going to be written 4083295323Serj */ 4084295323Serj ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); 4085295323Serj if (ret_val != E1000_SUCCESS) { 4086295323Serj DEBUGOUT("Could not detect valid bank, assuming bank 0\n"); 4087295323Serj bank = 0; 4088295323Serj } 4089295323Serj 4090295323Serj if (bank == 0) { 4091295323Serj new_bank_offset = nvm->flash_bank_size; 4092295323Serj old_bank_offset = 0; 4093295323Serj ret_val = e1000_erase_flash_bank_ich8lan(hw, 1); 4094295323Serj if (ret_val) 4095295323Serj goto release; 4096295323Serj } else { 4097295323Serj old_bank_offset = nvm->flash_bank_size; 4098295323Serj new_bank_offset = 0; 4099295323Serj ret_val = e1000_erase_flash_bank_ich8lan(hw, 0); 4100295323Serj if (ret_val) 4101295323Serj goto release; 4102295323Serj } 4103295323Serj for (i = 0; i < E1000_SHADOW_RAM_WORDS; i += 2) { 4104295323Serj /* Determine whether to write the value stored 4105295323Serj * in the other NVM bank or a modified value stored 4106295323Serj * in the shadow RAM 4107295323Serj */ 4108295323Serj ret_val = e1000_read_flash_dword_ich8lan(hw, 4109295323Serj i + old_bank_offset, 4110295323Serj &dword); 4111295323Serj 4112295323Serj if (dev_spec->shadow_ram[i].modified) { 4113295323Serj dword &= 0xffff0000; 4114295323Serj dword |= (dev_spec->shadow_ram[i].value & 0xffff); 4115295323Serj } 4116295323Serj if (dev_spec->shadow_ram[i + 1].modified) { 4117295323Serj dword &= 0x0000ffff; 4118295323Serj dword |= ((dev_spec->shadow_ram[i + 1].value & 0xffff) 4119295323Serj << 16); 4120295323Serj } 4121295323Serj if (ret_val) 4122295323Serj break; 4123295323Serj 4124295323Serj /* If the word is 0x13, then make sure the signature bits 4125295323Serj * (15:14) are 11b until the commit has completed. 4126295323Serj * This will allow us to write 10b which indicates the 4127295323Serj * signature is valid. We want to do this after the write 4128295323Serj * has completed so that we don't mark the segment valid 4129295323Serj * while the write is still in progress 4130295323Serj */ 4131295323Serj if (i == E1000_ICH_NVM_SIG_WORD - 1) 4132295323Serj dword |= E1000_ICH_NVM_SIG_MASK << 16; 4133295323Serj 4134295323Serj /* Convert offset to bytes. */ 4135295323Serj act_offset = (i + new_bank_offset) << 1; 4136295323Serj 4137295323Serj usec_delay(100); 4138295323Serj 4139295323Serj /* Write the data to the new bank. Offset in words*/ 4140295323Serj act_offset = i + new_bank_offset; 4141295323Serj ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, 4142295323Serj dword); 4143295323Serj if (ret_val) 4144295323Serj break; 4145295323Serj } 4146295323Serj 4147295323Serj /* Don't bother writing the segment valid bits if sector 4148295323Serj * programming failed. 4149295323Serj */ 4150295323Serj if (ret_val) { 4151295323Serj DEBUGOUT("Flash commit failed.\n"); 4152295323Serj goto release; 4153295323Serj } 4154295323Serj 4155295323Serj /* Finally validate the new segment by setting bit 15:14 4156295323Serj * to 10b in word 0x13 , this can be done without an 4157295323Serj * erase as well since these bits are 11 to start with 4158295323Serj * and we need to change bit 14 to 0b 4159295323Serj */ 4160295323Serj act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD; 4161295323Serj 4162295323Serj /*offset in words but we read dword*/ 4163295323Serj --act_offset; 4164295323Serj ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword); 4165295323Serj 4166295323Serj if (ret_val) 4167295323Serj goto release; 4168295323Serj 4169295323Serj dword &= 0xBFFFFFFF; 4170295323Serj ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword); 4171295323Serj 4172295323Serj if (ret_val) 4173295323Serj goto release; 4174295323Serj 4175295323Serj /* And invalidate the previously valid segment by setting 4176295323Serj * its signature word (0x13) high_byte to 0b. This can be 4177295323Serj * done without an erase because flash erase sets all bits 4178295323Serj * to 1's. We can write 1's to 0's without an erase 4179295323Serj */ 4180295323Serj act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1; 4181295323Serj 4182295323Serj /* offset in words but we read dword*/ 4183295323Serj act_offset = old_bank_offset + E1000_ICH_NVM_SIG_WORD - 1; 4184295323Serj ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword); 4185295323Serj 4186295323Serj if (ret_val) 4187295323Serj goto release; 4188295323Serj 4189295323Serj dword &= 0x00FFFFFF; 4190295323Serj ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword); 4191295323Serj 4192295323Serj if (ret_val) 4193295323Serj goto release; 4194295323Serj 4195295323Serj /* Great! Everything worked, we can now clear the cached entries. */ 4196295323Serj for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { 4197295323Serj dev_spec->shadow_ram[i].modified = FALSE; 4198295323Serj dev_spec->shadow_ram[i].value = 0xFFFF; 4199295323Serj } 4200295323Serj 4201295323Serjrelease: 4202295323Serj nvm->ops.release(hw); 4203295323Serj 4204295323Serj /* Reload the EEPROM, or else modifications will not appear 4205295323Serj * until after the next adapter reset. 4206295323Serj */ 4207295323Serj if (!ret_val) { 4208295323Serj nvm->ops.reload(hw); 4209295323Serj msec_delay(10); 4210295323Serj } 4211295323Serj 4212295323Serjout: 4213295323Serj if (ret_val) 4214295323Serj DEBUGOUT1("NVM update error: %d\n", ret_val); 4215295323Serj 4216295323Serj return ret_val; 4217295323Serj} 4218295323Serj 4219295323Serj/** 4220169240Sjfv * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM 4221169589Sjfv * @hw: pointer to the HW structure 4222169240Sjfv * 4223169240Sjfv * The NVM checksum is updated by calling the generic update_nvm_checksum, 4224169240Sjfv * which writes the checksum to the shadow ram. The changes in the shadow 4225169240Sjfv * ram are then committed to the EEPROM by processing each bank at a time 4226169240Sjfv * checking for the modified bit and writing only the pending changes. 4227176667Sjfv * After a successful commit, the shadow ram is cleared and is ready for 4228169240Sjfv * future writes. 4229169240Sjfv **/ 4230177867Sjfvstatic s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw) 4231169240Sjfv{ 4232169240Sjfv struct e1000_nvm_info *nvm = &hw->nvm; 4233185353Sjfv struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 4234173788Sjfv u32 i, act_offset, new_bank_offset, old_bank_offset, bank; 4235169240Sjfv s32 ret_val; 4236267935Sjfv u16 data = 0; 4237169240Sjfv 4238169240Sjfv DEBUGFUNC("e1000_update_nvm_checksum_ich8lan"); 4239169240Sjfv 4240169240Sjfv ret_val = e1000_update_nvm_checksum_generic(hw); 4241169240Sjfv if (ret_val) 4242169240Sjfv goto out; 4243169240Sjfv 4244169240Sjfv if (nvm->type != e1000_nvm_flash_sw) 4245169240Sjfv goto out; 4246169240Sjfv 4247200243Sjfv nvm->ops.acquire(hw); 4248169240Sjfv 4249247064Sjfv /* We're writing to the opposite bank so if we're on bank 1, 4250169240Sjfv * write to bank 0 etc. We also need to erase the segment that 4251173788Sjfv * is going to be written 4252173788Sjfv */ 4253173788Sjfv ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); 4254190872Sjfv if (ret_val != E1000_SUCCESS) { 4255200243Sjfv DEBUGOUT("Could not detect valid bank, assuming bank 0\n"); 4256200243Sjfv bank = 0; 4257190872Sjfv } 4258173788Sjfv 4259173788Sjfv if (bank == 0) { 4260169240Sjfv new_bank_offset = nvm->flash_bank_size; 4261169240Sjfv old_bank_offset = 0; 4262190872Sjfv ret_val = e1000_erase_flash_bank_ich8lan(hw, 1); 4263203049Sjfv if (ret_val) 4264203049Sjfv goto release; 4265169240Sjfv } else { 4266169240Sjfv old_bank_offset = nvm->flash_bank_size; 4267169240Sjfv new_bank_offset = 0; 4268190872Sjfv ret_val = e1000_erase_flash_bank_ich8lan(hw, 0); 4269203049Sjfv if (ret_val) 4270203049Sjfv goto release; 4271169240Sjfv } 4272169240Sjfv for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { 4273173788Sjfv if (dev_spec->shadow_ram[i].modified) { 4274169240Sjfv data = dev_spec->shadow_ram[i].value; 4275169240Sjfv } else { 4276190872Sjfv ret_val = e1000_read_flash_word_ich8lan(hw, i + 4277228386Sjfv old_bank_offset, 4278228386Sjfv &data); 4279190872Sjfv if (ret_val) 4280190872Sjfv break; 4281169240Sjfv } 4282247064Sjfv /* If the word is 0x13, then make sure the signature bits 4283169240Sjfv * (15:14) are 11b until the commit has completed. 4284169240Sjfv * This will allow us to write 10b which indicates the 4285169240Sjfv * signature is valid. We want to do this after the write 4286169240Sjfv * has completed so that we don't mark the segment valid 4287173788Sjfv * while the write is still in progress 4288173788Sjfv */ 4289169240Sjfv if (i == E1000_ICH_NVM_SIG_WORD) 4290169240Sjfv data |= E1000_ICH_NVM_SIG_MASK; 4291169240Sjfv 4292169240Sjfv /* Convert offset to bytes. */ 4293169240Sjfv act_offset = (i + new_bank_offset) << 1; 4294169240Sjfv 4295169240Sjfv usec_delay(100); 4296267935Sjfv 4297169240Sjfv /* Write the bytes to the new bank. */ 4298169240Sjfv ret_val = e1000_retry_write_flash_byte_ich8lan(hw, 4299228386Sjfv act_offset, 4300228386Sjfv (u8)data); 4301169240Sjfv if (ret_val) 4302169240Sjfv break; 4303169240Sjfv 4304169240Sjfv usec_delay(100); 4305169240Sjfv ret_val = e1000_retry_write_flash_byte_ich8lan(hw, 4306228386Sjfv act_offset + 1, 4307228386Sjfv (u8)(data >> 8)); 4308169240Sjfv if (ret_val) 4309169240Sjfv break; 4310267935Sjfv } 4311169240Sjfv 4312247064Sjfv /* Don't bother writing the segment valid bits if sector 4313173788Sjfv * programming failed. 4314173788Sjfv */ 4315169240Sjfv if (ret_val) { 4316169240Sjfv DEBUGOUT("Flash commit failed.\n"); 4317203049Sjfv goto release; 4318169240Sjfv } 4319169240Sjfv 4320247064Sjfv /* Finally validate the new segment by setting bit 15:14 4321169240Sjfv * to 10b in word 0x13 , this can be done without an 4322169240Sjfv * erase as well since these bits are 11 to start with 4323173788Sjfv * and we need to change bit 14 to 0b 4324173788Sjfv */ 4325169240Sjfv act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD; 4326190872Sjfv ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data); 4327203049Sjfv if (ret_val) 4328203049Sjfv goto release; 4329200243Sjfv 4330169240Sjfv data &= 0xBFFF; 4331267935Sjfv ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset * 2 + 1, 4332228386Sjfv (u8)(data >> 8)); 4333203049Sjfv if (ret_val) 4334203049Sjfv goto release; 4335169240Sjfv 4336247064Sjfv /* And invalidate the previously valid segment by setting 4337169240Sjfv * its signature word (0x13) high_byte to 0b. This can be 4338169240Sjfv * done without an erase because flash erase sets all bits 4339173788Sjfv * to 1's. We can write 1's to 0's without an erase 4340173788Sjfv */ 4341169240Sjfv act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1; 4342267935Sjfv 4343169240Sjfv ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0); 4344267935Sjfv 4345203049Sjfv if (ret_val) 4346203049Sjfv goto release; 4347169240Sjfv 4348169240Sjfv /* Great! Everything worked, we can now clear the cached entries. */ 4349169240Sjfv for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { 4350169240Sjfv dev_spec->shadow_ram[i].modified = FALSE; 4351169240Sjfv dev_spec->shadow_ram[i].value = 0xFFFF; 4352169240Sjfv } 4353169240Sjfv 4354203049Sjfvrelease: 4355177867Sjfv nvm->ops.release(hw); 4356169240Sjfv 4357247064Sjfv /* Reload the EEPROM, or else modifications will not appear 4358169240Sjfv * until after the next adapter reset. 4359169240Sjfv */ 4360203049Sjfv if (!ret_val) { 4361203049Sjfv nvm->ops.reload(hw); 4362203049Sjfv msec_delay(10); 4363203049Sjfv } 4364169240Sjfv 4365169240Sjfvout: 4366190872Sjfv if (ret_val) 4367190872Sjfv DEBUGOUT1("NVM update error: %d\n", ret_val); 4368190872Sjfv 4369169240Sjfv return ret_val; 4370169240Sjfv} 4371169240Sjfv 4372169240Sjfv/** 4373169240Sjfv * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum 4374169589Sjfv * @hw: pointer to the HW structure 4375169240Sjfv * 4376169240Sjfv * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19. 4377185353Sjfv * If the bit is 0, that the EEPROM had been modified, but the checksum was not 4378185353Sjfv * calculated, in which case we need to calculate the checksum and set bit 6. 4379169240Sjfv **/ 4380177867Sjfvstatic s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw) 4381169240Sjfv{ 4382247064Sjfv s32 ret_val; 4383169240Sjfv u16 data; 4384247064Sjfv u16 word; 4385247064Sjfv u16 valid_csum_mask; 4386169240Sjfv 4387169240Sjfv DEBUGFUNC("e1000_validate_nvm_checksum_ich8lan"); 4388169240Sjfv 4389247064Sjfv /* Read NVM and check Invalid Image CSUM bit. If this bit is 0, 4390247064Sjfv * the checksum needs to be fixed. This bit is an indication that 4391247064Sjfv * the NVM was prepared by OEM software and did not calculate 4392247064Sjfv * the checksum...a likely scenario. 4393169240Sjfv */ 4394247064Sjfv switch (hw->mac.type) { 4395247064Sjfv case e1000_pch_lpt: 4396295323Serj case e1000_pch_spt: 4397333213Smarius case e1000_pch_cnp: 4398247064Sjfv word = NVM_COMPAT; 4399247064Sjfv valid_csum_mask = NVM_COMPAT_VALID_CSUM; 4400247064Sjfv break; 4401247064Sjfv default: 4402247064Sjfv word = NVM_FUTURE_INIT_WORD1; 4403247064Sjfv valid_csum_mask = NVM_FUTURE_INIT_WORD1_VALID_CSUM; 4404247064Sjfv break; 4405247064Sjfv } 4406247064Sjfv 4407247064Sjfv ret_val = hw->nvm.ops.read(hw, word, 1, &data); 4408169240Sjfv if (ret_val) 4409247064Sjfv return ret_val; 4410169240Sjfv 4411247064Sjfv if (!(data & valid_csum_mask)) { 4412247064Sjfv data |= valid_csum_mask; 4413247064Sjfv ret_val = hw->nvm.ops.write(hw, word, 1, &data); 4414169240Sjfv if (ret_val) 4415247064Sjfv return ret_val; 4416177867Sjfv ret_val = hw->nvm.ops.update(hw); 4417169240Sjfv if (ret_val) 4418247064Sjfv return ret_val; 4419169240Sjfv } 4420169240Sjfv 4421247064Sjfv return e1000_validate_nvm_checksum_generic(hw); 4422169240Sjfv} 4423169240Sjfv 4424169240Sjfv/** 4425169240Sjfv * e1000_write_flash_data_ich8lan - Writes bytes to the NVM 4426169589Sjfv * @hw: pointer to the HW structure 4427169589Sjfv * @offset: The offset (in bytes) of the byte/word to read. 4428169589Sjfv * @size: Size of data to read, 1=byte 2=word 4429169589Sjfv * @data: The byte(s) to write to the NVM. 4430169240Sjfv * 4431169240Sjfv * Writes one/two bytes to the NVM using the flash access registers. 4432169240Sjfv **/ 4433173788Sjfvstatic s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, 4434228386Sjfv u8 size, u16 data) 4435169240Sjfv{ 4436169240Sjfv union ich8_hws_flash_status hsfsts; 4437169240Sjfv union ich8_hws_flash_ctrl hsflctl; 4438169240Sjfv u32 flash_linear_addr; 4439169240Sjfv u32 flash_data = 0; 4440247064Sjfv s32 ret_val; 4441169240Sjfv u8 count = 0; 4442169240Sjfv 4443169240Sjfv DEBUGFUNC("e1000_write_ich8_data"); 4444169240Sjfv 4445322955Smarius if (hw->mac.type >= e1000_pch_spt) { 4446295323Serj if (size != 4 || offset > ICH_FLASH_LINEAR_ADDR_MASK) 4447295323Serj return -E1000_ERR_NVM; 4448295323Serj } else { 4449295323Serj if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK) 4450295323Serj return -E1000_ERR_NVM; 4451295323Serj } 4452169240Sjfv 4453256200Sjfv flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) + 4454256200Sjfv hw->nvm.flash_base_addr); 4455169240Sjfv 4456169240Sjfv do { 4457169240Sjfv usec_delay(1); 4458169240Sjfv /* Steps */ 4459169240Sjfv ret_val = e1000_flash_cycle_init_ich8lan(hw); 4460169240Sjfv if (ret_val != E1000_SUCCESS) 4461169240Sjfv break; 4462295323Serj /* In SPT, This register is in Lan memory space, not 4463295323Serj * flash. Therefore, only 32 bit access is supported 4464295323Serj */ 4465322955Smarius if (hw->mac.type >= e1000_pch_spt) 4466295323Serj hsflctl.regval = 4467295323Serj E1000_READ_FLASH_REG(hw, ICH_FLASH_HSFSTS)>>16; 4468295323Serj else 4469295323Serj hsflctl.regval = 4470295323Serj E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL); 4471169240Sjfv 4472169240Sjfv /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ 4473185353Sjfv hsflctl.hsf_ctrl.fldbcount = size - 1; 4474169240Sjfv hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE; 4475295323Serj /* In SPT, This register is in Lan memory space, 4476295323Serj * not flash. Therefore, only 32 bit access is 4477295323Serj * supported 4478295323Serj */ 4479322955Smarius if (hw->mac.type >= e1000_pch_spt) 4480295323Serj E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS, 4481295323Serj hsflctl.regval << 16); 4482295323Serj else 4483295323Serj E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, 4484295323Serj hsflctl.regval); 4485169240Sjfv 4486169240Sjfv E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr); 4487169240Sjfv 4488169240Sjfv if (size == 1) 4489169240Sjfv flash_data = (u32)data & 0x00FF; 4490169240Sjfv else 4491169240Sjfv flash_data = (u32)data; 4492169240Sjfv 4493169240Sjfv E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FDATA0, flash_data); 4494169240Sjfv 4495247064Sjfv /* check if FCERR is set to 1 , if set to 1, clear it 4496173788Sjfv * and try the whole sequence a few more times else done 4497173788Sjfv */ 4498256200Sjfv ret_val = 4499256200Sjfv e1000_flash_cycle_ich8lan(hw, 4500256200Sjfv ICH_FLASH_WRITE_COMMAND_TIMEOUT); 4501185353Sjfv if (ret_val == E1000_SUCCESS) 4502169240Sjfv break; 4503185353Sjfv 4504247064Sjfv /* If we're here, then things are most likely 4505185353Sjfv * completely hosed, but if the error condition 4506185353Sjfv * is detected, it won't hurt to give it another 4507185353Sjfv * try...ICH_FLASH_CYCLE_REPEAT_COUNT times. 4508185353Sjfv */ 4509185353Sjfv hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS); 4510247064Sjfv if (hsfsts.hsf_status.flcerr) 4511185353Sjfv /* Repeat for some time before giving up. */ 4512185353Sjfv continue; 4513247064Sjfv if (!hsfsts.hsf_status.flcdone) { 4514228386Sjfv DEBUGOUT("Timeout error - flash cycle did not complete.\n"); 4515185353Sjfv break; 4516169240Sjfv } 4517169240Sjfv } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 4518169240Sjfv 4519169240Sjfv return ret_val; 4520169240Sjfv} 4521169240Sjfv 4522295323Serj/** 4523295323Serj* e1000_write_flash_data32_ich8lan - Writes 4 bytes to the NVM 4524295323Serj* @hw: pointer to the HW structure 4525295323Serj* @offset: The offset (in bytes) of the dwords to read. 4526295323Serj* @data: The 4 bytes to write to the NVM. 4527295323Serj* 4528295323Serj* Writes one/two/four bytes to the NVM using the flash access registers. 4529295323Serj**/ 4530295323Serjstatic s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset, 4531295323Serj u32 data) 4532295323Serj{ 4533295323Serj union ich8_hws_flash_status hsfsts; 4534295323Serj union ich8_hws_flash_ctrl hsflctl; 4535295323Serj u32 flash_linear_addr; 4536295323Serj s32 ret_val; 4537295323Serj u8 count = 0; 4538267935Sjfv 4539295323Serj DEBUGFUNC("e1000_write_flash_data32_ich8lan"); 4540295323Serj 4541322955Smarius if (hw->mac.type >= e1000_pch_spt) { 4542295323Serj if (offset > ICH_FLASH_LINEAR_ADDR_MASK) 4543295323Serj return -E1000_ERR_NVM; 4544295323Serj } 4545295323Serj flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) + 4546295323Serj hw->nvm.flash_base_addr); 4547295323Serj do { 4548295323Serj usec_delay(1); 4549295323Serj /* Steps */ 4550295323Serj ret_val = e1000_flash_cycle_init_ich8lan(hw); 4551295323Serj if (ret_val != E1000_SUCCESS) 4552295323Serj break; 4553295323Serj 4554295323Serj /* In SPT, This register is in Lan memory space, not 4555295323Serj * flash. Therefore, only 32 bit access is supported 4556295323Serj */ 4557322955Smarius if (hw->mac.type >= e1000_pch_spt) 4558295323Serj hsflctl.regval = E1000_READ_FLASH_REG(hw, 4559295323Serj ICH_FLASH_HSFSTS) 4560295323Serj >> 16; 4561295323Serj else 4562295323Serj hsflctl.regval = E1000_READ_FLASH_REG16(hw, 4563295323Serj ICH_FLASH_HSFCTL); 4564295323Serj 4565295323Serj hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1; 4566295323Serj hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE; 4567295323Serj 4568295323Serj /* In SPT, This register is in Lan memory space, 4569295323Serj * not flash. Therefore, only 32 bit access is 4570295323Serj * supported 4571295323Serj */ 4572322955Smarius if (hw->mac.type >= e1000_pch_spt) 4573295323Serj E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS, 4574295323Serj hsflctl.regval << 16); 4575295323Serj else 4576295323Serj E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, 4577295323Serj hsflctl.regval); 4578295323Serj 4579295323Serj E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr); 4580295323Serj 4581295323Serj E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FDATA0, data); 4582295323Serj 4583295323Serj /* check if FCERR is set to 1 , if set to 1, clear it 4584295323Serj * and try the whole sequence a few more times else done 4585295323Serj */ 4586295323Serj ret_val = e1000_flash_cycle_ich8lan(hw, 4587295323Serj ICH_FLASH_WRITE_COMMAND_TIMEOUT); 4588295323Serj 4589295323Serj if (ret_val == E1000_SUCCESS) 4590295323Serj break; 4591295323Serj 4592295323Serj /* If we're here, then things are most likely 4593295323Serj * completely hosed, but if the error condition 4594295323Serj * is detected, it won't hurt to give it another 4595295323Serj * try...ICH_FLASH_CYCLE_REPEAT_COUNT times. 4596295323Serj */ 4597295323Serj hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS); 4598295323Serj 4599295323Serj if (hsfsts.hsf_status.flcerr) 4600295323Serj /* Repeat for some time before giving up. */ 4601295323Serj continue; 4602295323Serj if (!hsfsts.hsf_status.flcdone) { 4603295323Serj DEBUGOUT("Timeout error - flash cycle did not complete.\n"); 4604295323Serj break; 4605295323Serj } 4606295323Serj } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 4607295323Serj 4608295323Serj return ret_val; 4609295323Serj} 4610295323Serj 4611169240Sjfv/** 4612169240Sjfv * e1000_write_flash_byte_ich8lan - Write a single byte to NVM 4613169589Sjfv * @hw: pointer to the HW structure 4614169589Sjfv * @offset: The index of the byte to read. 4615169589Sjfv * @data: The byte to write to the NVM. 4616169240Sjfv * 4617169240Sjfv * Writes a single byte to the NVM using the flash access registers. 4618169240Sjfv **/ 4619177867Sjfvstatic s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, 4620228386Sjfv u8 data) 4621169240Sjfv{ 4622169240Sjfv u16 word = (u16)data; 4623169240Sjfv 4624169240Sjfv DEBUGFUNC("e1000_write_flash_byte_ich8lan"); 4625169240Sjfv 4626169240Sjfv return e1000_write_flash_data_ich8lan(hw, offset, 1, word); 4627169240Sjfv} 4628169240Sjfv 4629295323Serj/** 4630295323Serj* e1000_retry_write_flash_dword_ich8lan - Writes a dword to NVM 4631295323Serj* @hw: pointer to the HW structure 4632295323Serj* @offset: The offset of the word to write. 4633295323Serj* @dword: The dword to write to the NVM. 4634295323Serj* 4635295323Serj* Writes a single dword to the NVM using the flash access registers. 4636295323Serj* Goes through a retry algorithm before giving up. 4637295323Serj**/ 4638295323Serjstatic s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw, 4639295323Serj u32 offset, u32 dword) 4640295323Serj{ 4641295323Serj s32 ret_val; 4642295323Serj u16 program_retries; 4643267935Sjfv 4644295323Serj DEBUGFUNC("e1000_retry_write_flash_dword_ich8lan"); 4645267935Sjfv 4646295323Serj /* Must convert word offset into bytes. */ 4647295323Serj offset <<= 1; 4648295323Serj 4649295323Serj ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword); 4650295323Serj 4651295323Serj if (!ret_val) 4652295323Serj return ret_val; 4653295323Serj for (program_retries = 0; program_retries < 100; program_retries++) { 4654295323Serj DEBUGOUT2("Retrying Byte %8.8X at offset %u\n", dword, offset); 4655295323Serj usec_delay(100); 4656295323Serj ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword); 4657295323Serj if (ret_val == E1000_SUCCESS) 4658295323Serj break; 4659295323Serj } 4660295323Serj if (program_retries == 100) 4661295323Serj return -E1000_ERR_NVM; 4662295323Serj 4663295323Serj return E1000_SUCCESS; 4664295323Serj} 4665295323Serj 4666169240Sjfv/** 4667169240Sjfv * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM 4668169589Sjfv * @hw: pointer to the HW structure 4669169589Sjfv * @offset: The offset of the byte to write. 4670169589Sjfv * @byte: The byte to write to the NVM. 4671169240Sjfv * 4672169240Sjfv * Writes a single byte to the NVM using the flash access registers. 4673169240Sjfv * Goes through a retry algorithm before giving up. 4674169240Sjfv **/ 4675176667Sjfvstatic s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw, 4676228386Sjfv u32 offset, u8 byte) 4677169240Sjfv{ 4678169240Sjfv s32 ret_val; 4679169240Sjfv u16 program_retries; 4680169240Sjfv 4681169240Sjfv DEBUGFUNC("e1000_retry_write_flash_byte_ich8lan"); 4682169240Sjfv 4683169240Sjfv ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte); 4684247064Sjfv if (!ret_val) 4685247064Sjfv return ret_val; 4686169240Sjfv 4687169240Sjfv for (program_retries = 0; program_retries < 100; program_retries++) { 4688169240Sjfv DEBUGOUT2("Retrying Byte %2.2X at offset %u\n", byte, offset); 4689169240Sjfv usec_delay(100); 4690169240Sjfv ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte); 4691169240Sjfv if (ret_val == E1000_SUCCESS) 4692169240Sjfv break; 4693169240Sjfv } 4694247064Sjfv if (program_retries == 100) 4695247064Sjfv return -E1000_ERR_NVM; 4696169240Sjfv 4697247064Sjfv return E1000_SUCCESS; 4698169240Sjfv} 4699169240Sjfv 4700169240Sjfv/** 4701169240Sjfv * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM 4702169589Sjfv * @hw: pointer to the HW structure 4703169589Sjfv * @bank: 0 for first bank, 1 for second bank, etc. 4704169240Sjfv * 4705169240Sjfv * Erases the bank specified. Each bank is a 4k block. Banks are 0 based. 4706169240Sjfv * bank N is 4096 * N + flash_reg_addr. 4707169240Sjfv **/ 4708177867Sjfvstatic s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank) 4709169240Sjfv{ 4710169240Sjfv struct e1000_nvm_info *nvm = &hw->nvm; 4711169240Sjfv union ich8_hws_flash_status hsfsts; 4712169240Sjfv union ich8_hws_flash_ctrl hsflctl; 4713169240Sjfv u32 flash_linear_addr; 4714173788Sjfv /* bank size is in 16bit words - adjust to bytes */ 4715173788Sjfv u32 flash_bank_size = nvm->flash_bank_size * 2; 4716247064Sjfv s32 ret_val; 4717185353Sjfv s32 count = 0; 4718185353Sjfv s32 j, iteration, sector_size; 4719169240Sjfv 4720169240Sjfv DEBUGFUNC("e1000_erase_flash_bank_ich8lan"); 4721169240Sjfv 4722169240Sjfv hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS); 4723169240Sjfv 4724247064Sjfv /* Determine HW Sector size: Read BERASE bits of hw flash status 4725173788Sjfv * register 4726173788Sjfv * 00: The Hw sector is 256 bytes, hence we need to erase 16 4727169240Sjfv * consecutive sectors. The start index for the nth Hw sector 4728169240Sjfv * can be calculated as = bank * 4096 + n * 256 4729169240Sjfv * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector. 4730169240Sjfv * The start index for the nth Hw sector can be calculated 4731169240Sjfv * as = bank * 4096 4732169240Sjfv * 10: The Hw sector is 8K bytes, nth sector = bank * 8192 4733169240Sjfv * (ich9 only, otherwise error condition) 4734169240Sjfv * 11: The Hw sector is 64K bytes, nth sector = bank * 65536 4735169240Sjfv */ 4736169240Sjfv switch (hsfsts.hsf_status.berasesz) { 4737169240Sjfv case 0: 4738169240Sjfv /* Hw sector size 256 */ 4739169240Sjfv sector_size = ICH_FLASH_SEG_SIZE_256; 4740169240Sjfv iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256; 4741169240Sjfv break; 4742169240Sjfv case 1: 4743169240Sjfv sector_size = ICH_FLASH_SEG_SIZE_4K; 4744194865Sjfv iteration = 1; 4745169240Sjfv break; 4746169240Sjfv case 2: 4747195850Sjfv sector_size = ICH_FLASH_SEG_SIZE_8K; 4748195850Sjfv iteration = 1; 4749169240Sjfv break; 4750169240Sjfv case 3: 4751169240Sjfv sector_size = ICH_FLASH_SEG_SIZE_64K; 4752194865Sjfv iteration = 1; 4753169240Sjfv break; 4754169240Sjfv default: 4755247064Sjfv return -E1000_ERR_NVM; 4756169240Sjfv } 4757169240Sjfv 4758169240Sjfv /* Start with the base address, then add the sector offset. */ 4759169240Sjfv flash_linear_addr = hw->nvm.flash_base_addr; 4760200243Sjfv flash_linear_addr += (bank) ? flash_bank_size : 0; 4761169240Sjfv 4762256200Sjfv for (j = 0; j < iteration; j++) { 4763169240Sjfv do { 4764256200Sjfv u32 timeout = ICH_FLASH_ERASE_COMMAND_TIMEOUT; 4765256200Sjfv 4766169240Sjfv /* Steps */ 4767169240Sjfv ret_val = e1000_flash_cycle_init_ich8lan(hw); 4768169240Sjfv if (ret_val) 4769247064Sjfv return ret_val; 4770169240Sjfv 4771247064Sjfv /* Write a value 11 (block Erase) in Flash 4772173788Sjfv * Cycle field in hw flash control 4773173788Sjfv */ 4774322955Smarius if (hw->mac.type >= e1000_pch_spt) 4775295323Serj hsflctl.regval = 4776295323Serj E1000_READ_FLASH_REG(hw, 4777295323Serj ICH_FLASH_HSFSTS)>>16; 4778295323Serj else 4779295323Serj hsflctl.regval = 4780295323Serj E1000_READ_FLASH_REG16(hw, 4781295323Serj ICH_FLASH_HSFCTL); 4782267935Sjfv 4783169240Sjfv hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE; 4784322955Smarius if (hw->mac.type >= e1000_pch_spt) 4785295323Serj E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS, 4786295323Serj hsflctl.regval << 16); 4787295323Serj else 4788295323Serj E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, 4789295323Serj hsflctl.regval); 4790169240Sjfv 4791247064Sjfv /* Write the last 24 bits of an index within the 4792169240Sjfv * block into Flash Linear address field in Flash 4793169240Sjfv * Address. 4794169240Sjfv */ 4795169240Sjfv flash_linear_addr += (j * sector_size); 4796185353Sjfv E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, 4797228386Sjfv flash_linear_addr); 4798169240Sjfv 4799256200Sjfv ret_val = e1000_flash_cycle_ich8lan(hw, timeout); 4800185353Sjfv if (ret_val == E1000_SUCCESS) 4801169240Sjfv break; 4802185353Sjfv 4803247064Sjfv /* Check if FCERR is set to 1. If 1, 4804185353Sjfv * clear it and try the whole sequence 4805185353Sjfv * a few more times else Done 4806185353Sjfv */ 4807185353Sjfv hsfsts.regval = E1000_READ_FLASH_REG16(hw, 4808185353Sjfv ICH_FLASH_HSFSTS); 4809247064Sjfv if (hsfsts.hsf_status.flcerr) 4810185353Sjfv /* repeat for some time before giving up */ 4811185353Sjfv continue; 4812247064Sjfv else if (!hsfsts.hsf_status.flcdone) 4813247064Sjfv return ret_val; 4814169240Sjfv } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT); 4815169240Sjfv } 4816169240Sjfv 4817247064Sjfv return E1000_SUCCESS; 4818169240Sjfv} 4819169240Sjfv 4820169240Sjfv/** 4821169240Sjfv * e1000_valid_led_default_ich8lan - Set the default LED settings 4822169589Sjfv * @hw: pointer to the HW structure 4823169589Sjfv * @data: Pointer to the LED settings 4824169240Sjfv * 4825169240Sjfv * Reads the LED default settings from the NVM to data. If the NVM LED 4826169240Sjfv * settings is all 0's or F's, set the LED default to a valid LED default 4827169240Sjfv * setting. 4828169240Sjfv **/ 4829177867Sjfvstatic s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data) 4830169240Sjfv{ 4831169240Sjfv s32 ret_val; 4832169240Sjfv 4833169240Sjfv DEBUGFUNC("e1000_valid_led_default_ich8lan"); 4834169240Sjfv 4835177867Sjfv ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data); 4836169240Sjfv if (ret_val) { 4837169240Sjfv DEBUGOUT("NVM Read Error\n"); 4838247064Sjfv return ret_val; 4839169240Sjfv } 4840169240Sjfv 4841228386Sjfv if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) 4842169240Sjfv *data = ID_LED_DEFAULT_ICH8LAN; 4843169240Sjfv 4844247064Sjfv return E1000_SUCCESS; 4845169240Sjfv} 4846169240Sjfv 4847169240Sjfv/** 4848194865Sjfv * e1000_id_led_init_pchlan - store LED configurations 4849194865Sjfv * @hw: pointer to the HW structure 4850194865Sjfv * 4851194865Sjfv * PCH does not control LEDs via the LEDCTL register, rather it uses 4852194865Sjfv * the PHY LED configuration register. 4853194865Sjfv * 4854194865Sjfv * PCH also does not have an "always on" or "always off" mode which 4855194865Sjfv * complicates the ID feature. Instead of using the "on" mode to indicate 4856194865Sjfv * in ledctl_mode2 the LEDs to use for ID (see e1000_id_led_init_generic()), 4857194865Sjfv * use "link_up" mode. The LEDs will still ID on request if there is no 4858194865Sjfv * link based on logic in e1000_led_[on|off]_pchlan(). 4859194865Sjfv **/ 4860194865Sjfvstatic s32 e1000_id_led_init_pchlan(struct e1000_hw *hw) 4861194865Sjfv{ 4862194865Sjfv struct e1000_mac_info *mac = &hw->mac; 4863194865Sjfv s32 ret_val; 4864194865Sjfv const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP; 4865194865Sjfv const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT; 4866194865Sjfv u16 data, i, temp, shift; 4867194865Sjfv 4868194865Sjfv DEBUGFUNC("e1000_id_led_init_pchlan"); 4869194865Sjfv 4870194865Sjfv /* Get default ID LED modes */ 4871194865Sjfv ret_val = hw->nvm.ops.valid_led_default(hw, &data); 4872194865Sjfv if (ret_val) 4873247064Sjfv return ret_val; 4874194865Sjfv 4875194865Sjfv mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL); 4876194865Sjfv mac->ledctl_mode1 = mac->ledctl_default; 4877194865Sjfv mac->ledctl_mode2 = mac->ledctl_default; 4878194865Sjfv 4879194865Sjfv for (i = 0; i < 4; i++) { 4880194865Sjfv temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK; 4881194865Sjfv shift = (i * 5); 4882194865Sjfv switch (temp) { 4883194865Sjfv case ID_LED_ON1_DEF2: 4884194865Sjfv case ID_LED_ON1_ON2: 4885194865Sjfv case ID_LED_ON1_OFF2: 4886194865Sjfv mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift); 4887194865Sjfv mac->ledctl_mode1 |= (ledctl_on << shift); 4888194865Sjfv break; 4889194865Sjfv case ID_LED_OFF1_DEF2: 4890194865Sjfv case ID_LED_OFF1_ON2: 4891194865Sjfv case ID_LED_OFF1_OFF2: 4892194865Sjfv mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift); 4893194865Sjfv mac->ledctl_mode1 |= (ledctl_off << shift); 4894194865Sjfv break; 4895194865Sjfv default: 4896194865Sjfv /* Do nothing */ 4897194865Sjfv break; 4898194865Sjfv } 4899194865Sjfv switch (temp) { 4900194865Sjfv case ID_LED_DEF1_ON2: 4901194865Sjfv case ID_LED_ON1_ON2: 4902194865Sjfv case ID_LED_OFF1_ON2: 4903194865Sjfv mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift); 4904194865Sjfv mac->ledctl_mode2 |= (ledctl_on << shift); 4905194865Sjfv break; 4906194865Sjfv case ID_LED_DEF1_OFF2: 4907194865Sjfv case ID_LED_ON1_OFF2: 4908194865Sjfv case ID_LED_OFF1_OFF2: 4909194865Sjfv mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift); 4910194865Sjfv mac->ledctl_mode2 |= (ledctl_off << shift); 4911194865Sjfv break; 4912194865Sjfv default: 4913194865Sjfv /* Do nothing */ 4914194865Sjfv break; 4915194865Sjfv } 4916194865Sjfv } 4917194865Sjfv 4918247064Sjfv return E1000_SUCCESS; 4919194865Sjfv} 4920194865Sjfv 4921194865Sjfv/** 4922169240Sjfv * e1000_get_bus_info_ich8lan - Get/Set the bus type and width 4923169589Sjfv * @hw: pointer to the HW structure 4924169240Sjfv * 4925169240Sjfv * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability 4926300050Seadler * register, so the bus width is hard coded. 4927169240Sjfv **/ 4928177867Sjfvstatic s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw) 4929169240Sjfv{ 4930169240Sjfv struct e1000_bus_info *bus = &hw->bus; 4931169240Sjfv s32 ret_val; 4932169240Sjfv 4933169240Sjfv DEBUGFUNC("e1000_get_bus_info_ich8lan"); 4934169240Sjfv 4935169240Sjfv ret_val = e1000_get_bus_info_pcie_generic(hw); 4936169240Sjfv 4937247064Sjfv /* ICH devices are "PCI Express"-ish. They have 4938169240Sjfv * a configuration space, but do not contain 4939169240Sjfv * PCI Express Capability registers, so bus width 4940169240Sjfv * must be hardcoded. 4941169240Sjfv */ 4942169240Sjfv if (bus->width == e1000_bus_width_unknown) 4943169240Sjfv bus->width = e1000_bus_width_pcie_x1; 4944169240Sjfv 4945169240Sjfv return ret_val; 4946169240Sjfv} 4947169240Sjfv 4948169240Sjfv/** 4949169240Sjfv * e1000_reset_hw_ich8lan - Reset the hardware 4950169589Sjfv * @hw: pointer to the HW structure 4951169240Sjfv * 4952169240Sjfv * Does a full reset of the hardware which includes a reset of the PHY and 4953169240Sjfv * MAC. 4954169240Sjfv **/ 4955177867Sjfvstatic s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw) 4956169240Sjfv{ 4957200243Sjfv struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 4958247064Sjfv u16 kum_cfg; 4959247064Sjfv u32 ctrl, reg; 4960169240Sjfv s32 ret_val; 4961169240Sjfv 4962169240Sjfv DEBUGFUNC("e1000_reset_hw_ich8lan"); 4963169240Sjfv 4964247064Sjfv /* Prevent the PCI-E bus from sticking if there is no TLP connection 4965169240Sjfv * on the last TLP read/write transaction when MAC is reset. 4966169240Sjfv */ 4967169240Sjfv ret_val = e1000_disable_pcie_master_generic(hw); 4968185353Sjfv if (ret_val) 4969169240Sjfv DEBUGOUT("PCI-E Master disable polling has failed.\n"); 4970169240Sjfv 4971169240Sjfv DEBUGOUT("Masking off all interrupts\n"); 4972169240Sjfv E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 4973169240Sjfv 4974247064Sjfv /* Disable the Transmit and Receive units. Then delay to allow 4975169240Sjfv * any pending transactions to complete before we hit the MAC 4976169240Sjfv * with the global reset. 4977169240Sjfv */ 4978169240Sjfv E1000_WRITE_REG(hw, E1000_RCTL, 0); 4979169240Sjfv E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); 4980169240Sjfv E1000_WRITE_FLUSH(hw); 4981169240Sjfv 4982169240Sjfv msec_delay(10); 4983169240Sjfv 4984169240Sjfv /* Workaround for ICH8 bit corruption issue in FIFO memory */ 4985169240Sjfv if (hw->mac.type == e1000_ich8lan) { 4986169240Sjfv /* Set Tx and Rx buffer allocation to 8k apiece. */ 4987169240Sjfv E1000_WRITE_REG(hw, E1000_PBA, E1000_PBA_8K); 4988169240Sjfv /* Set Packet Buffer Size to 16k. */ 4989169240Sjfv E1000_WRITE_REG(hw, E1000_PBS, E1000_PBS_16K); 4990169240Sjfv } 4991169240Sjfv 4992200243Sjfv if (hw->mac.type == e1000_pchlan) { 4993200243Sjfv /* Save the NVM K1 bit setting*/ 4994247064Sjfv ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &kum_cfg); 4995200243Sjfv if (ret_val) 4996200243Sjfv return ret_val; 4997200243Sjfv 4998247064Sjfv if (kum_cfg & E1000_NVM_K1_ENABLE) 4999200243Sjfv dev_spec->nvm_k1_enabled = TRUE; 5000200243Sjfv else 5001200243Sjfv dev_spec->nvm_k1_enabled = FALSE; 5002200243Sjfv } 5003200243Sjfv 5004169240Sjfv ctrl = E1000_READ_REG(hw, E1000_CTRL); 5005169240Sjfv 5006213234Sjfv if (!hw->phy.ops.check_reset_block(hw)) { 5007247064Sjfv /* Full-chip reset requires MAC and PHY reset at the same 5008169240Sjfv * time to make sure the interface between MAC and the 5009169240Sjfv * external PHY is reset. 5010169240Sjfv */ 5011169240Sjfv ctrl |= E1000_CTRL_PHY_RST; 5012213234Sjfv 5013247064Sjfv /* Gate automatic PHY configuration by hardware on 5014213234Sjfv * non-managed 82579 5015213234Sjfv */ 5016213234Sjfv if ((hw->mac.type == e1000_pch2lan) && 5017213234Sjfv !(E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID)) 5018213234Sjfv e1000_gate_hw_phy_config_ich8lan(hw, TRUE); 5019169240Sjfv } 5020169240Sjfv ret_val = e1000_acquire_swflag_ich8lan(hw); 5021185353Sjfv DEBUGOUT("Issuing a global reset to ich8lan\n"); 5022169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, (ctrl | E1000_CTRL_RST)); 5023228386Sjfv /* cannot issue a flush here because it hangs the hardware */ 5024169240Sjfv msec_delay(20); 5025169240Sjfv 5026247064Sjfv /* Set Phy Config Counter to 50msec */ 5027247064Sjfv if (hw->mac.type == e1000_pch2lan) { 5028247064Sjfv reg = E1000_READ_REG(hw, E1000_FEXTNVM3); 5029247064Sjfv reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK; 5030247064Sjfv reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC; 5031247064Sjfv E1000_WRITE_REG(hw, E1000_FEXTNVM3, reg); 5032247064Sjfv } 5033247064Sjfv 5034194865Sjfv if (!ret_val) 5035228386Sjfv E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex); 5036194865Sjfv 5037213234Sjfv if (ctrl & E1000_CTRL_PHY_RST) { 5038213234Sjfv ret_val = hw->phy.ops.get_cfg_done(hw); 5039203049Sjfv if (ret_val) 5040247064Sjfv return ret_val; 5041203049Sjfv 5042213234Sjfv ret_val = e1000_post_phy_reset_ich8lan(hw); 5043213234Sjfv if (ret_val) 5044247064Sjfv return ret_val; 5045169240Sjfv } 5046169240Sjfv 5047247064Sjfv /* For PCH, this write will make sure that any noise 5048200243Sjfv * will be detected as a CRC error and be dropped rather than show up 5049200243Sjfv * as a bad packet to the DMA engine. 5050200243Sjfv */ 5051200243Sjfv if (hw->mac.type == e1000_pchlan) 5052200243Sjfv E1000_WRITE_REG(hw, E1000_CRC_OFFSET, 0x65656565); 5053200243Sjfv 5054169240Sjfv E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 5055218588Sjfv E1000_READ_REG(hw, E1000_ICR); 5056169240Sjfv 5057247064Sjfv reg = E1000_READ_REG(hw, E1000_KABGTXD); 5058247064Sjfv reg |= E1000_KABGTXD_BGSQLBIAS; 5059247064Sjfv E1000_WRITE_REG(hw, E1000_KABGTXD, reg); 5060169240Sjfv 5061247064Sjfv return E1000_SUCCESS; 5062169240Sjfv} 5063169240Sjfv 5064169240Sjfv/** 5065169240Sjfv * e1000_init_hw_ich8lan - Initialize the hardware 5066169589Sjfv * @hw: pointer to the HW structure 5067169240Sjfv * 5068169240Sjfv * Prepares the hardware for transmit and receive by doing the following: 5069169240Sjfv * - initialize hardware bits 5070169240Sjfv * - initialize LED identification 5071169240Sjfv * - setup receive address registers 5072169240Sjfv * - setup flow control 5073176667Sjfv * - setup transmit descriptors 5074169240Sjfv * - clear statistics 5075169240Sjfv **/ 5076177867Sjfvstatic s32 e1000_init_hw_ich8lan(struct e1000_hw *hw) 5077169240Sjfv{ 5078169240Sjfv struct e1000_mac_info *mac = &hw->mac; 5079169240Sjfv u32 ctrl_ext, txdctl, snoop; 5080169240Sjfv s32 ret_val; 5081169240Sjfv u16 i; 5082169240Sjfv 5083169240Sjfv DEBUGFUNC("e1000_init_hw_ich8lan"); 5084169240Sjfv 5085169240Sjfv e1000_initialize_hw_bits_ich8lan(hw); 5086169240Sjfv 5087169240Sjfv /* Initialize identification LED */ 5088190872Sjfv ret_val = mac->ops.id_led_init(hw); 5089247064Sjfv /* An error is not fatal and we should not stop init due to this */ 5090190872Sjfv if (ret_val) 5091200243Sjfv DEBUGOUT("Error initializing identification LED\n"); 5092169240Sjfv 5093169240Sjfv /* Setup the receive address. */ 5094169240Sjfv e1000_init_rx_addrs_generic(hw, mac->rar_entry_count); 5095169240Sjfv 5096169240Sjfv /* Zero out the Multicast HASH table */ 5097169240Sjfv DEBUGOUT("Zeroing the MTA\n"); 5098169240Sjfv for (i = 0; i < mac->mta_reg_count; i++) 5099169240Sjfv E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 5100169240Sjfv 5101247064Sjfv /* The 82578 Rx buffer will stall if wakeup is enabled in host and 5102228386Sjfv * the ME. Disable wakeup by clearing the host wakeup bit. 5103194865Sjfv * Reset the phy after disabling host wakeup to reset the Rx buffer. 5104194865Sjfv */ 5105194865Sjfv if (hw->phy.type == e1000_phy_82578) { 5106228386Sjfv hw->phy.ops.read_reg(hw, BM_PORT_GEN_CFG, &i); 5107228386Sjfv i &= ~BM_WUC_HOST_WU_BIT; 5108228386Sjfv hw->phy.ops.write_reg(hw, BM_PORT_GEN_CFG, i); 5109194865Sjfv ret_val = e1000_phy_hw_reset_ich8lan(hw); 5110194865Sjfv if (ret_val) 5111194865Sjfv return ret_val; 5112194865Sjfv } 5113194865Sjfv 5114169240Sjfv /* Setup link and flow control */ 5115177867Sjfv ret_val = mac->ops.setup_link(hw); 5116169240Sjfv 5117169240Sjfv /* Set the transmit descriptor write-back policy for both queues */ 5118173788Sjfv txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0)); 5119256200Sjfv txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) | 5120256200Sjfv E1000_TXDCTL_FULL_TX_DESC_WB); 5121256200Sjfv txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) | 5122256200Sjfv E1000_TXDCTL_MAX_TX_DESC_PREFETCH); 5123173788Sjfv E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl); 5124173788Sjfv txdctl = E1000_READ_REG(hw, E1000_TXDCTL(1)); 5125256200Sjfv txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) | 5126256200Sjfv E1000_TXDCTL_FULL_TX_DESC_WB); 5127256200Sjfv txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) | 5128256200Sjfv E1000_TXDCTL_MAX_TX_DESC_PREFETCH); 5129173788Sjfv E1000_WRITE_REG(hw, E1000_TXDCTL(1), txdctl); 5130169240Sjfv 5131247064Sjfv /* ICH8 has opposite polarity of no_snoop bits. 5132173788Sjfv * By default, we should use snoop behavior. 5133173788Sjfv */ 5134169240Sjfv if (mac->type == e1000_ich8lan) 5135169240Sjfv snoop = PCIE_ICH8_SNOOP_ALL; 5136169240Sjfv else 5137200243Sjfv snoop = (u32) ~(PCIE_NO_SNOOP_ALL); 5138169240Sjfv e1000_set_pcie_no_snoop_generic(hw, snoop); 5139169240Sjfv 5140169240Sjfv ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 5141169240Sjfv ctrl_ext |= E1000_CTRL_EXT_RO_DIS; 5142169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 5143169240Sjfv 5144247064Sjfv /* Clear all of the statistics registers (clear on read). It is 5145169240Sjfv * important that we do this after we have tried to establish link 5146169240Sjfv * because the symbol error count will increment wildly if there 5147169240Sjfv * is no link. 5148169240Sjfv */ 5149169240Sjfv e1000_clear_hw_cntrs_ich8lan(hw); 5150169240Sjfv 5151169240Sjfv return ret_val; 5152169240Sjfv} 5153247064Sjfv 5154169240Sjfv/** 5155169240Sjfv * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits 5156169589Sjfv * @hw: pointer to the HW structure 5157169240Sjfv * 5158169240Sjfv * Sets/Clears required hardware bits necessary for correctly setting up the 5159169240Sjfv * hardware for transmit and receive. 5160169240Sjfv **/ 5161173788Sjfvstatic void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw) 5162169240Sjfv{ 5163169240Sjfv u32 reg; 5164169240Sjfv 5165169240Sjfv DEBUGFUNC("e1000_initialize_hw_bits_ich8lan"); 5166169240Sjfv 5167169240Sjfv /* Extended Device Control */ 5168169240Sjfv reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 5169169240Sjfv reg |= (1 << 22); 5170194865Sjfv /* Enable PHY low-power state when MAC is at D3 w/o WoL */ 5171194865Sjfv if (hw->mac.type >= e1000_pchlan) 5172194865Sjfv reg |= E1000_CTRL_EXT_PHYPDEN; 5173169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg); 5174169240Sjfv 5175169240Sjfv /* Transmit Descriptor Control 0 */ 5176173788Sjfv reg = E1000_READ_REG(hw, E1000_TXDCTL(0)); 5177169240Sjfv reg |= (1 << 22); 5178173788Sjfv E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg); 5179169240Sjfv 5180169240Sjfv /* Transmit Descriptor Control 1 */ 5181173788Sjfv reg = E1000_READ_REG(hw, E1000_TXDCTL(1)); 5182169240Sjfv reg |= (1 << 22); 5183173788Sjfv E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg); 5184169240Sjfv 5185169240Sjfv /* Transmit Arbitration Control 0 */ 5186173788Sjfv reg = E1000_READ_REG(hw, E1000_TARC(0)); 5187169240Sjfv if (hw->mac.type == e1000_ich8lan) 5188169240Sjfv reg |= (1 << 28) | (1 << 29); 5189169240Sjfv reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27); 5190173788Sjfv E1000_WRITE_REG(hw, E1000_TARC(0), reg); 5191169240Sjfv 5192169240Sjfv /* Transmit Arbitration Control 1 */ 5193173788Sjfv reg = E1000_READ_REG(hw, E1000_TARC(1)); 5194169240Sjfv if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR) 5195169240Sjfv reg &= ~(1 << 28); 5196169240Sjfv else 5197169240Sjfv reg |= (1 << 28); 5198169240Sjfv reg |= (1 << 24) | (1 << 26) | (1 << 30); 5199173788Sjfv E1000_WRITE_REG(hw, E1000_TARC(1), reg); 5200169240Sjfv 5201169240Sjfv /* Device Status */ 5202169240Sjfv if (hw->mac.type == e1000_ich8lan) { 5203169240Sjfv reg = E1000_READ_REG(hw, E1000_STATUS); 5204333213Smarius reg &= ~(1U << 31); 5205169240Sjfv E1000_WRITE_REG(hw, E1000_STATUS, reg); 5206169240Sjfv } 5207169240Sjfv 5208247064Sjfv /* work-around descriptor data corruption issue during nfs v2 udp 5209205869Sjfv * traffic, just disable the nfs filtering capability 5210205869Sjfv */ 5211205869Sjfv reg = E1000_READ_REG(hw, E1000_RFCTL); 5212205869Sjfv reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS); 5213256200Sjfv 5214247064Sjfv /* Disable IPv6 extension header parsing because some malformed 5215247064Sjfv * IPv6 headers can hang the Rx. 5216247064Sjfv */ 5217247064Sjfv if (hw->mac.type == e1000_ich8lan) 5218247064Sjfv reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS); 5219205869Sjfv E1000_WRITE_REG(hw, E1000_RFCTL, reg); 5220205869Sjfv 5221247064Sjfv /* Enable ECC on Lynxpoint */ 5222322955Smarius if (hw->mac.type >= e1000_pch_lpt) { 5223247064Sjfv reg = E1000_READ_REG(hw, E1000_PBECCSTS); 5224247064Sjfv reg |= E1000_PBECCSTS_ECC_ENABLE; 5225247064Sjfv E1000_WRITE_REG(hw, E1000_PBECCSTS, reg); 5226247064Sjfv 5227247064Sjfv reg = E1000_READ_REG(hw, E1000_CTRL); 5228247064Sjfv reg |= E1000_CTRL_MEHE; 5229247064Sjfv E1000_WRITE_REG(hw, E1000_CTRL, reg); 5230247064Sjfv } 5231247064Sjfv 5232169240Sjfv return; 5233169240Sjfv} 5234169240Sjfv 5235169240Sjfv/** 5236169240Sjfv * e1000_setup_link_ich8lan - Setup flow control and link settings 5237169589Sjfv * @hw: pointer to the HW structure 5238169240Sjfv * 5239169240Sjfv * Determines which flow control settings to use, then configures flow 5240169240Sjfv * control. Calls the appropriate media-specific link configuration 5241169240Sjfv * function. Assuming the adapter has a valid link partner, a valid link 5242169240Sjfv * should be established. Assumes the hardware has previously been reset 5243169240Sjfv * and the transmitter and receiver are not enabled. 5244169240Sjfv **/ 5245177867Sjfvstatic s32 e1000_setup_link_ich8lan(struct e1000_hw *hw) 5246169240Sjfv{ 5247247064Sjfv s32 ret_val; 5248169240Sjfv 5249169240Sjfv DEBUGFUNC("e1000_setup_link_ich8lan"); 5250169240Sjfv 5251177867Sjfv if (hw->phy.ops.check_reset_block(hw)) 5252247064Sjfv return E1000_SUCCESS; 5253169240Sjfv 5254247064Sjfv /* ICH parts do not have a word in the NVM to determine 5255169240Sjfv * the default flow control setting, so we explicitly 5256169240Sjfv * set it to full. 5257169240Sjfv */ 5258185353Sjfv if (hw->fc.requested_mode == e1000_fc_default) 5259185353Sjfv hw->fc.requested_mode = e1000_fc_full; 5260169240Sjfv 5261247064Sjfv /* Save off the requested flow control mode for use later. Depending 5262185353Sjfv * on the link partner's capabilities, we may or may not use this mode. 5263185353Sjfv */ 5264185353Sjfv hw->fc.current_mode = hw->fc.requested_mode; 5265169240Sjfv 5266185353Sjfv DEBUGOUT1("After fix-ups FlowControl is now = %x\n", 5267190872Sjfv hw->fc.current_mode); 5268169240Sjfv 5269169240Sjfv /* Continue to configure the copper link. */ 5270177867Sjfv ret_val = hw->mac.ops.setup_physical_interface(hw); 5271169240Sjfv if (ret_val) 5272247064Sjfv return ret_val; 5273169240Sjfv 5274173788Sjfv E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time); 5275194865Sjfv if ((hw->phy.type == e1000_phy_82578) || 5276213234Sjfv (hw->phy.type == e1000_phy_82579) || 5277247064Sjfv (hw->phy.type == e1000_phy_i217) || 5278194865Sjfv (hw->phy.type == e1000_phy_82577)) { 5279213234Sjfv E1000_WRITE_REG(hw, E1000_FCRTV_PCH, hw->fc.refresh_time); 5280213234Sjfv 5281194865Sjfv ret_val = hw->phy.ops.write_reg(hw, 5282228386Sjfv PHY_REG(BM_PORT_CTRL_PAGE, 27), 5283228386Sjfv hw->fc.pause_time); 5284194865Sjfv if (ret_val) 5285247064Sjfv return ret_val; 5286194865Sjfv } 5287169240Sjfv 5288247064Sjfv return e1000_set_fc_watermarks_generic(hw); 5289169240Sjfv} 5290169240Sjfv 5291169240Sjfv/** 5292169240Sjfv * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface 5293169589Sjfv * @hw: pointer to the HW structure 5294169240Sjfv * 5295169240Sjfv * Configures the kumeran interface to the PHY to wait the appropriate time 5296169240Sjfv * when polling the PHY, then call the generic setup_copper_link to finish 5297169240Sjfv * configuring the copper link. 5298169240Sjfv **/ 5299177867Sjfvstatic s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw) 5300169240Sjfv{ 5301169240Sjfv u32 ctrl; 5302169240Sjfv s32 ret_val; 5303169240Sjfv u16 reg_data; 5304169240Sjfv 5305169240Sjfv DEBUGFUNC("e1000_setup_copper_link_ich8lan"); 5306169240Sjfv 5307169240Sjfv ctrl = E1000_READ_REG(hw, E1000_CTRL); 5308169240Sjfv ctrl |= E1000_CTRL_SLU; 5309169240Sjfv ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 5310169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 5311169240Sjfv 5312247064Sjfv /* Set the mac to wait the maximum time between each iteration 5313169240Sjfv * and increase the max iterations when polling the phy; 5314173788Sjfv * this fixes erroneous timeouts at 10Mbps. 5315173788Sjfv */ 5316200243Sjfv ret_val = e1000_write_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_TIMEOUTS, 5317228386Sjfv 0xFFFF); 5318169240Sjfv if (ret_val) 5319247064Sjfv return ret_val; 5320194865Sjfv ret_val = e1000_read_kmrn_reg_generic(hw, 5321228386Sjfv E1000_KMRNCTRLSTA_INBAND_PARAM, 5322228386Sjfv ®_data); 5323169240Sjfv if (ret_val) 5324247064Sjfv return ret_val; 5325169240Sjfv reg_data |= 0x3F; 5326194865Sjfv ret_val = e1000_write_kmrn_reg_generic(hw, 5327228386Sjfv E1000_KMRNCTRLSTA_INBAND_PARAM, 5328228386Sjfv reg_data); 5329169240Sjfv if (ret_val) 5330247064Sjfv return ret_val; 5331169240Sjfv 5332190872Sjfv switch (hw->phy.type) { 5333190872Sjfv case e1000_phy_igp_3: 5334169240Sjfv ret_val = e1000_copper_link_setup_igp(hw); 5335169240Sjfv if (ret_val) 5336247064Sjfv return ret_val; 5337190872Sjfv break; 5338190872Sjfv case e1000_phy_bm: 5339194865Sjfv case e1000_phy_82578: 5340176667Sjfv ret_val = e1000_copper_link_setup_m88(hw); 5341176667Sjfv if (ret_val) 5342247064Sjfv return ret_val; 5343190872Sjfv break; 5344194865Sjfv case e1000_phy_82577: 5345213234Sjfv case e1000_phy_82579: 5346194865Sjfv ret_val = e1000_copper_link_setup_82577(hw); 5347194865Sjfv if (ret_val) 5348247064Sjfv return ret_val; 5349194865Sjfv break; 5350190872Sjfv case e1000_phy_ife: 5351177867Sjfv ret_val = hw->phy.ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, 5352228386Sjfv ®_data); 5353173788Sjfv if (ret_val) 5354247064Sjfv return ret_val; 5355173788Sjfv 5356173788Sjfv reg_data &= ~IFE_PMC_AUTO_MDIX; 5357173788Sjfv 5358173788Sjfv switch (hw->phy.mdix) { 5359173788Sjfv case 1: 5360173788Sjfv reg_data &= ~IFE_PMC_FORCE_MDIX; 5361173788Sjfv break; 5362173788Sjfv case 2: 5363173788Sjfv reg_data |= IFE_PMC_FORCE_MDIX; 5364173788Sjfv break; 5365173788Sjfv case 0: 5366173788Sjfv default: 5367173788Sjfv reg_data |= IFE_PMC_AUTO_MDIX; 5368173788Sjfv break; 5369173788Sjfv } 5370177867Sjfv ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_MDIX_CONTROL, 5371228386Sjfv reg_data); 5372173788Sjfv if (ret_val) 5373247064Sjfv return ret_val; 5374190872Sjfv break; 5375190872Sjfv default: 5376190872Sjfv break; 5377173788Sjfv } 5378169240Sjfv 5379247064Sjfv return e1000_setup_copper_link_generic(hw); 5380169240Sjfv} 5381169240Sjfv 5382169240Sjfv/** 5383247064Sjfv * e1000_setup_copper_link_pch_lpt - Configure MAC/PHY interface 5384247064Sjfv * @hw: pointer to the HW structure 5385247064Sjfv * 5386247064Sjfv * Calls the PHY specific link setup function and then calls the 5387247064Sjfv * generic setup_copper_link to finish configuring the link for 5388247064Sjfv * Lynxpoint PCH devices 5389247064Sjfv **/ 5390247064Sjfvstatic s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw) 5391247064Sjfv{ 5392247064Sjfv u32 ctrl; 5393247064Sjfv s32 ret_val; 5394247064Sjfv 5395247064Sjfv DEBUGFUNC("e1000_setup_copper_link_pch_lpt"); 5396247064Sjfv 5397247064Sjfv ctrl = E1000_READ_REG(hw, E1000_CTRL); 5398247064Sjfv ctrl |= E1000_CTRL_SLU; 5399247064Sjfv ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 5400247064Sjfv E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 5401247064Sjfv 5402247064Sjfv ret_val = e1000_copper_link_setup_82577(hw); 5403247064Sjfv if (ret_val) 5404247064Sjfv return ret_val; 5405247064Sjfv 5406247064Sjfv return e1000_setup_copper_link_generic(hw); 5407247064Sjfv} 5408247064Sjfv 5409247064Sjfv/** 5410169240Sjfv * e1000_get_link_up_info_ich8lan - Get current link speed and duplex 5411169589Sjfv * @hw: pointer to the HW structure 5412169589Sjfv * @speed: pointer to store current link speed 5413169589Sjfv * @duplex: pointer to store the current link duplex 5414169240Sjfv * 5415176667Sjfv * Calls the generic get_speed_and_duplex to retrieve the current link 5416169240Sjfv * information and then calls the Kumeran lock loss workaround for links at 5417169240Sjfv * gigabit speeds. 5418169240Sjfv **/ 5419177867Sjfvstatic s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed, 5420228386Sjfv u16 *duplex) 5421169240Sjfv{ 5422169240Sjfv s32 ret_val; 5423169240Sjfv 5424169240Sjfv DEBUGFUNC("e1000_get_link_up_info_ich8lan"); 5425169240Sjfv 5426169240Sjfv ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, duplex); 5427169240Sjfv if (ret_val) 5428247064Sjfv return ret_val; 5429169240Sjfv 5430169240Sjfv if ((hw->mac.type == e1000_ich8lan) && 5431169240Sjfv (hw->phy.type == e1000_phy_igp_3) && 5432169240Sjfv (*speed == SPEED_1000)) { 5433169240Sjfv ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw); 5434169240Sjfv } 5435169240Sjfv 5436169240Sjfv return ret_val; 5437169240Sjfv} 5438169240Sjfv 5439169240Sjfv/** 5440169240Sjfv * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround 5441169589Sjfv * @hw: pointer to the HW structure 5442169240Sjfv * 5443169240Sjfv * Work-around for 82566 Kumeran PCS lock loss: 5444169240Sjfv * On link status change (i.e. PCI reset, speed change) and link is up and 5445169240Sjfv * speed is gigabit- 5446169240Sjfv * 0) if workaround is optionally disabled do nothing 5447169240Sjfv * 1) wait 1ms for Kumeran link to come up 5448169240Sjfv * 2) check Kumeran Diagnostic register PCS lock loss bit 5449169240Sjfv * 3) if not set the link is locked (all is good), otherwise... 5450169240Sjfv * 4) reset the PHY 5451169240Sjfv * 5) repeat up to 10 times 5452169240Sjfv * Note: this is only called for IGP3 copper when speed is 1gb. 5453169240Sjfv **/ 5454173788Sjfvstatic s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw) 5455169240Sjfv{ 5456185353Sjfv struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 5457169240Sjfv u32 phy_ctrl; 5458247064Sjfv s32 ret_val; 5459169240Sjfv u16 i, data; 5460173788Sjfv bool link; 5461169240Sjfv 5462169240Sjfv DEBUGFUNC("e1000_kmrn_lock_loss_workaround_ich8lan"); 5463169240Sjfv 5464218588Sjfv if (!dev_spec->kmrn_lock_loss_workaround_enabled) 5465247064Sjfv return E1000_SUCCESS; 5466169240Sjfv 5467247064Sjfv /* Make sure link is up before proceeding. If not just return. 5468169240Sjfv * Attempting this while link is negotiating fouled up link 5469173788Sjfv * stability 5470173788Sjfv */ 5471169240Sjfv ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 5472247064Sjfv if (!link) 5473247064Sjfv return E1000_SUCCESS; 5474169240Sjfv 5475169240Sjfv for (i = 0; i < 10; i++) { 5476169240Sjfv /* read once to clear */ 5477177867Sjfv ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data); 5478169240Sjfv if (ret_val) 5479247064Sjfv return ret_val; 5480169240Sjfv /* and again to get new status */ 5481177867Sjfv ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data); 5482169240Sjfv if (ret_val) 5483247064Sjfv return ret_val; 5484169240Sjfv 5485169240Sjfv /* check for PCS lock */ 5486247064Sjfv if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS)) 5487247064Sjfv return E1000_SUCCESS; 5488169240Sjfv 5489169240Sjfv /* Issue PHY reset */ 5490177867Sjfv hw->phy.ops.reset(hw); 5491169240Sjfv msec_delay_irq(5); 5492169240Sjfv } 5493169240Sjfv /* Disable GigE link negotiation */ 5494169240Sjfv phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL); 5495169240Sjfv phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE | 5496228386Sjfv E1000_PHY_CTRL_NOND0A_GBE_DISABLE); 5497169240Sjfv E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); 5498169240Sjfv 5499247064Sjfv /* Call gig speed drop workaround on Gig disable before accessing 5500173788Sjfv * any PHY registers 5501173788Sjfv */ 5502169240Sjfv e1000_gig_downshift_workaround_ich8lan(hw); 5503169240Sjfv 5504169240Sjfv /* unable to acquire PCS lock */ 5505247064Sjfv return -E1000_ERR_PHY; 5506169240Sjfv} 5507169240Sjfv 5508169240Sjfv/** 5509176667Sjfv * e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state 5510169589Sjfv * @hw: pointer to the HW structure 5511176667Sjfv * @state: boolean value used to set the current Kumeran workaround state 5512169240Sjfv * 5513169240Sjfv * If ICH8, set the current Kumeran workaround state (enabled - TRUE 5514169240Sjfv * /disabled - FALSE). 5515169240Sjfv **/ 5516173788Sjfvvoid e1000_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw, 5517228386Sjfv bool state) 5518169240Sjfv{ 5519185353Sjfv struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 5520169240Sjfv 5521169240Sjfv DEBUGFUNC("e1000_set_kmrn_lock_loss_workaround_ich8lan"); 5522169240Sjfv 5523169240Sjfv if (hw->mac.type != e1000_ich8lan) { 5524169240Sjfv DEBUGOUT("Workaround applies to ICH8 only.\n"); 5525185353Sjfv return; 5526169240Sjfv } 5527169240Sjfv 5528169240Sjfv dev_spec->kmrn_lock_loss_workaround_enabled = state; 5529169240Sjfv 5530169240Sjfv return; 5531169240Sjfv} 5532169240Sjfv 5533169240Sjfv/** 5534169240Sjfv * e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3 5535169589Sjfv * @hw: pointer to the HW structure 5536169240Sjfv * 5537169240Sjfv * Workaround for 82566 power-down on D3 entry: 5538169240Sjfv * 1) disable gigabit link 5539169240Sjfv * 2) write VR power-down enable 5540169240Sjfv * 3) read it back 5541169240Sjfv * Continue if successful, else issue LCD reset and repeat 5542169240Sjfv **/ 5543173788Sjfvvoid e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw) 5544169240Sjfv{ 5545169240Sjfv u32 reg; 5546169240Sjfv u16 data; 5547169240Sjfv u8 retry = 0; 5548169240Sjfv 5549169240Sjfv DEBUGFUNC("e1000_igp3_phy_powerdown_workaround_ich8lan"); 5550169240Sjfv 5551169240Sjfv if (hw->phy.type != e1000_phy_igp_3) 5552247064Sjfv return; 5553169240Sjfv 5554169240Sjfv /* Try the workaround twice (if needed) */ 5555169240Sjfv do { 5556169240Sjfv /* Disable link */ 5557169240Sjfv reg = E1000_READ_REG(hw, E1000_PHY_CTRL); 5558169240Sjfv reg |= (E1000_PHY_CTRL_GBE_DISABLE | 5559228386Sjfv E1000_PHY_CTRL_NOND0A_GBE_DISABLE); 5560169240Sjfv E1000_WRITE_REG(hw, E1000_PHY_CTRL, reg); 5561169240Sjfv 5562247064Sjfv /* Call gig speed drop workaround on Gig disable before 5563173788Sjfv * accessing any PHY registers 5564173788Sjfv */ 5565169240Sjfv if (hw->mac.type == e1000_ich8lan) 5566169240Sjfv e1000_gig_downshift_workaround_ich8lan(hw); 5567169240Sjfv 5568169240Sjfv /* Write VR power-down enable */ 5569177867Sjfv hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data); 5570169240Sjfv data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK; 5571185353Sjfv hw->phy.ops.write_reg(hw, IGP3_VR_CTRL, 5572228386Sjfv data | IGP3_VR_CTRL_MODE_SHUTDOWN); 5573169240Sjfv 5574169240Sjfv /* Read it back and test */ 5575177867Sjfv hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data); 5576169589Sjfv data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK; 5577169589Sjfv if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry) 5578169240Sjfv break; 5579169240Sjfv 5580169240Sjfv /* Issue PHY reset and repeat at most one more time */ 5581169240Sjfv reg = E1000_READ_REG(hw, E1000_CTRL); 5582169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, reg | E1000_CTRL_PHY_RST); 5583169240Sjfv retry++; 5584169240Sjfv } while (retry); 5585169240Sjfv} 5586169240Sjfv 5587169240Sjfv/** 5588169240Sjfv * e1000_gig_downshift_workaround_ich8lan - WoL from S5 stops working 5589169589Sjfv * @hw: pointer to the HW structure 5590169240Sjfv * 5591169240Sjfv * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC), 5592176667Sjfv * LPLU, Gig disable, MDIC PHY reset): 5593169240Sjfv * 1) Set Kumeran Near-end loopback 5594169240Sjfv * 2) Clear Kumeran Near-end loopback 5595228386Sjfv * Should only be called for ICH8[m] devices with any 1G Phy. 5596169240Sjfv **/ 5597173788Sjfvvoid e1000_gig_downshift_workaround_ich8lan(struct e1000_hw *hw) 5598169240Sjfv{ 5599247064Sjfv s32 ret_val; 5600169240Sjfv u16 reg_data; 5601169240Sjfv 5602169240Sjfv DEBUGFUNC("e1000_gig_downshift_workaround_ich8lan"); 5603169240Sjfv 5604169240Sjfv if ((hw->mac.type != e1000_ich8lan) || 5605228386Sjfv (hw->phy.type == e1000_phy_ife)) 5606247064Sjfv return; 5607169240Sjfv 5608181027Sjfv ret_val = e1000_read_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, 5609228386Sjfv ®_data); 5610169240Sjfv if (ret_val) 5611247064Sjfv return; 5612169240Sjfv reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK; 5613181027Sjfv ret_val = e1000_write_kmrn_reg_generic(hw, 5614228386Sjfv E1000_KMRNCTRLSTA_DIAG_OFFSET, 5615228386Sjfv reg_data); 5616169240Sjfv if (ret_val) 5617247064Sjfv return; 5618169240Sjfv reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK; 5619247064Sjfv e1000_write_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, 5620247064Sjfv reg_data); 5621169240Sjfv} 5622169240Sjfv 5623169240Sjfv/** 5624228386Sjfv * e1000_suspend_workarounds_ich8lan - workarounds needed during S0->Sx 5625176667Sjfv * @hw: pointer to the HW structure 5626176667Sjfv * 5627176667Sjfv * During S0 to Sx transition, it is possible the link remains at gig 5628176667Sjfv * instead of negotiating to a lower speed. Before going to Sx, set 5629228386Sjfv * 'Gig Disable' to force link speed negotiation to a lower speed based on 5630228386Sjfv * the LPLU setting in the NVM or custom setting. For PCH and newer parts, 5631228386Sjfv * the OEM bits PHY register (LED, GbE disable and LPLU configurations) also 5632228386Sjfv * needs to be written. 5633247064Sjfv * Parts that support (and are linked to a partner which support) EEE in 5634247064Sjfv * 100Mbps should disable LPLU since 100Mbps w/ EEE requires less power 5635247064Sjfv * than 10Mbps w/o EEE. 5636176667Sjfv **/ 5637228386Sjfvvoid e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw) 5638176667Sjfv{ 5639247064Sjfv struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 5640176667Sjfv u32 phy_ctrl; 5641213234Sjfv s32 ret_val; 5642176667Sjfv 5643228386Sjfv DEBUGFUNC("e1000_suspend_workarounds_ich8lan"); 5644194865Sjfv 5645213234Sjfv phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL); 5646228386Sjfv phy_ctrl |= E1000_PHY_CTRL_GBE_DISABLE; 5647247064Sjfv 5648247064Sjfv if (hw->phy.type == e1000_phy_i217) { 5649247064Sjfv u16 phy_reg, device_id = hw->device_id; 5650247064Sjfv 5651247064Sjfv if ((device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) || 5652267935Sjfv (device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) || 5653267935Sjfv (device_id == E1000_DEV_ID_PCH_I218_LM3) || 5654295323Serj (device_id == E1000_DEV_ID_PCH_I218_V3) || 5655322955Smarius (hw->mac.type >= e1000_pch_spt)) { 5656247064Sjfv u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6); 5657247064Sjfv 5658247064Sjfv E1000_WRITE_REG(hw, E1000_FEXTNVM6, 5659247064Sjfv fextnvm6 & ~E1000_FEXTNVM6_REQ_PLL_CLK); 5660247064Sjfv } 5661247064Sjfv 5662247064Sjfv ret_val = hw->phy.ops.acquire(hw); 5663247064Sjfv if (ret_val) 5664247064Sjfv goto out; 5665247064Sjfv 5666247064Sjfv if (!dev_spec->eee_disable) { 5667247064Sjfv u16 eee_advert; 5668247064Sjfv 5669247064Sjfv ret_val = 5670247064Sjfv e1000_read_emi_reg_locked(hw, 5671247064Sjfv I217_EEE_ADVERTISEMENT, 5672247064Sjfv &eee_advert); 5673247064Sjfv if (ret_val) 5674247064Sjfv goto release; 5675247064Sjfv 5676247064Sjfv /* Disable LPLU if both link partners support 100BaseT 5677247064Sjfv * EEE and 100Full is advertised on both ends of the 5678256200Sjfv * link, and enable Auto Enable LPI since there will 5679256200Sjfv * be no driver to enable LPI while in Sx. 5680247064Sjfv */ 5681247064Sjfv if ((eee_advert & I82579_EEE_100_SUPPORTED) && 5682247064Sjfv (dev_spec->eee_lp_ability & 5683247064Sjfv I82579_EEE_100_SUPPORTED) && 5684256200Sjfv (hw->phy.autoneg_advertised & ADVERTISE_100_FULL)) { 5685247064Sjfv phy_ctrl &= ~(E1000_PHY_CTRL_D0A_LPLU | 5686247064Sjfv E1000_PHY_CTRL_NOND0A_LPLU); 5687256200Sjfv 5688256200Sjfv /* Set Auto Enable LPI after link up */ 5689256200Sjfv hw->phy.ops.read_reg_locked(hw, 5690256200Sjfv I217_LPI_GPIO_CTRL, 5691256200Sjfv &phy_reg); 5692256200Sjfv phy_reg |= I217_LPI_GPIO_CTRL_AUTO_EN_LPI; 5693256200Sjfv hw->phy.ops.write_reg_locked(hw, 5694256200Sjfv I217_LPI_GPIO_CTRL, 5695256200Sjfv phy_reg); 5696256200Sjfv } 5697247064Sjfv } 5698247064Sjfv 5699247064Sjfv /* For i217 Intel Rapid Start Technology support, 5700247064Sjfv * when the system is going into Sx and no manageability engine 5701247064Sjfv * is present, the driver must configure proxy to reset only on 5702247064Sjfv * power good. LPI (Low Power Idle) state must also reset only 5703247064Sjfv * on power good, as well as the MTA (Multicast table array). 5704247064Sjfv * The SMBus release must also be disabled on LCD reset. 5705247064Sjfv */ 5706247064Sjfv if (!(E1000_READ_REG(hw, E1000_FWSM) & 5707267935Sjfv E1000_ICH_FWSM_FW_VALID)) { 5708247064Sjfv /* Enable proxy to reset only on power good. */ 5709247064Sjfv hw->phy.ops.read_reg_locked(hw, I217_PROXY_CTRL, 5710247064Sjfv &phy_reg); 5711247064Sjfv phy_reg |= I217_PROXY_CTRL_AUTO_DISABLE; 5712247064Sjfv hw->phy.ops.write_reg_locked(hw, I217_PROXY_CTRL, 5713247064Sjfv phy_reg); 5714247064Sjfv 5715247064Sjfv /* Set bit enable LPI (EEE) to reset only on 5716247064Sjfv * power good. 5717247064Sjfv */ 5718247064Sjfv hw->phy.ops.read_reg_locked(hw, I217_SxCTRL, &phy_reg); 5719247064Sjfv phy_reg |= I217_SxCTRL_ENABLE_LPI_RESET; 5720247064Sjfv hw->phy.ops.write_reg_locked(hw, I217_SxCTRL, phy_reg); 5721247064Sjfv 5722247064Sjfv /* Disable the SMB release on LCD reset. */ 5723247064Sjfv hw->phy.ops.read_reg_locked(hw, I217_MEMPWR, &phy_reg); 5724247064Sjfv phy_reg &= ~I217_MEMPWR_DISABLE_SMB_RELEASE; 5725247064Sjfv hw->phy.ops.write_reg_locked(hw, I217_MEMPWR, phy_reg); 5726247064Sjfv } 5727247064Sjfv 5728247064Sjfv /* Enable MTA to reset for Intel Rapid Start Technology 5729247064Sjfv * Support 5730247064Sjfv */ 5731247064Sjfv hw->phy.ops.read_reg_locked(hw, I217_CGFREG, &phy_reg); 5732247064Sjfv phy_reg |= I217_CGFREG_ENABLE_MTA_RESET; 5733247064Sjfv hw->phy.ops.write_reg_locked(hw, I217_CGFREG, phy_reg); 5734247064Sjfv 5735247064Sjfvrelease: 5736247064Sjfv hw->phy.ops.release(hw); 5737247064Sjfv } 5738247064Sjfvout: 5739213234Sjfv E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); 5740247064Sjfv 5741228386Sjfv if (hw->mac.type == e1000_ich8lan) 5742228386Sjfv e1000_gig_downshift_workaround_ich8lan(hw); 5743213234Sjfv 5744213234Sjfv if (hw->mac.type >= e1000_pchlan) { 5745213234Sjfv e1000_oem_bits_config_ich8lan(hw, FALSE); 5746247064Sjfv 5747247064Sjfv /* Reset PHY to activate OEM bits on 82577/8 */ 5748247064Sjfv if (hw->mac.type == e1000_pchlan) 5749247064Sjfv e1000_phy_hw_reset_generic(hw); 5750247064Sjfv 5751213234Sjfv ret_val = hw->phy.ops.acquire(hw); 5752213234Sjfv if (ret_val) 5753213234Sjfv return; 5754213234Sjfv e1000_write_smbus_addr(hw); 5755213234Sjfv hw->phy.ops.release(hw); 5756176667Sjfv } 5757176667Sjfv 5758176667Sjfv return; 5759176667Sjfv} 5760176667Sjfv 5761176667Sjfv/** 5762228386Sjfv * e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0 5763228386Sjfv * @hw: pointer to the HW structure 5764228386Sjfv * 5765228386Sjfv * During Sx to S0 transitions on non-managed devices or managed devices 5766228386Sjfv * on which PHY resets are not blocked, if the PHY registers cannot be 5767228386Sjfv * accessed properly by the s/w toggle the LANPHYPC value to power cycle 5768228386Sjfv * the PHY. 5769247064Sjfv * On i217, setup Intel Rapid Start Technology. 5770228386Sjfv **/ 5771295323Serju32 e1000_resume_workarounds_pchlan(struct e1000_hw *hw) 5772228386Sjfv{ 5773228386Sjfv s32 ret_val; 5774228386Sjfv 5775228386Sjfv DEBUGFUNC("e1000_resume_workarounds_pchlan"); 5776247064Sjfv if (hw->mac.type < e1000_pch2lan) 5777295323Serj return E1000_SUCCESS; 5778228386Sjfv 5779247064Sjfv ret_val = e1000_init_phy_workarounds_pchlan(hw); 5780228386Sjfv if (ret_val) { 5781247064Sjfv DEBUGOUT1("Failed to init PHY flow ret_val=%d\n", ret_val); 5782295323Serj return ret_val; 5783228386Sjfv } 5784228386Sjfv 5785247064Sjfv /* For i217 Intel Rapid Start Technology support when the system 5786247064Sjfv * is transitioning from Sx and no manageability engine is present 5787247064Sjfv * configure SMBus to restore on reset, disable proxy, and enable 5788247064Sjfv * the reset on MTA (Multicast table array). 5789247064Sjfv */ 5790247064Sjfv if (hw->phy.type == e1000_phy_i217) { 5791247064Sjfv u16 phy_reg; 5792228386Sjfv 5793247064Sjfv ret_val = hw->phy.ops.acquire(hw); 5794247064Sjfv if (ret_val) { 5795247064Sjfv DEBUGOUT("Failed to setup iRST\n"); 5796295323Serj return ret_val; 5797247064Sjfv } 5798228386Sjfv 5799256200Sjfv /* Clear Auto Enable LPI after link up */ 5800256200Sjfv hw->phy.ops.read_reg_locked(hw, I217_LPI_GPIO_CTRL, &phy_reg); 5801256200Sjfv phy_reg &= ~I217_LPI_GPIO_CTRL_AUTO_EN_LPI; 5802256200Sjfv hw->phy.ops.write_reg_locked(hw, I217_LPI_GPIO_CTRL, phy_reg); 5803256200Sjfv 5804247064Sjfv if (!(E1000_READ_REG(hw, E1000_FWSM) & 5805247064Sjfv E1000_ICH_FWSM_FW_VALID)) { 5806247064Sjfv /* Restore clear on SMB if no manageability engine 5807247064Sjfv * is present 5808247064Sjfv */ 5809247064Sjfv ret_val = hw->phy.ops.read_reg_locked(hw, I217_MEMPWR, 5810247064Sjfv &phy_reg); 5811247064Sjfv if (ret_val) 5812247064Sjfv goto release; 5813247064Sjfv phy_reg |= I217_MEMPWR_DISABLE_SMB_RELEASE; 5814247064Sjfv hw->phy.ops.write_reg_locked(hw, I217_MEMPWR, phy_reg); 5815228386Sjfv 5816247064Sjfv /* Disable Proxy */ 5817247064Sjfv hw->phy.ops.write_reg_locked(hw, I217_PROXY_CTRL, 0); 5818247064Sjfv } 5819247064Sjfv /* Enable reset on MTA */ 5820247064Sjfv ret_val = hw->phy.ops.read_reg_locked(hw, I217_CGFREG, 5821247064Sjfv &phy_reg); 5822247064Sjfv if (ret_val) 5823247064Sjfv goto release; 5824247064Sjfv phy_reg &= ~I217_CGFREG_ENABLE_MTA_RESET; 5825247064Sjfv hw->phy.ops.write_reg_locked(hw, I217_CGFREG, phy_reg); 5826228386Sjfvrelease: 5827247064Sjfv if (ret_val) 5828247064Sjfv DEBUGOUT1("Error %d in resume workarounds\n", ret_val); 5829247064Sjfv hw->phy.ops.release(hw); 5830295323Serj return ret_val; 5831247064Sjfv } 5832295323Serj return E1000_SUCCESS; 5833228386Sjfv} 5834228386Sjfv 5835228386Sjfv/** 5836169240Sjfv * e1000_cleanup_led_ich8lan - Restore the default LED operation 5837169589Sjfv * @hw: pointer to the HW structure 5838169240Sjfv * 5839169240Sjfv * Return the LED back to the default configuration. 5840169240Sjfv **/ 5841177867Sjfvstatic s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw) 5842169240Sjfv{ 5843169240Sjfv DEBUGFUNC("e1000_cleanup_led_ich8lan"); 5844169240Sjfv 5845169240Sjfv if (hw->phy.type == e1000_phy_ife) 5846203049Sjfv return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED, 5847228386Sjfv 0); 5848169240Sjfv 5849203049Sjfv E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default); 5850203049Sjfv return E1000_SUCCESS; 5851169240Sjfv} 5852169240Sjfv 5853169240Sjfv/** 5854176667Sjfv * e1000_led_on_ich8lan - Turn LEDs on 5855169589Sjfv * @hw: pointer to the HW structure 5856169240Sjfv * 5857176667Sjfv * Turn on the LEDs. 5858169240Sjfv **/ 5859177867Sjfvstatic s32 e1000_led_on_ich8lan(struct e1000_hw *hw) 5860169240Sjfv{ 5861169240Sjfv DEBUGFUNC("e1000_led_on_ich8lan"); 5862169240Sjfv 5863169240Sjfv if (hw->phy.type == e1000_phy_ife) 5864203049Sjfv return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED, 5865228386Sjfv (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON)); 5866169240Sjfv 5867203049Sjfv E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2); 5868203049Sjfv return E1000_SUCCESS; 5869169240Sjfv} 5870169240Sjfv 5871169240Sjfv/** 5872176667Sjfv * e1000_led_off_ich8lan - Turn LEDs off 5873169589Sjfv * @hw: pointer to the HW structure 5874169240Sjfv * 5875176667Sjfv * Turn off the LEDs. 5876169240Sjfv **/ 5877177867Sjfvstatic s32 e1000_led_off_ich8lan(struct e1000_hw *hw) 5878169240Sjfv{ 5879169240Sjfv DEBUGFUNC("e1000_led_off_ich8lan"); 5880169240Sjfv 5881169240Sjfv if (hw->phy.type == e1000_phy_ife) 5882203049Sjfv return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED, 5883228386Sjfv (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF)); 5884169240Sjfv 5885203049Sjfv E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1); 5886203049Sjfv return E1000_SUCCESS; 5887169240Sjfv} 5888169240Sjfv 5889169240Sjfv/** 5890194865Sjfv * e1000_setup_led_pchlan - Configures SW controllable LED 5891194865Sjfv * @hw: pointer to the HW structure 5892194865Sjfv * 5893194865Sjfv * This prepares the SW controllable LED for use. 5894194865Sjfv **/ 5895194865Sjfvstatic s32 e1000_setup_led_pchlan(struct e1000_hw *hw) 5896194865Sjfv{ 5897194865Sjfv DEBUGFUNC("e1000_setup_led_pchlan"); 5898194865Sjfv 5899194865Sjfv return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, 5900228386Sjfv (u16)hw->mac.ledctl_mode1); 5901194865Sjfv} 5902194865Sjfv 5903194865Sjfv/** 5904194865Sjfv * e1000_cleanup_led_pchlan - Restore the default LED operation 5905194865Sjfv * @hw: pointer to the HW structure 5906194865Sjfv * 5907194865Sjfv * Return the LED back to the default configuration. 5908194865Sjfv **/ 5909194865Sjfvstatic s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw) 5910194865Sjfv{ 5911194865Sjfv DEBUGFUNC("e1000_cleanup_led_pchlan"); 5912194865Sjfv 5913194865Sjfv return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, 5914228386Sjfv (u16)hw->mac.ledctl_default); 5915194865Sjfv} 5916194865Sjfv 5917194865Sjfv/** 5918194865Sjfv * e1000_led_on_pchlan - Turn LEDs on 5919194865Sjfv * @hw: pointer to the HW structure 5920194865Sjfv * 5921194865Sjfv * Turn on the LEDs. 5922194865Sjfv **/ 5923194865Sjfvstatic s32 e1000_led_on_pchlan(struct e1000_hw *hw) 5924194865Sjfv{ 5925194865Sjfv u16 data = (u16)hw->mac.ledctl_mode2; 5926194865Sjfv u32 i, led; 5927194865Sjfv 5928194865Sjfv DEBUGFUNC("e1000_led_on_pchlan"); 5929194865Sjfv 5930247064Sjfv /* If no link, then turn LED on by setting the invert bit 5931194865Sjfv * for each LED that's mode is "link_up" in ledctl_mode2. 5932194865Sjfv */ 5933194865Sjfv if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) { 5934194865Sjfv for (i = 0; i < 3; i++) { 5935194865Sjfv led = (data >> (i * 5)) & E1000_PHY_LED0_MASK; 5936194865Sjfv if ((led & E1000_PHY_LED0_MODE_MASK) != 5937194865Sjfv E1000_LEDCTL_MODE_LINK_UP) 5938194865Sjfv continue; 5939194865Sjfv if (led & E1000_PHY_LED0_IVRT) 5940194865Sjfv data &= ~(E1000_PHY_LED0_IVRT << (i * 5)); 5941194865Sjfv else 5942194865Sjfv data |= (E1000_PHY_LED0_IVRT << (i * 5)); 5943194865Sjfv } 5944194865Sjfv } 5945194865Sjfv 5946194865Sjfv return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data); 5947194865Sjfv} 5948194865Sjfv 5949194865Sjfv/** 5950194865Sjfv * e1000_led_off_pchlan - Turn LEDs off 5951194865Sjfv * @hw: pointer to the HW structure 5952194865Sjfv * 5953194865Sjfv * Turn off the LEDs. 5954194865Sjfv **/ 5955194865Sjfvstatic s32 e1000_led_off_pchlan(struct e1000_hw *hw) 5956194865Sjfv{ 5957194865Sjfv u16 data = (u16)hw->mac.ledctl_mode1; 5958194865Sjfv u32 i, led; 5959194865Sjfv 5960194865Sjfv DEBUGFUNC("e1000_led_off_pchlan"); 5961194865Sjfv 5962247064Sjfv /* If no link, then turn LED off by clearing the invert bit 5963194865Sjfv * for each LED that's mode is "link_up" in ledctl_mode1. 5964194865Sjfv */ 5965194865Sjfv if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) { 5966194865Sjfv for (i = 0; i < 3; i++) { 5967194865Sjfv led = (data >> (i * 5)) & E1000_PHY_LED0_MASK; 5968194865Sjfv if ((led & E1000_PHY_LED0_MODE_MASK) != 5969194865Sjfv E1000_LEDCTL_MODE_LINK_UP) 5970194865Sjfv continue; 5971194865Sjfv if (led & E1000_PHY_LED0_IVRT) 5972194865Sjfv data &= ~(E1000_PHY_LED0_IVRT << (i * 5)); 5973194865Sjfv else 5974194865Sjfv data |= (E1000_PHY_LED0_IVRT << (i * 5)); 5975194865Sjfv } 5976194865Sjfv } 5977194865Sjfv 5978194865Sjfv return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data); 5979194865Sjfv} 5980194865Sjfv 5981194865Sjfv/** 5982213234Sjfv * e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset 5983169589Sjfv * @hw: pointer to the HW structure 5984169240Sjfv * 5985213234Sjfv * Read appropriate register for the config done bit for completion status 5986213234Sjfv * and configure the PHY through s/w for EEPROM-less parts. 5987213234Sjfv * 5988213234Sjfv * NOTE: some silicon which is EEPROM-less will fail trying to read the 5989213234Sjfv * config done bit, so only an error is logged and continues. If we were 5990213234Sjfv * to return with error, EEPROM-less silicon would not be able to be reset 5991213234Sjfv * or change link. 5992169240Sjfv **/ 5993177867Sjfvstatic s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw) 5994169240Sjfv{ 5995173788Sjfv s32 ret_val = E1000_SUCCESS; 5996178523Sjfv u32 bank = 0; 5997213234Sjfv u32 status; 5998173788Sjfv 5999213234Sjfv DEBUGFUNC("e1000_get_cfg_done_ich8lan"); 6000194865Sjfv 6001213234Sjfv e1000_get_cfg_done_generic(hw); 6002213234Sjfv 6003213234Sjfv /* Wait for indication from h/w that it has completed basic config */ 6004213234Sjfv if (hw->mac.type >= e1000_ich10lan) { 6005213234Sjfv e1000_lan_init_done_ich8lan(hw); 6006213234Sjfv } else { 6007213234Sjfv ret_val = e1000_get_auto_rd_done_generic(hw); 6008213234Sjfv if (ret_val) { 6009247064Sjfv /* When auto config read does not complete, do not 6010213234Sjfv * return with an error. This can happen in situations 6011213234Sjfv * where there is no eeprom and prevents getting link. 6012213234Sjfv */ 6013213234Sjfv DEBUGOUT("Auto Read Done did not complete\n"); 6014213234Sjfv ret_val = E1000_SUCCESS; 6015213234Sjfv } 6016194865Sjfv } 6017194865Sjfv 6018213234Sjfv /* Clear PHY Reset Asserted bit */ 6019213234Sjfv status = E1000_READ_REG(hw, E1000_STATUS); 6020213234Sjfv if (status & E1000_STATUS_PHYRA) 6021213234Sjfv E1000_WRITE_REG(hw, E1000_STATUS, status & ~E1000_STATUS_PHYRA); 6022213234Sjfv else 6023213234Sjfv DEBUGOUT("PHY Reset Asserted not set - needs delay\n"); 6024169240Sjfv 6025169240Sjfv /* If EEPROM is not marked present, init the IGP 3 PHY manually */ 6026200243Sjfv if (hw->mac.type <= e1000_ich9lan) { 6027247064Sjfv if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) && 6028185353Sjfv (hw->phy.type == e1000_phy_igp_3)) { 6029178523Sjfv e1000_phy_init_script_igp3(hw); 6030178523Sjfv } 6031178523Sjfv } else { 6032178523Sjfv if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) { 6033185353Sjfv /* Maybe we should do a basic PHY config */ 6034178523Sjfv DEBUGOUT("EEPROM not present\n"); 6035178523Sjfv ret_val = -E1000_ERR_CONFIG; 6036178523Sjfv } 6037169240Sjfv } 6038169240Sjfv 6039173788Sjfv return ret_val; 6040169240Sjfv} 6041169240Sjfv 6042169240Sjfv/** 6043173788Sjfv * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down 6044173788Sjfv * @hw: pointer to the HW structure 6045173788Sjfv * 6046173788Sjfv * In the case of a PHY power down to save power, or to turn off link during a 6047173788Sjfv * driver unload, or wake on lan is not enabled, remove the link. 6048173788Sjfv **/ 6049177867Sjfvstatic void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw) 6050173788Sjfv{ 6051173788Sjfv /* If the management interface is not enabled, then power down */ 6052185353Sjfv if (!(hw->mac.ops.check_mng_mode(hw) || 6053185353Sjfv hw->phy.ops.check_reset_block(hw))) 6054173788Sjfv e1000_power_down_phy_copper(hw); 6055173788Sjfv 6056173788Sjfv return; 6057173788Sjfv} 6058173788Sjfv 6059173788Sjfv/** 6060169240Sjfv * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters 6061169589Sjfv * @hw: pointer to the HW structure 6062169240Sjfv * 6063169240Sjfv * Clears hardware counters specific to the silicon family and calls 6064169240Sjfv * clear_hw_cntrs_generic to clear all general purpose counters. 6065169240Sjfv **/ 6066177867Sjfvstatic void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw) 6067169240Sjfv{ 6068194865Sjfv u16 phy_data; 6069228386Sjfv s32 ret_val; 6070194865Sjfv 6071169240Sjfv DEBUGFUNC("e1000_clear_hw_cntrs_ich8lan"); 6072169240Sjfv 6073169240Sjfv e1000_clear_hw_cntrs_base_generic(hw); 6074169240Sjfv 6075185353Sjfv E1000_READ_REG(hw, E1000_ALGNERRC); 6076185353Sjfv E1000_READ_REG(hw, E1000_RXERRC); 6077185353Sjfv E1000_READ_REG(hw, E1000_TNCRS); 6078185353Sjfv E1000_READ_REG(hw, E1000_CEXTERR); 6079185353Sjfv E1000_READ_REG(hw, E1000_TSCTC); 6080185353Sjfv E1000_READ_REG(hw, E1000_TSCTFC); 6081169240Sjfv 6082185353Sjfv E1000_READ_REG(hw, E1000_MGTPRC); 6083185353Sjfv E1000_READ_REG(hw, E1000_MGTPDC); 6084185353Sjfv E1000_READ_REG(hw, E1000_MGTPTC); 6085169240Sjfv 6086185353Sjfv E1000_READ_REG(hw, E1000_IAC); 6087185353Sjfv E1000_READ_REG(hw, E1000_ICRXOC); 6088194865Sjfv 6089194865Sjfv /* Clear PHY statistics registers */ 6090194865Sjfv if ((hw->phy.type == e1000_phy_82578) || 6091213234Sjfv (hw->phy.type == e1000_phy_82579) || 6092247064Sjfv (hw->phy.type == e1000_phy_i217) || 6093194865Sjfv (hw->phy.type == e1000_phy_82577)) { 6094228386Sjfv ret_val = hw->phy.ops.acquire(hw); 6095228386Sjfv if (ret_val) 6096228386Sjfv return; 6097228386Sjfv ret_val = hw->phy.ops.set_page(hw, 6098228386Sjfv HV_STATS_PAGE << IGP_PAGE_SHIFT); 6099228386Sjfv if (ret_val) 6100228386Sjfv goto release; 6101228386Sjfv hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data); 6102228386Sjfv hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data); 6103228386Sjfv hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data); 6104228386Sjfv hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data); 6105228386Sjfv hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data); 6106228386Sjfv hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data); 6107228386Sjfv hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data); 6108228386Sjfv hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data); 6109228386Sjfv hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data); 6110228386Sjfv hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data); 6111228386Sjfv hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data); 6112228386Sjfv hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data); 6113228386Sjfv hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data); 6114228386Sjfv hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data); 6115228386Sjfvrelease: 6116228386Sjfv hw->phy.ops.release(hw); 6117194865Sjfv } 6118169240Sjfv} 6119169240Sjfv 6120