Searched refs:pcw (Results 1 - 7 of 7) sorted by relevance
| /linux-master/drivers/clk/mediatek/ |
| H A D | clk-pll.c | 41 u32 pcw, int postdiv)
54 vco = (u64)fin * pcw;
93 static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw, argument
106 /* postdiv and pcw need to set at the same time if on same register */
112 /* set pcw */
115 val |= pcw << pll->data->pcw_shift;
132 * @pcw: The pcw value (output)
138 void mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw, u32 *postdiv, argument
172 *pcw
40 __mtk_pll_recalc_rate(struct mtk_clk_pll *pll, u32 fin, u32 pcw, int postdiv) argument
179 u32 pcw = 0; local
192 u32 pcw; local
207 u32 pcw = 0; local
[all...] |
| H A D | clk-pll.h | 55 * MediaTek PLLs are configured through their pcw value. The pcw value describes
95 void mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw, u32 *postdiv,
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| H A D | clk-pllfh.c | 32 u32 pcw = 0; local
35 mtk_pll_calc_values(pll, &pcw, &postdiv, rate, parent_rate);
37 return fh->ops->hopping(fh, pcw, postdiv);
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| /linux-master/drivers/phy/mediatek/ |
| H A D | phy-mtk-mipi-dsi-mt8183.c | 52 u64 pcw; local
81 pcw = div_u64(((u64)mipi_tx->data_rate * txdiv) << 24, 26000000);
82 writel(pcw, base + MIPITX_PLL_CON0);
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| H A D | phy-mtk-mipi-dsi-mt8173.c | 127 u64 pcw; local
190 * PCW bit 24~30 = integer part of pcw
191 * PCW bit 0~23 = fractional part of pcw
192 * pcw = data_Rate*4*txdiv/(Ref_clk*2);
196 pcw = div_u64(((u64)mipi_tx->data_rate * 2 * txdiv) << 24, 26000000);
197 writel(pcw, base + MIPITX_DSI_PLL_CON2);
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| H A D | phy-mtk-hdmi-mt8195.c | 213 u64 tmds_clk, pixel_clk, da_hdmitx21_ref_ck, ns_hdmipll_ck, pcw; local
269 * formula: pcw=(frequency_out*2^pcw_bit) / frequency_in / FBKDIV_HS3;
273 pcw = div_u64(((u64)ns_hdmipll_ck) << PCW_DECIMAL_WIDTH,
276 if (pcw > GENMASK_ULL(32, 0))
279 fbkdiv_high = FIELD_GET(GENMASK_ULL(63, 32), pcw);
280 fbkdiv_low = FIELD_GET(GENMASK(31, 0), pcw);
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| /linux-master/drivers/ptp/ |
| H A D | ptp_fc3.c | 458 s64 pcw; local
472 pcw = div_s64((s64)delta * idtfc3->tdc_apll_freq * 124, NSEC_PER_SEC);
474 put_unaligned_le64(pcw, buf);
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