clk/mediatek/clk-pll.c

41 		u32 pcw, int postdiv)
54 	vco = (u64)fin * pcw;
93 static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw,
106 	/* postdiv and pcw need to set at the same time if on same register */
112 	/* set pcw */
115 	val |= pcw << pll->data->pcw_shift;
132  * @pcw:	The pcw value (output)
138 void mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw, u32 *postdiv,
172 	*pcw = (u32)_pcw;
179 	u32 pcw = 0;
182 	mtk_pll_calc_values(pll, &pcw, &postdiv, rate, parent_rate);
183 	mtk_pll_set_rate_regs(pll, pcw, postdiv);
192 	u32 pcw;
197 	pcw = readl(pll->pcw_addr) >> pll->data->pcw_shift;
198 	pcw &= GENMASK(pll->data->pcwbits - 1, 0);
200 	return __mtk_pll_recalc_rate(pll, parent_rate, pcw, postdiv);
207 	u32 pcw = 0;
210 	mtk_pll_calc_values(pll, &pcw, &postdiv, rate, *prate);
212 	return __mtk_pll_recalc_rate(pll, *prate, pcw, postdiv);