Searched refs:pcie_speed_table (Results 1 - 10 of 10) sorted by relevance

/linux-master/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dsmu7_hwmgr.h106 struct smu7_single_dpm_table pcie_speed_table; member in struct:smu7_dpm_table
H A Dsmu7_hwmgr.c662 phm_reset_single_dpm_table(&data->dpm_table.pcie_speed_table,
673 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, i - 1,
679 data->dpm_table.pcie_speed_table.count = max_entry - 1;
683 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 0,
688 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 1,
693 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 2,
698 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 3,
703 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 4,
708 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 5,
714 data->dpm_table.pcie_speed_table
[all...]
/linux-master/drivers/gpu/drm/radeon/
H A Dci_dpm.h71 struct ci_single_dpm_table pcie_speed_table; member in struct:ci_dpm_table
H A Dci_dpm.c2589 for (i = 0; i < dpm_table->pcie_speed_table.count; i++) {
2591 (u8)dpm_table->pcie_speed_table.dpm_levels[i].value;
2593 r600_encode_pci_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1);
2599 pi->smc_state_table.LinkLevelCount = (u8)dpm_table->pcie_speed_table.count;
2601 ci_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
3365 &pi->dpm_table.pcie_speed_table,
3369 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 0,
3373 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 0,
3376 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 1,
3379 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table,
[all...]
/linux-master/drivers/gpu/drm/amd/pm/powerplay/smumgr/
H A Dvegam_smumgr.c577 /* Index (dpm_table->pcie_speed_table.count)
579 for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) {
581 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value;
583 dpm_table->pcie_speed_table.dpm_levels[i].param1);
591 (uint8_t)dpm_table->pcie_speed_table.count;
595 phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
872 uint8_t pcie_entry_cnt = (uint8_t) hw_data->dpm_table.pcie_speed_table.count;
2034 PP_ASSERT_WITH_CODE(hw_data->dpm_table.pcie_speed_table.count >= 1,
2038 hw_data->dpm_table.pcie_speed_table.count;
2103 for (i = 0; i <= hw_data->dpm_table.pcie_speed_table
[all...]
H A Dfiji_smumgr.c834 /* Index (dpm_table->pcie_speed_table.count)
836 for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) {
838 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value;
840 dpm_table->pcie_speed_table.dpm_levels[i].param1);
848 (uint8_t)dpm_table->pcie_speed_table.count;
850 phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
1008 uint8_t pcie_entry_cnt = (uint8_t) data->dpm_table.pcie_speed_table.count;
H A Dtonga_smumgr.c514 /* Index (dpm_table->pcie_speed_table.count) is reserved for PCIE boot level. */
515 for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) {
517 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value;
519 (uint8_t)encode_pcie_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1);
531 (uint8_t)dpm_table->pcie_speed_table.count;
533 phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
693 uint8_t pcie_entry_count = (uint8_t) data->dpm_table.pcie_speed_table.count;
2346 PP_ASSERT_WITH_CODE((1 <= data->dpm_table.pcie_speed_table.count),
2350 table->PCIeBootLinkLevel = (uint8_t) (data->dpm_table.pcie_speed_table.count);
H A Dpolaris10_smumgr.c823 /* Index (dpm_table->pcie_speed_table.count)
825 for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) {
827 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value;
829 dpm_table->pcie_speed_table.dpm_levels[i].param1);
837 (uint8_t)dpm_table->pcie_speed_table.count;
841 phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
1044 uint8_t pcie_entry_cnt = (uint8_t) hw_data->dpm_table.pcie_speed_table.count;
2030 table->PCIeBootLinkLevel = hw_data->dpm_table.pcie_speed_table.count;
2093 for (i = 0; i <= hw_data->dpm_table.pcie_speed_table.count; i++) {
H A Diceland_smumgr.c771 /* Index (dpm_table->pcie_speed_table.count) is reserved for PCIE boot level. */
772 for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) {
774 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value;
776 (uint8_t)encode_pcie_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1);
788 (uint8_t)dpm_table->pcie_speed_table.count;
790 phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
H A Dci_smumgr.c1004 /* Index dpm_table->pcie_speed_table.count is reserved for PCIE boot level.*/
1005 for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) {
1007 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value;
1009 (uint8_t)encode_pcie_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1);
1016 (uint8_t)dpm_table->pcie_speed_table.count;
1018 phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
2054 PP_ASSERT_WITH_CODE((1 <= data->dpm_table.pcie_speed_table.count),
2058 table->PCIeBootLinkLevel = (uint8_t)data->dpm_table.pcie_speed_table.count;

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