Searched refs:opp_id (Results 1 - 25 of 39) sorted by relevance

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/linux-master/drivers/gpu/drm/amd/display/dc/inc/hw/
H A Dmpc.h243 * @opp_id: The OPP instance that owns this MPC tree.
245 int opp_id; member in struct:mpc_tree
263 uint32_t opp_id; member in struct:mpcc_state
388 * - [in] opp_id - The OPP to lock cursor updates on
397 int opp_id,
469 int opp_id,
474 int opp_id,
478 int opp_id,
483 int opp_id,
510 int opp_id,
[all...]
H A Dhubp.h75 int opp_id; member in struct:hubp
H A Dtiming_generator.h308 void (*set_odm_combine)(struct timing_generator *optc, int *opp_id, int opp_cnt,
/linux-master/drivers/gpu/drm/amd/display/dc/dcn10/
H A Ddcn10_mpc.c149 unsigned int opp_id; local
153 REG_GET(MPCC_OPP_ID[mpcc_id], MPCC_OPP_ID, &opp_id);
155 if (top_sel == 0xf && opp_id == 0xf && idle)
237 REG_SET(MPCC_OPP_ID[mpcc_id], 0, MPCC_OPP_ID, tree->opp_id);
240 REG_SET(MPCC_UPDATE_LOCK_SEL[mpcc_id], 0, MPCC_UPDATE_LOCK_SEL, tree->opp_id);
246 REG_UPDATE(MUX[tree->opp_id], MPC_OUT_MUX, mpcc_id);
302 REG_UPDATE(MUX[tree->opp_id], MPC_OUT_MUX, tree->opp_list->mpcc_id);
306 REG_UPDATE(MUX[tree->opp_id], MPC_OUT_MUX, 0xf);
375 int opp_id; local
387 for (opp_id
396 int opp_id; local
417 unsigned int opp_id; local
476 mpc1_cursor_lock(struct mpc *mpc, int opp_id, bool lock) argument
483 mpc1_get_mpc_out_mux(struct mpc *mpc, int opp_id) argument
[all...]
H A Ddcn10_mpc.h201 void mpc1_cursor_lock(struct mpc *mpc, int opp_id, bool lock);
203 unsigned int mpc1_get_mpc_out_mux(struct mpc *mpc, int opp_id);
/linux-master/drivers/gpu/drm/amd/display/dc/optc/dcn31/
H A Ddcn31_optc.c43 static void optc31_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt, argument
61 memory_mask = 0x1 << (opp_id[0] * 2) | 0x1 << (opp_id[1] * 2);
63 memory_mask = 0x3 << (opp_id[0] * 2) | 0x3 << (opp_id[1] * 2);
76 OPTC_SEG0_SRC_SEL, opp_id[0],
77 OPTC_SEG1_SRC_SEL, opp_id[1]);
81 OPTC_SEG0_SRC_SEL, opp_id[0],
82 OPTC_SEG1_SRC_SEL, opp_id[1],
83 OPTC_SEG2_SRC_SEL, opp_id[
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/optc/dcn314/
H A Ddcn314_optc.c50 static void optc314_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt, argument
74 memory_mask = 0x1 << (opp_id[0] * 2) | 0x1 << (opp_id[1] * 2);
76 memory_mask = 0x3 << (opp_id[0] * 2) | 0x3 << (opp_id[1] * 2);
87 OPTC_SEG0_SRC_SEL, opp_id[0],
88 OPTC_SEG1_SRC_SEL, opp_id[1]);
92 OPTC_SEG0_SRC_SEL, opp_id[0],
93 OPTC_SEG1_SRC_SEL, opp_id[1],
94 OPTC_SEG2_SRC_SEL, opp_id[
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/optc/dcn35/
H A Ddcn35_optc.c50 * @opp_id: Output Plane Processor instance ID.
56 static void optc35_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt, argument
80 memory_mask = 0x1 << (opp_id[0] * 2) | 0x1 << (opp_id[1] * 2);
82 memory_mask = 0x3 << (opp_id[0] * 2) | 0x3 << (opp_id[1] * 2);
93 OPTC_SEG0_SRC_SEL, opp_id[0],
94 OPTC_SEG1_SRC_SEL, opp_id[1]);
98 OPTC_SEG0_SRC_SEL, opp_id[0],
99 OPTC_SEG1_SRC_SEL, opp_id[
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/optc/dcn32/
H A Ddcn32_optc.c45 static void optc32_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt, argument
69 memory_mask = 0x1 << (opp_id[0] * 2) | 0x1 << (opp_id[1] * 2);
71 memory_mask = 0x3 << (opp_id[0] * 2) | 0x3 << (opp_id[1] * 2);
82 OPTC_SEG0_SRC_SEL, opp_id[0],
83 OPTC_SEG1_SRC_SEL, opp_id[1]);
87 OPTC_SEG0_SRC_SEL, opp_id[0],
88 OPTC_SEG1_SRC_SEL, opp_id[1],
89 OPTC_SEG2_SRC_SEL, opp_id[
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/optc/dcn30/
H A Ddcn30_optc.c218 void optc3_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt, argument
243 memory_mask = 0x3 << (opp_id[0] * 2) | 0x3 << (opp_id[1] * 2);
248 memory_mask = 0x1 << (opp_id[0] * 2) | 0x1 << (opp_id[1] * 2) | 0x1 << (opp_id[2] * 2) | 0x1 << (opp_id[3] * 2);
258 OPTC_SEG0_SRC_SEL, opp_id[0],
259 OPTC_SEG1_SRC_SEL, opp_id[1]);
263 OPTC_SEG0_SRC_SEL, opp_id[
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_mpc.c75 int opp_id,
107 REG_UPDATE(DENORM_CONTROL[opp_id],
113 int opp_id,
118 REG_UPDATE_2(DENORM_CONTROL[opp_id],
121 REG_UPDATE_2(DENORM_CLAMP_G_Y[opp_id],
124 REG_UPDATE_2(DENORM_CLAMP_B_CB[opp_id],
133 int opp_id,
142 REG_SET(CSC_MODE[opp_id], 0, MPC_OCSC_MODE, ocsc_mode);
170 ocsc_regs.csc_c11_c12 = REG(CSC_C11_C12_A[opp_id]);
171 ocsc_regs.csc_c33_c34 = REG(CSC_C33_C34_A[opp_id]);
73 mpc2_set_denorm( struct mpc *mpc, int opp_id, enum dc_color_depth output_depth) argument
111 mpc2_set_denorm_clamp( struct mpc *mpc, int opp_id, struct mpc_denorm_clamp denorm_clamp) argument
131 mpc2_set_output_csc( struct mpc *mpc, int opp_id, const uint16_t *regval, enum mpc_output_csc_mode ocsc_mode) argument
185 mpc2_set_ocsc_default( struct mpc *mpc, int opp_id, enum dc_color_space color_space, enum mpc_output_csc_mode ocsc_mode) argument
[all...]
H A Ddcn20_mpc.h284 int opp_id,
289 int opp_id,
294 int opp_id,
300 int opp_id,
/linux-master/drivers/gpu/drm/amd/display/dc/dcn201/
H A Ddcn201_mpc.c44 int opp_id,
51 REG_UPDATE_2(MUX[opp_id],
56 REG_UPDATE_3(MUX[opp_id],
42 mpc201_set_out_rate_control( struct mpc *mpc, int opp_id, bool enable, bool rate_2x_mode, struct mpc_dwb_flow_control *flow_control) argument
H A Ddcn201_hubp.c145 hubp201->base.opp_id = OPP_ID_INVALID;
/linux-master/drivers/gpu/drm/amd/display/dc/dcn30/
H A Ddcn30_mpc.c50 int opp_id; local
54 for (opp_id = 0; opp_id < MAX_OPP; opp_id++) {
55 if (REG(MUX[opp_id]))
57 REG_UPDATE_2(MUX[opp_id], MPC_OUT_RATE_CONTROL_DISABLE,
374 int opp_id,
407 REG_UPDATE(DENORM_CONTROL[opp_id],
413 int opp_id,
419 REG_UPDATE_2(DENORM_CONTROL[opp_id],
372 mpc3_set_denorm( struct mpc *mpc, int opp_id, enum dc_color_depth output_depth) argument
411 mpc3_set_denorm_clamp( struct mpc *mpc, int opp_id, struct mpc_denorm_clamp denorm_clamp) argument
1286 mpc3_set_output_csc( struct mpc *mpc, int opp_id, const uint16_t *regval, enum mpc_output_csc_mode ocsc_mode) argument
1325 mpc3_set_ocsc_default( struct mpc *mpc, int opp_id, enum dc_color_space color_space, enum mpc_output_csc_mode ocsc_mode) argument
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/dcn31/
H A Ddcn31_hubp.c115 hubp2->base.opp_id = OPP_ID_INVALID;
/linux-master/drivers/gpu/drm/amd/display/dc/optc/dcn20/
H A Ddcn20_optc.c188 void optc2_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt, argument
211 memory_mask = 0x3 << (opp_id[0] * 2) | 0x3 << (opp_id[1] * 2);
219 OPTC_SEG0_SRC_SEL, opp_id[0],
220 OPTC_SEG1_SRC_SEL, opp_id[1]);
H A Ddcn20_optc.h107 void optc2_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt,
/linux-master/drivers/gpu/drm/amd/display/dc/core/
H A Ddc_hw_sequencer.c674 block_sequence[*num_steps].params.set_output_csc_params.opp_id = current_mpc_pipe->stream_res.opp->inst;
681 block_sequence[*num_steps].params.set_ocsc_default_params.opp_id = current_mpc_pipe->stream_res.opp->inst;
870 int opp_id = params->set_output_csc_params.opp_id; local
876 opp_id,
884 int opp_id = params->set_ocsc_default_params.opp_id; local
890 opp_id,
/linux-master/drivers/gpu/drm/amd/display/dc/hwss/
H A Dhw_sequencer.h126 int opp_id; member in struct:set_output_csc_params
133 int opp_id; member in struct:set_ocsc_default_params
297 uint16_t *matrix, int opp_id);
/linux-master/drivers/gpu/drm/amd/display/dc/dcn32/
H A Ddcn32_hubp.c221 hubp2->base.opp_id = OPP_ID_INVALID;
/linux-master/drivers/gpu/drm/amd/display/dc/dcn35/
H A Ddcn35_hubp.c235 hubp2->base.opp_id = OPP_ID_INVALID;
/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn20/
H A Ddcn20_hwseq.h53 int opp_id);
/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn201/
H A Ddcn201_hwseq.c295 res_pool->opps[i]->mpc_tree_params.opp_id = res_pool->opps[i]->inst;
314 hubp->opp_id = OPP_ID_INVALID;
519 hubp->opp_id = pipe_ctx->stream_res.opp->inst;
/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn10/
H A Ddcn10_hwseq.h68 int opp_id);

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