Searched refs:nvif_rd32 (Results 1 - 17 of 17) sorted by relevance

/linux-master/drivers/gpu/drm/nouveau/nvif/
H A Duserc361.c30 hi = nvif_rd32(&user->object, 0x084);
31 lo = nvif_rd32(&user->object, 0x080);
32 } while (hi != nvif_rd32(&user->object, 0x084));
/linux-master/drivers/gpu/drm/nouveau/dispnv50/
H A Dsorc37d.c45 u32 tmp = nvif_rd32(&disp->caps, 0x000144 + (or * 8));
H A Ddisp.c144 if (!(nvif_rd32(&device->object, 0x070000) & 0x00000002))
/linux-master/drivers/gpu/drm/nouveau/
H A Dnouveau_led.c44 div = nvif_rd32(device, 0x61c880) & 0x00ffffff;
45 duty = nvif_rd32(device, 0x61c884) & 0x00ffffff;
H A Dnouveau_dma.c45 val = nvif_rd32(chan->userd, chan->user_get);
47 val |= (uint64_t)nvif_rd32(chan->userd, chan->user_get_hi) << 32;
104 uint32_t get = nvif_rd32(chan->userd, 0x88);
H A Dnouveau_svm.c457 const u32 instlo = nvif_rd32(memory, offset + 0x00);
458 const u32 insthi = nvif_rd32(memory, offset + 0x04);
459 const u32 addrlo = nvif_rd32(memory, offset + 0x08);
460 const u32 addrhi = nvif_rd32(memory, offset + 0x0c);
461 const u32 timelo = nvif_rd32(memory, offset + 0x10);
462 const u32 timehi = nvif_rd32(memory, offset + 0x14);
463 const u32 engine = nvif_rd32(memory, offset + 0x18);
464 const u32 info = nvif_rd32(memory, offset + 0x1c);
733 buffer->put = nvif_rd32(device, buffer->putaddr);
734 buffer->get = nvif_rd32(devic
[all...]
H A Dnouveau_backlight.c69 int val = (nvif_rd32(device, NV40_PMC_BACKLIGHT) &
82 int reg = nvif_rd32(device, NV40_PMC_BACKLIGHT);
104 if (!(nvif_rd32(device, NV40_PMC_BACKLIGHT) & NV40_PMC_BACKLIGHT_MASK))
H A Dnouveau_bios.c245 sel_clk_binding = nvif_rd32(device, NV_PRAMDAC_SEL_CLK) & 0x50000;
341 return nvif_rd32(device, 0x001800) & 0x0000000f;
344 return (nvif_rd32(device, NV_PEXTDEV_BOOT_0) >> 24) & 0xf;
346 return (nvif_rd32(device, NV_PEXTDEV_BOOT_0) >> 16) & 0xf;
676 sel_clk_binding = nvif_rd32(device, NV_PRAMDAC_SEL_CLK) & 0x50000;
1960 nvif_wr32(device, NV_PBUS_DEBUG_4, nvif_rd32(device, NV_PBUS_DEBUG_4) | 0x18);
H A Dnouveau_debugfs.c63 nvif_rd32(&drm->client.device.object, 0x101000));
/linux-master/drivers/gpu/drm/nouveau/dispnv04/
H A Darb.c202 uint32_t cfg1 = nvif_rd32(device, NV04_PFB_CFG1);
223 sim_data.memory_type = nvif_rd32(device, NV04_PFB_CFG0) & 0x1;
224 sim_data.memory_width = (nvif_rd32(device, NV_PEXTDEV_BOOT_0) & 0x10) ? 128 : 64;
H A Ddac.c84 if (!(nvif_rd32(device, NV_PRMCIO_INP0__COLOR) & 1))
90 if ( (nvif_rd32(device, NV_PRMCIO_INP0__COLOR) & 1))
96 if (!(nvif_rd32(device, NV_PRMCIO_INP0__COLOR) & 1))
264 saved_powerctrl_2 = nvif_rd32(device, NV_PBUS_POWERCTRL_2);
268 saved_powerctrl_4 = nvif_rd32(device, NV_PBUS_POWERCTRL_4);
H A Dhw.h66 val = nvif_rd32(device, reg);
86 val = nvif_rd32(device, reg);
265 return !!(nvif_rd32(device, NV_PBUS_DEBUG_1) & (1 << 28));
H A Dtvnv17.h140 return nvif_rd32(&device->object, reg);
H A Dhw.c178 pll1 = nvif_rd32(device, reg1);
180 pll2 = nvif_rd32(device, reg1 + 4);
184 pll2 = nvif_rd32(device, reg2);
751 if ( (nvif_rd32(device, NV_PRMCIO_INP0__COLOR) & 8))
755 if (!(nvif_rd32(device, NV_PRMCIO_INP0__COLOR) & 8))
H A Doverlay.c434 nvif_wr32(dev, NV_PVIDEO_SU_STATE, nvif_rd32(dev, NV_PVIDEO_SU_STATE) ^ (1 << 16));
H A Ddfp.c340 if (nvif_rd32(device, NV_PEXTDEV_BOOT_0) & NV_PEXTDEV_BOOT_0_STRAP_FP_IFACE_12BIT)
/linux-master/drivers/gpu/drm/nouveau/include/nvif/
H A Dobject.h67 #define nvif_rd32(a,b) ({ ((u32)nvif_rd((a), ioread32_native, 4, (b))); }) macro
73 u32 _addr = (b), _data = nvif_rd32(__object, _addr); \
125 #define NVIF_RD32_(p,o,dr) nvif_rd32((p), (o) + (dr))

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