Searched refs:num_txq (Results 1 - 25 of 29) sorted by relevance

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/linux-master/drivers/net/ethernet/atheros/alx/
H A Dalx.h121 int num_txq; member in struct:alx_priv
H A Dmain.c146 if (r_idx >= alx->num_txq)
147 r_idx = r_idx % alx->num_txq;
537 for (i = 0; i < alx->num_txq; i++)
659 alx->num_txq +
672 for (i = 0; i < alx->num_txq; i++) {
695 for (i = 0; i < alx->num_txq; i++)
759 for (i = 0; i < alx->num_txq; i++) {
814 for (i = 0, vector = 1; i < alx->num_txq; i++, vector++) {
831 int err, num_vec, num_txq, num_rxq; local
833 num_txq
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/linux-master/drivers/net/ethernet/intel/idpf/
H A Didpf_ethtool.c189 u16 num_txq, num_rxq; local
194 num_txq = vport_config->user_config.num_req_tx_qs;
197 combined = min(num_txq, num_rxq);
210 ch->tx_count = num_txq - combined;
225 u16 combined, num_txq, num_rxq; local
239 num_txq = vport_config->user_config.num_req_tx_qs;
242 combined = min(num_txq, num_rxq);
253 if (ch->combined_count && ch->tx_count == num_txq - combined)
277 if (num_req_tx_q == num_txq && num_req_rx_q == num_rxq)
286 vport_config->user_config.num_req_tx_qs = num_txq;
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H A Didpf_txrx.c152 for (j = 0; j < txq_grp->num_txq; j++)
270 for (j = 0; j < vport->txq_grps[i].num_txq; j++) {
813 for (j = 0; j < txq_grp->num_txq; j++) {
922 vport->txqs = kcalloc(vport->num_txq, sizeof(struct idpf_queue *),
931 for (j = 0; j < tx_grp->num_txq; j++, k++) {
952 vport->num_txq = le16_to_cpu(vport_msg->num_tx_q);
1104 vport->num_txq_grp = vport->num_txq;
1117 * @num_txq: return parameter for number of TX queues
1121 u16 *num_txq, u16 *num_rxq)
1124 *num_txq
1120 idpf_vport_calc_numq_per_grp(struct idpf_vport *vport, u16 *num_txq, u16 *num_rxq) argument
1159 idpf_txq_group_alloc(struct idpf_vport *vport, u16 num_txq) argument
1388 u16 num_txq, num_rxq; local
3850 u16 num_txq = q_vec->num_txq; local
4001 u16 num_txq; local
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H A Didpf_virtchnl.c752 for (i = 0; i < vport->num_txq; i++)
760 for (i = 0; i < vport->num_txq; i++)
1103 for (j = 0; j < tx_qgrp->num_txq && k < num_regs; j++, k++)
1173 if (num_regs < vport->num_txq) {
1180 if (num_regs < vport->num_txq) {
1436 totqs = vport->num_txq + vport->num_complq;
1446 for (j = 0; j < tx_qgrp->num_txq; j++, k++) {
1690 u32 num_msgs, num_chunks, num_txq, num_rxq, num_q; local
1697 num_txq = vport->num_txq
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H A Didpf_singleq_txrx.c581 u16 num_txq = q_vec->num_txq; local
585 budget_per_q = num_txq ? max(budget / num_txq, 1) : 0;
586 for (i = 0; i < num_txq; i++) {
H A Didpf_txrx.h514 * @num_txq: Number of TX queues
538 u16 num_txq; member in struct:idpf_q_vector
845 * @num_txq: Number of TX queues associated
859 u16 num_txq; member in struct:idpf_txq_group
H A Didpf.h252 * @num_txq: Number of allocated TX queues
297 u16 num_txq; member in struct:idpf_vport
H A Didpf_lib.c1285 return netif_set_real_num_tx_queues(vport->netdev, vport->num_txq);
1919 err = idpf_send_add_queues_msg(vport, new_vport->num_txq,
1940 for (j = 0; j < tx_qgrp->num_txq; j++)
/linux-master/drivers/net/ethernet/stmicro/stmmac/
H A Ddwmac5.h106 u32 num_txq, u32 num_rxq,
H A Ddwmac5.c577 u32 num_txq, u32 num_rxq,
576 dwmac5_fpe_configure(void __iomem *ioaddr, struct stmmac_fpe_cfg *cfg, u32 num_txq, u32 num_rxq, bool enable) argument
H A Dhwif.h423 u32 num_txq, u32 num_rxq,
/linux-master/drivers/net/ethernet/intel/ice/
H A Dice_sriov.c433 u16 num_msix_per_vf, num_txq, num_rxq, avail_qs; local
462 num_txq = min_t(u16, num_msix_per_vf - ICE_NONQ_VECS_VF,
466 num_txq = 0;
467 else if (num_txq > avail_qs)
468 num_txq = rounddown_pow_of_two(avail_qs);
478 if (num_txq < ICE_MIN_QS_PER_VF || num_rxq < ICE_MIN_QS_PER_VF) {
492 pf->vfs.num_qps_per = min_t(int, num_txq, num_rxq);
H A Dice_lib.c185 vsi->num_txq = vsi->req_txq;
620 vsi->num_txq = ch->num_txq;
1102 vsi->num_txq = tx_count;
1105 if (vsi->type == ICE_VSI_VF && vsi->num_txq != vsi->num_rxq) {
1108 * in the above for loop, make num_txq equal to num_rxq.
1110 vsi->num_txq = vsi->num_rxq;
1999 if (vsi->num_txq > ICE_LAN_TXQ_MAX_QDIS)
2030 return ice_vsi_stop_tx_rings(vsi, rst_src, rel_vmvf_num, vsi->tx_rings, vsi->num_txq);
2249 if (!vsi->alloc_txq && vsi->num_txq)
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H A Dice.h162 for ((i) = 0; (i) < (vsi)->num_txq; (i)++)
220 u16 num_txq; member in struct:ice_channel
404 u16 num_txq; /* Used Tx queues */ member in struct:ice_vsi
H A Dice_xsk.c169 if (q_idx >= vsi->num_rxq || q_idx >= vsi->num_txq)
377 if (qid >= vsi->num_rxq || qid >= vsi->num_txq) {
1102 if (queue_id >= vsi->num_txq || queue_id >= vsi->num_rxq)
H A Dice_base.c821 tx_rings_rem = vsi->num_txq;
835 q_base = vsi->num_txq - tx_rings_rem;
1005 return ice_vsi_cfg_txqs(vsi, vsi->tx_rings, vsi->num_txq);
H A Dice_main.c2763 max_txqs[i] = vsi->num_txq + vsi->num_xdp_txq;
2873 max_txqs[i] = vsi->num_txq;
4000 pf->max_pf_txqs = func_caps->common_cap.num_txq;
6700 vsi->num_txq);
6952 if (!vsi->num_txq || !vsi->num_rxq)
7141 if (!vsi->num_txq) {
7288 err = netif_set_real_num_tx_queues(vsi->netdev, vsi->num_txq);
8296 if (vsi->num_txq <
8424 for (i = 0; i < ch->num_txq; i++) {
8465 if (ch->num_txq || c
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H A Dice_ethtool.c2938 tx_rings = kcalloc(vsi->num_txq, sizeof(*tx_rings), GFP_KERNEL);
3468 (u16)pf->hw.func_caps.common_cap.num_txq);
3523 ch->tx_count = vsi->num_txq - ch->combined_count;
3627 if (ch->tx_count == vsi->num_txq - curr_combined)
3790 if (q_num < vsi->num_rxq && q_num < vsi->num_txq) {
3801 } else if (q_num < vsi->num_txq) {
3958 if (q_num < vsi->num_rxq && q_num < vsi->num_txq) {
3973 } else if (q_num < vsi->num_txq) {
4042 if (v_idx >= vsi->num_rxq && v_idx >= vsi->num_txq)
H A Dice_type.h264 u16 num_txq; /* Number/Total Tx queues */ member in struct:ice_hw_common_caps
H A Dice_common.c2111 caps->num_txq = number;
2113 ice_debug(hw, ICE_DBG_INIT, "%s: num_txq = %d\n", prefix,
2114 caps->num_txq);
2870 func_caps->common_cap.num_txq = 1;
2900 dev_caps->common_cap.num_txq = num_funcs;
/linux-master/drivers/net/ethernet/brocade/bna/
H A Dbna_enet.c167 ioceth->attr.num_txq = ntohl(rsp->max_cfg);
1679 ioceth->attr.num_txq = BFI_ENET_DEF_TXQ;
1906 attr->num_txq * sizeof(struct bna_tx);
1914 attr->num_txq * sizeof(struct bna_txq);
2026 bna_num_txq_set(struct bna *bna, int num_txq) argument
2029 (num_txq <= bna->ioceth.attr.num_txq)) {
2030 bna->ioceth.attr.num_txq = num_txq;
H A Dbna_types.h306 int num_txq; member in struct:bna_attr
476 int num_txq; member in struct:bna_tx
505 int num_txq; member in struct:bna_tx_config
H A Dbna.h265 int bna_num_txq_set(struct bna *bna, int num_txq);
306 void bna_tx_res_req(int num_txq, int txq_depth,
H A Dbna_tx_rx.c3097 cfg_req->num_queues = tx->num_txq;
3098 for (i = 0; i < tx->num_txq; i++) {
3282 i < tx->num_txq; i++, txq = list_next_entry(txq, qe)) {
3316 bna_tx_res_req(int num_txq, int txq_depth, struct bna_res_info *res_info) argument
3326 mem_info->num = num_txq;
3336 mem_info->num = num_txq;
3342 mem_info->num = num_txq;
3348 mem_info->num = num_txq;
3354 mem_info->num = num_txq;
3359 res_info[BNA_TX_RES_INTR_T_TXCMPL].res_u.intr_info.num = num_txq;
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