1/* 2 * Copyright (c) 2013, 2021 Johannes Berg <johannes@sipsolutions.net> 3 * 4 * This file is free software: you may copy, redistribute and/or modify it 5 * under the terms of the GNU General Public License as published by the 6 * Free Software Foundation, either version 2 of the License, or (at your 7 * option) any later version. 8 * 9 * This file is distributed in the hope that it will be useful, but 10 * WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 12 * General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program. If not, see <http://www.gnu.org/licenses/>. 16 * 17 * This file incorporates work covered by the following copyright and 18 * permission notice: 19 * 20 * Copyright (c) 2012 Qualcomm Atheros, Inc. 21 * 22 * Permission to use, copy, modify, and/or distribute this software for any 23 * purpose with or without fee is hereby granted, provided that the above 24 * copyright notice and this permission notice appear in all copies. 25 * 26 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 27 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 28 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 29 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 30 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 31 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 32 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 33 */ 34 35#include <linux/module.h> 36#include <linux/pci.h> 37#include <linux/interrupt.h> 38#include <linux/ip.h> 39#include <linux/ipv6.h> 40#include <linux/if_vlan.h> 41#include <linux/mdio.h> 42#include <linux/bitops.h> 43#include <linux/netdevice.h> 44#include <linux/etherdevice.h> 45#include <net/ip6_checksum.h> 46#include <linux/crc32.h> 47#include "alx.h" 48#include "hw.h" 49#include "reg.h" 50 51static const char alx_drv_name[] = "alx"; 52 53static void alx_free_txbuf(struct alx_tx_queue *txq, int entry) 54{ 55 struct alx_buffer *txb = &txq->bufs[entry]; 56 57 if (dma_unmap_len(txb, size)) { 58 dma_unmap_single(txq->dev, 59 dma_unmap_addr(txb, dma), 60 dma_unmap_len(txb, size), 61 DMA_TO_DEVICE); 62 dma_unmap_len_set(txb, size, 0); 63 } 64 65 if (txb->skb) { 66 dev_kfree_skb_any(txb->skb); 67 txb->skb = NULL; 68 } 69} 70 71static int alx_refill_rx_ring(struct alx_priv *alx, gfp_t gfp) 72{ 73 struct alx_rx_queue *rxq = alx->qnapi[0]->rxq; 74 struct sk_buff *skb; 75 struct alx_buffer *cur_buf; 76 dma_addr_t dma; 77 u16 cur, next, count = 0; 78 79 next = cur = rxq->write_idx; 80 if (++next == alx->rx_ringsz) 81 next = 0; 82 cur_buf = &rxq->bufs[cur]; 83 84 while (!cur_buf->skb && next != rxq->read_idx) { 85 struct alx_rfd *rfd = &rxq->rfd[cur]; 86 87 /* 88 * When DMA RX address is set to something like 89 * 0x....fc0, it will be very likely to cause DMA 90 * RFD overflow issue. 91 * 92 * To work around it, we apply rx skb with 64 bytes 93 * longer space, and offset the address whenever 94 * 0x....fc0 is detected. 95 */ 96 skb = __netdev_alloc_skb(alx->dev, alx->rxbuf_size + 64, gfp); 97 if (!skb) 98 break; 99 100 if (((unsigned long)skb->data & 0xfff) == 0xfc0) 101 skb_reserve(skb, 64); 102 103 dma = dma_map_single(&alx->hw.pdev->dev, 104 skb->data, alx->rxbuf_size, 105 DMA_FROM_DEVICE); 106 if (dma_mapping_error(&alx->hw.pdev->dev, dma)) { 107 dev_kfree_skb(skb); 108 break; 109 } 110 111 /* Unfortunately, RX descriptor buffers must be 4-byte 112 * aligned, so we can't use IP alignment. 113 */ 114 if (WARN_ON(dma & 3)) { 115 dev_kfree_skb(skb); 116 break; 117 } 118 119 cur_buf->skb = skb; 120 dma_unmap_len_set(cur_buf, size, alx->rxbuf_size); 121 dma_unmap_addr_set(cur_buf, dma, dma); 122 rfd->addr = cpu_to_le64(dma); 123 124 cur = next; 125 if (++next == alx->rx_ringsz) 126 next = 0; 127 cur_buf = &rxq->bufs[cur]; 128 count++; 129 } 130 131 if (count) { 132 /* flush all updates before updating hardware */ 133 wmb(); 134 rxq->write_idx = cur; 135 alx_write_mem16(&alx->hw, ALX_RFD_PIDX, cur); 136 } 137 138 return count; 139} 140 141static struct alx_tx_queue *alx_tx_queue_mapping(struct alx_priv *alx, 142 struct sk_buff *skb) 143{ 144 unsigned int r_idx = skb->queue_mapping; 145 146 if (r_idx >= alx->num_txq) 147 r_idx = r_idx % alx->num_txq; 148 149 return alx->qnapi[r_idx]->txq; 150} 151 152static struct netdev_queue *alx_get_tx_queue(const struct alx_tx_queue *txq) 153{ 154 return netdev_get_tx_queue(txq->netdev, txq->queue_idx); 155} 156 157static inline int alx_tpd_avail(struct alx_tx_queue *txq) 158{ 159 if (txq->write_idx >= txq->read_idx) 160 return txq->count + txq->read_idx - txq->write_idx - 1; 161 return txq->read_idx - txq->write_idx - 1; 162} 163 164static bool alx_clean_tx_irq(struct alx_tx_queue *txq) 165{ 166 struct alx_priv *alx; 167 struct netdev_queue *tx_queue; 168 u16 hw_read_idx, sw_read_idx; 169 unsigned int total_bytes = 0, total_packets = 0; 170 int budget = ALX_DEFAULT_TX_WORK; 171 172 alx = netdev_priv(txq->netdev); 173 tx_queue = alx_get_tx_queue(txq); 174 175 sw_read_idx = txq->read_idx; 176 hw_read_idx = alx_read_mem16(&alx->hw, txq->c_reg); 177 178 if (sw_read_idx != hw_read_idx) { 179 while (sw_read_idx != hw_read_idx && budget > 0) { 180 struct sk_buff *skb; 181 182 skb = txq->bufs[sw_read_idx].skb; 183 if (skb) { 184 total_bytes += skb->len; 185 total_packets++; 186 budget--; 187 } 188 189 alx_free_txbuf(txq, sw_read_idx); 190 191 if (++sw_read_idx == txq->count) 192 sw_read_idx = 0; 193 } 194 txq->read_idx = sw_read_idx; 195 196 netdev_tx_completed_queue(tx_queue, total_packets, total_bytes); 197 } 198 199 if (netif_tx_queue_stopped(tx_queue) && netif_carrier_ok(alx->dev) && 200 alx_tpd_avail(txq) > txq->count / 4) 201 netif_tx_wake_queue(tx_queue); 202 203 return sw_read_idx == hw_read_idx; 204} 205 206static void alx_schedule_link_check(struct alx_priv *alx) 207{ 208 schedule_work(&alx->link_check_wk); 209} 210 211static void alx_schedule_reset(struct alx_priv *alx) 212{ 213 schedule_work(&alx->reset_wk); 214} 215 216static int alx_clean_rx_irq(struct alx_rx_queue *rxq, int budget) 217{ 218 struct alx_priv *alx; 219 struct alx_rrd *rrd; 220 struct alx_buffer *rxb; 221 struct sk_buff *skb; 222 u16 length, rfd_cleaned = 0; 223 int work = 0; 224 225 alx = netdev_priv(rxq->netdev); 226 227 while (work < budget) { 228 rrd = &rxq->rrd[rxq->rrd_read_idx]; 229 if (!(rrd->word3 & cpu_to_le32(1 << RRD_UPDATED_SHIFT))) 230 break; 231 rrd->word3 &= ~cpu_to_le32(1 << RRD_UPDATED_SHIFT); 232 233 if (ALX_GET_FIELD(le32_to_cpu(rrd->word0), 234 RRD_SI) != rxq->read_idx || 235 ALX_GET_FIELD(le32_to_cpu(rrd->word0), 236 RRD_NOR) != 1) { 237 alx_schedule_reset(alx); 238 return work; 239 } 240 241 rxb = &rxq->bufs[rxq->read_idx]; 242 dma_unmap_single(rxq->dev, 243 dma_unmap_addr(rxb, dma), 244 dma_unmap_len(rxb, size), 245 DMA_FROM_DEVICE); 246 dma_unmap_len_set(rxb, size, 0); 247 skb = rxb->skb; 248 rxb->skb = NULL; 249 250 if (rrd->word3 & cpu_to_le32(1 << RRD_ERR_RES_SHIFT) || 251 rrd->word3 & cpu_to_le32(1 << RRD_ERR_LEN_SHIFT)) { 252 rrd->word3 = 0; 253 dev_kfree_skb_any(skb); 254 goto next_pkt; 255 } 256 257 length = ALX_GET_FIELD(le32_to_cpu(rrd->word3), 258 RRD_PKTLEN) - ETH_FCS_LEN; 259 skb_put(skb, length); 260 skb->protocol = eth_type_trans(skb, rxq->netdev); 261 262 skb_checksum_none_assert(skb); 263 if (alx->dev->features & NETIF_F_RXCSUM && 264 !(rrd->word3 & (cpu_to_le32(1 << RRD_ERR_L4_SHIFT) | 265 cpu_to_le32(1 << RRD_ERR_IPV4_SHIFT)))) { 266 switch (ALX_GET_FIELD(le32_to_cpu(rrd->word2), 267 RRD_PID)) { 268 case RRD_PID_IPV6UDP: 269 case RRD_PID_IPV4UDP: 270 case RRD_PID_IPV4TCP: 271 case RRD_PID_IPV6TCP: 272 skb->ip_summed = CHECKSUM_UNNECESSARY; 273 break; 274 } 275 } 276 277 napi_gro_receive(&rxq->np->napi, skb); 278 work++; 279 280next_pkt: 281 if (++rxq->read_idx == rxq->count) 282 rxq->read_idx = 0; 283 if (++rxq->rrd_read_idx == rxq->count) 284 rxq->rrd_read_idx = 0; 285 286 if (++rfd_cleaned > ALX_RX_ALLOC_THRESH) 287 rfd_cleaned -= alx_refill_rx_ring(alx, GFP_ATOMIC); 288 } 289 290 if (rfd_cleaned) 291 alx_refill_rx_ring(alx, GFP_ATOMIC); 292 293 return work; 294} 295 296static int alx_poll(struct napi_struct *napi, int budget) 297{ 298 struct alx_napi *np = container_of(napi, struct alx_napi, napi); 299 struct alx_priv *alx = np->alx; 300 struct alx_hw *hw = &alx->hw; 301 unsigned long flags; 302 bool tx_complete = true; 303 int work = 0; 304 305 if (np->txq) 306 tx_complete = alx_clean_tx_irq(np->txq); 307 if (np->rxq) 308 work = alx_clean_rx_irq(np->rxq, budget); 309 310 if (!tx_complete || work == budget) 311 return budget; 312 313 napi_complete_done(&np->napi, work); 314 315 /* enable interrupt */ 316 if (alx->hw.pdev->msix_enabled) { 317 alx_mask_msix(hw, np->vec_idx, false); 318 } else { 319 spin_lock_irqsave(&alx->irq_lock, flags); 320 alx->int_mask |= ALX_ISR_TX_Q0 | ALX_ISR_RX_Q0; 321 alx_write_mem32(hw, ALX_IMR, alx->int_mask); 322 spin_unlock_irqrestore(&alx->irq_lock, flags); 323 } 324 325 alx_post_write(hw); 326 327 return work; 328} 329 330static bool alx_intr_handle_misc(struct alx_priv *alx, u32 intr) 331{ 332 struct alx_hw *hw = &alx->hw; 333 334 if (intr & ALX_ISR_FATAL) { 335 netif_warn(alx, hw, alx->dev, 336 "fatal interrupt 0x%x, resetting\n", intr); 337 alx_schedule_reset(alx); 338 return true; 339 } 340 341 if (intr & ALX_ISR_ALERT) 342 netdev_warn(alx->dev, "alert interrupt: 0x%x\n", intr); 343 344 if (intr & ALX_ISR_PHY) { 345 /* suppress PHY interrupt, because the source 346 * is from PHY internal. only the internal status 347 * is cleared, the interrupt status could be cleared. 348 */ 349 alx->int_mask &= ~ALX_ISR_PHY; 350 alx_write_mem32(hw, ALX_IMR, alx->int_mask); 351 alx_schedule_link_check(alx); 352 } 353 354 return false; 355} 356 357static irqreturn_t alx_intr_handle(struct alx_priv *alx, u32 intr) 358{ 359 struct alx_hw *hw = &alx->hw; 360 361 spin_lock(&alx->irq_lock); 362 363 /* ACK interrupt */ 364 alx_write_mem32(hw, ALX_ISR, intr | ALX_ISR_DIS); 365 intr &= alx->int_mask; 366 367 if (alx_intr_handle_misc(alx, intr)) 368 goto out; 369 370 if (intr & (ALX_ISR_TX_Q0 | ALX_ISR_RX_Q0)) { 371 napi_schedule(&alx->qnapi[0]->napi); 372 /* mask rx/tx interrupt, enable them when napi complete */ 373 alx->int_mask &= ~ALX_ISR_ALL_QUEUES; 374 alx_write_mem32(hw, ALX_IMR, alx->int_mask); 375 } 376 377 alx_write_mem32(hw, ALX_ISR, 0); 378 379 out: 380 spin_unlock(&alx->irq_lock); 381 return IRQ_HANDLED; 382} 383 384static irqreturn_t alx_intr_msix_ring(int irq, void *data) 385{ 386 struct alx_napi *np = data; 387 struct alx_hw *hw = &np->alx->hw; 388 389 /* mask interrupt to ACK chip */ 390 alx_mask_msix(hw, np->vec_idx, true); 391 /* clear interrupt status */ 392 alx_write_mem32(hw, ALX_ISR, np->vec_mask); 393 394 napi_schedule(&np->napi); 395 396 return IRQ_HANDLED; 397} 398 399static irqreturn_t alx_intr_msix_misc(int irq, void *data) 400{ 401 struct alx_priv *alx = data; 402 struct alx_hw *hw = &alx->hw; 403 u32 intr; 404 405 /* mask interrupt to ACK chip */ 406 alx_mask_msix(hw, 0, true); 407 408 /* read interrupt status */ 409 intr = alx_read_mem32(hw, ALX_ISR); 410 intr &= (alx->int_mask & ~ALX_ISR_ALL_QUEUES); 411 412 if (alx_intr_handle_misc(alx, intr)) 413 return IRQ_HANDLED; 414 415 /* clear interrupt status */ 416 alx_write_mem32(hw, ALX_ISR, intr); 417 418 /* enable interrupt again */ 419 alx_mask_msix(hw, 0, false); 420 421 return IRQ_HANDLED; 422} 423 424static irqreturn_t alx_intr_msi(int irq, void *data) 425{ 426 struct alx_priv *alx = data; 427 428 return alx_intr_handle(alx, alx_read_mem32(&alx->hw, ALX_ISR)); 429} 430 431static irqreturn_t alx_intr_legacy(int irq, void *data) 432{ 433 struct alx_priv *alx = data; 434 struct alx_hw *hw = &alx->hw; 435 u32 intr; 436 437 intr = alx_read_mem32(hw, ALX_ISR); 438 439 if (intr & ALX_ISR_DIS || !(intr & alx->int_mask)) 440 return IRQ_NONE; 441 442 return alx_intr_handle(alx, intr); 443} 444 445static const u16 txring_header_reg[] = {ALX_TPD_PRI0_ADDR_LO, 446 ALX_TPD_PRI1_ADDR_LO, 447 ALX_TPD_PRI2_ADDR_LO, 448 ALX_TPD_PRI3_ADDR_LO}; 449 450static void alx_init_ring_ptrs(struct alx_priv *alx) 451{ 452 struct alx_hw *hw = &alx->hw; 453 u32 addr_hi = ((u64)alx->descmem.dma) >> 32; 454 struct alx_napi *np; 455 int i; 456 457 for (i = 0; i < alx->num_napi; i++) { 458 np = alx->qnapi[i]; 459 if (np->txq) { 460 np->txq->read_idx = 0; 461 np->txq->write_idx = 0; 462 alx_write_mem32(hw, 463 txring_header_reg[np->txq->queue_idx], 464 np->txq->tpd_dma); 465 } 466 467 if (np->rxq) { 468 np->rxq->read_idx = 0; 469 np->rxq->write_idx = 0; 470 np->rxq->rrd_read_idx = 0; 471 alx_write_mem32(hw, ALX_RRD_ADDR_LO, np->rxq->rrd_dma); 472 alx_write_mem32(hw, ALX_RFD_ADDR_LO, np->rxq->rfd_dma); 473 } 474 } 475 476 alx_write_mem32(hw, ALX_TX_BASE_ADDR_HI, addr_hi); 477 alx_write_mem32(hw, ALX_TPD_RING_SZ, alx->tx_ringsz); 478 479 alx_write_mem32(hw, ALX_RX_BASE_ADDR_HI, addr_hi); 480 alx_write_mem32(hw, ALX_RRD_RING_SZ, alx->rx_ringsz); 481 alx_write_mem32(hw, ALX_RFD_RING_SZ, alx->rx_ringsz); 482 alx_write_mem32(hw, ALX_RFD_BUF_SZ, alx->rxbuf_size); 483 484 /* load these pointers into the chip */ 485 alx_write_mem32(hw, ALX_SRAM9, ALX_SRAM_LOAD_PTR); 486} 487 488static void alx_free_txring_buf(struct alx_tx_queue *txq) 489{ 490 int i; 491 492 if (!txq->bufs) 493 return; 494 495 for (i = 0; i < txq->count; i++) 496 alx_free_txbuf(txq, i); 497 498 memset(txq->bufs, 0, txq->count * sizeof(struct alx_buffer)); 499 memset(txq->tpd, 0, txq->count * sizeof(struct alx_txd)); 500 txq->write_idx = 0; 501 txq->read_idx = 0; 502 503 netdev_tx_reset_queue(alx_get_tx_queue(txq)); 504} 505 506static void alx_free_rxring_buf(struct alx_rx_queue *rxq) 507{ 508 struct alx_buffer *cur_buf; 509 u16 i; 510 511 if (!rxq->bufs) 512 return; 513 514 for (i = 0; i < rxq->count; i++) { 515 cur_buf = rxq->bufs + i; 516 if (cur_buf->skb) { 517 dma_unmap_single(rxq->dev, 518 dma_unmap_addr(cur_buf, dma), 519 dma_unmap_len(cur_buf, size), 520 DMA_FROM_DEVICE); 521 dev_kfree_skb(cur_buf->skb); 522 cur_buf->skb = NULL; 523 dma_unmap_len_set(cur_buf, size, 0); 524 dma_unmap_addr_set(cur_buf, dma, 0); 525 } 526 } 527 528 rxq->write_idx = 0; 529 rxq->read_idx = 0; 530 rxq->rrd_read_idx = 0; 531} 532 533static void alx_free_buffers(struct alx_priv *alx) 534{ 535 int i; 536 537 for (i = 0; i < alx->num_txq; i++) 538 if (alx->qnapi[i] && alx->qnapi[i]->txq) 539 alx_free_txring_buf(alx->qnapi[i]->txq); 540 541 if (alx->qnapi[0] && alx->qnapi[0]->rxq) 542 alx_free_rxring_buf(alx->qnapi[0]->rxq); 543} 544 545static int alx_reinit_rings(struct alx_priv *alx) 546{ 547 alx_free_buffers(alx); 548 549 alx_init_ring_ptrs(alx); 550 551 if (!alx_refill_rx_ring(alx, GFP_KERNEL)) 552 return -ENOMEM; 553 554 return 0; 555} 556 557static void alx_add_mc_addr(struct alx_hw *hw, const u8 *addr, u32 *mc_hash) 558{ 559 u32 crc32, bit, reg; 560 561 crc32 = ether_crc(ETH_ALEN, addr); 562 reg = (crc32 >> 31) & 0x1; 563 bit = (crc32 >> 26) & 0x1F; 564 565 mc_hash[reg] |= BIT(bit); 566} 567 568static void __alx_set_rx_mode(struct net_device *netdev) 569{ 570 struct alx_priv *alx = netdev_priv(netdev); 571 struct alx_hw *hw = &alx->hw; 572 struct netdev_hw_addr *ha; 573 u32 mc_hash[2] = {}; 574 575 if (!(netdev->flags & IFF_ALLMULTI)) { 576 netdev_for_each_mc_addr(ha, netdev) 577 alx_add_mc_addr(hw, ha->addr, mc_hash); 578 579 alx_write_mem32(hw, ALX_HASH_TBL0, mc_hash[0]); 580 alx_write_mem32(hw, ALX_HASH_TBL1, mc_hash[1]); 581 } 582 583 hw->rx_ctrl &= ~(ALX_MAC_CTRL_MULTIALL_EN | ALX_MAC_CTRL_PROMISC_EN); 584 if (netdev->flags & IFF_PROMISC) 585 hw->rx_ctrl |= ALX_MAC_CTRL_PROMISC_EN; 586 if (netdev->flags & IFF_ALLMULTI) 587 hw->rx_ctrl |= ALX_MAC_CTRL_MULTIALL_EN; 588 589 alx_write_mem32(hw, ALX_MAC_CTRL, hw->rx_ctrl); 590} 591 592static void alx_set_rx_mode(struct net_device *netdev) 593{ 594 __alx_set_rx_mode(netdev); 595} 596 597static int alx_set_mac_address(struct net_device *netdev, void *data) 598{ 599 struct alx_priv *alx = netdev_priv(netdev); 600 struct alx_hw *hw = &alx->hw; 601 struct sockaddr *addr = data; 602 603 if (!is_valid_ether_addr(addr->sa_data)) 604 return -EADDRNOTAVAIL; 605 606 if (netdev->addr_assign_type & NET_ADDR_RANDOM) 607 netdev->addr_assign_type ^= NET_ADDR_RANDOM; 608 609 eth_hw_addr_set(netdev, addr->sa_data); 610 memcpy(hw->mac_addr, addr->sa_data, netdev->addr_len); 611 alx_set_macaddr(hw, hw->mac_addr); 612 613 return 0; 614} 615 616static int alx_alloc_tx_ring(struct alx_priv *alx, struct alx_tx_queue *txq, 617 int offset) 618{ 619 txq->bufs = kcalloc(txq->count, sizeof(struct alx_buffer), GFP_KERNEL); 620 if (!txq->bufs) 621 return -ENOMEM; 622 623 txq->tpd = alx->descmem.virt + offset; 624 txq->tpd_dma = alx->descmem.dma + offset; 625 offset += sizeof(struct alx_txd) * txq->count; 626 627 return offset; 628} 629 630static int alx_alloc_rx_ring(struct alx_priv *alx, struct alx_rx_queue *rxq, 631 int offset) 632{ 633 rxq->bufs = kcalloc(rxq->count, sizeof(struct alx_buffer), GFP_KERNEL); 634 if (!rxq->bufs) 635 return -ENOMEM; 636 637 rxq->rrd = alx->descmem.virt + offset; 638 rxq->rrd_dma = alx->descmem.dma + offset; 639 offset += sizeof(struct alx_rrd) * rxq->count; 640 641 rxq->rfd = alx->descmem.virt + offset; 642 rxq->rfd_dma = alx->descmem.dma + offset; 643 offset += sizeof(struct alx_rfd) * rxq->count; 644 645 return offset; 646} 647 648static int alx_alloc_rings(struct alx_priv *alx) 649{ 650 int i, offset = 0; 651 652 /* physical tx/rx ring descriptors 653 * 654 * Allocate them as a single chunk because they must not cross a 655 * 4G boundary (hardware has a single register for high 32 bits 656 * of addresses only) 657 */ 658 alx->descmem.size = sizeof(struct alx_txd) * alx->tx_ringsz * 659 alx->num_txq + 660 sizeof(struct alx_rrd) * alx->rx_ringsz + 661 sizeof(struct alx_rfd) * alx->rx_ringsz; 662 alx->descmem.virt = dma_alloc_coherent(&alx->hw.pdev->dev, 663 alx->descmem.size, 664 &alx->descmem.dma, GFP_KERNEL); 665 if (!alx->descmem.virt) 666 return -ENOMEM; 667 668 /* alignment requirements */ 669 BUILD_BUG_ON(sizeof(struct alx_txd) % 8); 670 BUILD_BUG_ON(sizeof(struct alx_rrd) % 8); 671 672 for (i = 0; i < alx->num_txq; i++) { 673 offset = alx_alloc_tx_ring(alx, alx->qnapi[i]->txq, offset); 674 if (offset < 0) { 675 netdev_err(alx->dev, "Allocation of tx buffer failed!\n"); 676 return -ENOMEM; 677 } 678 } 679 680 offset = alx_alloc_rx_ring(alx, alx->qnapi[0]->rxq, offset); 681 if (offset < 0) { 682 netdev_err(alx->dev, "Allocation of rx buffer failed!\n"); 683 return -ENOMEM; 684 } 685 686 return 0; 687} 688 689static void alx_free_rings(struct alx_priv *alx) 690{ 691 int i; 692 693 alx_free_buffers(alx); 694 695 for (i = 0; i < alx->num_txq; i++) 696 if (alx->qnapi[i] && alx->qnapi[i]->txq) 697 kfree(alx->qnapi[i]->txq->bufs); 698 699 if (alx->qnapi[0] && alx->qnapi[0]->rxq) 700 kfree(alx->qnapi[0]->rxq->bufs); 701 702 if (alx->descmem.virt) 703 dma_free_coherent(&alx->hw.pdev->dev, 704 alx->descmem.size, 705 alx->descmem.virt, 706 alx->descmem.dma); 707} 708 709static void alx_free_napis(struct alx_priv *alx) 710{ 711 struct alx_napi *np; 712 int i; 713 714 for (i = 0; i < alx->num_napi; i++) { 715 np = alx->qnapi[i]; 716 if (!np) 717 continue; 718 719 netif_napi_del(&np->napi); 720 kfree(np->txq); 721 kfree(np->rxq); 722 kfree(np); 723 alx->qnapi[i] = NULL; 724 } 725} 726 727static const u16 tx_pidx_reg[] = {ALX_TPD_PRI0_PIDX, ALX_TPD_PRI1_PIDX, 728 ALX_TPD_PRI2_PIDX, ALX_TPD_PRI3_PIDX}; 729static const u16 tx_cidx_reg[] = {ALX_TPD_PRI0_CIDX, ALX_TPD_PRI1_CIDX, 730 ALX_TPD_PRI2_CIDX, ALX_TPD_PRI3_CIDX}; 731static const u32 tx_vect_mask[] = {ALX_ISR_TX_Q0, ALX_ISR_TX_Q1, 732 ALX_ISR_TX_Q2, ALX_ISR_TX_Q3}; 733static const u32 rx_vect_mask[] = {ALX_ISR_RX_Q0, ALX_ISR_RX_Q1, 734 ALX_ISR_RX_Q2, ALX_ISR_RX_Q3, 735 ALX_ISR_RX_Q4, ALX_ISR_RX_Q5, 736 ALX_ISR_RX_Q6, ALX_ISR_RX_Q7}; 737 738static int alx_alloc_napis(struct alx_priv *alx) 739{ 740 struct alx_napi *np; 741 struct alx_rx_queue *rxq; 742 struct alx_tx_queue *txq; 743 int i; 744 745 alx->int_mask &= ~ALX_ISR_ALL_QUEUES; 746 747 /* allocate alx_napi structures */ 748 for (i = 0; i < alx->num_napi; i++) { 749 np = kzalloc(sizeof(struct alx_napi), GFP_KERNEL); 750 if (!np) 751 goto err_out; 752 753 np->alx = alx; 754 netif_napi_add(alx->dev, &np->napi, alx_poll); 755 alx->qnapi[i] = np; 756 } 757 758 /* allocate tx queues */ 759 for (i = 0; i < alx->num_txq; i++) { 760 np = alx->qnapi[i]; 761 txq = kzalloc(sizeof(*txq), GFP_KERNEL); 762 if (!txq) 763 goto err_out; 764 765 np->txq = txq; 766 txq->p_reg = tx_pidx_reg[i]; 767 txq->c_reg = tx_cidx_reg[i]; 768 txq->queue_idx = i; 769 txq->count = alx->tx_ringsz; 770 txq->netdev = alx->dev; 771 txq->dev = &alx->hw.pdev->dev; 772 np->vec_mask |= tx_vect_mask[i]; 773 alx->int_mask |= tx_vect_mask[i]; 774 } 775 776 /* allocate rx queues */ 777 np = alx->qnapi[0]; 778 rxq = kzalloc(sizeof(*rxq), GFP_KERNEL); 779 if (!rxq) 780 goto err_out; 781 782 np->rxq = rxq; 783 rxq->np = alx->qnapi[0]; 784 rxq->queue_idx = 0; 785 rxq->count = alx->rx_ringsz; 786 rxq->netdev = alx->dev; 787 rxq->dev = &alx->hw.pdev->dev; 788 np->vec_mask |= rx_vect_mask[0]; 789 alx->int_mask |= rx_vect_mask[0]; 790 791 return 0; 792 793err_out: 794 netdev_err(alx->dev, "error allocating internal structures\n"); 795 alx_free_napis(alx); 796 return -ENOMEM; 797} 798 799static const int txq_vec_mapping_shift[] = { 800 0, ALX_MSI_MAP_TBL1_TXQ0_SHIFT, 801 0, ALX_MSI_MAP_TBL1_TXQ1_SHIFT, 802 1, ALX_MSI_MAP_TBL2_TXQ2_SHIFT, 803 1, ALX_MSI_MAP_TBL2_TXQ3_SHIFT, 804}; 805 806static void alx_config_vector_mapping(struct alx_priv *alx) 807{ 808 struct alx_hw *hw = &alx->hw; 809 u32 tbl[2] = {0, 0}; 810 int i, vector, idx, shift; 811 812 if (alx->hw.pdev->msix_enabled) { 813 /* tx mappings */ 814 for (i = 0, vector = 1; i < alx->num_txq; i++, vector++) { 815 idx = txq_vec_mapping_shift[i * 2]; 816 shift = txq_vec_mapping_shift[i * 2 + 1]; 817 tbl[idx] |= vector << shift; 818 } 819 820 /* rx mapping */ 821 tbl[0] |= 1 << ALX_MSI_MAP_TBL1_RXQ0_SHIFT; 822 } 823 824 alx_write_mem32(hw, ALX_MSI_MAP_TBL1, tbl[0]); 825 alx_write_mem32(hw, ALX_MSI_MAP_TBL2, tbl[1]); 826 alx_write_mem32(hw, ALX_MSI_ID_MAP, 0); 827} 828 829static int alx_enable_msix(struct alx_priv *alx) 830{ 831 int err, num_vec, num_txq, num_rxq; 832 833 num_txq = min_t(int, num_online_cpus(), ALX_MAX_TX_QUEUES); 834 num_rxq = 1; 835 num_vec = max_t(int, num_txq, num_rxq) + 1; 836 837 err = pci_alloc_irq_vectors(alx->hw.pdev, num_vec, num_vec, 838 PCI_IRQ_MSIX); 839 if (err < 0) { 840 netdev_warn(alx->dev, "Enabling MSI-X interrupts failed!\n"); 841 return err; 842 } 843 844 alx->num_vec = num_vec; 845 alx->num_napi = num_vec - 1; 846 alx->num_txq = num_txq; 847 alx->num_rxq = num_rxq; 848 849 return err; 850} 851 852static int alx_request_msix(struct alx_priv *alx) 853{ 854 struct net_device *netdev = alx->dev; 855 int i, err, vector = 0, free_vector = 0; 856 857 err = request_irq(pci_irq_vector(alx->hw.pdev, 0), alx_intr_msix_misc, 858 0, netdev->name, alx); 859 if (err) 860 goto out_err; 861 862 for (i = 0; i < alx->num_napi; i++) { 863 struct alx_napi *np = alx->qnapi[i]; 864 865 vector++; 866 867 if (np->txq && np->rxq) 868 sprintf(np->irq_lbl, "%s-TxRx-%u", netdev->name, 869 np->txq->queue_idx); 870 else if (np->txq) 871 sprintf(np->irq_lbl, "%s-tx-%u", netdev->name, 872 np->txq->queue_idx); 873 else if (np->rxq) 874 sprintf(np->irq_lbl, "%s-rx-%u", netdev->name, 875 np->rxq->queue_idx); 876 else 877 sprintf(np->irq_lbl, "%s-unused", netdev->name); 878 879 np->vec_idx = vector; 880 err = request_irq(pci_irq_vector(alx->hw.pdev, vector), 881 alx_intr_msix_ring, 0, np->irq_lbl, np); 882 if (err) 883 goto out_free; 884 } 885 return 0; 886 887out_free: 888 free_irq(pci_irq_vector(alx->hw.pdev, free_vector++), alx); 889 890 vector--; 891 for (i = 0; i < vector; i++) 892 free_irq(pci_irq_vector(alx->hw.pdev,free_vector++), 893 alx->qnapi[i]); 894 895out_err: 896 return err; 897} 898 899static int alx_init_intr(struct alx_priv *alx) 900{ 901 int ret; 902 903 ret = pci_alloc_irq_vectors(alx->hw.pdev, 1, 1, 904 PCI_IRQ_MSI | PCI_IRQ_LEGACY); 905 if (ret < 0) 906 return ret; 907 908 alx->num_vec = 1; 909 alx->num_napi = 1; 910 alx->num_txq = 1; 911 alx->num_rxq = 1; 912 return 0; 913} 914 915static void alx_irq_enable(struct alx_priv *alx) 916{ 917 struct alx_hw *hw = &alx->hw; 918 int i; 919 920 /* level-1 interrupt switch */ 921 alx_write_mem32(hw, ALX_ISR, 0); 922 alx_write_mem32(hw, ALX_IMR, alx->int_mask); 923 alx_post_write(hw); 924 925 if (alx->hw.pdev->msix_enabled) { 926 /* enable all msix irqs */ 927 for (i = 0; i < alx->num_vec; i++) 928 alx_mask_msix(hw, i, false); 929 } 930} 931 932static void alx_irq_disable(struct alx_priv *alx) 933{ 934 struct alx_hw *hw = &alx->hw; 935 int i; 936 937 alx_write_mem32(hw, ALX_ISR, ALX_ISR_DIS); 938 alx_write_mem32(hw, ALX_IMR, 0); 939 alx_post_write(hw); 940 941 if (alx->hw.pdev->msix_enabled) { 942 for (i = 0; i < alx->num_vec; i++) { 943 alx_mask_msix(hw, i, true); 944 synchronize_irq(pci_irq_vector(alx->hw.pdev, i)); 945 } 946 } else { 947 synchronize_irq(pci_irq_vector(alx->hw.pdev, 0)); 948 } 949} 950 951static int alx_realloc_resources(struct alx_priv *alx) 952{ 953 int err; 954 955 alx_free_rings(alx); 956 alx_free_napis(alx); 957 pci_free_irq_vectors(alx->hw.pdev); 958 959 err = alx_init_intr(alx); 960 if (err) 961 return err; 962 963 err = alx_alloc_napis(alx); 964 if (err) 965 return err; 966 967 err = alx_alloc_rings(alx); 968 if (err) 969 return err; 970 971 return 0; 972} 973 974static int alx_request_irq(struct alx_priv *alx) 975{ 976 struct pci_dev *pdev = alx->hw.pdev; 977 struct alx_hw *hw = &alx->hw; 978 int err; 979 u32 msi_ctrl; 980 981 msi_ctrl = (hw->imt >> 1) << ALX_MSI_RETRANS_TM_SHIFT; 982 983 if (alx->hw.pdev->msix_enabled) { 984 alx_write_mem32(hw, ALX_MSI_RETRANS_TIMER, msi_ctrl); 985 err = alx_request_msix(alx); 986 if (!err) 987 goto out; 988 989 /* msix request failed, realloc resources */ 990 err = alx_realloc_resources(alx); 991 if (err) 992 goto out; 993 } 994 995 if (alx->hw.pdev->msi_enabled) { 996 alx_write_mem32(hw, ALX_MSI_RETRANS_TIMER, 997 msi_ctrl | ALX_MSI_MASK_SEL_LINE); 998 err = request_irq(pci_irq_vector(pdev, 0), alx_intr_msi, 0, 999 alx->dev->name, alx); 1000 if (!err) 1001 goto out; 1002 1003 /* fall back to legacy interrupt */ 1004 pci_free_irq_vectors(alx->hw.pdev); 1005 } 1006 1007 alx_write_mem32(hw, ALX_MSI_RETRANS_TIMER, 0); 1008 err = request_irq(pci_irq_vector(pdev, 0), alx_intr_legacy, IRQF_SHARED, 1009 alx->dev->name, alx); 1010out: 1011 if (!err) 1012 alx_config_vector_mapping(alx); 1013 else 1014 netdev_err(alx->dev, "IRQ registration failed!\n"); 1015 return err; 1016} 1017 1018static void alx_free_irq(struct alx_priv *alx) 1019{ 1020 struct pci_dev *pdev = alx->hw.pdev; 1021 int i; 1022 1023 free_irq(pci_irq_vector(pdev, 0), alx); 1024 if (alx->hw.pdev->msix_enabled) { 1025 for (i = 0; i < alx->num_napi; i++) 1026 free_irq(pci_irq_vector(pdev, i + 1), alx->qnapi[i]); 1027 } 1028 1029 pci_free_irq_vectors(pdev); 1030} 1031 1032static int alx_identify_hw(struct alx_priv *alx) 1033{ 1034 struct alx_hw *hw = &alx->hw; 1035 int rev = alx_hw_revision(hw); 1036 1037 if (rev > ALX_REV_C0) 1038 return -EINVAL; 1039 1040 hw->max_dma_chnl = rev >= ALX_REV_B0 ? 4 : 2; 1041 1042 return 0; 1043} 1044 1045static int alx_init_sw(struct alx_priv *alx) 1046{ 1047 struct pci_dev *pdev = alx->hw.pdev; 1048 struct alx_hw *hw = &alx->hw; 1049 int err; 1050 1051 err = alx_identify_hw(alx); 1052 if (err) { 1053 dev_err(&pdev->dev, "unrecognized chip, aborting\n"); 1054 return err; 1055 } 1056 1057 alx->hw.lnk_patch = 1058 pdev->device == ALX_DEV_ID_AR8161 && 1059 pdev->subsystem_vendor == PCI_VENDOR_ID_ATTANSIC && 1060 pdev->subsystem_device == 0x0091 && 1061 pdev->revision == 0; 1062 1063 hw->smb_timer = 400; 1064 hw->mtu = alx->dev->mtu; 1065 alx->rxbuf_size = ALX_MAX_FRAME_LEN(hw->mtu); 1066 /* MTU range: 34 - 9256 */ 1067 alx->dev->min_mtu = 34; 1068 alx->dev->max_mtu = ALX_MAX_FRAME_LEN(ALX_MAX_FRAME_SIZE); 1069 alx->tx_ringsz = 256; 1070 alx->rx_ringsz = 512; 1071 hw->imt = 200; 1072 alx->int_mask = ALX_ISR_MISC; 1073 hw->dma_chnl = hw->max_dma_chnl; 1074 hw->ith_tpd = alx->tx_ringsz / 3; 1075 hw->link_speed = SPEED_UNKNOWN; 1076 hw->duplex = DUPLEX_UNKNOWN; 1077 hw->adv_cfg = ADVERTISED_Autoneg | 1078 ADVERTISED_10baseT_Half | 1079 ADVERTISED_10baseT_Full | 1080 ADVERTISED_100baseT_Full | 1081 ADVERTISED_100baseT_Half | 1082 ADVERTISED_1000baseT_Full; 1083 hw->flowctrl = ALX_FC_ANEG | ALX_FC_RX | ALX_FC_TX; 1084 1085 hw->rx_ctrl = ALX_MAC_CTRL_WOLSPED_SWEN | 1086 ALX_MAC_CTRL_MHASH_ALG_HI5B | 1087 ALX_MAC_CTRL_BRD_EN | 1088 ALX_MAC_CTRL_PCRCE | 1089 ALX_MAC_CTRL_CRCE | 1090 ALX_MAC_CTRL_RXFC_EN | 1091 ALX_MAC_CTRL_TXFC_EN | 1092 7 << ALX_MAC_CTRL_PRMBLEN_SHIFT; 1093 mutex_init(&alx->mtx); 1094 1095 return 0; 1096} 1097 1098 1099static netdev_features_t alx_fix_features(struct net_device *netdev, 1100 netdev_features_t features) 1101{ 1102 if (netdev->mtu > ALX_MAX_TSO_PKT_SIZE) 1103 features &= ~(NETIF_F_TSO | NETIF_F_TSO6); 1104 1105 return features; 1106} 1107 1108static void alx_netif_stop(struct alx_priv *alx) 1109{ 1110 int i; 1111 1112 netif_trans_update(alx->dev); 1113 if (netif_carrier_ok(alx->dev)) { 1114 netif_carrier_off(alx->dev); 1115 netif_tx_disable(alx->dev); 1116 for (i = 0; i < alx->num_napi; i++) 1117 napi_disable(&alx->qnapi[i]->napi); 1118 } 1119} 1120 1121static void alx_halt(struct alx_priv *alx) 1122{ 1123 struct alx_hw *hw = &alx->hw; 1124 1125 lockdep_assert_held(&alx->mtx); 1126 1127 alx_netif_stop(alx); 1128 hw->link_speed = SPEED_UNKNOWN; 1129 hw->duplex = DUPLEX_UNKNOWN; 1130 1131 alx_reset_mac(hw); 1132 1133 /* disable l0s/l1 */ 1134 alx_enable_aspm(hw, false, false); 1135 alx_irq_disable(alx); 1136 alx_free_buffers(alx); 1137} 1138 1139static void alx_configure(struct alx_priv *alx) 1140{ 1141 struct alx_hw *hw = &alx->hw; 1142 1143 alx_configure_basic(hw); 1144 alx_disable_rss(hw); 1145 __alx_set_rx_mode(alx->dev); 1146 1147 alx_write_mem32(hw, ALX_MAC_CTRL, hw->rx_ctrl); 1148} 1149 1150static void alx_activate(struct alx_priv *alx) 1151{ 1152 lockdep_assert_held(&alx->mtx); 1153 1154 /* hardware setting lost, restore it */ 1155 alx_reinit_rings(alx); 1156 alx_configure(alx); 1157 1158 /* clear old interrupts */ 1159 alx_write_mem32(&alx->hw, ALX_ISR, ~(u32)ALX_ISR_DIS); 1160 1161 alx_irq_enable(alx); 1162 1163 alx_schedule_link_check(alx); 1164} 1165 1166static void alx_reinit(struct alx_priv *alx) 1167{ 1168 lockdep_assert_held(&alx->mtx); 1169 1170 alx_halt(alx); 1171 alx_activate(alx); 1172} 1173 1174static int alx_change_mtu(struct net_device *netdev, int mtu) 1175{ 1176 struct alx_priv *alx = netdev_priv(netdev); 1177 int max_frame = ALX_MAX_FRAME_LEN(mtu); 1178 1179 netdev->mtu = mtu; 1180 alx->hw.mtu = mtu; 1181 alx->rxbuf_size = max(max_frame, ALX_DEF_RXBUF_SIZE); 1182 netdev_update_features(netdev); 1183 if (netif_running(netdev)) { 1184 mutex_lock(&alx->mtx); 1185 alx_reinit(alx); 1186 mutex_unlock(&alx->mtx); 1187 } 1188 return 0; 1189} 1190 1191static void alx_netif_start(struct alx_priv *alx) 1192{ 1193 int i; 1194 1195 netif_tx_wake_all_queues(alx->dev); 1196 for (i = 0; i < alx->num_napi; i++) 1197 napi_enable(&alx->qnapi[i]->napi); 1198 netif_carrier_on(alx->dev); 1199} 1200 1201static int __alx_open(struct alx_priv *alx, bool resume) 1202{ 1203 int err; 1204 1205 err = alx_enable_msix(alx); 1206 if (err < 0) { 1207 err = alx_init_intr(alx); 1208 if (err) 1209 return err; 1210 } 1211 1212 if (!resume) 1213 netif_carrier_off(alx->dev); 1214 1215 err = alx_alloc_napis(alx); 1216 if (err) 1217 goto out_disable_adv_intr; 1218 1219 err = alx_alloc_rings(alx); 1220 if (err) 1221 goto out_free_rings; 1222 1223 alx_configure(alx); 1224 1225 err = alx_request_irq(alx); 1226 if (err) 1227 goto out_free_rings; 1228 1229 /* must be called after alx_request_irq because the chip stops working 1230 * if we copy the dma addresses in alx_init_ring_ptrs twice when 1231 * requesting msi-x interrupts failed 1232 */ 1233 alx_reinit_rings(alx); 1234 1235 netif_set_real_num_tx_queues(alx->dev, alx->num_txq); 1236 netif_set_real_num_rx_queues(alx->dev, alx->num_rxq); 1237 1238 /* clear old interrupts */ 1239 alx_write_mem32(&alx->hw, ALX_ISR, ~(u32)ALX_ISR_DIS); 1240 1241 alx_irq_enable(alx); 1242 1243 if (!resume) 1244 netif_tx_start_all_queues(alx->dev); 1245 1246 alx_schedule_link_check(alx); 1247 return 0; 1248 1249out_free_rings: 1250 alx_free_rings(alx); 1251 alx_free_napis(alx); 1252out_disable_adv_intr: 1253 pci_free_irq_vectors(alx->hw.pdev); 1254 return err; 1255} 1256 1257static void __alx_stop(struct alx_priv *alx) 1258{ 1259 lockdep_assert_held(&alx->mtx); 1260 1261 alx_free_irq(alx); 1262 1263 cancel_work_sync(&alx->link_check_wk); 1264 cancel_work_sync(&alx->reset_wk); 1265 1266 alx_halt(alx); 1267 alx_free_rings(alx); 1268 alx_free_napis(alx); 1269} 1270 1271static const char *alx_speed_desc(struct alx_hw *hw) 1272{ 1273 switch (alx_speed_to_ethadv(hw->link_speed, hw->duplex)) { 1274 case ADVERTISED_1000baseT_Full: 1275 return "1 Gbps Full"; 1276 case ADVERTISED_100baseT_Full: 1277 return "100 Mbps Full"; 1278 case ADVERTISED_100baseT_Half: 1279 return "100 Mbps Half"; 1280 case ADVERTISED_10baseT_Full: 1281 return "10 Mbps Full"; 1282 case ADVERTISED_10baseT_Half: 1283 return "10 Mbps Half"; 1284 default: 1285 return "Unknown speed"; 1286 } 1287} 1288 1289static void alx_check_link(struct alx_priv *alx) 1290{ 1291 struct alx_hw *hw = &alx->hw; 1292 unsigned long flags; 1293 int old_speed; 1294 int err; 1295 1296 lockdep_assert_held(&alx->mtx); 1297 1298 /* clear PHY internal interrupt status, otherwise the main 1299 * interrupt status will be asserted forever 1300 */ 1301 alx_clear_phy_intr(hw); 1302 1303 old_speed = hw->link_speed; 1304 err = alx_read_phy_link(hw); 1305 if (err < 0) 1306 goto reset; 1307 1308 spin_lock_irqsave(&alx->irq_lock, flags); 1309 alx->int_mask |= ALX_ISR_PHY; 1310 alx_write_mem32(hw, ALX_IMR, alx->int_mask); 1311 spin_unlock_irqrestore(&alx->irq_lock, flags); 1312 1313 if (old_speed == hw->link_speed) 1314 return; 1315 1316 if (hw->link_speed != SPEED_UNKNOWN) { 1317 netif_info(alx, link, alx->dev, 1318 "NIC Up: %s\n", alx_speed_desc(hw)); 1319 alx_post_phy_link(hw); 1320 alx_enable_aspm(hw, true, true); 1321 alx_start_mac(hw); 1322 1323 if (old_speed == SPEED_UNKNOWN) 1324 alx_netif_start(alx); 1325 } else { 1326 /* link is now down */ 1327 alx_netif_stop(alx); 1328 netif_info(alx, link, alx->dev, "Link Down\n"); 1329 err = alx_reset_mac(hw); 1330 if (err) 1331 goto reset; 1332 alx_irq_disable(alx); 1333 1334 /* MAC reset causes all HW settings to be lost, restore all */ 1335 err = alx_reinit_rings(alx); 1336 if (err) 1337 goto reset; 1338 alx_configure(alx); 1339 alx_enable_aspm(hw, false, true); 1340 alx_post_phy_link(hw); 1341 alx_irq_enable(alx); 1342 } 1343 1344 return; 1345 1346reset: 1347 alx_schedule_reset(alx); 1348} 1349 1350static int alx_open(struct net_device *netdev) 1351{ 1352 struct alx_priv *alx = netdev_priv(netdev); 1353 int ret; 1354 1355 mutex_lock(&alx->mtx); 1356 ret = __alx_open(alx, false); 1357 mutex_unlock(&alx->mtx); 1358 1359 return ret; 1360} 1361 1362static int alx_stop(struct net_device *netdev) 1363{ 1364 struct alx_priv *alx = netdev_priv(netdev); 1365 1366 mutex_lock(&alx->mtx); 1367 __alx_stop(alx); 1368 mutex_unlock(&alx->mtx); 1369 1370 return 0; 1371} 1372 1373static void alx_link_check(struct work_struct *work) 1374{ 1375 struct alx_priv *alx; 1376 1377 alx = container_of(work, struct alx_priv, link_check_wk); 1378 1379 mutex_lock(&alx->mtx); 1380 alx_check_link(alx); 1381 mutex_unlock(&alx->mtx); 1382} 1383 1384static void alx_reset(struct work_struct *work) 1385{ 1386 struct alx_priv *alx = container_of(work, struct alx_priv, reset_wk); 1387 1388 mutex_lock(&alx->mtx); 1389 alx_reinit(alx); 1390 mutex_unlock(&alx->mtx); 1391} 1392 1393static int alx_tpd_req(struct sk_buff *skb) 1394{ 1395 int num; 1396 1397 num = skb_shinfo(skb)->nr_frags + 1; 1398 /* we need one extra descriptor for LSOv2 */ 1399 if (skb_is_gso(skb) && skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6) 1400 num++; 1401 1402 return num; 1403} 1404 1405static int alx_tx_csum(struct sk_buff *skb, struct alx_txd *first) 1406{ 1407 u8 cso, css; 1408 1409 if (skb->ip_summed != CHECKSUM_PARTIAL) 1410 return 0; 1411 1412 cso = skb_checksum_start_offset(skb); 1413 if (cso & 1) 1414 return -EINVAL; 1415 1416 css = cso + skb->csum_offset; 1417 first->word1 |= cpu_to_le32((cso >> 1) << TPD_CXSUMSTART_SHIFT); 1418 first->word1 |= cpu_to_le32((css >> 1) << TPD_CXSUMOFFSET_SHIFT); 1419 first->word1 |= cpu_to_le32(1 << TPD_CXSUM_EN_SHIFT); 1420 1421 return 0; 1422} 1423 1424static int alx_tso(struct sk_buff *skb, struct alx_txd *first) 1425{ 1426 int err; 1427 1428 if (skb->ip_summed != CHECKSUM_PARTIAL) 1429 return 0; 1430 1431 if (!skb_is_gso(skb)) 1432 return 0; 1433 1434 err = skb_cow_head(skb, 0); 1435 if (err < 0) 1436 return err; 1437 1438 if (skb->protocol == htons(ETH_P_IP)) { 1439 struct iphdr *iph = ip_hdr(skb); 1440 1441 iph->check = 0; 1442 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr, 1443 0, IPPROTO_TCP, 0); 1444 first->word1 |= 1 << TPD_IPV4_SHIFT; 1445 } else if (skb_is_gso_v6(skb)) { 1446 tcp_v6_gso_csum_prep(skb); 1447 /* LSOv2: the first TPD only provides the packet length */ 1448 first->adrl.l.pkt_len = skb->len; 1449 first->word1 |= 1 << TPD_LSO_V2_SHIFT; 1450 } 1451 1452 first->word1 |= 1 << TPD_LSO_EN_SHIFT; 1453 first->word1 |= (skb_transport_offset(skb) & 1454 TPD_L4HDROFFSET_MASK) << TPD_L4HDROFFSET_SHIFT; 1455 first->word1 |= (skb_shinfo(skb)->gso_size & 1456 TPD_MSS_MASK) << TPD_MSS_SHIFT; 1457 return 1; 1458} 1459 1460static int alx_map_tx_skb(struct alx_tx_queue *txq, struct sk_buff *skb) 1461{ 1462 struct alx_txd *tpd, *first_tpd; 1463 dma_addr_t dma; 1464 int maplen, f, first_idx = txq->write_idx; 1465 1466 first_tpd = &txq->tpd[txq->write_idx]; 1467 tpd = first_tpd; 1468 1469 if (tpd->word1 & (1 << TPD_LSO_V2_SHIFT)) { 1470 if (++txq->write_idx == txq->count) 1471 txq->write_idx = 0; 1472 1473 tpd = &txq->tpd[txq->write_idx]; 1474 tpd->len = first_tpd->len; 1475 tpd->vlan_tag = first_tpd->vlan_tag; 1476 tpd->word1 = first_tpd->word1; 1477 } 1478 1479 maplen = skb_headlen(skb); 1480 dma = dma_map_single(txq->dev, skb->data, maplen, 1481 DMA_TO_DEVICE); 1482 if (dma_mapping_error(txq->dev, dma)) 1483 goto err_dma; 1484 1485 dma_unmap_len_set(&txq->bufs[txq->write_idx], size, maplen); 1486 dma_unmap_addr_set(&txq->bufs[txq->write_idx], dma, dma); 1487 1488 tpd->adrl.addr = cpu_to_le64(dma); 1489 tpd->len = cpu_to_le16(maplen); 1490 1491 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) { 1492 skb_frag_t *frag = &skb_shinfo(skb)->frags[f]; 1493 1494 if (++txq->write_idx == txq->count) 1495 txq->write_idx = 0; 1496 tpd = &txq->tpd[txq->write_idx]; 1497 1498 tpd->word1 = first_tpd->word1; 1499 1500 maplen = skb_frag_size(frag); 1501 dma = skb_frag_dma_map(txq->dev, frag, 0, 1502 maplen, DMA_TO_DEVICE); 1503 if (dma_mapping_error(txq->dev, dma)) 1504 goto err_dma; 1505 dma_unmap_len_set(&txq->bufs[txq->write_idx], size, maplen); 1506 dma_unmap_addr_set(&txq->bufs[txq->write_idx], dma, dma); 1507 1508 tpd->adrl.addr = cpu_to_le64(dma); 1509 tpd->len = cpu_to_le16(maplen); 1510 } 1511 1512 /* last TPD, set EOP flag and store skb */ 1513 tpd->word1 |= cpu_to_le32(1 << TPD_EOP_SHIFT); 1514 txq->bufs[txq->write_idx].skb = skb; 1515 1516 if (++txq->write_idx == txq->count) 1517 txq->write_idx = 0; 1518 1519 return 0; 1520 1521err_dma: 1522 f = first_idx; 1523 while (f != txq->write_idx) { 1524 alx_free_txbuf(txq, f); 1525 if (++f == txq->count) 1526 f = 0; 1527 } 1528 return -ENOMEM; 1529} 1530 1531static netdev_tx_t alx_start_xmit_ring(struct sk_buff *skb, 1532 struct alx_tx_queue *txq) 1533{ 1534 struct alx_priv *alx; 1535 struct alx_txd *first; 1536 int tso; 1537 1538 alx = netdev_priv(txq->netdev); 1539 1540 if (alx_tpd_avail(txq) < alx_tpd_req(skb)) { 1541 netif_tx_stop_queue(alx_get_tx_queue(txq)); 1542 goto drop; 1543 } 1544 1545 first = &txq->tpd[txq->write_idx]; 1546 memset(first, 0, sizeof(*first)); 1547 1548 tso = alx_tso(skb, first); 1549 if (tso < 0) 1550 goto drop; 1551 else if (!tso && alx_tx_csum(skb, first)) 1552 goto drop; 1553 1554 if (alx_map_tx_skb(txq, skb) < 0) 1555 goto drop; 1556 1557 netdev_tx_sent_queue(alx_get_tx_queue(txq), skb->len); 1558 1559 /* flush updates before updating hardware */ 1560 wmb(); 1561 alx_write_mem16(&alx->hw, txq->p_reg, txq->write_idx); 1562 1563 if (alx_tpd_avail(txq) < txq->count / 8) 1564 netif_tx_stop_queue(alx_get_tx_queue(txq)); 1565 1566 return NETDEV_TX_OK; 1567 1568drop: 1569 dev_kfree_skb_any(skb); 1570 return NETDEV_TX_OK; 1571} 1572 1573static netdev_tx_t alx_start_xmit(struct sk_buff *skb, 1574 struct net_device *netdev) 1575{ 1576 struct alx_priv *alx = netdev_priv(netdev); 1577 return alx_start_xmit_ring(skb, alx_tx_queue_mapping(alx, skb)); 1578} 1579 1580static void alx_tx_timeout(struct net_device *dev, unsigned int txqueue) 1581{ 1582 struct alx_priv *alx = netdev_priv(dev); 1583 1584 alx_schedule_reset(alx); 1585} 1586 1587static int alx_mdio_read(struct net_device *netdev, 1588 int prtad, int devad, u16 addr) 1589{ 1590 struct alx_priv *alx = netdev_priv(netdev); 1591 struct alx_hw *hw = &alx->hw; 1592 u16 val; 1593 int err; 1594 1595 if (prtad != hw->mdio.prtad) 1596 return -EINVAL; 1597 1598 if (devad == MDIO_DEVAD_NONE) 1599 err = alx_read_phy_reg(hw, addr, &val); 1600 else 1601 err = alx_read_phy_ext(hw, devad, addr, &val); 1602 1603 if (err) 1604 return err; 1605 return val; 1606} 1607 1608static int alx_mdio_write(struct net_device *netdev, 1609 int prtad, int devad, u16 addr, u16 val) 1610{ 1611 struct alx_priv *alx = netdev_priv(netdev); 1612 struct alx_hw *hw = &alx->hw; 1613 1614 if (prtad != hw->mdio.prtad) 1615 return -EINVAL; 1616 1617 if (devad == MDIO_DEVAD_NONE) 1618 return alx_write_phy_reg(hw, addr, val); 1619 1620 return alx_write_phy_ext(hw, devad, addr, val); 1621} 1622 1623static int alx_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 1624{ 1625 struct alx_priv *alx = netdev_priv(netdev); 1626 1627 if (!netif_running(netdev)) 1628 return -EAGAIN; 1629 1630 return mdio_mii_ioctl(&alx->hw.mdio, if_mii(ifr), cmd); 1631} 1632 1633#ifdef CONFIG_NET_POLL_CONTROLLER 1634static void alx_poll_controller(struct net_device *netdev) 1635{ 1636 struct alx_priv *alx = netdev_priv(netdev); 1637 int i; 1638 1639 if (alx->hw.pdev->msix_enabled) { 1640 alx_intr_msix_misc(0, alx); 1641 for (i = 0; i < alx->num_txq; i++) 1642 alx_intr_msix_ring(0, alx->qnapi[i]); 1643 } else if (alx->hw.pdev->msi_enabled) 1644 alx_intr_msi(0, alx); 1645 else 1646 alx_intr_legacy(0, alx); 1647} 1648#endif 1649 1650static void alx_get_stats64(struct net_device *dev, 1651 struct rtnl_link_stats64 *net_stats) 1652{ 1653 struct alx_priv *alx = netdev_priv(dev); 1654 struct alx_hw_stats *hw_stats = &alx->hw.stats; 1655 1656 spin_lock(&alx->stats_lock); 1657 1658 alx_update_hw_stats(&alx->hw); 1659 1660 net_stats->tx_bytes = hw_stats->tx_byte_cnt; 1661 net_stats->rx_bytes = hw_stats->rx_byte_cnt; 1662 net_stats->multicast = hw_stats->rx_mcast; 1663 net_stats->collisions = hw_stats->tx_single_col + 1664 hw_stats->tx_multi_col + 1665 hw_stats->tx_late_col + 1666 hw_stats->tx_abort_col; 1667 1668 net_stats->rx_errors = hw_stats->rx_frag + 1669 hw_stats->rx_fcs_err + 1670 hw_stats->rx_len_err + 1671 hw_stats->rx_ov_sz + 1672 hw_stats->rx_ov_rrd + 1673 hw_stats->rx_align_err + 1674 hw_stats->rx_ov_rxf; 1675 1676 net_stats->rx_fifo_errors = hw_stats->rx_ov_rxf; 1677 net_stats->rx_length_errors = hw_stats->rx_len_err; 1678 net_stats->rx_crc_errors = hw_stats->rx_fcs_err; 1679 net_stats->rx_frame_errors = hw_stats->rx_align_err; 1680 net_stats->rx_dropped = hw_stats->rx_ov_rrd; 1681 1682 net_stats->tx_errors = hw_stats->tx_late_col + 1683 hw_stats->tx_abort_col + 1684 hw_stats->tx_underrun + 1685 hw_stats->tx_trunc; 1686 1687 net_stats->tx_aborted_errors = hw_stats->tx_abort_col; 1688 net_stats->tx_fifo_errors = hw_stats->tx_underrun; 1689 net_stats->tx_window_errors = hw_stats->tx_late_col; 1690 1691 net_stats->tx_packets = hw_stats->tx_ok + net_stats->tx_errors; 1692 net_stats->rx_packets = hw_stats->rx_ok + net_stats->rx_errors; 1693 1694 spin_unlock(&alx->stats_lock); 1695} 1696 1697static const struct net_device_ops alx_netdev_ops = { 1698 .ndo_open = alx_open, 1699 .ndo_stop = alx_stop, 1700 .ndo_start_xmit = alx_start_xmit, 1701 .ndo_get_stats64 = alx_get_stats64, 1702 .ndo_set_rx_mode = alx_set_rx_mode, 1703 .ndo_validate_addr = eth_validate_addr, 1704 .ndo_set_mac_address = alx_set_mac_address, 1705 .ndo_change_mtu = alx_change_mtu, 1706 .ndo_eth_ioctl = alx_ioctl, 1707 .ndo_tx_timeout = alx_tx_timeout, 1708 .ndo_fix_features = alx_fix_features, 1709#ifdef CONFIG_NET_POLL_CONTROLLER 1710 .ndo_poll_controller = alx_poll_controller, 1711#endif 1712}; 1713 1714static int alx_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 1715{ 1716 struct net_device *netdev; 1717 struct alx_priv *alx; 1718 struct alx_hw *hw; 1719 bool phy_configured; 1720 int err; 1721 1722 err = pci_enable_device_mem(pdev); 1723 if (err) 1724 return err; 1725 1726 /* The alx chip can DMA to 64-bit addresses, but it uses a single 1727 * shared register for the high 32 bits, so only a single, aligned, 1728 * 4 GB physical address range can be used for descriptors. 1729 */ 1730 if (!dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) { 1731 dev_dbg(&pdev->dev, "DMA to 64-BIT addresses\n"); 1732 } else { 1733 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 1734 if (err) { 1735 dev_err(&pdev->dev, "No usable DMA config, aborting\n"); 1736 goto out_pci_disable; 1737 } 1738 } 1739 1740 err = pci_request_mem_regions(pdev, alx_drv_name); 1741 if (err) { 1742 dev_err(&pdev->dev, 1743 "pci_request_mem_regions failed\n"); 1744 goto out_pci_disable; 1745 } 1746 1747 pci_set_master(pdev); 1748 1749 if (!pdev->pm_cap) { 1750 dev_err(&pdev->dev, 1751 "Can't find power management capability, aborting\n"); 1752 err = -EIO; 1753 goto out_pci_release; 1754 } 1755 1756 netdev = alloc_etherdev_mqs(sizeof(*alx), 1757 ALX_MAX_TX_QUEUES, 1); 1758 if (!netdev) { 1759 err = -ENOMEM; 1760 goto out_pci_release; 1761 } 1762 1763 SET_NETDEV_DEV(netdev, &pdev->dev); 1764 alx = netdev_priv(netdev); 1765 spin_lock_init(&alx->hw.mdio_lock); 1766 spin_lock_init(&alx->irq_lock); 1767 spin_lock_init(&alx->stats_lock); 1768 alx->dev = netdev; 1769 alx->hw.pdev = pdev; 1770 alx->msg_enable = NETIF_MSG_LINK | NETIF_MSG_HW | NETIF_MSG_IFUP | 1771 NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR | NETIF_MSG_WOL; 1772 hw = &alx->hw; 1773 pci_set_drvdata(pdev, alx); 1774 1775 hw->hw_addr = pci_ioremap_bar(pdev, 0); 1776 if (!hw->hw_addr) { 1777 dev_err(&pdev->dev, "cannot map device registers\n"); 1778 err = -EIO; 1779 goto out_free_netdev; 1780 } 1781 1782 netdev->netdev_ops = &alx_netdev_ops; 1783 netdev->ethtool_ops = &alx_ethtool_ops; 1784 netdev->irq = pci_irq_vector(pdev, 0); 1785 netdev->watchdog_timeo = ALX_WATCHDOG_TIME; 1786 1787 if (ent->driver_data & ALX_DEV_QUIRK_MSI_INTX_DISABLE_BUG) 1788 pdev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; 1789 1790 err = alx_init_sw(alx); 1791 if (err) { 1792 dev_err(&pdev->dev, "net device private data init failed\n"); 1793 goto out_unmap; 1794 } 1795 1796 mutex_lock(&alx->mtx); 1797 1798 alx_reset_pcie(hw); 1799 1800 phy_configured = alx_phy_configured(hw); 1801 1802 if (!phy_configured) 1803 alx_reset_phy(hw); 1804 1805 err = alx_reset_mac(hw); 1806 if (err) { 1807 dev_err(&pdev->dev, "MAC Reset failed, error = %d\n", err); 1808 goto out_unlock; 1809 } 1810 1811 /* setup link to put it in a known good starting state */ 1812 if (!phy_configured) { 1813 err = alx_setup_speed_duplex(hw, hw->adv_cfg, hw->flowctrl); 1814 if (err) { 1815 dev_err(&pdev->dev, 1816 "failed to configure PHY speed/duplex (err=%d)\n", 1817 err); 1818 goto out_unlock; 1819 } 1820 } 1821 1822 netdev->hw_features = NETIF_F_SG | 1823 NETIF_F_HW_CSUM | 1824 NETIF_F_RXCSUM | 1825 NETIF_F_TSO | 1826 NETIF_F_TSO6; 1827 1828 if (alx_get_perm_macaddr(hw, hw->perm_addr)) { 1829 dev_warn(&pdev->dev, 1830 "Invalid permanent address programmed, using random one\n"); 1831 eth_hw_addr_random(netdev); 1832 memcpy(hw->perm_addr, netdev->dev_addr, netdev->addr_len); 1833 } 1834 1835 memcpy(hw->mac_addr, hw->perm_addr, ETH_ALEN); 1836 eth_hw_addr_set(netdev, hw->mac_addr); 1837 memcpy(netdev->perm_addr, hw->perm_addr, ETH_ALEN); 1838 1839 hw->mdio.prtad = 0; 1840 hw->mdio.mmds = 0; 1841 hw->mdio.dev = netdev; 1842 hw->mdio.mode_support = MDIO_SUPPORTS_C45 | 1843 MDIO_SUPPORTS_C22 | 1844 MDIO_EMULATE_C22; 1845 hw->mdio.mdio_read = alx_mdio_read; 1846 hw->mdio.mdio_write = alx_mdio_write; 1847 1848 if (!alx_get_phy_info(hw)) { 1849 dev_err(&pdev->dev, "failed to identify PHY\n"); 1850 err = -EIO; 1851 goto out_unlock; 1852 } 1853 1854 mutex_unlock(&alx->mtx); 1855 1856 INIT_WORK(&alx->link_check_wk, alx_link_check); 1857 INIT_WORK(&alx->reset_wk, alx_reset); 1858 netif_carrier_off(netdev); 1859 1860 err = register_netdev(netdev); 1861 if (err) { 1862 dev_err(&pdev->dev, "register netdevice failed\n"); 1863 goto out_unmap; 1864 } 1865 1866 netdev_info(netdev, 1867 "Qualcomm Atheros AR816x/AR817x Ethernet [%pM]\n", 1868 netdev->dev_addr); 1869 1870 return 0; 1871 1872out_unlock: 1873 mutex_unlock(&alx->mtx); 1874out_unmap: 1875 iounmap(hw->hw_addr); 1876out_free_netdev: 1877 free_netdev(netdev); 1878out_pci_release: 1879 pci_release_mem_regions(pdev); 1880out_pci_disable: 1881 pci_disable_device(pdev); 1882 return err; 1883} 1884 1885static void alx_remove(struct pci_dev *pdev) 1886{ 1887 struct alx_priv *alx = pci_get_drvdata(pdev); 1888 struct alx_hw *hw = &alx->hw; 1889 1890 /* restore permanent mac address */ 1891 alx_set_macaddr(hw, hw->perm_addr); 1892 1893 unregister_netdev(alx->dev); 1894 iounmap(hw->hw_addr); 1895 pci_release_mem_regions(pdev); 1896 1897 pci_disable_device(pdev); 1898 1899 mutex_destroy(&alx->mtx); 1900 1901 free_netdev(alx->dev); 1902} 1903 1904static int alx_suspend(struct device *dev) 1905{ 1906 struct alx_priv *alx = dev_get_drvdata(dev); 1907 1908 if (!netif_running(alx->dev)) 1909 return 0; 1910 1911 rtnl_lock(); 1912 netif_device_detach(alx->dev); 1913 1914 mutex_lock(&alx->mtx); 1915 __alx_stop(alx); 1916 mutex_unlock(&alx->mtx); 1917 rtnl_unlock(); 1918 1919 return 0; 1920} 1921 1922static int alx_resume(struct device *dev) 1923{ 1924 struct alx_priv *alx = dev_get_drvdata(dev); 1925 struct alx_hw *hw = &alx->hw; 1926 int err; 1927 1928 rtnl_lock(); 1929 mutex_lock(&alx->mtx); 1930 alx_reset_phy(hw); 1931 1932 if (!netif_running(alx->dev)) { 1933 err = 0; 1934 goto unlock; 1935 } 1936 1937 err = __alx_open(alx, true); 1938 if (err) 1939 goto unlock; 1940 1941 netif_device_attach(alx->dev); 1942 1943unlock: 1944 mutex_unlock(&alx->mtx); 1945 rtnl_unlock(); 1946 return err; 1947} 1948 1949static DEFINE_SIMPLE_DEV_PM_OPS(alx_pm_ops, alx_suspend, alx_resume); 1950 1951static pci_ers_result_t alx_pci_error_detected(struct pci_dev *pdev, 1952 pci_channel_state_t state) 1953{ 1954 struct alx_priv *alx = pci_get_drvdata(pdev); 1955 struct net_device *netdev = alx->dev; 1956 pci_ers_result_t rc = PCI_ERS_RESULT_NEED_RESET; 1957 1958 dev_info(&pdev->dev, "pci error detected\n"); 1959 1960 mutex_lock(&alx->mtx); 1961 1962 if (netif_running(netdev)) { 1963 netif_device_detach(netdev); 1964 alx_halt(alx); 1965 } 1966 1967 if (state == pci_channel_io_perm_failure) 1968 rc = PCI_ERS_RESULT_DISCONNECT; 1969 else 1970 pci_disable_device(pdev); 1971 1972 mutex_unlock(&alx->mtx); 1973 1974 return rc; 1975} 1976 1977static pci_ers_result_t alx_pci_error_slot_reset(struct pci_dev *pdev) 1978{ 1979 struct alx_priv *alx = pci_get_drvdata(pdev); 1980 struct alx_hw *hw = &alx->hw; 1981 pci_ers_result_t rc = PCI_ERS_RESULT_DISCONNECT; 1982 1983 dev_info(&pdev->dev, "pci error slot reset\n"); 1984 1985 mutex_lock(&alx->mtx); 1986 1987 if (pci_enable_device(pdev)) { 1988 dev_err(&pdev->dev, "Failed to re-enable PCI device after reset\n"); 1989 goto out; 1990 } 1991 1992 pci_set_master(pdev); 1993 1994 alx_reset_pcie(hw); 1995 if (!alx_reset_mac(hw)) 1996 rc = PCI_ERS_RESULT_RECOVERED; 1997out: 1998 mutex_unlock(&alx->mtx); 1999 2000 return rc; 2001} 2002 2003static void alx_pci_error_resume(struct pci_dev *pdev) 2004{ 2005 struct alx_priv *alx = pci_get_drvdata(pdev); 2006 struct net_device *netdev = alx->dev; 2007 2008 dev_info(&pdev->dev, "pci error resume\n"); 2009 2010 mutex_lock(&alx->mtx); 2011 2012 if (netif_running(netdev)) { 2013 alx_activate(alx); 2014 netif_device_attach(netdev); 2015 } 2016 2017 mutex_unlock(&alx->mtx); 2018} 2019 2020static const struct pci_error_handlers alx_err_handlers = { 2021 .error_detected = alx_pci_error_detected, 2022 .slot_reset = alx_pci_error_slot_reset, 2023 .resume = alx_pci_error_resume, 2024}; 2025 2026static const struct pci_device_id alx_pci_tbl[] = { 2027 { PCI_VDEVICE(ATTANSIC, ALX_DEV_ID_AR8161), 2028 .driver_data = ALX_DEV_QUIRK_MSI_INTX_DISABLE_BUG }, 2029 { PCI_VDEVICE(ATTANSIC, ALX_DEV_ID_E2200), 2030 .driver_data = ALX_DEV_QUIRK_MSI_INTX_DISABLE_BUG }, 2031 { PCI_VDEVICE(ATTANSIC, ALX_DEV_ID_E2400), 2032 .driver_data = ALX_DEV_QUIRK_MSI_INTX_DISABLE_BUG }, 2033 { PCI_VDEVICE(ATTANSIC, ALX_DEV_ID_E2500), 2034 .driver_data = ALX_DEV_QUIRK_MSI_INTX_DISABLE_BUG }, 2035 { PCI_VDEVICE(ATTANSIC, ALX_DEV_ID_AR8162), 2036 .driver_data = ALX_DEV_QUIRK_MSI_INTX_DISABLE_BUG }, 2037 { PCI_VDEVICE(ATTANSIC, ALX_DEV_ID_AR8171) }, 2038 { PCI_VDEVICE(ATTANSIC, ALX_DEV_ID_AR8172) }, 2039 {} 2040}; 2041 2042static struct pci_driver alx_driver = { 2043 .name = alx_drv_name, 2044 .id_table = alx_pci_tbl, 2045 .probe = alx_probe, 2046 .remove = alx_remove, 2047 .err_handler = &alx_err_handlers, 2048 .driver.pm = pm_sleep_ptr(&alx_pm_ops), 2049}; 2050 2051module_pci_driver(alx_driver); 2052MODULE_DEVICE_TABLE(pci, alx_pci_tbl); 2053MODULE_AUTHOR("Johannes Berg <johannes@sipsolutions.net>"); 2054MODULE_AUTHOR("Qualcomm Corporation"); 2055MODULE_DESCRIPTION( 2056 "Qualcomm Atheros(R) AR816x/AR817x PCI-E Ethernet Network Driver"); 2057MODULE_LICENSE("GPL"); 2058