/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn303/ |
H A D | dcn303_fpu.c | 125 .num_states = 1, 194 unsigned int num_states = 0; local 287 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) { 289 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; 290 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++]; 293 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; 294 dram_speed_mts[num_states++] = 302 while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES) { 303 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; 304 dram_speed_mts[num_states [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn302/ |
H A D | dcn302_fpu.c | 126 .num_states = 1, 198 unsigned int num_states = 0; local 282 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) { 284 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; 285 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++]; 288 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; 289 dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16; 296 while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES) { 297 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; 298 dram_speed_mts[num_states [all...] |
/linux-master/arch/powerpc/kernel/ |
H A D | rtas-proc.c | 508 int num_states = 0; local 517 num_states = sizeof(key_switch) / sizeof(char *); 518 if (state < num_states) { 525 num_states = sizeof(enclosure_switch) / sizeof(char *); 526 if (state < num_states) { 538 num_states = sizeof(lid_status) / sizeof(char *); 539 if (state < num_states) { 546 num_states = sizeof(power_source) / sizeof(char *); 547 if (state < num_states) { 558 num_states [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/dml2/ |
H A D | dml2_policy.c | 85 if (table->num_states == 0) { 91 if (index >= (int) table->num_states) 95 for (i = table->num_states; i > index; i--) { 105 table->num_states++; 113 if (table->num_states == 0) 116 for (i = index; i < (int) table->num_states - 1; i++) { 119 memset(&table->state_array[--table->num_states], 0, sizeof(struct soc_state_bounding_box_st)); 163 p->out_states->num_states = 0; 221 for (i = p->out_states->num_states - 1; i >= 0; i--) { 233 for (i = p->out_states->num_states [all...] |
H A D | dml2_translation_helper.h | 36 void dml2_translate_soc_states(const struct dc *in_dc, struct soc_states_st *out, int num_states);
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H A D | dml2_wrapper.h | 149 unsigned int num_states; member in struct:dml2_clks_limit_table
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H A D | dml2_wrapper.c | 58 dml2_translate_soc_states(in_dc, out, in_dc->dml.soc.num_states); 261 for (i = 0; i < dml2->v20.dml_core_ctx.states.num_states; i++) { 266 for (j = 0; j < dml2->v20.dml_core_ctx.states.num_states; j++) { 290 for (i = 0; i < dml2->v20.dml_core_ctx.states.num_states; i++) { 619 (lowest_state_idx < dml2->v20.dml_core_ctx.states.num_states - 1)) { 620 lowest_state_idx = dml2->v20.dml_core_ctx.states.num_states - 1;
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H A D | dml2_translation_helper.c | 268 p->in_states->num_states = 2; 304 p->in_states->num_states = 2; 341 for (i = 0; i < p->in_states->num_states; i++) { 395 if (dml2->config.bbox_overrides.clks_table.num_states) { 396 p->in_states->num_states = dml2->config.bbox_overrides.clks_table.num_states; 439 memcpy(&p->out_states->state_array[p->out_states->num_states - 1], 440 &p->in_states->state_array[p->in_states->num_states - 1], 548 void dml2_translate_soc_states(const struct dc *dc, struct soc_states_st *out, int num_states) argument 551 out->num_states [all...] |
/linux-master/net/netfilter/ipvs/ |
H A D | ip_vs_proto_ah_esp.c | 119 .num_states = 1, 141 .num_states = 1,
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/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn301/ |
H A D | dcn301_fpu.c | 212 .num_states = 5, 301 ASSERT(vlevel < dml->soc.num_states); 343 for (closest_clk_lvl = 0, j = dcn3_01_soc.num_states - 1; j >= 0; j--) { 368 dcn3_01_soc.num_states = clk_table->num_entries; 370 s[dcn3_01_soc.num_states] = 371 dcn3_01_soc.clock_limits[dcn3_01_soc.num_states - 1]; 372 s[dcn3_01_soc.num_states].state = dcn3_01_soc.num_states;
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/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn321/ |
H A D | dcn321_fpu.c | 122 .num_states = 1, 710 unsigned int i = 0, j = 0, num_states = 0; local 781 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) { 783 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; 784 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++]; 787 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; 788 dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16; 795 while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES) { 796 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; 797 dram_speed_mts[num_states [all...] |
/linux-master/drivers/gpu/drm/amd/amdgpu/ |
H A D | amdgpu_socbb.h | 78 uint32_t num_states; member in struct:gpu_info_soc_bounding_box_v1_0
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/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
H A D | dcn20_fpu.h | 61 unsigned int num_states);
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H A D | dcn20_fpu.c | 292 .num_states = 5, 403 .num_states = 5, 514 .num_states = 5, 765 .num_states = 8 1846 unsigned int num_states) 1854 if (num_states == 0) 1870 for (i = 0; i < num_states; i++) { 1901 bb->num_states = num_calculated_states; 1905 bb->clock_limits[num_calculated_states].state = bb->num_states; 1916 for (i = 0; i < bb->num_states; 1842 dcn20_update_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb, struct pp_smu_nv_clock_table *max_clocks, unsigned int *uclk_states, unsigned int num_states) argument [all...] |
H A D | display_mode_vba_20v2.c | 1320 mode_lib->vba.soc.clock_limits[mode_lib->vba.soc.num_states].dispclk_mhz, 2671 for (k = 0; k <= mode_lib->vba.soc.num_states; k++) 3548 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { 3630 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { 3981 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { 3983 mode_lib->vba.MaxDispclk[mode_lib->vba.soc.num_states], 4000 && i == mode_lib->vba.soc.num_states) 4007 && i == mode_lib->vba.soc.num_states) 4084 if (i != mode_lib->vba.soc.num_states) { 4116 for (i = 0; i <= mode_lib->vba.soc.num_states; [all...] |
/linux-master/drivers/regulator/ |
H A D | irq_helpers.c | 62 num_rdevs = rid->num_states; 167 num_rdevs = rid->num_states; 291 h->rdata.num_states = rdev_amount; 308 for (i = 0; i < h->rdata.num_states; i++) 427 if (WARN_ON(rid->num_states != 1 || hweight32(err) != 1))
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/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn314/ |
H A D | dcn314_fpu.c | 150 .num_states = 5, 217 for (closest_clk_lvl = 0, j = dcn3_14_soc.num_states - 1; j >= 0; j--) { 225 closest_clk_lvl = dcn3_14_soc.num_states - 1; 259 dcn3_14_soc.num_states = clk_table->num_entries;
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/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
H A D | dcn31_fpu.c | 169 .num_states = 5, 412 .num_states = 5, 609 for (closest_clk_lvl = 0, j = dcn3_1_soc.num_states - 1; j >= 0; j--) { 641 dcn3_1_soc.num_states = clk_table->num_entries; 702 dcn3_15_soc.num_states = clk_table->num_entries; 748 for (closest_clk_lvl = 0, j = dcn3_16_soc.num_states - 1; j >= 0; j--) { 758 closest_clk_lvl = dcn3_16_soc.num_states - 1; 793 dcn3_16_soc.num_states = clk_table->num_entries;
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/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn30/ |
H A D | dcn30_resource.c | 1672 if (vlevel < context->bw_ctx.dml.soc.num_states) 1676 (fast_validate || vlevel == context->bw_ctx.dml.soc.num_states || 1690 if (vlevel < context->bw_ctx.dml.soc.num_states) { 1700 if (vlevel == context->bw_ctx.dml.soc.num_states) 1867 vba->ValidationStatus[vba->soc.num_states] = DML_FAIL_DSC_VALIDATION_FAILURE; 2081 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states])); 2097 unsigned int num_states = 0; local 2190 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) { 2192 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; 2193 dram_speed_mts[num_states [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn35/ |
H A D | dcn35_fpu.c | 166 .num_states = 5, 256 for (closest_clk_lvl = 0, j = dcn3_5_soc.num_states - 1; 266 closest_clk_lvl = dcn3_5_soc.num_states - 1; 317 dcn3_5_soc.num_states = clk_table->num_entries; 356 dc->dml2_options.bbox_overrides.clks_table.num_states =
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/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn351/ |
H A D | dcn351_fpu.c | 204 .num_states = 8, 291 for (closest_clk_lvl = 0, j = dcn3_51_soc.num_states - 1; 301 closest_clk_lvl = dcn3_51_soc.num_states - 1; 352 dcn3_51_soc.num_states = clk_table->num_entries; 391 dc->dml2_options.bbox_overrides.clks_table.num_states =
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/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
H A D | dcn32_fpu.c | 143 .num_states = 1, 297 if (vlevel < context->bw_ctx.dml.vba.soc.num_states && 1404 if (new_vlevel < context->bw_ctx.dml.soc.num_states) { 1459 if (*vlevel < context->bw_ctx.dml.soc.num_states) { 1473 (*vlevel == context->bw_ctx.dml.soc.num_states || (vba->DRAMSpeedPerState[*vlevel] != vba->DRAMSpeedPerState[0] && 1494 /* For the case where *vlevel = num_states, bandwidth validation has failed for this config. 1501 if (*vlevel == context->bw_ctx.dml.soc.num_states && 1525 for (i = *vlevel; i < context->bw_ctx.dml.soc.num_states; i++) { 1532 if (*vlevel < context->bw_ctx.dml.soc.num_states 1563 if (*vlevel < context->bw_ctx.dml.soc.num_states) { 3107 unsigned int i = 0, j = 0, num_states = 0; local [all...] |
H A D | display_mode_vba_32.c | 112 mode_lib->vba.MaxDppclk[v->soc.num_states - 1])); 1654 start_state = v->soc.num_states - 1; 1658 for (i = v->soc.num_states - 1; i >= start_state; i--) { 1705 || i == v->soc.num_states - 1) 1710 || i == v->soc.num_states - 1 1712 && (!mode_lib->vba.FCLKChangeRequirementFinal || i == v->soc.num_states - 1 1741 start_state = v->soc.num_states - 1; 2033 for (i = start_state; i < v->soc.num_states; i++) { 2048 mode_lib->vba.MaxDispclk[v->soc.num_states - 1], 2071 mode_lib->vba.MaxDispclk[v->soc.num_states [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/ |
H A D | dm_pp_smu.h | 229 unsigned int *clock_values_in_khz, unsigned int *num_states);
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/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn20/ |
H A D | dcn20_resource.c | 1899 for (vlevel_split = vlevel; vlevel <= context->bw_ctx.dml.soc.num_states; vlevel++) 1904 if (vlevel > context->bw_ctx.dml.soc.num_states) 2053 if (vlevel > context->bw_ctx.dml.soc.num_states) 2126 context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states] = 2365 unsigned int num_states = 0; local 2372 (&pool->base.pp_smu->nv_funcs.pp_smu, uclk_states, &num_states); 2387 if (clock_limits_available && uclk_states_available && num_states) { 2389 dcn20_update_bounding_box(dc, loaded_bb, &max_clocks, uclk_states, num_states); 2587 if (loaded_bb->num_states == 1) { 2595 } else if (loaded_bb->num_states > [all...] |