Lines Matching refs:num_states
1672 if (vlevel < context->bw_ctx.dml.soc.num_states)
1676 (fast_validate || vlevel == context->bw_ctx.dml.soc.num_states ||
1690 if (vlevel < context->bw_ctx.dml.soc.num_states) {
1700 if (vlevel == context->bw_ctx.dml.soc.num_states)
1867 vba->ValidationStatus[vba->soc.num_states] = DML_FAIL_DSC_VALIDATION_FAILURE;
2081 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states]));
2097 unsigned int num_states = 0;
2190 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) {
2192 dcfclk_mhz[num_states] = dcfclk_sta_targets[i];
2193 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++];
2196 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j];
2197 dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;
2204 while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES) {
2205 dcfclk_mhz[num_states] = dcfclk_sta_targets[i];
2206 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++];
2209 while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES &&
2211 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j];
2212 dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;
2215 dcn3_0_soc.num_states = num_states;