Searched refs:mpll_param (Results 1 - 13 of 13) sorted by relevance

/linux-master/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dppatomctrl.c282 * @mpll_param: output parameter: memory clock parameters
288 pp_atomctrl_memory_clock_param *mpll_param,
303 mpll_param->mpll_fb_divider.clk_frac =
305 mpll_param->mpll_fb_divider.cl_kf =
307 mpll_param->mpll_post_divider =
309 mpll_param->vco_mode =
312 mpll_param->yclk_sel =
315 mpll_param->qdr =
318 mpll_param->half_rate =
321 mpll_param
285 atomctrl_get_memory_pll_dividers_si( struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_memory_clock_param *mpll_param, bool strobe_mode) argument
337 atomctrl_get_memory_pll_dividers_vi(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_memory_clock_param *mpll_param) argument
357 atomctrl_get_memory_pll_dividers_ai(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_memory_clock_param_ai *mpll_param) argument
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H A Dppatomctrl.h305 extern int atomctrl_get_memory_pll_dividers_si(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_memory_clock_param *mpll_param, bool strobe_mode);
311 uint32_t clock_value, pp_atomctrl_memory_clock_param *mpll_param);
313 uint32_t clock_value, pp_atomctrl_memory_clock_param_ai *mpll_param);
/linux-master/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_atombios.h164 struct atom_mpll_param *mpll_param);
H A Damdgpu_atombios.c1094 struct atom_mpll_param *mpll_param)
1101 memset(mpll_param, 0, sizeof(struct atom_mpll_param));
1119 mpll_param->clkfrac = le16_to_cpu(args.ulFbDiv.usFbDivFrac);
1120 mpll_param->clkf = le16_to_cpu(args.ulFbDiv.usFbDiv);
1121 mpll_param->post_div = args.ucPostDiv;
1122 mpll_param->dll_speed = args.ucDllSpeed;
1123 mpll_param->bwcntl = args.ucBWCntl;
1124 mpll_param->vco_mode =
1126 mpll_param->yclk_sel =
1128 mpll_param
1091 amdgpu_atombios_get_memory_pll_dividers(struct amdgpu_device *adev, u32 clock, bool strobe_mode, struct atom_mpll_param *mpll_param) argument
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/linux-master/drivers/gpu/drm/amd/pm/powerplay/smumgr/
H A Diceland_smumgr.c1064 pp_atomctrl_memory_clock_param mpll_param; local
1068 memory_clock, &mpll_param, strobe_mode);
1073 mpll_func_cntl = PHM_SET_FIELD(mpll_func_cntl, MPLL_FUNC_CNTL, BWCTRL, mpll_param.bw_ctrl);
1077 MPLL_FUNC_CNTL_1, CLKF, mpll_param.mpll_fb_divider.cl_kf);
1079 MPLL_FUNC_CNTL_1, CLKFRAC, mpll_param.mpll_fb_divider.clk_frac);
1081 MPLL_FUNC_CNTL_1, VCO_MODE, mpll_param.vco_mode);
1085 MPLL_AD_FUNC_CNTL, YCLK_POST_DIV, mpll_param.mpll_post_divider);
1090 MPLL_DQ_FUNC_CNTL, YCLK_SEL, mpll_param.yclk_sel);
1092 MPLL_DQ_FUNC_CNTL, YCLK_POST_DIV, mpll_param.mpll_post_divider);
1118 if (1 == mpll_param
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H A Dtonga_smumgr.c807 pp_atomctrl_memory_clock_param mpll_param; local
811 memory_clock, &mpll_param, strobe_mode);
819 mpll_param.bw_ctrl);
824 mpll_param.mpll_fb_divider.cl_kf);
827 mpll_param.mpll_fb_divider.clk_frac);
830 mpll_param.vco_mode);
835 mpll_param.mpll_post_divider);
841 mpll_param.yclk_sel);
844 mpll_param.mpll_post_divider);
870 if (1 == mpll_param
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H A Dci_smumgr.c1042 pp_atomctrl_memory_clock_param mpll_param; local
1046 memory_clock, &mpll_param, strobe_mode);
1050 mpll_func_cntl = PHM_SET_FIELD(mpll_func_cntl, MPLL_FUNC_CNTL, BWCTRL, mpll_param.bw_ctrl);
1053 MPLL_FUNC_CNTL_1, CLKF, mpll_param.mpll_fb_divider.cl_kf);
1055 MPLL_FUNC_CNTL_1, CLKFRAC, mpll_param.mpll_fb_divider.clk_frac);
1057 MPLL_FUNC_CNTL_1, VCO_MODE, mpll_param.vco_mode);
1060 MPLL_AD_FUNC_CNTL, YCLK_POST_DIV, mpll_param.mpll_post_divider);
1064 MPLL_DQ_FUNC_CNTL, YCLK_SEL, mpll_param.yclk_sel);
1066 MPLL_DQ_FUNC_CNTL, YCLK_POST_DIV, mpll_param.mpll_post_divider);
1077 if (1 == mpll_param
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H A Dvegam_smumgr.c966 struct pp_atomctrl_memory_clock_param_ai mpll_param; local
969 clock, &mpll_param),
973 mem_level->MclkFrequency = (uint32_t)mpll_param.ulClock;
974 mem_level->Fcw_int = (uint16_t)mpll_param.ulMclk_fcw_int;
975 mem_level->Fcw_frac = (uint16_t)mpll_param.ulMclk_fcw_frac;
976 mem_level->Postdiv = (uint8_t)mpll_param.ulPostDiv;
/linux-master/drivers/gpu/drm/radeon/
H A Dradeon_atombios.c2957 struct atom_mpll_param *mpll_param)
2964 memset(mpll_param, 0, sizeof(struct atom_mpll_param));
2981 mpll_param->clkfrac = le16_to_cpu(args.ulFbDiv.usFbDivFrac);
2982 mpll_param->clkf = le16_to_cpu(args.ulFbDiv.usFbDiv);
2983 mpll_param->post_div = args.ucPostDiv;
2984 mpll_param->dll_speed = args.ucDllSpeed;
2985 mpll_param->bwcntl = args.ucBWCntl;
2986 mpll_param->vco_mode =
2988 mpll_param->yclk_sel =
2990 mpll_param
2954 radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev, u32 clock, bool strobe_mode, struct atom_mpll_param *mpll_param) argument
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H A Dci_dpm.c2760 struct atom_mpll_param mpll_param; local
2763 ret = radeon_atom_get_memory_pll_dividers(rdev, memory_clock, strobe_mode, &mpll_param);
2768 mpll_func_cntl |= BWCTRL(mpll_param.bwcntl);
2771 mpll_func_cntl_1 |= CLKF(mpll_param.clkf) |
2772 CLKFRAC(mpll_param.clkfrac) | VCO_MODE(mpll_param.vco_mode);
2775 mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div);
2779 mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) |
2780 YCLK_POST_DIV(mpll_param.post_div);
2789 if (mpll_param
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H A Dsi_dpm.c4828 struct atom_mpll_param mpll_param; local
4831 ret = radeon_atom_get_memory_pll_dividers(rdev, memory_clock, strobe_mode, &mpll_param);
4836 mpll_func_cntl |= BWCTRL(mpll_param.bwcntl);
4839 mpll_func_cntl_1 |= CLKF(mpll_param.clkf) |
4840 CLKFRAC(mpll_param.clkfrac) | VCO_MODE(mpll_param.vco_mode);
4843 mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div);
4847 mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) |
4848 YCLK_POST_DIV(mpll_param.post_div);
4878 mclk_pwrmgt_cntl |= DLL_SPEED(mpll_param
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H A Dradeon.h302 struct atom_mpll_param *mpll_param);
/linux-master/drivers/gpu/drm/amd/pm/legacy-dpm/
H A Dsi_dpm.c5374 struct atom_mpll_param mpll_param; local
5377 ret = amdgpu_atombios_get_memory_pll_dividers(adev, memory_clock, strobe_mode, &mpll_param);
5382 mpll_func_cntl |= BWCTRL(mpll_param.bwcntl);
5385 mpll_func_cntl_1 |= CLKF(mpll_param.clkf) |
5386 CLKFRAC(mpll_param.clkfrac) | VCO_MODE(mpll_param.vco_mode);
5389 mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div);
5393 mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) |
5394 YCLK_POST_DIV(mpll_param.post_div);
5424 mclk_pwrmgt_cntl |= DLL_SPEED(mpll_param
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