Searched refs:min_dst_y_next_start (Results 1 - 24 of 24) sorted by path

/linux-master/drivers/gpu/drm/amd/display/dc/dcn10/
H A Ddcn10_hubp.c599 MIN_DST_Y_NEXT_START, dlg_attr->min_dst_y_next_start);
908 MIN_DST_Y_NEXT_START, &dlg_attr->min_dst_y_next_start);
H A Ddcn10_hw_sequencer_debug.c261 pool->hubps[i]->inst, dlg_regs->refcyc_h_blank_end, dlg_regs->dlg_vblank_end, dlg_regs->min_dst_y_next_start,
/linux-master/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_hubp.c94 MIN_DST_Y_NEXT_START, dlg_attr->min_dst_y_next_start);
1143 MIN_DST_Y_NEXT_START, &dlg_attr->min_dst_y_next_start);
1447 MIN_DST_Y_NEXT_START, &dlg_attr.min_dst_y_next_start);
1462 if (dlg_attr.min_dst_y_next_start != dml_dlg_attr->min_dst_y_next_start)
1464 dml_dlg_attr->min_dst_y_next_start, dlg_attr.min_dst_y_next_start);
/linux-master/drivers/gpu/drm/amd/display/dc/dcn21/
H A Ddcn21_hubp.c361 MIN_DST_Y_NEXT_START, &dlg_attr.min_dst_y_next_start);
376 if (dlg_attr.min_dst_y_next_start != dml_dlg_attr->min_dst_y_next_start)
378 dml_dlg_attr->min_dst_y_next_start, dlg_attr.min_dst_y_next_start);
/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn20/
H A Ddisplay_rq_dlg_calc_20.c945 disp_dlg_regs->min_dst_y_next_start = (unsigned int) ((double) dlg_vblank_start * dml_pow(2, 2));
946 ASSERT(disp_dlg_regs->min_dst_y_next_start < (unsigned int) dml_pow(2, 18));
960 dml_print("DML_DLG: %s: disp_dlg_regs->min_dst_y_next_start = 0x%0x\n",
962 disp_dlg_regs->min_dst_y_next_start);
H A Ddisplay_rq_dlg_calc_20v2.c945 disp_dlg_regs->min_dst_y_next_start = (unsigned int) (((double) dlg_vblank_start
947 ASSERT(disp_dlg_regs->min_dst_y_next_start < (unsigned int) dml_pow(2, 18));
961 dml_print("DML_DLG: %s: disp_dlg_regs->min_dst_y_next_start = 0x%0x\n",
963 disp_dlg_regs->min_dst_y_next_start);
/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn21/
H A Ddisplay_rq_dlg_calc_21.c991 disp_dlg_regs->min_dst_y_next_start = (unsigned int) (((double) dlg_vblank_start) * dml_pow(2, 2));
992 ASSERT(disp_dlg_regs->min_dst_y_next_start < (unsigned int)dml_pow(2, 18));
1011 "DML_DLG: %s: disp_dlg_regs->min_dst_y_next_start = 0x%0x\n",
1013 disp_dlg_regs->min_dst_y_next_start);
/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn30/
H A Ddisplay_rq_dlg_calc_30.c1056 disp_dlg_regs->min_dst_y_next_start = (unsigned int)(((double)dlg_vblank_start
1058 ASSERT(disp_dlg_regs->min_dst_y_next_start < (unsigned int)dml_pow(2, 18));
1072 dml_print("DML_DLG: %s: disp_dlg_regs->min_dst_y_next_start = 0x%0x\n",
1074 disp_dlg_regs->min_dst_y_next_start);
/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn31/
H A Ddisplay_rq_dlg_calc_31.c989 disp_dlg_regs->min_dst_y_next_start = (unsigned int) (((double) dlg_vblank_start) * dml_pow(2, 2));
991 ASSERT(disp_dlg_regs->min_dst_y_next_start < (unsigned int)dml_pow(2, 18));
994 dml_print("DML_DLG: %s: min_dst_y_next_start = 0x%0x\n", __func__, disp_dlg_regs->min_dst_y_next_start);
999 //old_impl_vs_vba_impl("min_dst_y_next_start", dlg_vblank_start, vba__min_dst_y_next_start);
/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn314/
H A Ddisplay_rq_dlg_calc_314.c1076 disp_dlg_regs->min_dst_y_next_start = vba__min_dst_y_next_start * dml_pow(2, 2);
1078 ASSERT(disp_dlg_regs->min_dst_y_next_start < (unsigned int)dml_pow(2, 18));
1081 dml_print("DML_DLG: %s: min_dst_y_next_start = 0x%0x\n", __func__, disp_dlg_regs->min_dst_y_next_start);
1086 //old_impl_vs_vba_impl("min_dst_y_next_start", dlg_vblank_start, vba__min_dst_y_next_start);
/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn32/
H A Ddisplay_rq_dlg_calc_32.c229 unsigned int min_dst_y_next_start; local
280 min_dst_y_next_start = get_min_dst_y_next_start(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);
283 dml_print("DML_DLG: %s: min_dst_y_next_start = %d\n", __func__, min_dst_y_next_start);
441 dlg_regs->min_dst_y_next_start = min_dst_y_next_start * dml_pow(2, 2);
442 ASSERT(dlg_regs->min_dst_y_next_start < (unsigned int)dml_pow(2, 18));
/linux-master/drivers/gpu/drm/amd/display/dc/dml/
H A Ddisplay_mode_structs.h622 unsigned int min_dst_y_next_start; member in struct:_vcs_dpi_display_dlg_regs_st
H A Ddisplay_mode_vba.c183 dml_get_pipe_attr_func(min_dst_y_next_start, mode_lib->vba.MIN_DST_Y_NEXT_START);
H A Ddisplay_mode_vba.h143 dml_get_pipe_attr_decl(min_dst_y_next_start); variable
H A Ddisplay_rq_dlg_helpers.c202 "DML_RQ_DLG_CALC: min_dst_y_next_start = 0x%0x\n",
203 dlg_regs->min_dst_y_next_start);
H A Ddml1_display_rq_dlg_calc.c1175 disp_dlg_regs->min_dst_y_next_start = (unsigned int) (((double) dlg_vblank_start
1177 ASSERT(disp_dlg_regs->min_dst_y_next_start < (unsigned int) dml_pow(2, 18));
1187 "DLG: %s: disp_dlg_regs->min_dst_y_next_start = 0x%0x",
1189 disp_dlg_regs->min_dst_y_next_start);
/linux-master/drivers/gpu/drm/amd/display/dc/dml2/
H A Ddisplay_mode_core.c10299 dml_get_per_surface_var_func(min_dst_y_next_start, dml_uint_t, mode_lib->mp.MIN_DST_Y_NEXT_START);
H A Ddisplay_mode_core.h183 dml_get_per_surface_var_decl(min_dst_y_next_start, dml_uint_t);
H A Ddisplay_mode_core_structs.h1873 dml_uint_t min_dst_y_next_start; member in struct:_vcs_dpi_dml_display_dlg_regs_st
H A Ddisplay_mode_util.c255 dml_print("DML: min_dst_y_next_start = 0x%x\n", dlg_regs->min_dst_y_next_start);
H A Ddml2_translation_helper.c1219 out->dlg_regs.min_dst_y_next_start = disp_dlg_regs->min_dst_y_next_start;
H A Ddml_display_rq_dlg_calc.c267 dml_uint_t min_dst_y_next_start; local
323 min_dst_y_next_start = (dml_uint_t)(dml_get_min_dst_y_next_start(mode_lib, pipe_idx));
326 dml_print("DML_DLG: %s: min_dst_y_next_start = %d\n", __func__, min_dst_y_next_start);
411 disp_dlg_regs->min_dst_y_next_start = (dml_uint_t)((dml_float_t) min_dst_y_next_start * dml_pow(2, 2));
412 ASSERT(disp_dlg_regs->min_dst_y_next_start < (dml_uint_t)dml_pow(2, 18));
/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn10/
H A Ddcn10_hwseq.c245 pool->hubps[i]->inst, dlg_regs->refcyc_h_blank_end, dlg_regs->dlg_vblank_end, dlg_regs->min_dst_y_next_start,
/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn20/
H A Ddcn20_hwseq.c2350 pipe_ctx->dlg_regs.min_dst_y_next_start);

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