Searched refs:mcr (Results 1 - 25 of 166) sorted by relevance

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/linux-master/arch/arm/mm/
H A Dproc-fa526.S39 mcr p15, 0, r0, c1, c0, 0 @ disable caches
58 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
59 mcr p15, 0, ip, c7, c10, 4 @ drain WB
61 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
67 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
83 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
87 mcr p15, 0, r0, c7, c10, 4 @ drain WB
104 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
106 mcr p15, 0, ip, c7, c14, 0 @ clean and invalidate whole D cache
108 mcr p1
[all...]
H A Dproc-mohawk.S44 mcr p15, 0, r0, c1, c0, 0 @ disable caches
62 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
63 mcr p15, 0, ip, c7, c10, 4 @ drain WB
64 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
68 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
81 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
82 mcr p15, 0, r0, c7, c0, 4 @ wait for interrupt
92 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
114 mcr p15, 0, ip, c7, c14, 0 @ clean & invalidate all D cache
138 mcr p1
[all...]
H A Dproc-arm946.S46 mcr p15, 0, r0, c1, c0, 0 @ disable caches
57 mcr p15, 0, ip, c7, c5, 0 @ flush I cache
58 mcr p15, 0, ip, c7, c6, 0 @ flush D cache
59 mcr p15, 0, ip, c7, c10, 4 @ drain WB
63 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
73 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
83 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
103 mcr p15, 0, ip, c7, c6, 0 @ flush D cache
107 2: mcr p15, 0, r3, c7, c14, 2 @ clean/flush D index
137 mcr p1
[all...]
H A Dproc-arm940.S39 mcr p15, 0, r0, c1, c0, 0 @ disable caches
50 mcr p15, 0, ip, c7, c5, 0 @ flush I cache
51 mcr p15, 0, ip, c7, c6, 0 @ flush D cache
52 mcr p15, 0, ip, c7, c10, 4 @ drain WB
56 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
66 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
76 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
108 mcr p15, 0, ip, c7, c6, 0 @ flush D cache
112 2: mcr p15, 0, r3, c7, c14, 2 @ clean/flush D index
162 2: mcr p1
[all...]
H A Dcache-v6.S42 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
43 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
44 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
45 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
51 mcr p15, 0, r0, c7, c5, 0 @ invalidate I-cache
66 mcr p15, 0, r0, c7, c14, 0 @ D cache clean+invalidate
68 mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate
73 mcr p15, 0, r0, c7, c15, 0 @ Cache clean+invalidate
136 USER( mcr p15, 0, r0, c7, c10, 1 ) @ clean D line
143 mcr p1
[all...]
H A Dtlb-v6.S39 mcr p15, 0, ip, c7, c10, 4 @ drain write buffer
48 mcr p15, 0, r0, c8, c6, 1 @ TLB invalidate D MVA (was 1)
52 mcr p15, 0, r0, c8, c7, 1 @ TLB invalidate MVA (was 1)
57 mcr p15, 0, ip, c7, c10, 4 @ data synchronization barrier
70 mcr p15, 0, r2, c7, c10, 4 @ drain write buffer
77 mcr p15, 0, r0, c8, c6, 1 @ TLB invalidate D MVA
78 mcr p15, 0, r0, c8, c5, 1 @ TLB invalidate I MVA
80 mcr p15, 0, r0, c8, c7, 1 @ TLB invalidate MVA
85 mcr p15, 0, r2, c7, c10, 4 @ data synchronization barrier
86 mcr p1
[all...]
H A Dtlb-fa.S40 mcr p15, 0, r3, c7, c10, 4 @ drain WB
43 1: mcr p15, 0, r0, c8, c7, 1 @ invalidate UTLB entry
47 mcr p15, 0, r3, c7, c10, 4 @ data write barrier
53 mcr p15, 0, r3, c7, c10, 4 @ drain WB
56 1: mcr p15, 0, r0, c8, c7, 1 @ invalidate UTLB entry
60 mcr p15, 0, r3, c7, c10, 4 @ data write barrier
61 mcr p15, 0, r3, c7, c5, 4 @ prefetch flush (isb)
H A Dproc-arm920.S61 mcr p15, 0, r0, c1, c0, 0 @ disable caches
77 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
78 mcr p15, 0, ip, c7, c10, 4 @ drain WB
80 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
85 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
95 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
108 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
132 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
158 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
193 1: mcr p1
[all...]
H A Dproc-sa1100.S41 mcr p15, 0, r0, c15, c1, 2 @ Enable clock switching
42 mcr p15, 0, r0, c9, c0, 5 @ Allow read-buffer operations from userland
53 mcr p15, 0, ip, c15, c2, 2 @ Disable clock switching
57 mcr p15, 0, r0, c1, c0, 0 @ disable caches
73 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
74 mcr p15, 0, ip, c7, c10, 4 @ drain WB
76 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
81 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
108 mcr p15, 0, r0, c15, c2, 2 @ disable clock switching
110 mcr p1
[all...]
H A Dproc-arm922.S63 mcr p15, 0, r0, c1, c0, 0 @ disable caches
79 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
80 mcr p15, 0, ip, c7, c10, 4 @ drain WB
82 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
87 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
97 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
110 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
134 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
160 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
195 1: mcr p1
[all...]
H A Dproc-sa110.S37 mcr p15, 0, r0, c15, c1, 2 @ Enable clock switching
45 mcr p15, 0, r0, c15, c2, 2 @ Disable clock switching
49 mcr p15, 0, r0, c1, c0, 0 @ disable caches
65 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
66 mcr p15, 0, ip, c7, c10, 4 @ drain WB
68 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
73 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
92 mcr p15, 0, ip, c15, c2, 2 @ disable clock switching
98 mcr p15, 0, r0, c15, c8, 2 @ Wait for interrupt, cache aligned
102 mcr p1
[all...]
H A Dproc-arm1020e.S69 mcr p15, 0, r0, c1, c0, 0 @ disable caches
85 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
86 mcr p15, 0, ip, c7, c10, 4 @ drain WB
88 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
93 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
103 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
118 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
141 mcr p15, 0, ip, c7, c10, 4 @ drain WB
144 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
174 1: mcr p1
[all...]
H A Dproc-arm926.S53 mcr p15, 0, r0, c1, c0, 0 @ disable caches
69 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
70 mcr p15, 0, ip, c7, c10, 4 @ drain WB
72 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
77 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
91 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer
96 mcr p15, 0, r2, c1, c0, 0 @ Disable I cache
97 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
98 mcr p15, 0, r1, c1, c0, 0 @ Restore ICache enable
109 mcr p1
[all...]
H A Dproc-xsc3.S68 1: mcr p15, 0, \rd, c7, c14, 2 @ clean/invalidate L1 D line
92 mcr p15, 0, r0, c1, c0, 0 @ disable caches
112 mcr p15, 0, r1, c1, c0, 0 @ ctrl register
113 mcr p15, 0, ip, c7, c7, 0 @ invalidate L1 caches and BTB
115 mcr p15, 0, r1, c1, c0, 0 @ ctrl register
118 mcr p15, 0, ip, c8, c7, 0 @ invalidate I and D TLBs
137 mcr p14, 0, r0, c7, c0, 0 @ go to idle
149 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
197 mcr p15, 0, r0, c7, c14, 1 @ clean/invalidate L1 D line
224 1: mcr p1
[all...]
H A Dproc-arm1020.S69 mcr p15, 0, r0, c1, c0, 0 @ disable caches
85 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
86 mcr p15, 0, ip, c7, c10, 4 @ drain WB
88 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
93 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
103 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
118 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
141 mcr p15, 0, ip, c7, c10, 4 @ drain WB
144 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
145 mcr p1
[all...]
H A Dproc-v6.S44 mcr p15, 0, r0, c1, c0, 0 @ disable caches
61 mcr p15, 0, r1, c1, c0, 0 @ disable MMU
63 mcr p15, 0, r1, c7, c5, 4 @ ISB
77 mcr p15, 0, r1, c7, c10, 4 @ DWB - WFI may enter a low-power mode
78 mcr p15, 0, r1, c7, c0, 4 @ wait for interrupt
82 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
104 mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB
105 mcr p15, 0, r2, c7, c10, 4 @ drain write buffer
106 mcr p15, 0, r0, c2, c0, 0 @ set TTB 0
113 mcr p1
[all...]
H A Dproc-arm925.S84 mcr p15, 0, r0, c1, c0, 0 @ disable caches
109 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
110 mcr p15, 0, ip, c7, c10, 4 @ drain WB
112 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
117 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
129 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer
131 mcr p15, 0, r2, c1, c0, 0 @ Disable I cache
132 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
133 mcr p15, 0, r1, c1, c0, 0 @ Restore ICache enable
143 mcr p1
[all...]
H A Dcache-fa.S44 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
65 mcr p15, 0, ip, c7, c14, 0 @ clean/invalidate D cache
91 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
126 1: mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
127 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
132 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB
133 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
134 mcr p15, 0, r0, c7, c5, 4 @ prefetch flush
148 1: mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D line
153 mcr p1
[all...]
H A Dproc-arm1026.S69 mcr p15, 0, r0, c1, c0, 0 @ disable caches
85 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
86 mcr p15, 0, ip, c7, c10, 4 @ drain WB
88 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
93 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
103 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
118 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
168 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
207 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
210 mcr p1
[all...]
H A Dproc-arm1022.S69 mcr p15, 0, r0, c1, c0, 0 @ disable caches
85 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
86 mcr p15, 0, ip, c7, c10, 4 @ drain WB
88 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
93 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
103 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
118 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
143 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
173 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
213 mcr p1
[all...]
/linux-master/drivers/w1/masters/
H A Dsgi_w1.c23 u32 __iomem *mcr; member in struct:sgi_w1_device
28 static u8 sgi_w1_wait(u32 __iomem *mcr) argument
33 mcr_val = readl(mcr);
49 writel(MCR_PACK(520, 65), dev->mcr);
50 ret = sgi_w1_wait(dev->mcr);
66 writel(MCR_PACK(6, 13), dev->mcr);
68 writel(MCR_PACK(80, 30), dev->mcr);
70 ret = sgi_w1_wait(dev->mcr);
86 sdev->mcr = devm_platform_ioremap_resource(pdev, 0);
87 if (IS_ERR(sdev->mcr))
[all...]
/linux-master/arch/sh/drivers/pci/
H A Dfixups-rts7751r2d.c41 unsigned long bcr1, mcr; local
54 mcr = __raw_readl(SH7751_MCR);
55 mcr = (mcr & PCIMCR_MRSET_OFF) & PCIMCR_RFSH_OFF;
56 pci_write_reg(chan, mcr, SH4_PCIMCR);
H A Dfixups-landisk.c41 unsigned long bcr1, mcr; local
47 mcr = __raw_readl(SH7751_MCR);
48 mcr = (mcr & PCIMCR_MRSET_OFF) & PCIMCR_RFSH_OFF;
49 pci_write_reg(chan, mcr, SH4_PCIMCR);
/linux-master/arch/arm/boot/compressed/
H A Dbig-endian.S13 mcr p15, 0, r0, c1, c0, 0 @ write control reg
/linux-master/drivers/gpu/drm/xe/regs/
H A Dxe_reg_defs.h30 * @mcr: register is multicast/replicated in the
37 u32 mcr:1; member in struct:xe_reg::__anon824::__anon825
117 .__reg = XE_REG_INITIALIZER(r_, ##__VA_ARGS__, .mcr = 1) \

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