/linux-master/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
H A D | smu7_hwmgr.c | 751 &data->dpm_table.mclk_table, 819 data->dpm_table.mclk_table.count = 0; 821 if (i == 0 || data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count-1].value != 823 data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].value = 825 data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].enabled = (i == 0) ? 1 : 0; 826 data->dpm_table.mclk_table.count++; 914 data->dpm_table.mclk_table 2209 struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table = local 2289 phm_ppt_v1_clock_voltage_dependency_table *mclk_table = pptable_info->vdd_dep_on_mclk; local 4087 struct smu7_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table); local 4963 struct smu7_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table); local 5126 struct smu7_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table); local 5209 struct phm_clock_voltage_dependency_table *mclk_table; local 5412 struct smu7_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table); local [all...] |
H A D | vega10_processpptables.c | 601 phm_ppt_v1_clock_voltage_dependency_table *mclk_table; local 606 mclk_table = kzalloc(struct_size(mclk_table, entries, mclk_dep_table->ucNumEntries), 608 if (!mclk_table) 611 mclk_table->count = (uint32_t)mclk_dep_table->ucNumEntries; 614 mclk_table->entries[i].vddInd = 616 mclk_table->entries[i].vddciInd = 618 mclk_table->entries[i].mvddInd = 620 mclk_table->entries[i].clk = 624 *pp_vega10_mclk_dep_table = mclk_table; [all...] |
H A D | smu10_hwmgr.c | 976 struct smu10_voltage_dependency_table *mclk_table = local 1006 if (low > mclk_table->count - 1 || high > mclk_table->count - 1) 1011 mclk_table->entries[low].clk/100, 1016 mclk_table->entries[high].clk/100, 1031 struct smu10_voltage_dependency_table *mclk_table = local 1062 for (i = 0; i < mclk_table->count; i++) 1065 mclk_table->entries[i].clk / 100, 1066 ((mclk_table->entries[i].clk / 100)
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H A D | vega10_hwmgr.c | 667 struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table = local 694 for (entry_id = 0; entry_id < mclk_table->count; ++entry_id) { 695 voltage_id = mclk_table->entries[entry_id].vddInd; 696 mclk_table->entries[entry_id].vddc = 698 voltage_id = mclk_table->entries[entry_id].vddciInd; 699 mclk_table->entries[entry_id].vddci = 701 voltage_id = mclk_table->entries[entry_id].mvddInd; 702 mclk_table->entries[entry_id].mvdd = 3420 struct vega10_single_dpm_table *mclk_table = &(data->dpm_table.mem_table); local 3437 for (i = 0; i < mclk_table 4039 vega10_get_uclk_index(struct pp_hwmgr *hwmgr, struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table, uint32_t frequency) argument 4067 struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table = table_info->vdd_dep_on_mclk; local 4650 struct vega10_single_dpm_table *mclk_table = &(data->dpm_table.mem_table); local 4796 struct vega10_single_dpm_table *mclk_table = &(data->dpm_table.mem_table); local 5155 struct vega10_single_dpm_table *mclk_table = &(data->dpm_table.mem_table); local [all...] |
H A D | process_pptables_v1_0.c | 367 phm_ppt_v1_clock_voltage_dependency_table *mclk_table; local 374 mclk_table = kzalloc(struct_size(mclk_table, entries, mclk_dep_table->ucNumEntries), 376 if (!mclk_table) 379 mclk_table->count = (uint32_t)mclk_dep_table->ucNumEntries; 384 entries, mclk_table, i); 395 *pp_tonga_mclk_dep_table = mclk_table;
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H A D | smu7_hwmgr.h | 105 struct smu7_single_dpm_table mclk_table; member in struct:smu7_dpm_table
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H A D | vega12_hwmgr.c | 2712 struct vega12_single_dpm_table *mclk_table = &(data->dpm_table.mem_table); 2715 int value = mclk_table->dpm_levels[mclk_table->count - 1].value;
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H A D | vega20_hwmgr.c | 1515 struct vega20_single_dpm_table *mclk_table = local 1519 int value = mclk_table->dpm_levels[mclk_table->count - 1].value;
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/linux-master/drivers/gpu/drm/amd/pm/powerplay/smumgr/ |
H A D | iceland_smumgr.c | 1361 for (i = 0; i < dpm_table->mclk_table.count; i++) { 1362 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value), 1364 result = iceland_populate_single_memory_level(hwmgr, dpm_table->mclk_table.dpm_levels[i].value, 1382 smu_data->smc_state_table.MemoryDpmLevelCount = (uint8_t)dpm_table->mclk_table.count; 1383 data->dpm_level_enable_mask.mclk_dpm_enable_mask = phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table); 1385 smu_data->smc_state_table.MemoryLevel[dpm_table->mclk_table.count-1].DisplayWatermark = PPSMC_DISPLAY_WATERMARK_HIGH; 1622 for (j = 0; j < data->dpm_table.mclk_table.count; j++) { 1625 data->dpm_table.mclk_table.dpm_levels[j].value, 1667 result = phm_find_boot_level(&(data->dpm_table.mclk_table), 1761 for (i = 0; i < data->dpm_table.mclk_table [all...] |
H A D | fiji_smumgr.c | 1234 for (i = 0; i < dpm_table->mclk_table.count; i++) { 1235 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value), 1239 dpm_table->mclk_table.dpm_levels[i].value, 1257 (uint8_t)dpm_table->mclk_table.count; 1259 phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table); 1261 levels[dpm_table->mclk_table.count - 1].DisplayWatermark = 1374 data->dpm_table.mclk_table.dpm_levels[0].value; 1395 data->dpm_table.mclk_table.dpm_levels[0].value, 1533 for (j = 0; j < data->dpm_table.mclk_table.count; j++) { 1536 data->dpm_table.mclk_table [all...] |
H A D | vegam_smumgr.c | 1049 for (i = 0; i < dpm_table->mclk_table.count; i++) { 1050 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value), 1054 dpm_table->mclk_table.dpm_levels[i].value, 1067 (uint8_t)dpm_table->mclk_table.count; 1069 phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table); 1071 for (i = 0; i < dpm_table->mclk_table.count; i++) 1075 levels[dpm_table->mclk_table.count - 1].DisplayWatermark = 1288 for (j = 0; j < hw_data->dpm_table.mclk_table.count; j++) { 1291 hw_data->dpm_table.mclk_table.dpm_levels[j].value, 1380 result = phm_find_boot_level(&(data->dpm_table.mclk_table), [all...] |
H A D | ci_smumgr.c | 1316 for (i = 0; i < dpm_table->mclk_table.count; i++) { 1317 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value), 1319 result = ci_populate_single_memory_level(hwmgr, dpm_table->mclk_table.dpm_levels[i].value, 1329 if ((dpm_table->mclk_table.count >= 2) 1339 smu_data->smc_state_table.MemoryDpmLevelCount = (uint8_t)dpm_table->mclk_table.count; 1340 data->dpm_level_enable_mask.mclk_dpm_enable_mask = phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table); 1341 smu_data->smc_state_table.MemoryLevel[dpm_table->mclk_table.count-1].DisplayWatermark = PPSMC_DISPLAY_WATERMARK_HIGH; 1661 for (j = 0; j < data->dpm_table.mclk_table.count; j++) { 1664 data->dpm_table.mclk_table.dpm_levels[j].value, 1706 result = phm_find_boot_level(&(data->dpm_table.mclk_table), [all...] |
H A D | tonga_smumgr.c | 1107 for (i = 0; i < dpm_table->mclk_table.count; i++) { 1108 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value), 1113 dpm_table->mclk_table.dpm_levels[i].value, 1130 smu_data->smc_state_table.MemoryDpmLevelCount = (uint8_t)dpm_table->mclk_table.count; 1131 data->dpm_level_enable_mask.mclk_dpm_enable_mask = phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table); 1133 smu_data->smc_state_table.MemoryLevel[dpm_table->mclk_table.count-1].DisplayWatermark = PPSMC_DISPLAY_WATERMARK_HIGH; 1498 for (j = 0; j < data->dpm_table.mclk_table.count; j++) { 1501 data->dpm_table.mclk_table.dpm_levels[j].value, 1545 result = phm_find_boot_level(&(data->dpm_table.mclk_table), 2140 for (i = 0; i < data->dpm_table.mclk_table [all...] |
H A D | polaris10_smumgr.c | 1223 for (i = 0; i < dpm_table->mclk_table.count; i++) { 1224 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value), 1228 dpm_table->mclk_table.dpm_levels[i].value, 1230 if (i == dpm_table->mclk_table.count - 1) 1237 (uint8_t)dpm_table->mclk_table.count; 1239 phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table); 1340 data->dpm_table.mclk_table.dpm_levels[0].value, 1499 for (j = 0; j < hw_data->dpm_table.mclk_table.count; j++) { 1502 hw_data->dpm_table.mclk_table.dpm_levels[j].value, 1505 result = atomctrl_set_ac_timing_ai(hwmgr, hw_data->dpm_table.mclk_table [all...] |
/linux-master/drivers/gpu/drm/radeon/ |
H A D | ci_dpm.c | 2512 for (j = 0; j < pi->dpm_table.mclk_table.count; j++) { 2515 pi->dpm_table.mclk_table.dpm_levels[j].value, 3292 for (i = 0; i < dpm_table->mclk_table.count; i++) { 3293 if (dpm_table->mclk_table.dpm_levels[i].value == 0) 3296 dpm_table->mclk_table.dpm_levels[i].value, 3304 if ((dpm_table->mclk_table.count >= 2) && 3314 pi->smc_state_table.MemoryDpmLevelCount = (u8)dpm_table->mclk_table.count; 3316 ci_get_dpm_level_enable_mask_value(&dpm_table->mclk_table); 3318 pi->smc_state_table.MemoryLevel[dpm_table->mclk_table.count - 1].DisplayWatermark = 3423 &pi->dpm_table.mclk_table, 3818 struct ci_single_dpm_table *mclk_table = &pi->dpm_table.mclk_table; local [all...] |
H A D | ci_dpm.h | 70 struct ci_single_dpm_table mclk_table; member in struct:ci_dpm_table
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