Searched refs:max_dac1_clock_32 (Results 1 - 16 of 16) sorted by relevance

/haiku/src/add-ons/accelerants/matrox/
H A DGetModeInfo.c120 max_pclk = si->ps.max_dac1_clock_32;
124 max_pclk = si->ps.max_dac1_clock_32;
/haiku/src/add-ons/accelerants/skeleton/
H A DGetModeInfo.c112 max_pclk = si->ps.max_dac1_clock_32;
116 max_pclk = si->ps.max_dac1_clock_32;
/haiku/src/add-ons/accelerants/via/
H A DGetModeInfo.c112 max_pclk = si->ps.max_dac1_clock_32;
116 max_pclk = si->ps.max_dac1_clock_32;
/haiku/src/add-ons/accelerants/matrox/engine/
H A Dmga_info.c129 si->ps.max_dac1_clock_32 = 0;
151 si->ps.max_dac1_clock_32 = pins[22];//ramdac
211 si->ps.max_dac1_clock_32 = pins[40] + 100;
291 si->ps.max_dac1_clock_32dh = si->ps.max_dac1_clock_32;
346 if (pins[43] == 0xff) si->ps.max_dac1_clock_32 = si->ps.max_dac1_clock_24;
347 else si->ps.max_dac1_clock_32 = 4 * pins[43];
428 si->ps.max_dac1_clock_32dh = si->ps.max_dac1_clock_32;
490 if (pins[42] == 0xff) si->ps.max_dac1_clock_32 = si->ps.max_dac1_clock_24;
491 else si->ps.max_dac1_clock_32 = 4 * pins[42];
493 if (pins[124] == 0xff) si->ps.max_dac1_clock_32dh = si->ps.max_dac1_clock_32;
[all...]
H A Dmga_dac.c368 max_pclk = si->ps.max_dac1_clock_32;
372 max_pclk = si->ps.max_dac1_clock_32;
515 max_pclk = si->ps.max_dac1_clock_32;
519 max_pclk = si->ps.max_dac1_clock_32;
649 max_pclk = si->ps.max_dac1_clock_32;
653 max_pclk = si->ps.max_dac1_clock_32;
/haiku/src/add-ons/accelerants/nvidia/
H A DGetModeInfo.c112 max_pclk = si->ps.max_dac1_clock_32;
116 max_pclk = si->ps.max_dac1_clock_32;
/haiku/src/add-ons/accelerants/via/engine/
H A Dinfo.c696 si->ps.max_dac1_clock_32 = 180;
730 si->ps.max_dac1_clock_32 = 230;
764 si->ps.max_dac1_clock_32 = 230;
798 si->ps.max_dac1_clock_32 = 280;
850 si->ps.max_dac1_clock_32 = 280;
900 si->ps.max_dac1_clock_32 = 280;
1052 LOG(2,("max_dac1_clock_32: %dMhz\n", si->ps.max_dac1_clock_32));
H A Ddac.c295 max_pclk = si->ps.max_dac1_clock_32;
299 max_pclk = si->ps.max_dac1_clock_32;
442 max_pclk = si->ps.max_dac1_clock_32;
446 max_pclk = si->ps.max_dac1_clock_32;
/haiku/headers/private/graphics/matrox/
H A DDriverInterface.h215 uint32 max_dac1_clock_32; member in struct:__anon785::__anon789
/haiku/src/add-ons/accelerants/skeleton/engine/
H A Ddac.c263 max_pclk = si->ps.max_dac1_clock_32;
267 max_pclk = si->ps.max_dac1_clock_32;
H A Dinfo.c2627 si->ps.max_dac1_clock_32 = 180;
2661 si->ps.max_dac1_clock_32 = 230;
2695 si->ps.max_dac1_clock_32 = 230;
2729 si->ps.max_dac1_clock_32 = 280;
2781 si->ps.max_dac1_clock_32 = 280;
2831 si->ps.max_dac1_clock_32 = 280;
3035 LOG(2,("max_dac1_clock_32: %dMhz\n", si->ps.max_dac1_clock_32));
/haiku/headers/private/graphics/skeleton/
H A DDriverInterface.h269 uint32 max_dac1_clock_32; member in struct:__anon937::__anon943
/haiku/headers/private/graphics/via/
H A DDriverInterface.h280 uint32 max_dac1_clock_32; member in struct:__anon7::__anon10
/haiku/headers/private/graphics/nvidia/
H A DDriverInterface.h409 uint32 max_dac1_clock_32; member in struct:__anon21::__anon27
/haiku/src/add-ons/accelerants/nvidia/engine/
H A Dnv_dac.c354 max_pclk = si->ps.max_dac1_clock_32;
358 max_pclk = si->ps.max_dac1_clock_32;
H A Dnv_info.c2983 si->ps.max_dac1_clock_32 = 180;
3017 si->ps.max_dac1_clock_32 = 230;
3051 si->ps.max_dac1_clock_32 = 230;
3085 si->ps.max_dac1_clock_32 = 280;
3137 si->ps.max_dac1_clock_32 = 280;
3202 si->ps.max_dac1_clock_32 = 280;
3379 LOG(2,("max_dac1_clock_32: %dMhz\n", si->ps.max_dac1_clock_32));

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