Searched refs:ixDIDT_SQ_EDC_STALL_PATTERN_1_2 (Results 1 - 8 of 8) sorted by relevance

/linux-master/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dvega10_powertune.c401 { ixDIDT_SQ_EDC_STALL_PATTERN_1_2, 0xFFFFFFFF, 0, 0x00030001 },
430 { ixDIDT_SQ_EDC_STALL_PATTERN_1_2, 0xFFFFFFFF, 0, 0x00000015 },
592 { ixDIDT_SQ_EDC_STALL_PATTERN_1_2, DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1_MASK, DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1__SHIFT, 0x0101 },
593 { ixDIDT_SQ_EDC_STALL_PATTERN_1_2, DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2_MASK, DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2__SHIFT, 0x0101 },
H A Dsmu7_hwmgr.c118 #define ixDIDT_SQ_EDC_STALL_PATTERN_1_2 0x0015 macro
145 ixDIDT_SQ_EDC_STALL_PATTERN_1_2,
/linux-master/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h7158 #define ixDIDT_SQ_EDC_STALL_PATTERN_1_2 0x0015 macro
H A Dgc_9_2_1_offset.h7408 #define ixDIDT_SQ_EDC_STALL_PATTERN_1_2 0x0015 macro
H A Dgc_9_1_offset.h7366 #define ixDIDT_SQ_EDC_STALL_PATTERN_1_2 0x0015 macro
H A Dgc_9_4_2_offset.h49 #define ixDIDT_SQ_EDC_STALL_PATTERN_1_2 0x0015 macro
H A Dgc_10_3_0_offset.h13490 #define ixDIDT_SQ_EDC_STALL_PATTERN_1_2 macro
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H A Dgc_10_1_0_offset.h11244 #define ixDIDT_SQ_EDC_STALL_PATTERN_1_2 macro
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