Searched refs:ixDIDT_SQ_EDC_CTRL (Results 1 - 8 of 8) sorted by relevance
| /linux-master/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
| H A D | vega10_powertune.c | 488 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_EN_MASK, DIDT_SQ_EDC_CTRL__EDC_EN__SHIFT, 0x0000 },
489 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_SW_RST_MASK, DIDT_SQ_EDC_CTRL__EDC_SW_RST__SHIFT, 0x0001 },
490 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK, DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT, 0x0000 },
491 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL_MASK, DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL__SHIFT, 0x0000 },
492 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK, DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT, 0x0000 },
493 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK, DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT, 0x0000 },
494 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK, DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT, 0x0000 },
495 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__GC_EDC_EN_MASK, DIDT_SQ_EDC_CTRL__GC_EDC_EN__SHIFT, 0x0000 },
496 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY_MASK, DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT, 0x0000 },
497 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MAS
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| H A D | smu7_hwmgr.c | 116 #define ixDIDT_SQ_EDC_CTRL 0x0013 macro
150 ixDIDT_SQ_EDC_CTRL,
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| /linux-master/drivers/gpu/drm/amd/include/asic_reg/gc/ |
| H A D | gc_9_0_offset.h | 7156 #define ixDIDT_SQ_EDC_CTRL 0x0013 macro
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| H A D | gc_9_2_1_offset.h | 7406 #define ixDIDT_SQ_EDC_CTRL 0x0013 macro
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| H A D | gc_9_1_offset.h | 7364 #define ixDIDT_SQ_EDC_CTRL 0x0013 macro
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| H A D | gc_9_4_2_offset.h | 47 #define ixDIDT_SQ_EDC_CTRL 0x0013 macro
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| H A D | gc_10_3_0_offset.h | 13488 #define ixDIDT_SQ_EDC_CTRL macro
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| H A D | gc_10_1_0_offset.h | 11242 #define ixDIDT_SQ_EDC_CTRL macro
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